Instruction processing method, device, chip, electronic device and storage medium

Abstract

The present disclosure provides an instruction processing method, device, chip, electronic device and storage medium, wherein the method includes: obtaining a first computing instruction to be processed; determining an addressing mode of first address information of first memory access data corresponding to the first computing instruction; the first memory access data includes an operand and / or a calculation result of the operand used to execute the first computing instruction; when the addressing mode is an address accumulation mode, obtaining accumulation step information based on the first computing instruction, and obtaining second address information of second memory access data corresponding to a second computing instruction; the second computing instruction is the previous instruction of the first computing instruction; based on the second address information and the accumulation step information, determining the first address information, and executing the first computing instruction based on the first address information.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular to an instruction processing method, device, chip, electronic device and storage medium. Background Art

[0002] Computer instructions are instructions and commands that direct the work of the machine. The process of executing instructions arranged in a certain order is the working process of the computer. The process of instruction execution mainly includes access to storage space and calculation of data. Among them, the forms of storage space access include direct addressing of immediate values ​​and indirect addressing using calculation results. Indirect addressing requires real-time calculation of address values, so indirect addressing brings additional instruction cycles, which affects the execution efficiency of instructions. Summary of the invention

[0003] The embodiments of the present disclosure at least provide an instruction processing method, device, chip, electronic device and storage medium.

[0004] In a first aspect, an embodiment of the present disclosure provides an instruction processing device, comprising: an instruction processing unit and an instruction execution unit; the instruction processing unit is configured to obtain a first calculation instruction to be processed; the instruction execution unit is configured to obtain cumulative step information based on the first calculation instruction, and obtain second address information of a second memory access data corresponding to a second calculation instruction; the second calculation instruction is the previous instruction of the first calculation instruction; based on the second address information and the cumulative step information, the first address information of the first memory access data corresponding to the first calculation instruction is determined, and the operand and / or the calculation result of the operand of the first calculation instruction is executed based on the first address information.

[0005] In the embodiment of the present disclosure, after the instruction processing unit obtains the first calculation instruction, the instruction execution unit can obtain the accumulated step information based on the first calculation instruction, and obtain the second address information of the second memory access data corresponding to the second calculation instruction, and then determine the first address information based on the second address information and the accumulated step information, and execute the first calculation instruction based on the first address information. In the above implementation, the address calculation can be hidden in the instruction processing process of the calculation instruction, thereby reducing additional instruction cycles, thereby speeding up the execution efficiency of the instruction.

[0006] In an optional embodiment, the instruction processing unit is configured to determine the addressing mode of the first address information of the first memory access data corresponding to the first calculation instruction after obtaining the first calculation instruction to be processed; the instruction execution unit is configured to obtain the accumulation step information based on the first calculation instruction when the addressing mode is the address accumulation mode, and obtain the second address information of the second memory access data corresponding to the second calculation instruction; and determine the first address information based on the second address information and the accumulation step information, and execute the first calculation instruction based on the first address information.

[0007] In the above implementation, after obtaining the first calculation instruction, the first address information of the first memory access data of the first calculation instruction is determined by using an address accumulation mode, so that the process of determining the first address information can be hidden in the instruction processing process of the first calculation instruction, thereby reducing additional instruction cycles and further speeding up the execution efficiency of the instruction.

[0008] In an optional embodiment, the instruction execution unit includes: an accumulator register and a first calculation unit; the accumulator register is configured to store the second address information; the first calculation unit is configured to perform accumulation calculation on the second address information and the accumulation step information after obtaining the accumulation step information sent by the instruction processing unit to obtain the first address information.

[0009] In an optional embodiment, the first address information includes: a first access address and a first storage address; the instruction execution unit includes: a second calculation unit: the second calculation unit is configured to: obtain the first access address and the first storage address sent by the first calculation unit, and obtain the operand stored in the storage position corresponding to the first access address; and use the operand obtained from the memory corresponding to the first access address as the first memory access data to execute the first calculation instruction, obtain the first calculation result of the first calculation instruction, and store the first calculation result to the storage position corresponding to the first storage address.

[0010] In an optional embodiment, the instruction processing unit is further configured to: when the addressing mode is a direct addressing mode, obtain the field content in the address field in the first calculation instruction; determine the first address information of the first memory access data based on the obtained field content, and send the first address information to the instruction execution unit, so that the instruction execution unit executes the first calculation instruction based on the first address information.

[0011] In an optional embodiment, the instruction processing unit includes: an instruction decoding unit; the instruction decoding unit is configured to determine a first enable flag in the first computing instruction, wherein the first enable flag is used to indicate whether an address accumulation mode for the first memory access data is enabled; and determine an addressing mode of the first address information of the first memory access data corresponding to the first computing instruction based on the first enable flag.

[0012] In an optional embodiment, the number of the first enable identifiers is multiple; each of the first enable identifiers corresponds to one data in the first memory access data; the instruction decoding unit is configured to: determine a first enable identifier that matches each data in the first memory access data among the multiple first enable identifiers; and determine the addressing mode of the first address information of each data in the first computing instruction based on the first enable identifier that matches each data in the first memory access data.

[0013] In an optional embodiment, the instruction decoding unit is configured to: after determining that the first enable flag is enabled and valid, detect a second enable flag in the second computing instruction; wherein the second enable flag is used to indicate whether the address accumulation mode indicated by the first enable flag in the first computing instruction is enabled and valid; and determine the first address information of the first memory access data corresponding to the first computing instruction based on the second enable flag.

[0014] In an optional embodiment, the instruction decoding unit is configured to: when it is determined that the second enable flag is enable disabled, determine that the first address information of the first memory access data corresponding to the first computing instruction is the second address information of the second memory access data corresponding to the second computing instruction.

[0015] In an optional embodiment, the second enable identifier includes multiple second sub-enable identifiers, each second sub-enable identifier corresponds to one data in the first memory access data; the instruction decoding unit is configured to: determine a second sub-enable identifier that matches each data in the first memory access data from the multiple second sub-enable identifiers; and determine the first address information of each data in the first memory access data based on the second sub-enable identifier that matches each data in the first memory access data.

[0016] In an optional embodiment, the instruction content of the first calculation instruction includes: at least one continuous first enable identifier and / or at least one continuous second enable identifier, wherein each of the first enable identifiers includes: a first identification field and a first field content, and each of the second enable identifiers includes: a second identification field and a second field content, the first identification field is used to indicate the addressing mode of the first calculation instruction, the first field content is used to indicate the cumulative step information or the first address information, the second identification field is used to indicate the addressing mode of the next calculation instruction of the first calculation instruction, and the second field content is used to indicate the cumulative step information or the first address information corresponding to the execution of the next calculation instruction.

[0017] In an optional implementation, the instruction processing device further includes: a register file; wherein the register file is used to store at least one of the following: the accumulation step information, the first memory access data and the first address information.

[0018] In an optional embodiment, the instruction execution unit includes an instruction decoding unit and an instruction issuing unit; the instruction decoding unit is configured to: decode the instruction content of the first computing instruction to obtain a decoding result; the instruction issuing unit is configured to: send an instruction to the register stack to obtain the accumulation step information based on the decoding result; the instruction execution unit is configured to: determine the first address information of the first memory access data in the register stack based on the second address information and the accumulation step information.

[0019] In an optional implementation, the register file includes a vector register file and a scalar register file, the vector register file is used to store the first memory access data of the first computing instruction, and the scalar register file is used to store the accumulation step information and / or the first address information.

[0020] In a second aspect, an embodiment of the present disclosure provides an instruction processing method, comprising: obtaining a first computing instruction to be processed; determining an addressing mode of first address information of first memory access data corresponding to the first computing instruction; the first memory access data includes an operand and / or a calculation result of the operand used to execute the first computing instruction; when the addressing mode is an address accumulation mode, obtaining accumulation step information based on the first computing instruction, and obtaining second address information of second memory access data corresponding to the second computing instruction; the second computing instruction is the previous instruction of the first computing instruction; determining the first address information based on the second address information and the accumulation step information, and executing the first computing instruction based on the first address information.

[0021] In a third aspect, an embodiment of the present disclosure provides an instruction processing device, comprising: a first acquisition unit, used to acquire a first calculation instruction to be processed; a determination unit, used to determine the addressing mode of first address information of first memory access data corresponding to the first calculation instruction; the first memory access data includes an operand and / or a calculation result of the operand used to execute the first calculation instruction; a second acquisition unit, used to acquire accumulation step information based on the first calculation instruction when the addressing mode is an address accumulation mode, and acquire second address information of second memory access data corresponding to the second calculation instruction; the second calculation instruction is the previous instruction of the first calculation instruction; an instruction execution unit, used to determine the first address information based on the second address information and the accumulation step information, and execute the first calculation instruction based on the first address information.

[0022] In a fourth aspect, an embodiment of the present disclosure further provides a chip, comprising the instruction processing device described in any one of the above-mentioned first aspects.

[0023] In a fifth aspect, an embodiment of the present disclosure further provides an electronic device, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the steps of the above-mentioned second aspect, or any possible implementation of the second aspect are performed; or a chip as described in the fourth aspect.

[0024] In a sixth aspect, an embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned second aspect, or any possible implementation of the second aspect are executed.

[0025] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following is a brief introduction to the drawings required for use in the embodiments. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can also be obtained based on these drawings without creative work.

[0027] Figure 1A flowchart of an instruction processing method provided by an embodiment of the present disclosure is shown;

[0028] Figure 2 A flowchart showing a specific method for determining an addressing mode of first address information of first memory access data corresponding to the first computing instruction in the instruction processing method provided by an embodiment of the present disclosure;

[0029] Figure 3 A flowchart showing another instruction processing method provided by an embodiment of the present disclosure is shown;

[0030] Figure 4 A schematic diagram showing the structure of a first instruction processing device provided by an embodiment of the present disclosure is shown;

[0031] Figure 5 A schematic diagram showing the structure of a second instruction processing device provided by an embodiment of the present disclosure is shown;

[0032] Figure 6 A schematic diagram showing the structure of a third instruction processing device provided by an embodiment of the present disclosure is shown;

[0033] Figure 7 A schematic diagram showing the instruction processing flow of the first instruction processing device provided by an embodiment of the present disclosure;

[0034] Figure 8 A schematic diagram showing the instruction processing flow of the second instruction processing device provided by an embodiment of the present disclosure;

[0035] Fig. 9 A schematic diagram of an instruction processing device provided by an embodiment of the present disclosure is shown;

[0036] Fig.10 A schematic diagram of an electronic device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0038] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0039] The term "and / or" herein only describes an association relationship, indicating that three relationships may exist. For example, A and / or B may represent the following three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C may represent including any one or more elements selected from the set consisting of A, B, and C.

[0040] Research has found that computer instructions are instructions and commands that direct the work of the machine. The process of executing instructions arranged in a certain order is the working process of the computer. The process of instruction execution mainly includes access to storage space and calculation of data. Among them, the forms of storage space access include immediate direct addressing and indirect addressing using calculation results. Indirect addressing requires real-time calculation of the address value, so the indirect addressing method brings additional instruction cycles, which affects the execution efficiency of instructions.

[0041] Based on the above research, the present disclosure provides an instruction processing method. In an embodiment of the present disclosure, after obtaining the first calculation instruction, the addressing mode of the first address information of the first memory access data corresponding to the first calculation instruction can be determined. In the case where the addressing mode is an address accumulation mode, the accumulation step information can be obtained based on the first calculation instruction, and the second address information of the second memory access data corresponding to the second calculation instruction can be obtained, and then the first address information is determined based on the second address information and the accumulation step information, and the first calculation instruction is executed based on the first address information. In an embodiment of the present disclosure, after obtaining the first calculation instruction, the first address information of the first memory access data of the first calculation instruction is determined by the address accumulation mode, so that the determination process of the first address information can be hidden in the instruction processing process of the first calculation instruction, thereby reducing additional instruction cycles, thereby speeding up the execution efficiency of the instruction.

[0042] To facilitate understanding of this embodiment, an instruction processing method disclosed in the embodiment of the present disclosure is first introduced in detail. The execution subject of the instruction processing method provided in the embodiment of the present disclosure is generally an electronic device with certain computing capabilities.

[0043] See also Figure 1 FIG. 1 is a flowchart of an instruction processing method provided by an embodiment of the present disclosure, wherein the method includes steps S101 to S107, wherein:

[0044] S101: Obtain a first computing instruction to be processed.

[0045] In the embodiment of the present disclosure, the first calculation instruction to be processed can be obtained from the instruction register. Here, the first calculation instruction can be any type of calculation instruction, such as a multiplication-accumulation instruction macc, which is not specifically limited in the present disclosure.

[0046] S103: Determine an addressing mode of first address information of first memory access data corresponding to the first computing instruction; the first memory access data includes an operand and / or a calculation result of the operand used to execute the first computing instruction.

[0047] Here, the addressing mode includes an address accumulation mode and a direct addressing mode. The address accumulation mode can be understood as determining the first address information (access address information or storage address information) of the first memory access data in the storage device according to a preset accumulation algorithm during the instruction execution process. The direct addressing mode can be understood as obtaining the first address information (access address information or storage address information) of the first memory access data in the storage device based on the address field in the first calculation instruction during the instruction execution process. The storage device can be a memory and a register stack in an internal storage device, and can also be an external storage device of the instruction processing device.

[0048] In the embodiment of the present disclosure, the addressing mode of the first address information of the first memory access data can be determined based on the instruction content of the first calculation instruction. In specific implementation, it can be determined based on the specified data bits in the first calculation instruction whether the addressing mode of the first address information of the first memory access data is the address accumulation mode or the direct addressing mode.

[0049] S105: When the addressing mode is the address accumulation mode, obtain accumulation step information based on the first calculation instruction, and obtain second address information of the second memory access data corresponding to the second calculation instruction; the second calculation instruction is the previous instruction of the first calculation instruction.

[0050] In the disclosed embodiment, the second computing instruction is the previous instruction of the first computing instruction. Here, the second address information is the first address information of the second access data corresponding to the second computing instruction in the storage device of the instruction processing device. Here, the second access data includes the operand used to execute the second computing instruction and / or the calculation result of the operand.

[0051] The inventors have found that for high-performance computing scenarios, the data access addresses of multiple instructions often have certain correlations, for example, the addresses often increase in a fixed step size. Based on this, in the embodiments of the present disclosure, a cumulative step size information can be preset. Here, the determination of the cumulative step size information is associated with the storage location of the first memory access data in the storage device of the instruction processing device.

[0052] S107: Determine the first address information based on the second address information and the accumulation step information, and execute the first calculation instruction based on the first address information.

[0053] After the second address information and the accumulation step information are determined, the second address information and the accumulation step information can be accumulated to obtain the first address information.

[0054] The following uses the dot product operation in the convolution operation as an example to illustrate the problem that the indirect addressing method in the prior art brings about additional instruction cycles.

[0055] Assume that the input data are x = [a1, a2, a3], y = [b1, b2, b3], let the vector x be stored in the first address information space 0-2, and y be stored in the first address information space 3-5, then the corresponding dot product calculation procedure is as follows:

[0056]

[0057]

[0058] In the above program code, mac is a multiply-accumulate instruction. For the above for loop instruction, each time the multiply-accumulate instruction mac is executed, the following instructions "x_addr=x_addr+1" and "y_addr=y_addr+1" must be executed. Therefore, for each loop of the for loop instruction, the above three instructions need to be issued and executed to realize the function of the multiply-accumulate instruction mac, and at this time, three instruction cycles will be consumed. For an instruction processing device with high processing performance requirements, realizing the function of an instruction through three instruction cycles will reduce the processing performance of the instruction processing device.

[0059] In an embodiment of the present disclosure, after obtaining the first calculation instruction, the addressing mode of the first address information of the first memory access data corresponding to the first calculation instruction can be determined. In the case where the addressing mode is an address accumulation mode, the accumulation step information can be obtained based on the first calculation instruction, and the second address information of the second memory access data corresponding to the second calculation instruction can be obtained, and then the first address information is determined based on the second address information and the accumulation step information, and the first calculation instruction is executed based on the first address information. In an embodiment of the present disclosure, after obtaining the first calculation instruction, the first address information of the first memory access data of the first calculation instruction is determined by the address accumulation mode, so that the determination process of the first address information can be hidden in the instruction processing process of the first calculation instruction, thereby reducing additional instruction cycles, thereby speeding up the execution efficiency of the instruction.

[0060] The above instruction processing method will be introduced below in conjunction with specific implementation methods.

[0061] In the embodiment of the present disclosure, first, a first computing instruction to be processed is obtained from an instruction register, and then an addressing mode of first address information of first memory access data corresponding to the first computing instruction is determined.

[0062] In an optional embodiment, if Figure 2 As shown, the above step S103: determining the addressing mode of the first address information of the first memory access data corresponding to the first computing instruction specifically includes the following steps:

[0063] Step S1031: determining a first enable flag in the first calculation instruction, wherein the first enable flag is used to indicate whether an address accumulation mode for the first memory access data is enabled and valid;

[0064] Step S1032: determining an addressing mode of first address information of first memory access data corresponding to the first computing instruction based on the first enable flag.

[0065] In the embodiment of the present disclosure, a designated data bit including a first enable flag may be determined among the data bits of the first computing instruction, and the value of the designated data bit may be determined as the first enable flag.

[0066] In a specific implementation, when the first enable flag is a first value, it can be determined that the address accumulation mode enable of the first memory access data is valid; when the first enable flag is a second value, it can be determined that the address accumulation mode enable of the first memory access data is prohibited.

[0067] Here, the first value and the second value can be set according to actual needs, and the present disclosure does not specifically limit this. For example, the first value can be set to "1" to indicate that the address accumulation mode of the first memory access data is enabled and valid, and the second value can be set to "0" to indicate that the address accumulation mode of the first memory access data is enabled and disabled.

[0068] In the embodiment of the present disclosure, after obtaining the first calculation instruction, the value of the specified data bit in the first calculation instruction can be obtained, and then the first enable flag can be determined according to the value of the specified data bit. After obtaining the first enable flag, it can be determined based on the first enable flag whether the address accumulation mode for the first memory access data is enabled.

[0069] When it is determined that the enable is valid, the addressing mode for the first address information of the first memory access data can be determined to be an address accumulation mode; when it is determined that the enable is prohibited, the addressing mode for the first address information of the first memory access data can be determined to be a non-address accumulation mode (for example, a direct addressing mode).

[0070] In the above implementation, by determining the first enable flag in the first computing instruction, and then determining the addressing mode of the first address information of the first memory access data according to the first enable flag, it is possible to hide the determination process of the first address information in the instruction processing process of the first computing instruction, thereby reducing additional instruction cycles and speeding up the execution efficiency of the instruction.

[0071] After the addressing mode of the first address information of the first memory access data is determined, the first address information of the first memory access data (ie, the above-mentioned first address information) can be determined based on the addressing mode, which is described below in different situations.

[0072] Case 1: The addressing mode is the address accumulation mode.

[0073] When the addressing mode is the address accumulation mode, the accumulation step information may be acquired based on the instruction content of the first calculation instruction.

[0074] In specific implementation, the accumulated step information may be obtained in a register stack or instruction encoding based on the instruction content of the first calculation instruction. These two methods will be introduced respectively below.

[0075] Method 1: Register file-based method.

[0076] When the addressing mode is the address accumulation mode, the instruction content of the first calculation instruction includes the index identifier of the register storing the accumulation step information in the register file. In this case, the data in the corresponding register can be read based on the index identifier, and the read data is determined as the accumulation step information.

[0077] Method 2: Based on instruction encoding.

[0078] When the addressing mode is the address accumulation mode, the instruction content of the first calculation instruction includes the accumulation step information. In this case, the accumulation step information can be directly determined according to the instruction content of the first calculation instruction.

[0079] After determining the cumulative step information in accordance with the methods described in Method 1 and Method 2 above, the second address information of the operand used in the process of executing the second calculation instruction can be obtained, and based on the second address information and the cumulative step information, the first address information can be determined, and then the first calculation instruction can be executed based on the first address information.

[0080] Case 2: The addressing mode is direct addressing mode.

[0081] In the case where the addressing mode is a direct addressing mode, the field content in the address field in the first calculation instruction is obtained; and the first address information of the first memory access data is determined based on the obtained field content.

[0082] In the embodiment of the present disclosure, when the addressing mode is the direct addressing mode, the first address information of the first memory access data (ie, the above-mentioned first address information) can be acquired based on the instruction content of the first calculation instruction.

[0083] In specific implementation, the first address information of the first memory access data may be obtained in a register stack or instruction encoding based on the instruction content of the first computing instruction. These two methods will be introduced respectively below.

[0084] Method 1: Register file-based method.

[0085] When the addressing mode is the direct addressing mode, the instruction content of the first calculation instruction includes the index identifier of the register storing the first address information in the register file. In this case, the first address information in the corresponding register can be read based on the index identifier.

[0086] Method 2: Based on instruction encoding.

[0087] When the addressing mode is the direct addressing mode, the instruction content of the first calculation instruction includes the first address information of the first memory access data. In this case, the first address information of the first memory access data can be directly determined according to the instruction content of the first calculation instruction.

[0088] After the first address information (ie, the first address information) of the first memory access data is determined according to the methods described in the first and second methods, the first calculation instruction can be executed based on the first address information.

[0089] For example, the instruction form of the first calculation instruction may be: Opcal (addr1 / dlt1=a, addr2 / dlt2=b, addr3 / dlt3=c), wherein Opcal is the first calculation instruction, and (addr1 / dlt1, addr2 / dlt2, addr3 / dlt3) is part of the instruction content of the first calculation instruction. Wherein, addr1 / dlt1 and addr2 / dlt2 are instruction contents for determining the access information of the operand in the first memory access data (for example, the access address of the operand), and addr3 / dlt3 is instruction content for determining the storage information of the calculation result of the first memory access data (for example, the storage address of the calculation result).

[0090] When the addressing mode is the address accumulation mode, part of the instruction content of the first calculation instruction includes the following information (dlt1=a1, dlt2=b1, dlt3=c1), where dlt1, dlt2, dlt3 can be expressed as the first enable flag enabling validity, a1, b1, c1 can be the accumulation step information, and can also be expressed as the index identifier of the register in the register file that stores the accumulation step information.

[0091] When the addressing mode is direct addressing mode, part of the instruction content of the first calculation instruction includes the following information (addr1=a2, addr2=b2, addr3=c2), wherein addr1, addr2, addr3 can be represented as the first enable flag enable / disable, a2, b2, c2 can be the first address information of the first memory access data, and can also be represented as the index flag of the register in the register stack that stores the first address information of the first memory access data.

[0092] In an optional implementation, the first enable identifier includes a plurality of first sub-enable identifiers; each of the first sub-enable identifiers corresponds to one data in the first memory access data.

[0093] Take the first calculation instruction Opcal (addr1 / dlt1=a, addr2 / dlt2=b, addr3 / dlt3=c) as an example for explanation, wherein addr / dlt is the first enable flag. addr indicates that the first enable flag is enabled or disabled, and dlt indicates that the first enable flag is enabled or valid.

[0094] addr1 / dlt1, addr2 / dlt2 and addr3 / dlt3 are the above-mentioned multiple first sub-enable identifiers, wherein the first sub-enable identifier addr1 / dlt1 is used to indicate the addressing mode of the access address of operand 1, the first sub-enable identifier addr2 / dlt2 is used to indicate the addressing mode of the access address of operand 2, and the first sub-enable identifier addr3 / dlt3 is used to indicate the addressing mode of the storage address of the calculation result of the operand of the first calculation instruction.

[0095] In this case, the above step S1032: determining the addressing mode of the first address information of the first memory access data corresponding to the first computing instruction based on the first enabling flag, includes the following steps:

[0096] Step S10321: determining a first sub-enabling identifier that matches each data in the first memory access data from among the plurality of first sub-enabling identifiers;

[0097] Step S10322: Determine the addressing mode of the first address information of each data in the first computing instruction based on the first sub-enable identifier that matches each data in the first memory access data.

[0098] It should be understood that the above-mentioned first enable flag may include multiple first sub-enable flags, each of which is used to indicate the addressing mode of the first address information of each data in the first memory access data. Here, each data in the first memory access data can be understood as each operand used to execute the first calculation instruction, and the calculation result of the operand.

[0099] That is to say, the addressing modes of each operand and the first address information of the calculation result of the operand may be the same or different, and the present disclosure does not make any specific limitation on this.

[0100] Here, for the operand, the first address information can be understood as the reading address of the operand (that is, the first access address mentioned below); for the calculation result of the operand, the first address information can be understood as the storage location of the calculation result (that is, the first storage address mentioned below).

[0101] In a first calculation instruction, the addressing modes of the first address information of each operand and the calculation result of the operand may not be completely the same. In this case, for each operation data and the calculation result of the operand, the first address information can be determined according to the corresponding addressing mode.

[0102] In specific implementation, the first sub-enable identifier that matches each data in the first memory access data can be determined from multiple first sub-enable identifiers, and then the addressing mode of the first address information of the corresponding data is determined to be the address accumulation mode based on the identifier content (addr1 / dlt1) of the matched first sub-enable identifier.

[0103] In the above implementation, by setting a corresponding first sub-enable flag for each data in the first memory access data (i.e., the operand and the calculation result of the operand), and controlling the first address information of each data according to the first sub-enable flag, the applicable scenarios of the technical solution can be expanded to meet the programming needs of programmers.

[0104] In the above Figure 2 Based on the described embodiments, Figure 3 As shown, the method provided in the embodiment of the present disclosure also includes the following steps:

[0105] Step S301: after determining that the first enable flag is enabled and valid, detecting a second enable flag in the second calculation instruction; wherein the second enable flag is used to indicate whether the address accumulation mode indicated by the first enable flag in the first calculation instruction is enabled and valid;

[0106] Step S302: determining first address information of first memory access data corresponding to the first computing instruction based on the second enable flag.

[0107] For high-performance computing scenarios, multiple loops are often required to implement the calculation process. The program for each layer of the loop process includes an initial instruction and a loop instruction; wherein the initial instruction is used to give the initial address. Assume that the loop instruction is an instruction that is executed N times in a loop. If the address accumulation mode is enabled in the loop instruction, the data address information corresponding to the first instruction in the loop instruction is determined after the address accumulation calculation is performed based on the data address information of the initial address. In this case, the data address information of the first instruction in the loop instruction may be incorrect, resulting in the acquisition of an incorrect operand, which in turn seriously affects the instruction calculation result.

[0108] Based on this, in the embodiment of the present disclosure, the above-mentioned address accumulation mode is extended so that the extended address accumulation mode can support the loop program more concisely and efficiently. The specific extension method is:

[0109] A second enable flag is set in the previous instruction of the first calculation instruction (ie, the second calculation instruction), and the second enable flag is used to indicate whether the address accumulation mode indicated by the first enable flag in the next calculation instruction of the second calculation instruction (ie, the first calculation instruction) is enabled.

[0110] In a specific implementation, when the first enable flag in the first computing instruction indicates that the address accumulation mode enable for the first memory access data is valid, if the second enable flag in the second computing instruction is enable disable, it is determined that the address accumulation mode indicated by the first enable flag in the first computing instruction is enable disable. That is, even if the addressing mode is determined to be the address accumulation mode according to the first enable flag in the first computing instruction, if the second enable flag is enable disable, the addressing mode for the first memory access data in the first computing instruction can be the direct addressing mode, or the first address information is determined according to the second address information.

[0111] For example, the second calculation instruction is an address initialization instruction in a loop program, and in the case where the first calculation instruction is the first loop instruction in the loop program, at this time, the first enable flag can be set in the first calculation instruction to enable valid, and the second enable flag can be set in the second calculation instruction to enable prohibited. At this time, for the first loop instruction, the first address information of the first memory access data can be determined by the direct addressing mode, or the second address information of the second memory access data corresponding to the second calculation instruction can be determined as the above-mentioned first address information. For other loop instructions in the loop program, for example, the Nth loop instruction, N is greater than 1, it can be determined whether the address accumulation mode is enabled and valid based on the second enable flag in the N-1th loop instruction.

[0112] In an embodiment of the present disclosure, when the second enable identifier is a third value, it can be determined that the address accumulation mode enable indicated by the first enable identifier in the next calculation instruction of the second calculation instruction is valid; when the second enable identifier is a fourth value, it can be determined that the address accumulation mode enable indicated by the first enable identifier in the next calculation instruction of the second calculation instruction is prohibited.

[0113] Here, the third value and the fourth value can be set according to actual needs, and the present disclosure does not specifically limit this. For example, the third value can be set to "1" to indicate that the enable is valid, and the fourth value can be set to "0" to indicate that the enable is disabled.

[0114] It should be understood that the extended scheme described in the above steps S301 and S302 can be applied not only to the calculation process of multiple cycles, but also to other calculation processes, for example, a calculation process similar to the calculation process of multiple cycles, or other scenarios that require specifying the enable or disable of the address accumulation mode indicated by the first enable flag in the first calculation instruction. The present disclosure does not make specific limitations on this, and it is subject to what can be implemented.

[0115] In an optional implementation, the above step S302: determining the first address information of the first memory access data corresponding to the first computing instruction based on the second enabling flag, specifically includes the following steps:

[0116] Step S3021: when it is determined that the second enable flag is enable disabled, determine that the first address information of the first memory access data corresponding to the first computing instruction is the second address information of the second memory access data corresponding to the second computing instruction.

[0117] In the embodiment of the present disclosure, when it is determined that the second enable flag is enabled and valid, the first address information of the first memory access data can be determined according to the address accumulation mode. In specific implementation, the accumulation step information can be obtained based on the first calculation instruction, and the second address information of the second memory access data corresponding to the second calculation instruction can be obtained; then, based on the second address information and the accumulation step information, the first address information is determined, and the first calculation instruction is executed based on the first address information.

[0118] When it is determined that the second enable flag is enable disabled, the second address information of the second memory access data corresponding to the second computing instruction may be determined as the first address information.

[0119] The following is an example of the loop program in the above embodiment. It can be seen from the above description that each layer of the loop program in the multiple loop program includes an initial instruction and a loop instruction. The initial instruction is used to give an initial address.

[0120] Assume that the second calculation instruction is an address initialization instruction in a loop program, and the first calculation instruction is the first loop instruction in the loop program. At this time, the second enable flag can be set in the second calculation instruction to enable or disable. At this time, for the first loop instruction, the second address information of the second memory access data corresponding to the second calculation instruction can be determined as the above-mentioned first address information. For example, the second address information in the address initialization instruction is determined as the first address information of the first calculation instruction.

[0121] In the disclosed embodiment, the programmer can set the second enable flag to enable or disable according to actual needs. Through this processing method, it is possible to avoid errors in the data address information of the first instruction in the loop instruction, so that accurate operands can be obtained. At the same time, through this processing method, the flexibility of the program written by the user can be improved, thereby meeting various programming needs of the programmer.

[0122] In the above implementation, by setting a second enable flag in the previous instruction of the first calculation instruction to determine whether the address accumulation mode indicated by the first enable flag in the first calculation instruction is enabled according to the second enable flag, the applicable scenarios of the technical solution of the present invention can be expanded. For the calculation process of multiple cycles, the calculation instructions can still be processed by the technical solution of the present invention, thereby improving the processing efficiency of the loop instructions.

[0123] In an optional implementation, when the second enable identifier includes multiple second sub-enable identifiers, and each second sub-enable identifier corresponds to one of the first memory access data, the above step S302: determining the first address information of the first memory access data corresponding to the first computing instruction based on the second enable identifier specifically includes the following steps:

[0124] (1) determining, from among the plurality of second sub-enable identifiers, a second sub-enable identifier that matches each data in the first memory access data;

[0125] (2) Determine first address information of each data in the first memory access data based on a second sub-enable identifier that matches each data in the first memory access data.

[0126] In the embodiment of the present disclosure, the second enable flag may include multiple second sub-enable flags, each second sub-enable flag corresponding to one of the first memory access data. Here, each of the first memory access data can be understood as each operand used to execute the first calculation instruction, and the calculation result of the operand.

[0127] In the embodiment of the present disclosure, a second sub-enable identifier matching each data in the first memory access data may be determined from multiple second sub-enable identifiers, and then first address information of the corresponding data may be determined according to the identifier value of the matched second sub-enable identifier.

[0128] For example, the second calculation instruction is:

[0129] opinit(addr1,addr2,addr3,nxt_dlt0_on,nxt_dlt1_on,nxt_dlt2_off);

[0130] opcal(addr1 / dlt1,addr2 / dlt2,addr3 / dlt3,nxt_dlt0_on,nxt_dlt1_on,nxt_dlt2_off).

[0131] Wherein, opcal is the first calculation instruction, opinit is the second calculation instruction, and (addr1 / dlt1, addr2 / dlt2, addr3 / dlt3, nxt_dlt_on[2:0]) is part of the instruction content of the first calculation instruction. Wherein, addr1 / dlt1 and addr2 / dlt2 are instruction contents for determining access information of the operand in the first memory access data, and addr3 / dlt3 is instruction content for determining storage information of the calculation result of the operand in the first memory access data.

[0132] Assume that the first enable flag in the first calculation instruction is that the address accumulation mode is enabled. It can be seen from the second enable flag (nxt_dlt0_on, nxt_dlt1_on, nxt_dlt2_off) in the second calculation instruction that the address accumulation mode of the access address of the operand corresponding to "dlt1" and "dlt2" in the first calculation instruction is enabled and the address accumulation mode of the storage address of the calculation result corresponding to "dlt3" in the first calculation instruction is disabled.

[0133] In this case, the access addresses of the operands corresponding to "dlt1" and "dlt2" can be determined based on the address accumulation mode, and the storage address of the calculation result of the second calculation instruction can be determined as the storage address of the calculation result of the first calculation instruction.

[0134] In the above implementation, by setting a corresponding second sub-enable flag for each data in the first memory access data, and controlling whether the first address information address accumulation mode of each data is enabled according to the second sub-enable flag, the applicable scenarios of the technical solution can be further expanded to meet the programming needs of programmers.

[0135] The above content is introduced below by taking the above dot product calculation program as an example. With respect to the above described dot product calculation program, after adopting the technical solution provided by the embodiment of the present disclosure, the program can be described as:

[0136]

[0137]

[0138] Among them, minit is an address initialization instruction, which is the previous instruction of the first instruction in the for loop, that is, minit is the second calculation instruction described above, and the first macc instruction in the for loop can be the first calculation instruction described above.

[0139] The address initialization instruction includes vector x, vector y, and the initial addresses of the calculation results of vector x and vector y. In the address initialization instruction, "nxt_dlt0_on, nxt_dlt1_on, nxt_dlt2_on" respectively indicate that the address accumulation mode corresponding to vector x in the first macc instruction of the for loop is enabled, the address accumulation mode corresponding to vector y in the first macc instruction of the for loop is enabled, and the address accumulation mode corresponding to the calculation results of vector x and vector y in the first macc instruction of the for loop is enabled.

[0140] At this time, for the first macc instruction of the for loop, the access addresses of vector x and vector y can be determined based on the address accumulation mode, and the storage addresses of the calculation results of vector x and vector y can be determined.

[0141] In an optional implementation, the instruction processing device comprises a register file, and the register file is used to store the accumulation step information and the first memory access data.

[0142] In this case, the above-mentioned step S105: obtaining the accumulation step information based on the first calculation instruction includes: obtaining the accumulation step information in the register file based on the instruction content of the first calculation instruction.

[0143] In this case, the above step S107: determining the first address information based on the second address information and the cumulative step information includes: determining the first address information of the first memory access data in the register stack based on the second address information and the cumulative step information.

[0144] In the embodiment of the present disclosure, when the addressing mode is the address accumulation mode, the instruction content of the first calculation instruction includes the index identifier of the register storing the accumulation step information in the register file. In this case, the data in the corresponding register can be read based on the index identifier, and the read data is determined as the accumulation step information.

[0145] After the accumulation step information is determined, the second address information and the accumulation step information may be accumulated and calculated to obtain the first address information of the first memory access data.

[0146] In an optional implementation, the register file includes a vector register file and a scalar register file, the vector register file is used to store the first memory access data of the first computing instruction, and the scalar register file is used to store the accumulation step information.

[0147] At present, the development of artificial intelligence has put forward higher requirements on computing power. In this context, the computing power density of instruction processing devices continues to increase, and the performance requirements for memory access are also increasing accordingly. In order to meet the memory access requirements, the current trend is to add high-speed internal storage space (for example, register files) inside the instruction processing device. The first computing unit of the instruction processing device can directly access these storage spaces (for example, register files) and perform efficient data reuse therein, thereby improving the computing efficiency of the first computing unit in the instruction processing device.

[0148] In an optional implementation, when the first address information includes: a first access address and a first storage address, the above step S107: executing the first calculation instruction based on the first address information specifically includes the following steps:

[0149] Step S1071: obtaining an operand stored in a storage location corresponding to the first access address;

[0150] Step S1072: Execute the first calculation instruction using the operand obtained from the memory corresponding to the first access address as the first memory access data, obtain a first calculation result of the first calculation instruction, and store the first calculation result in a storage location corresponding to the first storage address.

[0151] In the disclosed embodiment, the operand stored in the storage location corresponding to the first access address may be obtained. For example, the operand stored in the register corresponding to the first access address in the register file is obtained, and the first calculation instruction is executed on the obtained operand to obtain the first calculation result of the first calculation instruction, and the first calculation result is stored in the register corresponding to the first storage address in the register file.

[0152] In the above implementation, through the above processing method, the determination process of the first address information can be hidden in the instruction processing process of the first calculation instruction, thereby reducing additional instruction cycles and further speeding up the execution efficiency of the instruction.

[0153] Reference Figure 4 FIG. 4 is a schematic diagram of an instruction processing device provided by an embodiment of the present disclosure, wherein the device comprises: an instruction processing unit 41 and an instruction execution unit 42; wherein:

[0154] The instruction processing unit 41 is configured to obtain a first computing instruction to be processed;

[0155] The instruction execution unit 42 is configured to obtain the accumulation step information based on the first calculation instruction, and obtain the second address information of the second memory access data corresponding to the second calculation instruction; the second calculation instruction is the previous instruction of the first calculation instruction; and

[0156] Based on the second address information and the accumulated step information, the first address information of the first memory access data corresponding to the first calculation instruction is determined, and the operand and / or the calculation result of the operand of the first calculation instruction is executed based on the first address information.

[0157] In the embodiment of the present disclosure, after the instruction processing unit obtains the first calculation instruction, the instruction execution unit can obtain the accumulated step information based on the first calculation instruction, and obtain the second address information of the second memory access data corresponding to the second calculation instruction, and then determine the first address information based on the second address information and the accumulated step information, and execute the first calculation instruction based on the first address information. In the above implementation, the address calculation can be hidden in the instruction processing process of the calculation instruction, thereby reducing additional instruction cycles, thereby speeding up the execution efficiency of the instruction.

[0158] In an optional implementation, the instruction processing unit 41 is further configured to determine an addressing mode of first address information of first memory access data corresponding to the first computing instruction after acquiring the first computing instruction to be processed.

[0159] The instruction execution unit 42 is also configured to, when the addressing mode is the address accumulation mode, obtain the accumulation step information based on the first calculation instruction, and obtain the second address information of the second memory access data corresponding to the second calculation instruction; and determine the first address information based on the second address information and the accumulation step information, and execute the first calculation instruction based on the first address information.

[0160] In an embodiment of the present disclosure, after the instruction processing unit obtains the first calculation instruction, the addressing mode of the first address information of the first memory access data corresponding to the first calculation instruction can be determined. In the case where the addressing mode is an address accumulation mode, the instruction execution unit can obtain the accumulation step information based on the first calculation instruction, and obtain the second address information of the second memory access data corresponding to the second calculation instruction, and then determine the first address information based on the second address information and the accumulation step information, and execute the first calculation instruction based on the first address information. In an embodiment of the present disclosure, after the first calculation instruction is obtained, the first address information of the first memory access data of the first calculation instruction is determined by the address accumulation mode, so that the determination process of the first address information can be hidden in the instruction processing process of the first calculation instruction, thereby reducing additional instruction cycles, thereby speeding up the execution efficiency of the instruction.

[0161] In an optional embodiment, the instruction processing unit 41 is also configured to: when the addressing mode is a direct addressing mode, obtain the field content in the address field in the first calculation instruction; and determine the first address information of the first memory access data based on the obtained field content, and send the first address information to the instruction execution unit, so that the instruction execution unit executes the first calculation instruction based on the first address information.

[0162] In the embodiment of the present disclosure, when the addressing mode is the direct addressing mode, the first address information of the first memory access data (ie, the above-mentioned first address information) can be acquired based on the instruction content of the first calculation instruction.

[0163] In specific implementation, the first address information of the first memory access data can be obtained in the register stack or instruction code based on the instruction content of the first computing instruction. Specifically, the first address information of the first memory access data can be obtained by the two methods described in the second situation in the above embodiment, which will not be described in detail here.

[0164] In the embodiments of the present disclosure, Figure 5 As shown, the instruction execution unit 42 includes: an accumulator register 421 , a first calculation unit 442 and a second calculation unit 423 .

[0165] an accumulator register 421, configured to store the second address information;

[0166] A first calculation unit 422 is configured to perform accumulation calculation on the second address information and the accumulation step information to obtain the first address information;

[0167] The second computing unit 423 is configured to obtain the first access address and the first storage address sent by the first computing unit, and obtain the operand stored in the storage location corresponding to the first access address; and use the operand obtained from the memory corresponding to the first access address as the first memory access data to execute the first computing instruction, obtain the first computing result of the first computing instruction, and store the first computing result in the storage location corresponding to the first storage address.

[0168] In the embodiment of the present disclosure, when the instruction execution unit includes multiple second calculation units, an address accumulation unit may be set for each second calculation unit, and the address accumulation unit includes an accumulation register 421 and a first calculation unit 422. Further, the address accumulation unit may include multiple sub-accumulation units, and each sub-accumulation unit includes an accumulation register 421 and a first calculation unit 422. For example, each second calculation unit is used to calculate multiple operands to obtain calculation results. In this case, a sub-accumulation unit may be set corresponding to each operand and calculation result.

[0169] After the first calculation unit performs accumulation calculation on the second address information and the accumulation step information to obtain the first address information, the first calculation unit can send the first address information to the second calculation unit. The first address information includes a first access address and a first storage address.

[0170] After obtaining the first address information, the second calculation unit can obtain the operand stored in the storage location corresponding to the first access address. For example, the operand stored in the register corresponding to the first access address in the register stack of the instruction processing device is obtained, and the first calculation instruction is executed on the obtained operand to obtain the first calculation result of the first calculation instruction, and the first calculation result is stored in the register corresponding to the first storage address in the register stack.

[0171] In the above implementation, through the above processing method, the determination process of the first address information can be hidden in the instruction processing process of the first calculation instruction, thereby reducing additional instruction cycles and further speeding up the execution efficiency of the instruction.

[0172] In the embodiments of the present disclosure, Figure 5 As shown, the instruction processing unit 41 includes: an instruction reading unit 411, an instruction decoding unit 412 and an instruction issuing unit 413.

[0173] An instruction reading unit, configured to obtain a first computing instruction to be processed;

[0174] an instruction decoding unit, configured to determine a first enable flag in the first computing instruction, wherein the first enable flag is used to indicate whether an address accumulation mode for the first memory access data is enabled and valid; and determine an addressing mode of first address information of the first memory access data corresponding to the first computing instruction based on the first enable flag;

[0175] The instruction issuing unit is configured to realize data transmission between the instruction processing unit, the instruction execution unit and the register file.

[0176] In the embodiment of the present disclosure, after the instruction reading unit reads the first calculation instruction, the instruction decoding unit can obtain the value of the specified data bit in the first calculation instruction, and then determine the first enable flag according to the value of the specified data bit. After obtaining the first enable flag, it can be determined based on the first enable flag whether the address accumulation mode for the first memory access data is enabled.

[0177] When it is determined that the enable is valid, the addressing mode for the first address information of the first memory access data can be determined as the address accumulation mode; thereafter, the instruction issuing unit can transmit the accumulation step information to the instruction execution unit so that the instruction execution unit determines the first address information based on the second address information and the accumulation step information.

[0178] In the above implementation, by determining the first enable flag in the first computing instruction, and then determining the addressing mode of the first address information of the first memory access data according to the first enable flag, it is possible to hide the determination process of the first address information in the instruction processing process of the first computing instruction, thereby reducing additional instruction cycles and speeding up the execution efficiency of the instruction.

[0179] In an optional implementation, there are multiple first enable flags; each of the first enable flags corresponds to one data in the first memory access data.

[0180] In this case, the instruction decoding unit is configured to: determine a first enable identifier that matches each data in the first memory access data among the multiple first enable identifiers; and determine an addressing mode of the first address information of each data in the first computing instruction based on the first enable identifier that matches each data in the first memory access data.

[0181] It should be understood that the above-mentioned first enable flag may include multiple first sub-enable flags, each of which is used to indicate the addressing mode of the first address information of each data in the first memory access data. Here, each data in the first memory access data can be understood as each operand used to execute the first calculation instruction, and the calculation result of the operand.

[0182] That is to say, the addressing modes of each operand and the first address information of the calculation result of the operand may be the same or different, and the present disclosure does not make any specific limitation on this.

[0183] Here, for the operand, the first address information can be understood as the reading address of the operand (that is, the first access address mentioned below); for the calculation result of the operand, the first address information can be understood as the storage location of the calculation result (that is, the first storage address mentioned below).

[0184] In a first calculation instruction, the addressing modes of the first address information of each operand and the calculation result of the operand may not be completely the same. In this case, for each operation data and the calculation result of the operand, the first address information can be determined according to the corresponding addressing mode.

[0185] In the above implementation, by setting a corresponding first sub-enable flag for each data in the first memory access data (i.e., the operand and the calculation result of the operand), and controlling the first address information of each data according to the first sub-enable flag, the applicable scenarios of the technical solution can be expanded to meet the programming needs of programmers.

[0186] In an optional implementation, the instruction decoding unit 412 is configured to:

[0187] After determining that the first enable flag is enabled and valid, detecting the second enable flag in the second computing instruction; wherein the second enable flag is used to indicate whether the address accumulation mode indicated by the first enable flag in the first computing instruction is enabled and valid; and determining the first address information of the first memory access data corresponding to the first computing instruction based on the second enable flag.

[0188] It can be seen from the above embodiments that in the embodiments of the present disclosure, the above address accumulation mode is extended so that the extended address accumulation mode can support the loop program more concisely and efficiently. The specific extension method is:

[0189] A second enable flag is set in the previous instruction of the first calculation instruction (ie, the second calculation instruction), and the second enable flag is used to indicate whether the address accumulation mode indicated by the first enable flag in the next calculation instruction of the second calculation instruction (ie, the first calculation instruction) is enabled.

[0190] In a specific implementation, when the first enable flag in the first computing instruction indicates that the address accumulation mode enable for the first memory access data is valid, if the second enable flag in the second computing instruction is enable disable, it is determined that the address accumulation mode indicated by the first enable flag in the first computing instruction is enable disable. That is, even if the addressing mode is determined to be the address accumulation mode according to the first enable flag in the first computing instruction, if the second enable flag is enable disable, the addressing mode for the first memory access data in the first computing instruction can be the direct addressing mode, or the first address information is determined according to the second address information.

[0191] In an embodiment of the present disclosure, the instruction decoding unit is configured to: when it is determined that the second enable flag is enable disabled, determine that the first address information of the first memory access data corresponding to the first computing instruction is the second address information of the second memory access data corresponding to the second computing instruction.

[0192] When it is determined that the second enable flag is enable disabled, the second address information of the second memory access data corresponding to the second computing instruction may be determined as the first address information.

[0193] The following is an example of the loop program in the above embodiment. It can be seen from the above description that each layer of the loop program in the multiple loop program includes an initial instruction and a loop instruction. The initial instruction is used to give an initial address.

[0194] Assume that the second calculation instruction is an address initialization instruction in a loop program, and the first calculation instruction is the first loop instruction in the loop program. At this time, the second enable flag can be set in the second calculation instruction to enable or disable. At this time, for the first loop instruction, the second address information of the second memory access data corresponding to the second calculation instruction can be determined as the above-mentioned first address information. For example, the second address information in the address initialization instruction is determined as the first address information of the first calculation instruction.

[0195] In the disclosed embodiment, the programmer can set the second enable flag to enable or disable according to actual needs. Through this processing method, it is possible to avoid errors in the data address information of the first instruction in the loop instruction, so that accurate operands can be obtained. At the same time, through this processing method, the flexibility of the program written by the user can be improved, thereby meeting various programming needs of the programmer.

[0196] In the embodiment of the present disclosure, the second enable flag includes a plurality of second sub-enable flags, and each second sub-enable flag corresponds to one of the first memory access data.

[0197] In this case, the instruction decoding unit is configured to: determine a second sub-enable identifier that matches each data in the first memory access data from the multiple second sub-enable identifiers; and determine the first address information of each data in the first memory access data based on the second sub-enable identifier that matches each data in the first memory access data.

[0198] In the embodiment of the present disclosure, the second enable flag may include multiple second sub-enable flags, each second sub-enable flag corresponding to one of the first memory access data. Here, each of the first memory access data can be understood as each operand used to execute the first calculation instruction, and the calculation result of the operand.

[0199] In the embodiment of the present disclosure, a second sub-enable identifier matching each data in the first memory access data may be determined from multiple second sub-enable identifiers, and then first address information of the corresponding data may be determined according to the identifier value of the matched second sub-enable identifier.

[0200] In the above implementation, by setting a corresponding second sub-enable flag for each data in the first memory access data, and controlling whether the first address information address accumulation mode of each data is enabled according to the second sub-enable flag, the applicable scenarios of the technical solution can be further expanded to meet the programming needs of programmers.

[0201] In an embodiment of the present disclosure, the instruction content of the first calculation instruction includes: at least one first data bit and / or at least one second data bit, wherein each of the first data bits includes: a first enable flag and a first flag content, and each of the second data bits includes: a second enable flag and a second flag content, the first enable flag is used to indicate the addressing mode of the first calculation instruction, the first flag content is used to indicate the cumulative step information or the first address information, the second enable flag is used to indicate the addressing mode of the next calculation instruction of the first calculation instruction, and the second flag content is used to indicate the cumulative step information or the first address information corresponding to the execution of the next calculation instruction.

[0202] For example, the first calculation instruction is: opinit(addr1 / dlt1=a, addr2 / dlt2=b, addr3 / dlt3=c, nxt_dlt0_on, nxt_dlt1_on, nxt_dlt2_off).

[0203] Wherein, addr1 / dlt1=a, addr2 / dlt2=b, addr3 / dlt3=c are the at least one first data bit, addr / dlt is the first enable flag, a, b and c are the first flag content of the first enable flag. nxt_dlt0_on, nxt_dlt1_on, nxt_dlt2_off are the at least one second data bit, nxt_dlt0, nxt_dlt1 and nxt_dlt2 are the second enable flags, on or off is the second flag content of the second enable flag.

[0204] In the embodiments of the present disclosure, Figure 6 As shown, the instruction processing device further includes: a register stack 61; wherein the register stack is used to store at least one of the following: the accumulation step information, the first memory access data and the first address information.

[0205] In this case, the instruction decoding unit is configured to: decode the instruction content of the first calculation instruction to obtain a decoding result; the instruction issuing unit is configured to: send an instruction to the register stack to obtain the accumulation step information based on the decoding result; the instruction execution unit is configured to: determine the first address information of the first memory access data in the register stack based on the second address information and the accumulation step information.

[0206] The following will be combined Figure 7 The above instruction processing method is introduced, such as Figure 7As shown, the instruction processing device includes: an instruction processing unit, an instruction execution unit and a register stack; wherein the instruction execution unit includes: an address accumulation unit A and a second calculation unit A, an address accumulation unit B and a second calculation unit B, an address accumulation unit C and a second calculation unit C. wherein each of the address accumulation unit A, the address accumulation unit B and the address accumulation unit C includes: an accumulation register and a first calculation unit.

[0207] On this basis, the instruction processing method can be described as the following process:

[0208] Based on the idea of ​​the above-mentioned accumulation instruction, it can be applied to the design of the instruction processing device. The instruction processing device path is simply divided into three parts: the instruction processing unit, the instruction execution unit and the register stack. Among them, the instruction processing unit is responsible for reading, decoding and transmitting instructions, and the instruction execution unit includes arithmetic, memory access, etc.

[0209] The compute units in the execution unit support the following instructions:

[0210] opinit(addr1 / dlt1, addr1 / dlt1, addr2 / dlt2, nxt_dlt_on[2:0]);

[0211] opcal(addr1 / dlt1, addr1 / dlt1, addr1 / dlt1, nxt_dlt_on[2:0]).

[0212] The address parsing process when the instruction processing device executes the above instruction is as follows: Figure 7 As shown:

[0213] 1) The instruction reading unit reads the first calculation instruction, and the instruction decoding unit decodes the first calculation instruction and parses out the addressing mode (direct addressing ADR mode / address accumulation DLT mode), as well as whether DLT is enabled in the next DLT mode (nxt_dlt_on / nxt_dlt_off);

[0214] 2) The instruction issuing unit establishes a communication link with the register file to retrieve the value of addr / dlt from the register file or instruction encoding through the communication link;

[0215] 3) For addr mode, the instruction execution unit directly uses the value of addr to read the register file.

[0216] For the DLT mode, the last access address (i.e., the second address information corresponding to the second calculation instruction) is maintained in the accumulator register. Afterwards, the first calculation unit calculates the accumulation result and sends it to the second calculation unit of the instruction execution unit as the first address information. The second calculation unit of the instruction execution unit uses the first address information to access the register stack.

[0217] In an optional embodiment, the register file includes a vector register file and a scalar register file, the vector register file is used to store the first memory access data of the first computing instruction, and the scalar register file is used to store the accumulation step information and / or the first address information.

[0218] In this case, the following will be combined Figure 8 The above instruction processing method is introduced, such as Figure 8 As shown, the instruction processing device includes: an instruction processing unit, an instruction execution unit, a scalar register file and a vector register file; wherein the instruction execution unit includes: an address accumulation unit A and a second calculation unit A, an address accumulation unit B and a second calculation unit B, an address accumulation unit C and a second calculation unit C. wherein each of the address accumulation unit A, the address accumulation unit B and the address accumulation unit C includes: an accumulation register and a first calculation unit.

[0219] On this basis, the instruction processing method can be described as the following process:

[0220] Based on the idea of ​​the above-mentioned accumulation instruction, it can be applied to the design of the instruction processing device. The instruction processing device path is simply divided into three parts: the instruction processing unit, the instruction execution unit and the register stack. Among them, the instruction processing unit is responsible for reading, decoding and transmitting instructions, and the instruction execution unit includes arithmetic, memory access, etc.

[0221] The technical solution provided by the embodiments of the present disclosure can be extended to an instruction processing device including a parallel computing unit, such as a CPU (Central Processing Unit) or GPU (Graphics Processing Unit) including a SIMD (Single Instruction Multiple Data) unit. The main idea is that the instruction processing device includes two independent register files, wherein the scalar register file is mainly used to store simple scalar data or control information, and the vector register file is used to store SIMD / SIMT (Single Instruction Multiple Threads) data for parallel computing.

[0222] Here, the vector register file is used to store the first memory access data of the first computing instruction, and the scalar register file is used to store the accumulation step information and / or the first address information.

[0223] The address parsing process when the instruction processing device executes the above instruction is as follows: Figure 8 As shown:

[0224] 1) The instruction reading unit reads the first calculation instruction, and the instruction decoding unit decodes the first calculation instruction and parses out the addressing mode (direct addressing ADR mode / address accumulation DLT mode), as well as whether DLT is enabled in the next DLT mode (nxt_dlt_on / nxt_dlt_off);

[0225] 2) The instruction issuing unit establishes a communication link with the register file to retrieve the value of addr / dlt from the register file or instruction encoding through the communication link;

[0226] 3) For addr mode, the instruction execution unit directly uses the value of addr to read the vector register file.

[0227] For the dlt mode, the last access address (i.e., the second address information corresponding to the second calculation instruction) is maintained in the accumulator register. After that, the first calculation unit calculates the accumulation result and sends it to the second calculation unit of the instruction execution unit as the first address information. The second calculation unit of the instruction execution unit uses the address to access the vector register stack.

[0228] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0229] Based on the same inventive concept, an instruction processing device corresponding to the instruction processing method is also provided in the embodiment of the present disclosure. Since the principle of solving the problem by the device in the embodiment of the present disclosure is similar to the above-mentioned instruction processing method in the embodiment of the present disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0230] Reference Fig. 9 FIG. 1 is a schematic diagram of an instruction processing device provided by an embodiment of the present disclosure, wherein the device comprises: a first acquisition unit 91, a determination unit 92, a second acquisition unit 93 and an instruction execution unit 94; wherein:

[0231] A first acquisition unit 91, used to acquire a first computing instruction to be processed;

[0232] A determining unit 92, configured to determine an addressing mode of first address information of first memory access data corresponding to the first computing instruction; the first memory access data includes an operand and / or a calculation result of the operand used to execute the first computing instruction;

[0233] A second acquisition unit 93 is used to acquire accumulation step information based on the first calculation instruction and acquire second address information of second memory access data corresponding to the second calculation instruction when the addressing mode is the address accumulation mode; the second calculation instruction is the previous instruction of the first calculation instruction;

[0234] The instruction execution unit 94 is used to determine the first address information based on the second address information and the accumulation step information, and execute the first calculation instruction based on the first address information.

[0235] In one possible implementation, the instruction execution unit is further used to: when the first address information includes: a first access address and a first storage address, obtain the operand stored in the storage location corresponding to the first access address; use the operand obtained from the memory corresponding to the first access address as the first memory access data to execute the first calculation instruction, obtain the first calculation result of the first calculation instruction, and store the first calculation result to the storage location corresponding to the first storage address.

[0236] In a possible implementation, the device is further used to: when the addressing mode is a direct addressing mode, obtain the field content in the address field in the first calculation instruction; and determine the first address information of the first memory access data based on the obtained field content.

[0237] In one possible implementation, the determination unit is further used to: determine a first enable flag in the first computing instruction, wherein the first enable flag is used to indicate whether an address accumulation mode for the first memory access data is enabled; and determine an addressing mode of the first address information of the first memory access data corresponding to the first computing instruction based on the first enable flag.

[0238] In one possible implementation, the determination unit is further used to: when the first enable identifier includes multiple first sub-enable identifiers; when each of the first sub-enable identifiers corresponds to one data in the first memory access data, determine the first sub-enable identifier that matches each data in the first memory access data from the multiple first sub-enable identifiers; and based on the first sub-enable identifier that matches each data in the first memory access data, determine the addressing mode of the first address information of each data in the first computing instruction.

[0239] In a possible implementation, the device is also used to: after determining that the first enable flag is enabled and valid, detect a second enable flag in the second computing instruction; wherein the second enable flag is used to indicate whether the address accumulation mode indicated by the first enable flag in the first computing instruction is enabled and valid; and determine the first address information of the first memory access data corresponding to the first computing instruction based on the second enable flag.

[0240] In a possible implementation, the device is further used to: when it is determined that the second enable flag is enable disabled, determine that the first address information of the first memory access data corresponding to the first computing instruction is the second address information of the second memory access data corresponding to the second computing instruction.

[0241] In a possible implementation, the device is also used to: when the second enable identifier includes multiple second sub-enable identifiers, each second sub-enable identifier corresponds to one data in the first access data, determine the second sub-enable identifier that matches each data in the first access data from the multiple second sub-enable identifiers; and determine the first address information of each data in the first access data based on the second sub-enable identifier that matches each data in the first access data.

[0242] In one possible implementation, when the instruction processing device includes a register stack, and the register stack is used to store the accumulation step information and the first memory access data, the second acquisition unit is further used to: acquire the accumulation step information in the register stack based on the instruction content of the first calculation instruction; the instruction execution unit is further used to: determine the first address information of the first memory access data in the register stack based on the second address information and the accumulation step information.

[0243] In a possible implementation, the register file includes a vector register file and a scalar register file, the vector register file is used to store the first memory access data of the first computing instruction, and the scalar register file is used to store the accumulation step information.

[0244] In a possible implementation manner, the instruction processing device provided by the present disclosure may also be implemented as a processor, which will not be described in detail here.

[0245] For descriptions of the processing flow of each module in the device and the interaction flow between each module, reference may be made to the relevant descriptions in the above method embodiment, which will not be described in detail here.

[0246] Corresponds to Figure 1 The embodiment of the present disclosure also provides an electronic device 1000, such as Fig.10 FIG. 1 is a schematic diagram of the structure of an electronic device 1000 provided in an embodiment of the present disclosure, including:

[0247] Processor 101, memory 102, and bus 103; memory 102 is used to store execution instructions, including internal memory 1021 and external memory 1022; the internal memory 1021 is also called internal memory, which is used to temporarily store the operation data in the processor 101 and the data exchanged with the external memory 1022 such as a hard disk. The processor 101 exchanges data with the external memory 1022 through the internal memory 1021. When the electronic device 1000 is running, the processor 101 communicates with the memory 102 through the bus 103, so that the processor 101 executes the following instructions:

[0248] Obtain a first calculation instruction to be processed; determine the addressing mode of the first address information of the first memory access data corresponding to the first calculation instruction; the first memory access data includes an operand and / or a calculation result of the operand used to execute the first calculation instruction; when the addressing mode is an address accumulation mode, obtain the accumulation step information based on the first calculation instruction, and obtain the second address information of the second memory access data corresponding to the second calculation instruction; the second calculation instruction is the previous instruction of the first calculation instruction; based on the second address information and the accumulation step information, determine the first address information, and execute the first calculation instruction based on the first address information.

[0249] The present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the instruction processing method described in the above method embodiment are executed. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0250] The present disclosure also provides a computer program product that carries a program code. The program code includes instructions that can be used to execute the steps of the instruction processing method described in the above method embodiment. For details, please refer to the above method embodiment, which will not be repeated here.

[0251] The present disclosure also provides a chip, which includes the instruction processing device described in any one of the above embodiments. For details, please refer to the above device embodiments, which will not be described again.

[0252] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is implemented as a computer storage medium. In another optional embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0253] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0254] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0255] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0256] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling an electronic device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0257] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An instruction processing device, characterized in that: include: Instruction processing unit and instruction execution unit; The instruction processing unit is configured to obtain a first computing instruction to be processed, and determine an addressing mode of first address information of first memory access data corresponding to the first computing instruction; When the addressing mode is a direct addressing mode, obtaining a field content in an address field in the first computing instruction; determining first address information of the first memory access data based on the obtained field content, and sending the first address information to the instruction execution unit, so that the instruction execution unit executes the first computing instruction based on the first address information; The instruction execution unit is configured to, when the addressing mode is an address accumulation mode, obtain accumulation step information based on the first calculation instruction, and obtain second address information of the second memory access data corresponding to the second calculation instruction; The second calculation instruction is a previous instruction of the first calculation instruction; Determine, based on the second address information and the accumulation step information, first address information of the first memory access data corresponding to the first computing instruction, and execute the operand and / or the calculation result of the operand of the first computing instruction based on the first address information; Among them, the instruction content of the first calculation instruction includes: at least one first data bit and / or at least one second data bit, wherein each of the first data bits includes: a first enable flag and a first flag content, and each of the second data bits includes: a second enable flag and a second flag content, the first enable flag is used to indicate the addressing mode of the first calculation instruction, the first flag content is used to indicate the cumulative step information or the first address information, the second enable flag is used to indicate the addressing mode of the next calculation instruction of the first calculation instruction, and the second flag content is used to indicate the cumulative step information or the first address information corresponding to the execution of the next calculation instruction.

2. The instruction processing device according to claim 1, characterized in that: The instruction execution unit includes: an accumulator register and a first calculation unit; The accumulator register is configured to store the second address information; The first calculation unit is configured to, after acquiring the accumulation step information sent by the instruction processing unit, perform accumulation calculation on the second address information and the accumulation step information to obtain the first address information.

3. The instruction processing device according to claim 2, characterized in that: The first address information includes: a first access address and a first storage address; the instruction execution unit includes: a second calculation unit: The second computing unit is configured to obtain the first access address and the first storage address sent by the first computing unit, and obtain the operand stored in the storage location corresponding to the first access address; and use the operand obtained from the memory corresponding to the first access address as the first memory access data to execute the first computing instruction, obtain the first computing result of the first computing instruction, and store the first computing result in the storage location corresponding to the first storage address.

4. The instruction processing device according to any one of claims 1 to 3, characterized in that: The instruction processing unit includes: an instruction decoding unit; The instruction decoding unit is configured to determine a first enable flag in the first computing instruction, wherein the first enable flag is used to indicate whether an address accumulation mode for the first memory access data is enabled; and determine an addressing mode of the first address information of the first memory access data corresponding to the first computing instruction based on the first enable flag.

5. The instruction processing device according to claim 4, characterized in that: There are multiple first enabling identifiers; each of the first enabling identifiers corresponds to one data in the first memory access data; The instruction decoding unit is configured to: determine a first enabling identifier that matches each data in the first memory access data from among the plurality of first enabling identifiers; And based on a first enable flag matching each data in the first memory access data, an addressing mode of first address information of each data in the first computing instruction is determined.

6. The instruction processing device according to claim 4, characterized in that: The instruction decoding unit is configured to: After determining that the first enable flag is enabled and valid, detecting a second enable flag in the second calculation instruction; wherein the second enable flag is used to indicate whether the address accumulation mode indicated by the first enable flag in the first calculation instruction is enabled and valid; and First address information of first memory access data corresponding to the first computing instruction is determined based on the second enable flag.

7. The instruction processing device according to claim 6, characterized in that: The instruction decoding unit is configured to: When it is determined that the second enable flag is enable disabled, the first address information of the first memory access data corresponding to the first computing instruction is determined to be the second address information of the second memory access data corresponding to the second computing instruction.

8. The instruction processing device according to claim 6, characterized in that: The second enable flag includes a plurality of second sub-enable flags, each second sub-enable flag corresponding to one data in the first memory access data; The instruction decoding unit is configured to: determine a second sub-enable identifier that matches each data in the first memory access data from among the plurality of second sub-enable identifiers; as well as Based on the second sub-enable identifier that matches each data in the first memory access data, first address information of each data in the first memory access data is determined.

9. The instruction processing device according to any one of claims 1 to 3, characterized in that: The instruction processing device further includes: a register file; wherein the register file is used to store at least one of the following: the accumulation step information, the first memory access data and the first address information.

10. The instruction processing device according to claim 9, characterized in that: The instruction execution unit includes an instruction decoding unit and an instruction issuing unit; The instruction decoding unit is configured to: decode the instruction content of the first computing instruction to obtain a decoding result; The instruction issuing unit is configured to: send an instruction to obtain the accumulation step information to the register file based on the decoding result; The instruction execution unit is configured to determine the first address information of the first memory access data in the register file based on the second address information and the accumulation step information.

11. The instruction processing device according to claim 9, characterized in that: The register file includes a vector register file and a scalar register file, the vector register file is used to store the first memory access data of the first computing instruction, and the scalar register file is used to store the accumulation step information and / or the first address information.

12. A method for processing an instruction, characterized in that: include: Obtain a first computing instruction to be processed; wherein the instruction content of the first computing instruction includes: at least one first data bit and / or at least one second data bit, wherein each of the first data bits includes: a first enable flag and a first flag content, and each of the second data bits includes: a second enable flag and a second flag content, the first enable flag is used to indicate an addressing mode of the first computing instruction, the first flag content is used to indicate cumulative step information or first address information, the second enable flag is used to indicate an addressing mode of a next computing instruction of the first computing instruction, and the second flag content is used to indicate the cumulative step information or first address information corresponding to executing the next computing instruction; Determining an addressing mode of first address information of first memory access data corresponding to the first computing instruction; the first memory access data includes an operand and / or a calculation result of the operand used to execute the first computing instruction; In the case where the addressing mode is the address accumulation mode, the accumulation step information is obtained based on the first calculation instruction, and the second address information of the second memory access data corresponding to the second calculation instruction is obtained; the second calculation instruction is the previous instruction of the first calculation instruction; Determine the first address information based on the second address information and the accumulation step information, and execute the first calculation instruction based on the first address information; When the addressing mode is a direct addressing mode, the field content in the address field in the first calculation instruction is obtained; the first address information of the first memory access data is determined based on the obtained field content, and the first address information is sent to the instruction execution unit, so that the instruction execution unit executes the first calculation instruction based on the first address information.

13. A chip, characterized in that: An instruction processing device comprising any one of claims 1 to 11.

14. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the instruction processing method according to claim 12 are performed; or The chip as claimed in claim 13.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which, when executed by a processor, executes the steps of the instruction processing method as claimed in claim 12.

Images