Memory, storage system, and pre-charge method

Abstract

The embodiment of the application discloses a memory, a storage system and a pre-charging method, and belongs to the technical field of storage. The pre-charging method comprises the following steps: a pre-charging voltage is applied to a source line connection end; a voltage is applied to the gate of each memory cell in a memory cell stack; wherein the voltage applied to the gate of a programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of an unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell. By using the method, in the case that there is a programmed memory cell in the memory cell stack, the electrons in the doped region and the electrons in the channel of the memory cell coupled with the selected word line can be fully attracted to the source line connection end, so that the non-selected memory string can be fully pre-charged, and the programming interference on the memory cell coupled with the selected word line in the memory cell stack is reduced.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory, storage system and pre-charging method. Background Technology

[0002] Memory typically includes multiple memory strings. In some embodiments, each memory string includes a select transistor stack and a memory cell stack between its bit line connection and source line connection. The select transistor stack and the memory cell stack are connected by doped regions.

[0003] The related technology precharges the non-selected memory strings among the above multiple memory strings by applying a precharge voltage to the source line connection terminal of the non-selected memory string and applying a 0V voltage to the gate of each memory cell in the memory cell stack.

[0004] When precharging using the above method, if there are already programmed memory cells in the memory cell stack, it will lead to insufficient precharging, causing the memory cells coupled to the selected word line in the memory cell stack to be subject to strong programming interference. Summary of the Invention

[0005] This application provides a memory, a storage system, and a pre-charging method, which can be used to achieve a relatively sufficient pre-charging of non-selected memory strings. The technical solution is as follows:

[0006] On one hand, embodiments of this application provide a memory, the memory including a memory array and peripheral circuitry communicatively connected to the memory array;

[0007] The memory array includes a non-selected memory string, and between the bit line connection terminal and the source line connection terminal of the non-selected memory string, there is a select transistor stack and a memory cell stack. The select transistor stack and the memory cell stack are connected through a doped region. The memory cell stack includes programmed memory cells and unprogrammed memory cells.

[0008] The peripheral circuitry is configured to apply a pre-charge voltage to the source line connection terminal; apply a voltage to the gate of each memory cell in the memory cell stack; wherein the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell.

[0009] In one possible implementation, the peripheral circuitry is configured to apply a first voltage to both the gate of the programmed memory cell and the gate of the unprogrammed memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell.

[0010] In one possible implementation, the peripheral circuitry is configured to apply a first voltage to the gate of the programmed memory cell and a second voltage to the gate of the unprogrammed memory cell, wherein the first voltage is greater than a threshold voltage of the programmed memory cell and the second voltage is greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage.

[0011] In one possible implementation, the cutoff time for applying a first voltage to the gate of the programmed memory cell is earlier than the cutoff time for applying a pre-charge voltage to the source line connection.

[0012] In one possible implementation, the number of programmed memory cells is multiple; the cutoff time for applying a first voltage to the gate of a programmed memory cell far from the source line connection is no later than the cutoff time for applying a first voltage to the gate of a programmed memory cell close to the source line connection.

[0013] On the other hand, a storage system is provided, the storage system including a memory and a controller coupled to the memory, the controller being configured to control the memory;

[0014] The memory includes a memory array and peripheral circuitry communicatively connected to the memory array.

[0015] The memory array includes a non-selected memory string, and between the bit line connection terminal and the source line connection terminal of the non-selected memory string, there is a select transistor stack and a memory cell stack. The select transistor stack and the memory cell stack are connected through a doped region. The memory cell stack includes programmed memory cells and unprogrammed memory cells.

[0016] The peripheral circuitry is configured to apply a pre-charge voltage to the source line connection terminal; apply a voltage to the gate of each memory cell in the memory cell stack; wherein the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell.

[0017] In one possible implementation, the peripheral circuitry is configured to apply a first voltage to both the gate of the programmed memory cell and the gate of the unprogrammed memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell.

[0018] In one possible implementation, the peripheral circuitry is configured to apply a first voltage to the gate of the programmed memory cell and a second voltage to the gate of the unprogrammed memory cell, wherein the first voltage is greater than a threshold voltage of the programmed memory cell and the second voltage is greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage.

[0019] In one possible implementation, the cutoff time for applying a first voltage to the gate of the programmed memory cell is earlier than the cutoff time for applying a pre-charge voltage to the source line connection.

[0020] In one possible implementation, the number of programmed memory cells is multiple; the cutoff time for applying a first voltage to the gate of a programmed memory cell far from the source line connection is no later than the cutoff time for applying a first voltage to the gate of a programmed memory cell close to the source line connection.

[0021] On the other hand, a pre-charging method is provided for pre-charging a non-selected memory string, wherein a select transistor stack and a memory cell stack are included between the bit line connection terminal and the source line connection terminal of the non-selected memory string, the select transistor stack and the memory cell stack are connected through a doped region, and the memory cell stack includes programmed memory cells and unprogrammed memory cells; the method includes:

[0022] A pre-charge voltage is applied to the source line connection terminal;

[0023] A voltage is applied to the gate of each memory cell in the memory cell stack;

[0024] Wherein, the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell.

[0025] In one possible implementation, applying a voltage to the gate of each memory cell in the memory cell stack includes:

[0026] A first voltage is applied to the gate of both the programmed memory cell and the gate of the unprogrammed memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell.

[0027] In one possible implementation, applying a voltage to the gate of each memory cell in the memory cell stack includes:

[0028] A first voltage is applied to the gate of the programmed memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell;

[0029] A second voltage is applied to the gate of the unprogrammed memory cell, the second voltage being greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage.

[0030] In one possible implementation, the cutoff time for applying a first voltage to the gate of the programmed memory cell is earlier than the cutoff time for applying a pre-charge voltage to the source line connection.

[0031] In one possible implementation, the number of programmed memory cells is multiple; the cutoff time for applying a first voltage to the gate of a programmed memory cell far from the source line connection is no later than the cutoff time for applying a first voltage to the gate of a programmed memory cell close to the source line connection.

[0032] The technical solution provided in this application has at least the following beneficial effects:

[0033] The technical solution provided in this application, based on applying a pre-charge voltage to the source line connection terminal, applies a voltage greater than its respective threshold voltage to the gates of both programmed and unprogrammed memory cells in the memory cell stack. This method ensures that the channels of all memory cells in the stack are conducting, even when programmed memory cells exist. This allows electrons in the doped region and in the channels of memory cells coupled to the selected word line to be sufficiently attracted to the source line connection terminal, thereby achieving a more thorough pre-charge of the unselected memory string. This helps reduce programming interference experienced by memory cells coupled to the selected word line in the memory cell stack. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the structure of a system provided in an embodiment of this application;

[0036] Figure 2 This is a schematic diagram of the structure of a memory card provided in an embodiment of this application;

[0037] Figure 3 This is a schematic diagram of the structure of a solid-state driver provided in an embodiment of this application;

[0038] Figure 4 This is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0039] Figure 5 This is a cross-sectional schematic diagram of a storage string provided in an embodiment of this application;

[0040] Figure 6This is a flowchart of a pre-charging method provided in an embodiment of this application;

[0041] Figure 7 This is a schematic diagram illustrating a voltage application scenario provided in an embodiment of this application;

[0042] Figure 8 This is a flowchart of a pre-charging method provided in an embodiment of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0044] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0045] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “above something” but also includes “above something” or “on top of something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0046] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and (one or more) another element or feature as shown in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0047] Figure 1This is a schematic diagram of the structure of a system provided in an embodiment of this application. The system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0048] like Figure 1 As shown, system 100 includes host 101 and storage system 102, and storage system 102 includes one or more memory 103 and controller 104.

[0049] Host 101 can be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). Host 101 can be configured to send data to memory 103. Alternatively, host 101 can be configured to receive data from memory 103.

[0050] The memory 103 can be any memory involved in the embodiments of this application. Optionally, the memory 103 is a flash memory, such as a three-dimensional not AND (3D NAND) flash memory.

[0051] In some embodiments, controller 104 is coupled to memory 103 and host 101 and is configured to control memory 103. Controller 104 can manage data stored in memory 103 and communicate with host 101.

[0052] In some embodiments, the controller 104 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0053] In some embodiments, the controller 104 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multi-media cards (eMMCs). SSDs or eMMCs are used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as for enterprise storage arrays.

[0054] Controller 104 can be configured to control the operation of memory 103, such as read, erase, and program operations. Controller 104 can also be configured to manage various functions related to data stored or to be stored in memory 103, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 104 is also configured to process error correction codes (ECCs) regarding data read from or written to memory 103. Controller 104 can also perform any other suitable functions, such as formatting memory 103.

[0055] Controller 104 can communicate with external devices (e.g., host 101) according to a specific communication protocol. For example, controller 104 can communicate with external devices through at least one of various interface protocols, including but not limited to USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Drive Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0056] The controller 104 and one or more memories 103 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 102 can be implemented and packaged into different types of end electronic products.

[0057] like Figure 2 As shown, controller 104 and a single memory 103 can be integrated into memory card 200. Memory card 200 may include PC (Personal Computer Memory Card International Association, PCMCIA, abbreviated as PC) cards, CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC (Reduced-Size MMC), MMCmicro (Micro Multimedia Card)), SD cards (SD, miniSD (Small Secure Digital Storage Card), microSD (Micro Secure Digital Storage Card), SDHC (Secure Digital High Capacity)), UFS, etc. Memory card 200 may also include components that connect memory card 200 to a host computer (e.g., Figure 1 The memory card connector 201 is coupled to the host 101.

[0058] like Figure 3 As shown, controller 104 and multiple memories 103 can be integrated into solid-state drive 300. Solid-state drive 300 may also include a connection between solid-state drive 300 and a host (e.g., Figure 1 The solid-state drive connector 301 is coupled to the host 101. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 300 is greater than the storage capacity and / or operating speed of the memory card 200.

[0059] Figure 4 A schematic diagram of the structure of a memory provided in an embodiment of this application is shown. Figure 4 As shown, the memory 103 includes a memory array 410 and peripheral circuitry 420 that is communicatively connected to the memory array 410.

[0060] The memory array 410 includes a plurality of memory strings 411 arranged in an array. The plurality of memory strings 411 are located on the bearing side of a substrate (not shown) and extend in a direction perpendicular to the bearing surface of the substrate. Exemplarily, the bearing surface of the substrate refers to the surface of the substrate used to bear the memory array 410.

[0061] Each memory string 411 includes a plurality of memory cells 412, which are stacked in a direction perpendicular to the substrate bearing surface. Each memory cell 412 has the function of storing data, and the stored data is determined by the number of electrons stored in the memory cell 412. The number of electrons stored in the memory cell 412 determines the magnitude of the threshold voltage of the memory cell 412. Therefore, the threshold voltage of the memory cell 412 can indicate the data stored in the memory cell 412. Exemplarily, the memory cell 412 is a floating gate field-effect transistor or a charge trap field-effect transistor.

[0062] For example, the storage unit 412 can be a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC), etc. SLC, MLC, TLC, and QLC can store 1, 2, 3, and 4 bits of data, respectively.

[0063] Each memory string 411 also includes a Top Select Gate (TSG) 413 and a Bottom Select Gate (BSG) 414. The Top Select Gates 413 in different memory strings 411, at the same or similar height from the substrate support surface, are coupled to the same Drain Select Line (DSL) 430. The Bottom Select Gates 414 in different memory strings 411, at the same or similar height from the substrate support surface, are coupled to the same Source Select Line (SSL) 440. The Top Select Gates 413 and 414 are used to activate the selected memory string during erase or programming operations. In some embodiments, the Top Select Gate 413 is also referred to as the Top Select Gate or Drain Select Gate, and the Bottom Select Gate 414 is also referred to as the Bottom Select Gate or Source Select Gate. In some embodiments, dummy cells (DCs) are also present between the Top Select Gate 413 and the memory cell 412, and between the Bottom Select Gate 414 and the memory cell 412.

[0064] One end of each memory string 411 is coupled to a bit line (BL) 450, and the other end of each memory string 411 is coupled to a source line (SL) 460. For example, the end coupled to the bit line 450 is referred to as the bit line connection end, and the end coupled to the source line 460 is referred to as the source line connection end.

[0065] In different memory strings 411, memory cells 412 at the same or similar height from the substrate bearing surface are located on the same layer. Multiple memory cells 412 on the same layer form a memory cell row 41a, that is, the memory array 410 includes multiple memory cell rows, and the multiple memory cell rows are coupled to multiple word lines (WL) 470. By applying a voltage (V) to the word line 470 coupled to a memory cell row... WL It can control each storage cell in the row of storage cells.

[0066] All memory strings 411 in memory array 410 that share the same set of word lines 470 form a memory block 41b. For example, the source connection terminals of each memory string 411 in the same memory block 41b are coupled to the same source line 460, which is also called a common source line (CSL).

[0067] Peripheral circuitry 420 can be coupled to memory array 410 via drain select line 430, source select line 440, bit line 450, source line 460, and word line 470. Peripheral circuitry 420 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 410 by applying voltage and / or current signals to memory cells 412 via drain select line 430, source select line 440, bit line 450, source line 460, and word line 470, and by sensing voltage and / or current signals from memory cells 412.

[0068] The peripheral circuit 420 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. The peripheral circuit 420 is capable of performing operations such as erasing, programming, reading, or verifying on the memory strings 411 in the memory array 410. In some embodiments, the memory array 410 includes non-selected memory strings, and the peripheral circuit 420 is capable of pre-charging the non-selected memory strings in the memory array 410 according to the pre-charging method provided in the embodiments of this application.

[0069] Figure 5 A cross-sectional schematic diagram of a storage string provided in an embodiment of this application is shown. For example... Figure 5As shown, the memory string 411 is located on the carrier side of the substrate 510. Between the bit line connection terminal and the source line connection terminal of the memory string 411, there is a select transistor stack 530 and a memory cell stack 520, which are connected through a doped region 540. The memory cell stack 520 and the select transistor stack 530 are stacked in a direction perpendicular to the substrate carrier surface, with the select transistor stack 530 located on the side of the memory cell stack 520 away from the substrate carrier surface. Exemplarily, the memory cell stack 520 is composed of the memory cells of the memory string 411 and BSGs, and the select transistor stack 530 is composed of the TSGs of the memory string 411.

[0070] The substrate 510 can be made of silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0071] The memory cell stack 520 may include alternating conductive layers 521 and dielectric layers 522. The conductive layers 521 are made of conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. The conductive layers 521 may extend laterally to form SSL 440 or word lines 470.

[0072] like Figure 5 As shown, the memory cell stack 520 includes a channel structure extending vertically through a conductive layer 521 and a dielectric layer 522. The channel structure of the memory cell stack 520 includes a channel 523, a tunneling layer 524, a storage layer 525, and a barrier layer 526. The tunneling layer 524, storage layer 525, and barrier layer 526 may be referred to as functional layers. In some embodiments, the channel 523 may be made of silicon, for example, polycrystalline silicon. The tunneling layer 524 may be made of silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 525 may be made of silicon nitride, silicon oxynitride, or any combination thereof; exemplaryly, the storage layer 525 may be a floating gate or a charge trapping layer. The barrier layer 526 may be made of silicon oxide, silicon oxynitride, a high-dielectric-constant dielectric, or any combination thereof. In some embodiments, the channel structure of the storage cell stack 520 may have a column shape (e.g., cylinder, prism, frustum, etc.), with the channel 523, tunneling layer 524, storage layer 525 and barrier layer 526 arranged radially from the center of the column toward the outer surface of the column in this order.

[0073] The selector stack 530 may include alternating conductive layers 531 and dielectric layers 532. The conductive layer 531 is made of a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. The conductive layer 531 may extend laterally to form a DSL 430.

[0074] like Figure 5 As shown, the selector stack 530 includes a channel structure extending vertically through the conductive layer 531 and the dielectric layer 532. The channel structure of the selector stack 530 includes a channel 533 and an insulating layer 534. In some embodiments, the channel 533 may be made of silicon, for example, polycrystalline silicon. The insulating layer 534 may be made of silicon oxide. In some embodiments, the channel structure of the selector stack 530 may have a columnar shape (e.g., a cylinder, prism, frustum, etc.), with the channel 533 and the insulating layer 534 arranged radially from the center of the column toward the outer surface of the column in this order.

[0075] like Figure 5 As shown, the channel structure size of the selector stack 530 is smaller than that of the memory cell stack 520. This structure can reduce the space occupied by the channel structure of the selector stack 530, thereby providing a larger process window for forming the top select gate cutout structure, which is beneficial to improving the unit storage density of the memory.

[0076] The transistor stack 530 and the memory cell stack 520 are connected via a doped region 540, which is formed by doping a semiconductor material with impurities. For example, the material of the doped region 540 is a heavily N-type doped material to enhance its conductivity. Heavy doping refers to the situation where the concentration of impurities incorporated into the semiconductor material exceeds a concentration threshold. This concentration threshold is set empirically or can be flexibly adjusted according to the application scenario; for example, a concentration threshold of 10-1 per cubic centimeter. 18 Each atom. Doped region 540 is used to ensure a tight connection between the selector stack 530 and the memory cell stack 520.

[0077] It should be understood that, despite Figure 5 Although not shown in the diagram, the storage string 411 may also include other additional components, including but not limited to gate line gaps, source contacts, local contacts, interconnect layers, etc.

[0078] The pre-charging method provided in this application is used to pre-charge a non-selected memory string before programming a selected memory cell. When programming a selected memory cell, a programming voltage needs to be applied to the selected word line to cause electrons in the channel of the selected memory cell to tunnel to the floating gate or charge trapping layer. However, this programming voltage may cause electron tunneling in memory cells in the non-selected memory string coupled to the selected word line as well; that is, when programming the selected memory cell, memory cells in the non-selected memory string coupled to the selected word line are subject to programming interference.

[0079] To reduce programming interference, the non-selected memory string is pre-charged before programming the selected memory cell, thereby reducing programming interference experienced by memory cells in the non-selected memory string that are coupled to the selected word line. In an exemplary embodiment, for ease of operation, in addition to pre-charging the non-selected memory string, the selected memory string containing the selected memory cell is also pre-charged.

[0080] The pre-charging method provided in this application embodiment is used for charging devices having, for example, Figure 5 The unselected memory string in the structure shown is pre-charged. That is, the unselected memory string includes a select transistor stack and a memory cell stack between the bit line connection and the source line connection, and these are connected by doped regions. All memory cells in the unselected memory string are located within the memory cell stack; that is, the memory cell in the unselected memory string coupled to the selected word line refers to the memory cell in the memory cell stack coupled to the selected word line.

[0081] The presence of a large number of electrons in the doped region reduces the channel potential of the memory cells in the memory cell stack of a non-selected memory string during programming, thereby increasing the programming interference experienced by the memory cells in the stack. For example, the electrons in the doped region have a greater adverse effect on the memory cells closer to the doped region in the memory cell stack.

[0082] Therefore, during the pre-charging of the unselected memory string, in addition to reducing the electrons in the channels of the memory cells coupled to the selected word line in the memory cell stack, it is also necessary to reduce the electrons in the doped region. Reducing the electrons in the channels of the memory cells coupled to the selected word line increases the channel potential coupled during programming, while reducing the electrons in the doped region mitigates the decrease in channel potential caused by electrons in the doped region. By reducing both the electrons in the channels and the electrons in the doped region, the memory cells coupled to the selected word line can have a higher channel potential during programming, resulting in a smaller voltage drop between the gate and channel of the memory cells coupled to the selected word line, thereby reducing programming interference experienced by these cells.

[0083] Some embodiments are for having, for example Figure 5The pre-charging method for the unselected memory string in the illustrated structure is as follows: a pre-charging voltage is applied to the source line connection terminal of the unselected memory string, and a 0V voltage is applied to the gate of all memory cells in the memory cell stack. The inventors discovered that this 0V voltage is insufficient to turn on the channel of the programmed memory cell. If there are programmed memory cells in the memory cell stack, it cannot be guaranteed that electrons in the doped region and electrons in the channel of the memory cell coupled to the selected word line are sufficiently attracted to the source line connection terminal, which easily leads to insufficient pre-charging and causes severe programming interference to the memory cell coupled to the selected word line.

[0084] As can be seen from the above analysis, it is difficult to fully precharge non-selected memory strings using the precharging methods in some embodiments. Therefore, it is crucial to provide a method that can fully precharge non-selected memory strings.

[0085] This application provides a pre-charge method, which is executed by peripheral circuitry 420 in memory 103. The pre-charge method is used to pre-charge a non-selected memory string before programming a selected memory cell. A select transistor stack and a memory cell stack are included between the bit line connection and the source line connection of the non-selected memory string. The select transistor stack and the memory cell stack are connected through a doped region. The memory cell stack includes programmed memory cells and unprogrammed memory cells.

[0086] For a memory block, the programming process according to the programming direction includes multiple programming stages. Different programming stages correspond to different selected word lines. A programming stage is used to program the selected memory cell corresponding to that programming stage. The selected memory cell is the memory cell that needs to be written to among the various memory cells coupled to the selected word line. Before each programming stage, there is a precharge stage. The precharge stage is used to precharge the non-selected memory string corresponding to the programming stage. That is, before programming the selected memory cell corresponding to each programming stage, the non-selected memory string corresponding to each programming stage needs to be precharged.

[0087] The principle of pre-charging the non-selected memory string corresponding to each programming stage is the same. This application uses any programming stage as an example for illustration. That is, the selected word line and non-selected memory string in this application embodiment refer to the selected word line and non-selected memory string corresponding to any programming stage. It should be noted that the selected word lines corresponding to different programming stages are different, and the non-selected memory strings corresponding to different programming stages may be the same or different.

[0088] It should be noted that there may be one or more non-selected memory strings. The principle of precharging each non-selected memory string is the same. This application embodiment takes one non-selected memory string as an example for illustration. If there are multiple non-selected memory strings, the precharging method provided in this application embodiment can be used to precharge each non-selected memory string.

[0089] like Figure 6 As shown, the pre-charging method provided in this application embodiment includes steps 601 and 602.

[0090] In step 601, a pre-charge voltage is applied to the source line connection terminal.

[0091] The pre-charge voltage applies an electric field force pointing towards the source line connection to electrons in the doped region and in the channel of the memory cell coupled to the selected word line. This application does not limit the magnitude of the pre-charge voltage; exemplarily, the pre-charge voltage is a voltage between 0 and 10V, such as 2V.

[0092] In an exemplary embodiment, the source line connection is coupled to SL, and the pre-charge voltage is applied to the source line connection by applying a pre-charge voltage to SL coupled to the source line connection.

[0093] For example, during the pre-charging of a non-selected memory string, the bit line connection can be grounded, that is, a 0V voltage can be applied to the bit line connection, or a voltage greater than 0V but less than the pre-charging voltage can be applied to the bit line connection.

[0094] In an exemplary embodiment, during the pre-charging process of the unselected memory string, in addition to applying a pre-charging voltage to the source line connection, a turn-on voltage needs to be applied to the gate of the select transistor (BSG) on the source line connection side to turn on the BSG channel, thereby preventing the BSG from blocking the movement of electrons toward the source line connection. In an exemplary embodiment, the process of applying the turn-on voltage to the gate of the BSG is achieved by applying a turn-on voltage to the SSL coupled to the BSG. The turn-on voltage is greater than the threshold voltage of the BSG. For example, if the threshold voltage of the BSG is in the range of 1 to 4V, the turn-on voltage can be in the range of 5 to 15V.

[0095] In step 602, a voltage is applied to the gate of each memory cell in the memory cell stack; wherein the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell.

[0096] Applying a voltage greater than its respective threshold voltage to the gates of both programmed and unprogrammed memory cells in the memory cell stack can turn on the channels of all memory cells in the stack. In other words, even when programmed memory cells are present in the stack, it can still ensure that electrons in the doped region and electrons in the channels of memory cells coupled to the selected word line are sufficiently attracted to the source line connection, thereby achieving sufficient pre-charging of the unselected memory string.

[0097] A programmed storage unit refers to a storage unit that has been written with data, while an unprogrammed storage unit refers to a storage unit that has not been written with data. In the embodiments of this application, the storage unit stack contains both programmed and unprogrammed storage units.

[0098] Since no data has been written to the memory cells coupled to the selected word line in the memory cell stack, there must be unprogrammed memory cells in the memory cell stack. This application does not limit the circumstances under which programmed memory cells exist in the memory cell stack.

[0099] For example, taking the erase method corresponding to the memory block where the non-selected memory string is located as a full erase, the situations in which there are programmed memory cells in the memory cell stack include: the programming direction is the forward programming direction (that is, the direction from the source line connection end to the bit line connection end) and there are programmed memory cells between the memory cells coupled to the selected word line and the source line connection end; or, the programming direction is the reverse programming direction (that is, the direction from the bit line connection end to the source line connection end) and there are programmed memory cells between the memory cells coupled to the selected word line and the bit line connection end.

[0100] It should be noted that when the erasure method for the storage block containing the non-selected storage string is a full erase, any programmed storage unit is a storage unit that has been erased and then rewritten with data. In some embodiments, the erasure method for the storage block containing the non-selected storage string may also be a partial erase. In this case, any programmed storage unit may be a storage unit that has not been erased, or it may be a storage unit that has been erased and then rewritten with data.

[0101] In an exemplary embodiment, applying a voltage to the gate of each memory cell in the memory cell stack includes applying a first voltage to both the gate of the programmed memory cell and the gate of the unprogrammed memory cell. The first voltage is greater than a threshold voltage of the programmed memory cell.

[0102] Since the threshold voltage of an unprogrammed memory cell is lower than that of a programmed memory cell, by applying a first voltage greater than the threshold voltage of the programmed memory cell to both the gate of the programmed memory cell and the gate of the unprogrammed memory cell, it can be ensured that the channels of each memory cell in the memory cell stack are turned on. This implementation method is highly convenient to operate.

[0103] For example, there are multiple programmed memory cells, and the threshold voltage of different programmed memory cells may be different. The first voltage is a voltage greater than the threshold voltage of each programmed memory cell. For example, the threshold voltage of the programmed memory cell ranges from 0 to 5V, and correspondingly, the first voltage ranges from 5 to 7V.

[0104] For example, the process of applying a first voltage to the gate of both the programmed memory cell and the gate of both the unprogrammed memory cell is achieved by applying a first voltage to both the word lines coupled to the programmed memory cell and the word lines coupled to the unprogrammed memory cell.

[0105] This application does not limit the relationship between the pre-charge voltage and the first voltage. In an exemplary embodiment, the pre-charge voltage is greater than the first voltage. Of course, the pre-charge voltage can also be less than the first voltage.

[0106] In an exemplary embodiment, applying a voltage to the gate of each memory cell in the memory cell stack includes applying a first voltage to the gate of a programmed memory cell and applying a second voltage to the gate of an unprogrammed memory cell. The first voltage is greater than a threshold voltage of the programmed memory cell, and the second voltage is greater than a threshold voltage of the unprogrammed memory cell but less than the first voltage.

[0107] The second voltage enables the channel of the unprogrammed memory cell to conduct and is less than the first voltage. By applying the first voltage and the second voltage to the gate of the programmed memory cell and the gate of the unprogrammed memory cell respectively, power resources can be saved while ensuring that the channels of each memory cell in the memory cell stack are conducted.

[0108] For example, the second voltage is a default voltage continuously applied to the gate of the memory cell; that is, a second voltage is continuously applied to the gate of the unprogrammed memory cell, the default voltage being greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage. For example, the threshold voltage of the unprogrammed memory cell is negative, and the default voltage can be 0V.

[0109] For example, the process of applying a first voltage to the gate of a programmed memory cell is achieved by applying a first voltage to a word line coupled to the programmed memory cell; the process of applying a second voltage to the gate of an unprogrammed memory cell is achieved by applying a second voltage to a word line coupled to the unprogrammed memory cell.

[0110] In an exemplary embodiment, taking the application of a first voltage and a second voltage to the gate of a programmed memory cell and the gate of an unprogrammed memory cell, respectively, with the second voltage being a default voltage continuously applied to the gate of the memory cell, the order of applying the first voltage and the cutoff time of applying the pre-charge voltage is defined to further improve the pre-charge effect. In an exemplary embodiment, the cutoff time of applying the first voltage to the gate of the programmed memory cell is earlier than the cutoff time of applying the pre-charge voltage to the source line connection terminal. Exemplarily, when the cutoff time of applying the voltage is reached, the voltage drops to a default voltage, which is 0V.

[0111] When a first voltage is applied to the gate of a programmed memory cell, some electrons will be adsorbed around the programmed memory cell. The cutoff time of applying the first voltage to the gate of the programmed memory cell is earlier than the cutoff time of applying the pre-charge voltage to the source line connection terminal. This ensures that after the voltage applied to the gate of the programmed memory cell drops to 0V, the electrons adsorbed around the programmed memory cell can continue to migrate and diffuse towards the source line connection terminal under the action of the electric field force provided by the pre-charge voltage, thereby further improving the pre-charge effect on the unselected memory string.

[0112] In an exemplary embodiment, in addition to applying a pre-charge voltage to the source line connection terminal and a first voltage to the gate of the programmed memory cell, a turn-on voltage is also applied to the gate of the BSG. In this case, the cutoff time for applying the first voltage to the gate of the programmed memory cell is earlier than the cutoff time for applying the turn-on voltage to the gate of the BSG and the cutoff time for applying the pre-charge voltage to the source line connection terminal, to ensure sufficient pre-charge. Exemplarily, the cutoff time for applying the turn-on voltage to the gate of the BSG is no later than the cutoff time for applying the pre-charge voltage to the source line connection terminal.

[0113] In an exemplary embodiment, when there are multiple programmed memory cells, the cutoff time for applying the first voltage to the gate of the programmed memory cell farther from the source line connection is no later than the cutoff time for applying the first voltage to the gate of the programmed memory cell closer to the source line connection, to ensure sufficient pre-charging. That is, the cutoff time for applying the first voltage to the gate of each programmed memory cell is the same; or, the cutoff time for applying the first voltage to the gate of the programmed memory cell farther from the source line connection is earlier.

[0114] It should be noted that the above description only illustrates the order of the voltage application cutoff times by applying a first voltage and a second voltage to the gate of a programmed memory cell and the gate of an unprogrammed memory cell, respectively, with the second voltage being the default voltage continuously applied to the gate of the memory cell. The embodiments of this application are not limited to this.

[0115] In an exemplary embodiment, when a first voltage is applied to the gates of both the programmed and unprogrammed memory cells, the cutoff time for applying the first voltage to the gates of both the programmed and unprogrammed memory cells is earlier than the cutoff time for applying the pre-charge voltage to the source line connection terminal, to ensure sufficient pre-charge. Exemplarily, the cutoff time for applying the first voltage to the gate of the memory cell farther from the source line connection terminal is no later than the cutoff time for applying the first voltage to the gate of the memory cell closer to the source line connection terminal, to ensure sufficient pre-charge.

[0116] In an exemplary embodiment, when a first voltage and a second voltage are applied to the gate of a programmed memory cell and the gate of an unprogrammed memory cell, respectively, and the second voltage is not the default voltage continuously applied to the gate of the memory cell, the cutoff time for applying the first voltage to the gate of the programmed memory cell and the cutoff time for applying the second voltage to the gate of the unprogrammed memory cell are both earlier than the cutoff time for applying the pre-charge voltage to the source line connection terminal, to ensure sufficient pre-charge. Exemplarily, the cutoff time for applying the corresponding voltage to the gate of a memory cell farther from the source line connection terminal is no later than the cutoff time for applying the corresponding voltage to the gate of a memory cell closer to the source line connection terminal, to ensure sufficient pre-charge. Wherein, if the memory cell is a programmed memory cell, the corresponding voltage is the first voltage; if the memory cell is an unprogrammed memory cell, the corresponding voltage is the second voltage.

[0117] The embodiments of this application do not limit the relationship between the start times of the applied voltages. For example, except for the continuously applied default voltage, the start times of applying each voltage (e.g., pre-charge voltage, turn-on voltage, first voltage, etc.) are all the same.

[0118] Through steps 601 and 602 above, even when programmed memory cells exist in the memory cell stack, it is possible to achieve a more adequate pre-charge of non-selected memory strings, thereby reducing programming interference to memory cells coupled to selected word lines.

[0119] In an exemplary embodiment, during the pre-charging phase prior to the programming phase, in addition to pre-charging non-selected memory strings, selected memory strings can also be pre-charged to facilitate operation. Here, the selected memory string refers to the memory string containing the selected memory cell. The implementation process for pre-charging the selected memory string is detailed in the implementation process for pre-charging non-selected memory strings, and will not be repeated here. In the exemplary embodiment, the pre-charging process for each memory string requiring pre-charging can be executed simultaneously or in batches; this application embodiment does not limit this.

[0120] After precharging each memory string that requires precharging, the precharging phase before the programming phase is completed. Following the completion of the precharging phase before the programming phase, the programming phase begins to program the selected memory cells.

[0121] In an exemplary embodiment, the selected memory cell is programmed by applying a programming voltage to the selected word line, applying a pass voltage to the other word lines (i.e., non-selected word lines), and applying an on-state voltage to the DSL coupled to the TSG of the selected memory string. Furthermore, 0V is applied to the SSL coupled to the BSG of the selected memory string, the BL coupled to the bit line connection, and the SL coupled to the source line connection; 0V is also applied to the DSL coupled to the TSG of the non-selected memory string, the SSL coupled to the BSG, the BL coupled to the bit line connection, and the SL coupled to the source line connection.

[0122] A relatively high programming voltage, such as 22V, allows for a sufficiently high positive voltage difference between the gate and channel of the selected memory cell. This enables electrons in the channel of the selected memory cell to tunnel into the floating gate or charge trapping layer of the selected memory cell, thus enabling data writing. By adjusting the programming voltage, the number of electrons stored in the floating gate or charge trapping layer can be adjusted, thereby adjusting the threshold voltage of the selected memory cell. For example, the minimum voltage required for electrons in the channel to tunnel to the floating gate or charge trapping layer of the selected memory cell is called the tunneling voltage, and the programming voltage must be no less than the tunneling voltage. It is understood that the tunneling voltage is a voltage greater than the threshold voltage.

[0123] By applying a pass voltage to the non-selected word line, the channels of other memory cells in the selected memory string, excluding the selected memory cell, can be turned on. Since the pass voltage is lower than the programming voltage, the voltage difference between the gate and the channel of other memory cells in the selected memory string is relatively small, thereby preventing electrons in the channel from tunneling to the floating gate or charge trapping layer, thus achieving programming suppression of other memory cells in the selected memory string.

[0124] Applying a conduction voltage to the DSL coupled to the TSG of the selected memory string turns on the channel of the TSG of the selected memory string. During the programming of the selected memory cell, the channel of the BSG of the selected memory string, as well as the channels of the TSG and BSG of the non-selected memory strings, are all turned off.

[0125] The pre-charging method provided in this application, in addition to applying a pre-charging voltage to the source line connection terminal, applies a voltage greater than its respective threshold voltage to the gates of both programmed and unprogrammed memory cells in the memory cell stack. This approach ensures that the channels of all memory cells in the stack are conducting, even when programmed memory cells are present. This allows electrons in the doped region and in the channels of memory cells coupled to the selected word line to be sufficiently attracted to the source line connection terminal, thereby achieving a more thorough pre-charging of the unselected memory string and reducing programming interference experienced by memory cells coupled to the selected word line in the memory cell stack.

[0126] For example, taking the application of a first voltage to the gates of both programmed and unprogrammed memory cells as an example, the voltage application related to the unselected memory string during the pre-charge and programming phases is as follows: Figure 7 As shown.

[0127] During the pre-charge phase, a pre-charge voltage (V) is applied to the CSL coupled to the source line connection of the unselected memory string. CC Apply a turn-on voltage (V) to the BSG-coupled SSL of the non-selected memory string. BSG A first voltage (V) is applied to both the selected word line (Sel.WL) and the unselected word line (Unsel.WL). PRE For example, V PRE A voltage greater than 5V is applied. A 0V voltage is applied to the BL coupled to the bit line connector of the non-selected memory string and the DSL coupled to the TSG of the non-selected memory string.

[0128] exist Figure 7 Under the voltage applied during the pre-charge phase shown, V is applied. CC Start time, application of V BSG The start time and the application of V PRE The start time for all is t0, and V is applied. PRE The deadline is t1, and V is applied. CC The deadline and the application of V BSG The deadline for all of them is t2. The order of t0, t1, and t2 from earliest to latest is: t0, t1, t2.

[0129] It should be noted that the 0V voltage is the default voltage that is continuously applied. When the cutoff time for applying a voltage greater than 0V is reached, the voltage greater than 0V drops to 0V.

[0130] During the programming phase, a programming voltage (V) is applied to the selected word line (Sel.WL). PGM Apply a pass voltage (V) to the unselected word line (Unsel.WL).PASS A 0V voltage is applied to the source line connection coupled to CSL, BSG coupled to SSL, TSG coupled to DSL, and bit line connection coupled to BL of the non-selected memory string.

[0131] exist Figure 7 Under the voltage application condition shown in the programming stage, V is applied. PGM Start time and application of V PASS The start time for all is t3, and V is applied. PGM The deadline and the application of V PASS The deadline for all is t6. PGM It reaches its maximum value at t4. V PGM and V PASS All begin to decrease at time t5. The order of t3, t4, t5, and t6 from earliest to latest is: t3, t4, t5, t6.

[0132] The above Figure 6 The illustrated embodiments describe a method for pre-charging a non-selected memory string by applying a pre-charge voltage to the source line connection. In exemplary embodiments, pre-charging of the non-selected memory string can also be achieved by applying a pre-charge voltage to the bit line connection. In some embodiments, the process of pre-charging a non-selected memory string is as follows: applying a pre-charge voltage to the bit line connection; applying a 0V voltage to the gates of all memory cells in the memory cell stack. The inventors have found that this 0V voltage is insufficient to turn on the channel of the programmed memory cell. If there is a programmed memory cell between the bit line connection and the target memory cell, although electrons in the doped region can be sufficiently attracted to the bit line connection, electrons in the channel of the target memory cell cannot be sufficiently attracted to the bit line connection, which can easily lead to insufficient pre-charging and cause severe programming interference to the target memory cell. Here, the target memory cell refers to the memory cell in the memory cell stack that is coupled to the selected word line.

[0133] As can be seen from the above analysis, it is difficult to fully precharge non-selected memory strings using the precharging methods in some embodiments. Therefore, it is crucial to provide a method that can fully precharge non-selected memory strings.

[0134] In an exemplary embodiment, according to Figure 8 The pre-charge method shown in steps 801 and 802 pre-charges the non-selected memory string to reduce programming interference to the target memory cell.

[0135] In step 801, a pre-charge voltage is applied to the bit line connection terminal.

[0136] The pre-charge voltage applies an electric field force pointing towards the bit line connection to electrons in the doped region and in the channel of the target memory cell. The target memory cell refers to the memory cell in the memory cell stack coupled to the selected word line. This application does not limit the magnitude of the pre-charge voltage; exemplarily, the pre-charge voltage is a voltage between 0 and 10V, such as 2V.

[0137] In an exemplary embodiment, the bit line connection is coupled to the BL, and the pre-charge voltage is applied to the bit line connection by applying a pre-charge voltage to the BL coupled to the bit line connection.

[0138] For example, when applying a pre-charge voltage to the source line connection, the source line connection can be grounded, that is, a 0V voltage can be applied to the source line connection, or a voltage greater than 0V but less than the pre-charge voltage can be applied to the source line connection.

[0139] In an exemplary embodiment, during the pre-charging process of the unselected memory string, in addition to applying a pre-charging voltage to the bit line connection terminal, a turn-on voltage is also applied to the gate of the select transistor (i.e., each select transistor in the select transistor stack, also referred to as TSG) on the bit line connection terminal side to turn on the TSG channel, thereby preventing the TSG from blocking the movement of electrons toward the bit line connection terminal. In an exemplary embodiment, the process of applying the turn-on voltage to the gate of the TSG is achieved by applying a turn-on voltage to the DSL coupled to the TSG. The turn-on voltage is greater than the threshold voltage of the TSG. For example, if the threshold voltage of the TSG is in the range of 1 to 4V, the turn-on voltage can be in the range of 5 to 15V.

[0140] In step 802, the channel of the memory cell located between the bit line connection terminal and the target memory cell in the memory cell stack is turned on. The memory cell located between the bit line connection terminal and the target memory cell includes a programmed memory cell. The target memory cell is a memory cell in the memory cell stack that is coupled to the selected word line.

[0141] A programmed memory cell refers to a memory cell located between the bit line connector and the target memory cell that has been written with data. A memory cell with written data can be a memory cell that has not been erased, or a memory cell that has been erased and rewritten with data. When the memory cell between the bit line connector and the target memory cell includes a programmed memory cell, making the channel of the memory cell between the bit line connector and the target memory cell conductive can prevent non-conductive channels from blocking the movement of electrons in the target memory cell's channel towards the bit line connector. This allows electrons in the target memory cell's channel and electrons in the doped region to be more effectively attracted to the bit line connector.

[0142] This application does not limit whether the storage unit located between the bit line connection terminal and the target storage unit includes unprogrammed storage units. An unprogrammed storage unit refers to a storage unit located between the bit line connection terminal and the target storage unit that has not been written with data. That is, the storage units located between the bit line connection terminal and the target storage unit can all be programmed storage units, or they can include both programmed and unprogrammed storage units.

[0143] For example, since the doped region is located between the bit line connection and the target memory cell, and there is a select transistor stack between the doped region and the bit line connection, and there are no memory cells in the select transistor stack, the memory cell located between the bit line connection and the target memory cell is equivalent to the memory cell located between the doped region and the target memory cell.

[0144] This application does not limit the cases where the memory cell located between the bit line connection end and the target memory cell includes a programmed memory cell. For example, taking the erase method corresponding to the memory block where the non-selected memory string is located as a full erase as an example, the cases where the memory cell located between the bit line connection end and the target memory cell includes a programmed memory cell include: the programming direction is the reverse programming direction, and there is a memory cell between the doped region and the target memory cell that has been erased and rewritten with data.

[0145] For example, the erasure method corresponding to the memory block where the non-selected memory string is located may also be partial erasure. In this case, the situation where the memory cell located between the bit line connection end and the target memory cell includes the programmed memory cell may also be other cases, such as there are unerased memory cells between the bit line connection end and the target memory cell.

[0146] In one possible implementation, turning on the channel of a memory cell located between the bit line connection and the target memory cell in the memory cell stack can be achieved by applying a first voltage to the gate of the memory cell located between the bit line connection and the target memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell.

[0147] Because the threshold voltage of an unprogrammed memory cell is lower than that of a programmed memory cell, regardless of whether the memory cell between the bit line connection and the target memory cell includes an unprogrammed memory cell, applying a first voltage to the gate of the memory cell between the bit line connection and the target memory cell ensures that the channel of the memory cell between the bit line connection and the target memory cell is turned on. This implementation method is highly convenient to operate.

[0148] For example, there are multiple programmed memory cells, and the threshold voltage of different programmed memory cells may be different. The first voltage is a voltage greater than the threshold voltage of each programmed memory cell. For example, if the threshold voltage of the programmed memory cell is in the range of 0 to 5V, then the first voltage can be in the range of 5 to 7V.

[0149] For example, the process of applying a first voltage to the gate of a memory cell located between the bit line connection terminal and the target memory cell is achieved by applying a first voltage to the word line coupled to the memory cell located between the bit line connection terminal and the target memory cell.

[0150] This application does not limit the relationship between the pre-charge voltage and the first voltage. In an exemplary embodiment, the pre-charge voltage is greater than the first voltage. Of course, the pre-charge voltage can also be less than the first voltage.

[0151] In an exemplary embodiment, the memory cell located between the bit line connection terminal and the target memory cell further includes an unprogrammed memory cell. In this case, the method for turning on the channel of the memory cell located between the bit line connection terminal and the target memory cell in the memory cell stack can also be: applying a first voltage to the gate of the programmed memory cell; and applying a second voltage to the gate of the unprogrammed memory cell. The first voltage is greater than the threshold voltage of the programmed memory cell, and the second voltage is greater than the threshold voltage of the unprogrammed memory cell but less than the first voltage.

[0152] The second voltage enables the channel of the unprogrammed memory cell to conduct and is less than the first voltage. By applying the first voltage and the second voltage to the gate of the programmed memory cell and the gate of the unprogrammed memory cell respectively, power resources can be saved while ensuring that the channels of both programmed and unprogrammed memory cells are conducted.

[0153] For example, the second voltage is a default voltage continuously applied to the gate of the memory cell; that is, a second voltage is continuously applied to the gate of the unprogrammed memory cell, the default voltage being greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage. For example, the threshold voltage of the unprogrammed memory cell is negative, and the default voltage can be 0V.

[0154] For example, the process of applying a first voltage to the gate of a programmed memory cell is achieved by applying a first voltage to a word line coupled to the programmed memory cell; the process of applying a second voltage to the gate of an unprogrammed memory cell is achieved by applying a second voltage to a word line coupled to the unprogrammed memory cell.

[0155] For example, the memory cell stack includes not only memory cells located between the bit line connection and the target memory cell, but also memory cells not located between the bit line connection and the target memory cell. The memory cells not located between the bit line connection and the target memory cell include both the target memory cell and memory cells located between the source line connection and the target memory cell.

[0156] In an exemplary embodiment, in addition to making the channels of the memory cells located between the bit line connection terminal and the target memory cell conductive, the channels of the memory cells in the memory cell stack not located between the bit line connection terminal and the target memory cell can also be made conductive, thereby making the channels of all memory cells in the memory cell stack conductive. The implementation principle of making the channels of memory cells not located between the bit line connection terminal and the target memory cell conductive is the same as the implementation principle of making the channels of memory cells located between the bit line connection terminal and the target memory cell conductive, and will not be repeated here.

[0157] In an exemplary embodiment, since the memory cells not located between the bit line connection terminal and the target memory cell do not block the movement of electrons in the channel of the target memory cell toward the bit line connection terminal, it is only necessary to apply a default voltage (e.g., 0V) to the gate of the memory cells not located between the bit line connection terminal and the target memory cell, without needing to concern oneself with whether the channel of the memory cells not located between the bit line connection terminal and the target memory cell is turned on.

[0158] In an exemplary embodiment, taking the application of a first voltage and a second voltage to the gate of a programmed memory cell and the gate of an unprogrammed memory cell, respectively, with the second voltage being a default voltage continuously applied to the gate of the memory cell, the order of applying the first voltage and the cutoff time of applying the pre-charge voltage is defined to further improve the pre-charge effect. In an exemplary embodiment, the cutoff time of applying the first voltage to the gate of the programmed memory cell is earlier than the cutoff time of applying the pre-charge voltage to the bit line connection terminal. Exemplarily, when the cutoff time of applying the voltage is reached, the voltage drops to a default voltage, which is 0V.

[0159] When a first voltage is applied to the gate of a programmed memory cell, some electrons will be adsorbed around the programmed memory cell. The cutoff time of applying the first voltage to the gate of the programmed memory cell is earlier than the cutoff time of applying the pre-charge voltage to the bit line connection terminal. This ensures that after the voltage applied to the gate of the programmed memory cell drops to 0V, the electrons adsorbed around the programmed memory cell can continue to migrate and diffuse towards the bit line connection terminal under the action of the electric field force provided by the pre-charge voltage, thereby further improving the pre-charge effect on the unselected memory string.

[0160] In an exemplary embodiment, in addition to applying a pre-charge voltage to the bit line connection terminal and a first voltage to the gate of the programmed memory cell, an on-state voltage is also applied to the gate of the TSG. In this case, the off-time of applying the first voltage to the gate of the programmed memory cell is earlier than the off-time of applying the on-state voltage to the gate of the TSG and the off-time of applying the pre-charge voltage to the bit line connection terminal, to ensure sufficient pre-charge. Exemplarily, the off-time of applying the on-state voltage to the gate of the TSG is no later than the off-time of applying the pre-charge voltage to the bit line connection terminal.

[0161] In an exemplary embodiment, when there are multiple programmed memory cells, the cutoff time for applying the first voltage to the gate of the programmed memory cell farther from the bit line connection terminal is no later than the cutoff time for applying the first voltage to the gate of the programmed memory cell closer to the bit line connection terminal, so as to ensure sufficient pre-charging. That is, the cutoff time for applying the first voltage to the gate of each programmed memory cell is the same; or, the cutoff time for applying the first voltage to the gate of the programmed memory cell farther from the bit line connection terminal is earlier.

[0162] It should be noted that the above description only illustrates the order of the voltage application cutoff times by applying a first voltage and a second voltage to the gate of a programmed memory cell and the gate of an unprogrammed memory cell, respectively, with the second voltage being the default voltage continuously applied to the gate of the memory cell. The embodiments of this application are not limited to this.

[0163] In an exemplary embodiment, when a first voltage is applied to the gate of a memory cell located between the bit line connection terminal and the target memory cell, the cutoff time for applying the first voltage to the gate of the memory cell located between the bit line connection terminal and the target memory cell is earlier than the cutoff time for applying the pre-charge voltage to the bit line connection terminal, so as to ensure sufficient pre-charge. Exemplarily, during the process of applying the first voltage to the gate of the memory cell located between the bit line connection terminal and the target memory cell, the cutoff time for applying the first voltage to the gate of the memory cell farther from the bit line connection terminal is not later than the cutoff time for applying the first voltage to the gate of the memory cell closer to the bit line connection terminal, so as to ensure sufficient pre-charge.

[0164] In an exemplary embodiment, when a first voltage and a second voltage are applied to the gate of a programmed memory cell and the gate of an unprogrammed memory cell, respectively, and the second voltage is not the default voltage continuously applied to the gate of the memory cell, the cutoff time for applying the first voltage to the gate of the programmed memory cell and the cutoff time for applying the second voltage to the gate of the unprogrammed memory cell are both earlier than the cutoff time for applying the pre-charge voltage to the bit line connection terminal, to ensure sufficient pre-charge. Exemplarily, the cutoff time for applying the corresponding voltage to the gate of a memory cell farther from the bit line connection terminal is no later than the cutoff time for applying the corresponding voltage to the gate of a memory cell closer to the bit line connection terminal, to ensure sufficient pre-charge. Wherein, if the memory cell is a programmed memory cell, the corresponding voltage is the first voltage; if the memory cell is an unprogrammed memory cell, the corresponding voltage is the second voltage.

[0165] The embodiments of this application do not limit the relationship between the start times of the applied voltages. For example, except for the continuously applied default voltage, the start times of applying each voltage (e.g., pre-charge voltage, turn-on voltage, first voltage, etc.) are all the same.

[0166] Through steps 801 and 802 above, it is possible to achieve a more adequate pre-charge of the non-selected memory string when there are programmed memory cells between the bit line connection terminal and the target memory cell, thereby reducing the programming interference to the memory cells coupled with the selected word line.

[0167] The pre-charging method provided in this application, based on applying a pre-charging voltage to the bit line connection terminal, opens the channel of the memory cell located between the bit line connection terminal and the target memory cell. This avoids the phenomenon that non-conductive channels block the movement of electrons in the target memory cell channel towards the bit line connection terminal. As a result, electrons in the doped region and electrons in the target memory cell channel are attracted to the bit line connection terminal more fully, thereby achieving more sufficient pre-charging of the non-selected memory string. This is beneficial for reducing programming interference to the target memory cell in the memory cell stack.

[0168] In an exemplary embodiment, a memory is also provided, the memory including a memory array and peripheral circuitry communicatively connected to the memory array;

[0169] The memory array includes unselected memory strings. Between the bit line connection and the source line connection of the unselected memory strings, there is a select transistor stack and a memory cell stack. The select transistor stack and the memory cell stack are connected through a doped region. The memory cell stack includes programmed memory cells and unprogrammed memory cells.

[0170] The peripheral circuitry is configured to apply a pre-charge voltage to the source line connection terminal; apply a voltage to the gate of each memory cell in the memory cell stack; wherein the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell.

[0171] In one possible implementation, the peripheral circuitry is configured to apply a first voltage to both the gate of the programmed memory cell and the gate of the unprogrammed memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell.

[0172] In one possible implementation, the peripheral circuitry is configured to apply a first voltage to the gate of a programmed memory cell and a second voltage to the gate of an unprogrammed memory cell. The first voltage is greater than a threshold voltage of the programmed memory cell, and the second voltage is greater than a threshold voltage of the unprogrammed memory cell but less than the first voltage.

[0173] In one possible implementation, the cutoff time for applying a first voltage to the gate of the programmed memory cell is earlier than the cutoff time for applying a pre-charge voltage to the source line connection.

[0174] In one possible implementation, there are multiple programmed memory cells; the cutoff time for applying the first voltage to the gate of a programmed memory cell that is far from the source line connection is no later than the cutoff time for applying the first voltage to the gate of a programmed memory cell that is close to the source line connection.

[0175] In an exemplary embodiment, a memory is also provided, the memory including a memory array and peripheral circuitry communicatively connected to the memory array;

[0176] The memory array includes unselected memory strings, and between the bit line connection terminals and source line connection terminals of the unselected memory strings are a select transistor stack and a memory cell stack, which are connected through doped regions.

[0177] The peripheral circuitry is configured to apply a pre-charge voltage to the bit line connection terminal; to conduct the channel of the memory cell located between the bit line connection terminal and the target memory cell in the memory cell stack, the memory cell located between the bit line connection terminal and the target memory cell including the programmed memory cell; wherein the target memory cell is the memory cell in the memory cell stack coupled to the selected word line.

[0178] In an exemplary embodiment, a storage system is also provided, the storage system including a memory and a controller coupled to the memory, the controller being configured to control the memory;

[0179] The memory includes a memory array and peripheral circuitry that is communicatively connected to the memory array;

[0180] The memory array includes unselected memory strings. Between the bit line connection and the source line connection of the unselected memory strings, there is a select transistor stack and a memory cell stack. The select transistor stack and the memory cell stack are connected through a doped region. The memory cell stack includes programmed memory cells and unprogrammed memory cells.

[0181] The peripheral circuitry is configured to apply a pre-charge voltage to the source line connection terminal; apply a voltage to the gate of each memory cell in the memory cell stack; wherein the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell.

[0182] In one possible implementation, the peripheral circuitry is configured to apply a first voltage to both the gate of the programmed memory cell and the gate of the unprogrammed memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell.

[0183] In one possible implementation, the peripheral circuitry is configured to apply a first voltage to the gate of a programmed memory cell and a second voltage to the gate of an unprogrammed memory cell. The first voltage is greater than a threshold voltage of the programmed memory cell, and the second voltage is greater than a threshold voltage of the unprogrammed memory cell but less than the first voltage.

[0184] In one possible implementation, the cutoff time for applying a first voltage to the gate of the programmed memory cell is earlier than the cutoff time for applying a pre-charge voltage to the source line connection.

[0185] In one possible implementation, there are multiple programmed memory cells; the cutoff time for applying the first voltage to the gate of a programmed memory cell that is far from the source line connection is no later than the cutoff time for applying the first voltage to the gate of a programmed memory cell that is close to the source line connection.

[0186] In an exemplary embodiment, a storage system is also provided, the storage system including a memory and a controller coupled to the memory, the controller being configured to control the memory;

[0187] The memory includes a memory array and peripheral circuitry that is communicatively connected to the memory array;

[0188] The memory array includes unselected memory strings, and between the bit line connection terminals and source line connection terminals of the unselected memory strings are a select transistor stack and a memory cell stack, which are connected through doped regions.

[0189] The peripheral circuitry is configured to apply a pre-charge voltage to the bit line connection terminal; to conduct the channel of the memory cell located between the bit line connection terminal and the target memory cell in the memory cell stack, the memory cell located between the bit line connection terminal and the target memory cell including the programmed memory cell; wherein the target memory cell is the memory cell in the memory cell stack coupled to the selected word line.

[0190] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0191] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A memory, characterized in that, The memory includes a memory array and peripheral circuitry communicatively connected to the memory array. The memory array includes a non-selected memory string, and between the bit line connection terminal and the source line connection terminal of the non-selected memory string, there is a select transistor stack and a memory cell stack. The select transistor stack and the memory cell stack are connected through a doped region. The memory cell stack includes programmed memory cells and unprogrammed memory cells. The peripheral circuit is configured to apply a pre-charge voltage to the source line connection terminal; A voltage is applied to the gate of each memory cell in the memory cell stack; wherein the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell. The voltage applied to the gate of the programmed memory cell includes a first voltage, and the cutoff time for applying the first voltage to the gate of the programmed memory cell is earlier than the cutoff time for applying the precharge voltage to the source line connection.

2. The memory according to claim 1, characterized in that, The peripheral circuitry is configured to apply the first voltage to the gate of the unprogrammed memory cell.

3. The memory according to claim 1, characterized in that, The peripheral circuitry is configured to apply a second voltage to the gate of the unprogrammed memory cell, the second voltage being greater than a threshold voltage of the unprogrammed memory cell and less than the first voltage.

4. The memory according to claim 1, characterized in that, The number of programmed memory cells is multiple; the cutoff time for applying the first voltage to the gate of the programmed memory cell that is far from the source line connection terminal is no later than the cutoff time for applying the first voltage to the gate of the programmed memory cell that is close to the source line connection terminal.

5. A storage system, characterized in that, The storage system includes a memory and a controller coupled to the memory, the controller being configured to control the memory; The memory includes a memory array and peripheral circuitry communicatively connected to the memory array. The memory array includes a non-selected memory string, and between the bit line connection terminal and the source line connection terminal of the non-selected memory string, there is a select transistor stack and a memory cell stack. The select transistor stack and the memory cell stack are connected through a doped region. The memory cell stack includes programmed memory cells and unprogrammed memory cells. The peripheral circuit is configured to apply a pre-charge voltage to the source line connection terminal; A voltage is applied to the gate of each memory cell in the memory cell stack; wherein the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell. The voltage applied to the gate of the programmed memory cell includes a first voltage, and the cutoff time for applying the first voltage to the gate of the programmed memory cell is earlier than the cutoff time for applying the precharge voltage to the source line connection.

6. The storage system according to claim 5, characterized in that, The peripheral circuitry is configured to apply the first voltage to the gate of the unprogrammed memory cell.

7. The storage system according to claim 5, characterized in that, The peripheral circuitry is configured to apply a second voltage to the gate of the unprogrammed memory cell, the second voltage being greater than a threshold voltage of the unprogrammed memory cell and less than the first voltage.

8. The storage system according to claim 5, characterized in that, The number of programmed memory cells is multiple; the cutoff time for applying the first voltage to the gate of the programmed memory cell that is far from the source line connection terminal is no later than the cutoff time for applying the first voltage to the gate of the programmed memory cell that is close to the source line connection terminal.

9. A pre-charging method, characterized in that, The pre-charge method is used to pre-charge a non-selected memory string, wherein the bit line connection terminal and the source line connection terminal of the non-selected memory string include a select transistor stack and a memory cell stack, the select transistor stack and the memory cell stack are connected through a doped region, and the memory cell stack includes programmed memory cells and unprogrammed memory cells; the method includes: A pre-charge voltage is applied to the source line connection terminal; A voltage is applied to the gate of each memory cell in the memory cell stack; Wherein, the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell; The voltage applied to the gate of the programmed memory cell includes a first voltage, and the cutoff time for applying the first voltage to the gate of the programmed memory cell is earlier than the cutoff time for applying the precharge voltage to the source line connection.

10. The method according to claim 9, characterized in that, Applying a voltage to the gate of each memory cell in the memory cell stack includes: The first voltage is applied to the gate of the unprogrammed memory cell.

11. The method according to claim 9, characterized in that, Applying a voltage to the gate of each memory cell in the memory cell stack includes: A second voltage is applied to the gate of the unprogrammed memory cell, the second voltage being greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage.

12. The method according to claim 9, characterized in that, The number of programmed memory cells is multiple; the cutoff time for applying the first voltage to the gate of the programmed memory cell that is far from the source line connection terminal is no later than the cutoff time for applying the first voltage to the gate of the programmed memory cell that is close to the source line connection terminal.

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