Power-fail recovery in cross-point memory with threshold switch selectors

Abstract

This invention is entitled "Power-Off Recovery in Crosspoint Memory with Threshold Switch Selector". In a memory array with a crosspoint structure, at each crosspoint node, a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switch selector, such as a bidirectional threshold switch. When a voltage higher than a threshold voltage is applied, the threshold switch selector switches to a conductive state. During a prolonged power outage, this threshold voltage may drift upwards. If this drift is excessive, it may make the memory cell difficult to access and may interfere with the access of stored data values. Techniques for determining whether excessive drift of the voltage threshold may have occurred are presented, including read-based tests and time-based tests.

Description

Background Technology

[0001] Memory is widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery).

[0002] An example of non-volatile memory is magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data, unlike some other memory technologies that use charge to store data. Generally, MRAM comprises a large number of magnetic memory cells formed on a semiconductor substrate, where each memory cell represents (at least) one data bit. Data bits are written to the memory cell by changing the magnetization direction of the magnetic elements within the memory cell, and bits are read by measuring the resistance of the memory cell (low resistance typically indicates a "0" bit and high resistance typically indicates a "1" bit). As used herein, the magnetization direction is the direction of the magnetic moment orientation.

[0003] Although MRAM is a promising technology, achieving high bit density and high durability for fast write operations in previous MRAM memory cell designs has been challenging. Attached Figure Description

[0004] Components with similar numbers refer to common parts in different drawings.

[0005] Figure 1 It is a block diagram of one implementation of a memory system connected to a host computer.

[0006] Figure 2 This is a block diagram of one implementation of the front-end processor circuitry. In some implementations, the front-end processor circuitry is part of the controller.

[0007] Figure 3 This is a block diagram of one implementation of the back-end processor circuitry. In some implementations, the back-end processor circuitry is part of the controller.

[0008] Figure 4 This is a block diagram of one implementation scheme of a memory package.

[0009] Figure 5 This is a block diagram of one implementation scheme for a memory die.

[0010] Figure 6A and Figure 6B An example of a control circuit coupled to a memory structure via wafer-to-wafer bonding is shown.

[0011] Figure 7A An implementation of a memory array forming a cross-point architecture is depicted in oblique view.

[0012] Figure 7B and Figure 7C They were presented respectively Figure 7A Side and top views of the intersection structure.

[0013] Figure 7D An implementation of a portion of a two-level memory array forming a cross-point architecture is depicted in oblique view.

[0014] Figure 8 An implementation scheme of the structure of an MRAM memory cell is shown.

[0015] Figure 9 An implementation scheme of an MRAM memory cell design implemented with a cross-point array is shown in more detail.

[0016] Figure 10A and Figure 10B This demonstrates the writing of MRAM memory cells using a spin torque transfer (STT) mechanism.

[0017] Figure 11A and Figure 11B An implementation scheme for incorporating a threshold switch selector into an MRAM memory array with a crosspoint architecture is demonstrated.

[0018] Figure 12 and Figure 13 In the read operation, they are respectively used for Figure 11A and Figure 11B An implementation of a set of waveforms of current and voltage for layer 1 unit.

[0019] Figure 14 An example of the voltage of an MRAM device is shown when the threshold switch selector switches from the off state to the on state.

[0020] Figure 15 This is a high-level flowchart of one implementation for determining whether the threshold voltage of a threshold switch selector may have drifted.

[0021] Figures 16 to 18 Provided Figure 15 A more detailed implementation plan for the process. Detailed Implementation

[0022] In a memory array with a cross-point architecture, a first set of conductive lines extends across the surface of the substrate, and a second set of conductive lines is formed above the first set of conductive lines, extending over the substrate in a direction perpendicular to the first set of conductive lines. The memory cell is located at the intersection of these two sets of conductive lines. Implementations of the memory cell may include programmable resistive elements, such as MRAM memory cells, connected in series with a selector switch. One type of selector switch is a threshold switch selector, such as a bidirectional threshold switch, which, compared to other switching elements, such as transistors, can be implemented in a small area and does not require additional control lines. If a voltage higher than a certain level (i.e., a threshold voltage) is applied across the threshold switch selector, it will switch to a conductive state.

[0023] Threshold switch selectors exhibit threshold voltage drift, where the threshold voltage drifts to a higher value if the device remains inactive for an extended period. This can make accessing data stored on the array difficult or even impossible, as the threshold voltage may exceed the maximum voltage level available on the memory device. Even if the threshold switch selector can be turned on, the resulting voltage applied across the memory when the device is powered on can interfere with the data stored in the memory cells or even damage the memory cells. This problem is particularly severe when the memory device is powered off for extended periods. Therefore, the following presents a technique for inferring whether the threshold voltage of a threshold switch selector on a power-off memory array may have drifted to an excessively high value. This process can be performed as part of a power-on test and can include read-based or time-based tests.

[0024] Figure 1 This is a block diagram of one embodiment of a memory system 100 connected to host 120. The memory system 100 can implement the techniques proposed herein for determining whether the threshold voltage of a threshold switch selector used in a crosspoint memory array has drifted excessively. Many different types of memory systems can be used with the techniques proposed herein. Example memory systems include: solid-state drives (“SSDs”); memory cards that include dual embedded memory modules (DIMMs) for DRAM replacement; and embedded memory devices; however, other types of memory systems may also be used.

[0025] Figure 1The memory system 100 includes a controller 102, non-volatile memory 104 for storing data, and local memory (e.g., DRAM / ReRAM / MRAM) 106. The controller 102 includes front-end processor (FEP) circuitry 110 and one or more back-end processor (BEP) circuits 112. In one embodiment, the FEP circuitry 110 is implemented on an application-specific integrated circuit (ASIC). In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. In other embodiments, a unified controller ASIC may combine both front-end and back-end functions. The ASICs for each of the BEP circuitry 112 and the FEP circuitry 110 are implemented on the same semiconductor, such that the controller 102 is fabricated as a system-on-a-chip (“SoC”). Both the FEP circuitry 110 and the BEP circuitry 112 include their own processors. In one embodiment, the FEP circuitry 110 and the BEP circuitry 112 are used in a master-slave configuration, where the FEP circuitry 110 is the master device and each BEP circuitry 112 is a slave device. For example, FEP circuit 110 implements a Flash Translation Layer (FTL) or Media Management Layer (MML) that performs memory management (e.g., garbage collection, wear leveling, etc.), logic-to-physical address translation, communication with the host, DRAM (Local Volatile Memory) management, and overall operation management of the SSD (or other non-volatile memory system). BEP circuit 112 manages memory operations within the memory package / die based on requests from FEP circuit 110. For example, BEP circuit 112 can implement read, erase, and program processes. Additionally, BEP circuit 112 can perform buffer management, set specific voltage levels required by FEP circuit 110, perform error correction (ECC), control the switching mode interface to the memory package, etc. In one embodiment, each BEP circuit 112 is responsible for its own set of memory packages.

[0026] In one embodiment, the non-volatile memory 104 includes multiple memory packages. Each memory package includes one or more memory dies. Therefore, the controller 102 is connected to one or more non-volatile memory dies. In one embodiment, each memory die in the memory package 104 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package may include other types of memory, such as memory-class memory (SCM) or phase-change memory (PCM) based on resistive random access memory (such as ReRAM, MRAM, FeRAM, or RRAM). In other embodiments, a BEP or FEP may be included on the memory die.

[0027] Controller 102 communicates with host 120 via interface 130, which implements protocols such as PCI Express (PCIe) or NVM Express (NVMe) or Compute Fast Link (CXL) using JEDEC standard Double Data Rate or Low Power Double Data Rate (DDR or LPDDR) interfaces (such as DDR5 or LPDDR5). To work with memory system 100, host 120 includes host processor 122, host memory 124, and PCIe interface 126 connected along bus 128. Host memory 124 is the host's physical memory and can be DRAM, SRAM, MRAM, non-volatile memory, or another type of storage device. Host 120 is external to and separate from memory system 100. In one embodiment, memory system 100 is embedded within host 120.

[0028] Figure 2 This is a block diagram of one implementation scheme of FEP circuit 110. Figure 2 A PCIe interface 150 communicating with a host 120 and a host processor 152 communicating with the PCIe interface are shown. The host processor 152 can be any type of processor known in the art suitable for implementation. The host processor 152 communicates with a network on-chip (NOC) 154. An NOC is a communication subsystem on an integrated circuit, typically between cores in a SoC. NOCs can span synchronous and asynchronous clock domains or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication and brings significant improvements compared to conventional bus and cross-switch interconnects. Compared to other designs, NOCs improve the scalability of SoCs and the power efficiency of complex SoCs. The wires and links of a NOC are shared by many signals. Because all links in a NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems increases, NOCs offer enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). Connected to and communicating with the NOC 154 are the memory processor 156, SRAM 160, and DRAM controller 162. The DRAM controller 162 operates and communicates with the DRAM (e.g., DRAM 106). SRAM 160 is local RAM used by the memory processor 156. The memory processor 156 runs the FEP circuitry and performs various memory operations. Two PCIe interfaces, 164 and 166, also communicate with the NOC. Figure 2In one implementation, the SSD controller will include two BEP circuits 112; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 112. In other implementations, there may be more or fewer than two BEP circuits 112; therefore, there may be more than two PCIe interfaces.

[0029] FEP circuit 110 may also include a flash translation layer (FTL), or more generally a media management layer (MML) 158, which performs memory management (e.g., garbage collection, wear leveling, load balancing, etc.), logic-to-physical address translation, communication with the host, DRAM (local volatile memory) management, and overall operation management of SSDs or other non-volatile storage systems. The media management layer (MML) 158 may be integrated as part of memory management that can handle memory errors and interact with the host interface. Specifically, the MML may be a module within FEP circuit 110 and may be responsible for the internals of memory management. Specifically, MML 158 may include algorithms in the memory device firmware that translate writes from the host into writes to the die's memory structure (e.g., the following). Figure 5 And the writes (502 / 602 in Figure 6). MML 158 may be needed because: 1) the memory may have limited endurance; 2) the memory structure may only have multiple pages written to; and / or 3) the memory structure may not need to be written to unless it is erased as a block. MML 158 understands these potential limitations of the memory structure, which may not be visible to the host. Therefore, MML 158 attempts to translate writes from the host into writes to the memory structure.

[0030] Figure 3 This is a block diagram of one implementation scheme of BEP circuit 112. Figure 3 This is shown for communicating with FEP circuit 110 (e.g., with...). Figure 2The PCIe interface 200 communicates with one of the PCIe interfaces 164 and 166. The PCIe interface 200 communicates with two NOCs 202 and 204. In one embodiment, the two NOCs can be combined into a single large NOC. Each NOC (202 / 204) is connected to SRAM (230 / 260), buffers (232 / 262), a processor (220 / 250), and a data path controller (222 / 252) via an XOR engine (224 / 254) and an ECC engine (226 / 256). The ECC engine 226 / 256 performs error correction, as is known in the art. The XOR engine 224 / 254 performs XOR on the data, enabling data to be combined and stored in a recoverable manner in the event of programming errors. The data path controller 222 is connected to the interface module for communication with the memory package via four channels. Therefore, the top NOC 202 is associated with interface 228 for four channels of communication with the memory package, and the bottom NOC 204 is associated with interface 258 for four additional channels of communication with the memory package. Each interface 228 / 258 includes four switching mode interfaces (TM interfaces), four buffers, and four schedulers. One scheduler, buffer, and TM interface exist for each channel. The processor can be any standard processor known in the art. The data path controllers 222 / 252 can be a processor, FPGA, microprocessor, or other type of controller. The XOR engines 224 / 254 and ECC engines 226 / 256 are dedicated hardware circuits referred to as hardware accelerators. In other embodiments, the XOR engines 224 / 254 and ECC engines 226 / 256 can be implemented in software. The schedulers, buffers, and TM interfaces are hardware circuits.

[0031] Figure 4 This is a block diagram of one embodiment of a memory package 104 including multiple memory dies 292 connected to a memory bus (data lines and chip enable lines) 294. The memory bus 294 is connected to a switching mode interface 296 for communication with the TM interface of the BEP circuit 112 (see, for example...). Figure 3 In some implementations, the memory package may include a small controller connected to the memory bus and the TM interface. The memory package may have one or more memory dies. In one implementation, each memory package includes eight or 16 memory dies; however, other numbers of memory dies may also be implemented. In another implementation, the interface is switched to the JEDEC standard DDR or LPDDR, with or without variations such as relaxed timing settings or smaller page sizes. The techniques described herein are not limited to any particular number of memory dies.

[0032] Figure 5This is a block diagram illustrating one example of a memory system 500 that can implement the techniques described herein. The memory system 500 includes a memory array 502, which may include any of the memory cells described below. The array terminal lines of the memory array 502 include individual word line layers organized in rows and individual bit line layers organized in columns. However, other orientations may also be implemented. The memory system 500 includes a row control circuitry system 520, the outputs of which are connected to corresponding word lines of the memory array 502. The row control circuitry system 520 receives a set of M row address signals and one or more various control signals from system control logic circuitry 560, and typically includes circuitry such as a row decoder 522, an array terminal driver 524, and a block selection circuitry system 526 for both read and write operations. The memory system 500 also includes a column control circuitry system 510, the inputs / outputs of which are connected to corresponding bit lines of the memory array 502. Although only a single block is shown for array 502, a memory die may include multiple arrays or "blocks" that can be accessed individually. The column control circuit system 510 receives a set of N column address signals and one or more various control signals from the system control logic unit 560, and typically includes circuits such as column decoder 512, array terminal receiver or driver 514, block selection circuit system 516, read / write circuit system, and I / O multiplexer.

[0033] System control logic unit 560 receives data and commands from the host and provides output data and status to the host. In other embodiments, system control logic unit 560 receives data and commands from a separate controller circuit and provides output data to that controller circuit, wherein the controller circuit communicates with the host. In some embodiments, system control logic unit 560 may include a state machine that provides die-level control for memory operations. In one embodiment, the state machine is programmable by software. In other embodiments, the state machine does not use software and is implemented entirely in hardware (e.g., electrical circuitry). In another embodiment, the state machine is replaced by a microcontroller, wherein the microcontroller is on or outside the memory chip. System control logic unit 560 may also include a power control module that controls the power and voltage supplied to rows and columns of memory 502 during memory operations, and may include charge pump and regulator circuitry for generating regulated voltages. System control logic unit 560 may include one or more state machines, registers, and other control logic units for controlling the operation of memory system 500. Figure 5 Such registers are shown at point 561; for example, such registers can be used to store the threshold voltage V of a threshold switch selector. 阈值The relevant processes and related data are discussed in more detail below. In some embodiments, all components of the memory system 500 (including the system control logic unit 560) may be formed as part of a single die. In other embodiments, some or all of the system control logic unit 560 may be formed on different dies.

[0034] For the purposes of this document, the phrase “one or more control circuits” may include a controller, a state machine, a microcontroller and / or other control circuitry system represented by the system control logic unit 560, or other similar circuitry for controlling non-volatile memory.

[0035] In one embodiment, memory structure 502 includes a three-dimensional memory array of non-volatile memory cells, wherein multiple memory stages are formed over a single substrate (such as a wafer). The memory structure may include any type of non-volatile memory, which is integrally formed in one or more physical stages of memory cells having active regions disposed over a silicon (or other type of) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge-trapping material.

[0036] In another embodiment, memory structure 502 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR flash memory) may also be used.

[0037] The exact type of memory array architecture or memory cell included in memory structure 502 is not limited to the examples described above. Many different types of memory array architectures or memory technologies can be used to form memory structure 326. Implementing the novel embodiments claimed herein does not require a specific non-volatile memory technology. Other examples of suitable technologies for the memory cells of memory structure 502 include ReRAM (Resistive Random Access Memory), magnetoresistive memory (e.g., MRAM, spin-torque MRAM, spin-orbit torque MRAM), FeRAM, phase-change memory (e.g., PCM), and so on. Examples of suitable technologies for the memory cell architecture of memory structure 502 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit-line arrays, and so on.

[0038] One example of a ReRAM crosspoint memory includes reversible resistive switching elements arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell. Based on the physical repositioning of ions within a solid electrolyte, the conductive bridge memory element can be used as a state-changing element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, ion mobility also increases, leading to a decrease in the programming threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element can have a wide range of programming thresholds across the entire temperature range.

[0039] Another example is magnetoresistive random access memory (MRAM) that uses magnetic storage elements to store data. These elements are formed of two ferromagnetic layers separated by a thin insulating layer, each of which can remain magnetized. One of these layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the memory by an external magnetic field. Memory devices are constructed from a grid of such memory cells. In one implementation for programming, each memory cell is located between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below. When current passes through them, an induced magnetic field is generated. MRAM-based memory implementations will be discussed in more detail below.

[0040] Phase-change memories (PCMs) utilize the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve a non-thermal phase transition by changing the coordination state of germanium atoms using only programmed current pulses. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage, light, or other waves. The memory elements within each selectable memory cell or bit may include additional series elements as selectors, such as bidirectional threshold switches or metal-insulator substrates.

[0041] Those skilled in the art will recognize that the techniques described herein are not limited to a single particular memory structure, memory configuration, or material composition, but encompass many related memory structures within the technical essence and scope as described herein and as understood by those skilled in the art.

[0042] Can Figure 5The components are divided into two parts: the memory structure 502 of the memory cells; and the peripheral circuitry, including all other components. A key characteristic of the memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory die reserved for the memory structure 502 within the memory system 500; however, this reduces the area of ​​the memory die available for the peripheral circuitry. This can impose significant limitations on these peripheral components. For example, the need to mount sense amplifier circuitry within the available area can be a major constraint on sense amplifier design architecture. The reduced available area relative to the system control logic unit 560 may limit the available functionality that can be implemented on the chip. Therefore, a fundamental trade-off must be made between the amount of dedicated area for the memory structure 502 and the amount of dedicated area for the peripheral circuitry in the design of the memory die for the memory system 500.

[0043] Another area where memory structure 502 often conflicts with peripheral circuitry lies in the processing involved in forming these areas, as these areas typically involve different processing techniques and trade-offs when implementing different techniques on a single die. For example, when memory structure 502 is NAND flash memory, it is an NMOS structure, while peripheral circuitry is typically CMOS-based. Components such as sense amplifier circuitry, charge pumps, logic elements in state machines, and other peripheral circuitry in system control logic unit 560 typically employ PMOS devices. The processing operations used to manufacture CMOS dies will differ in many ways from those optimized for NMOS flash NAND memory or other memory cell technologies.

[0044] To mitigate these limitations, the implementation scheme described below can... Figure 5The components are separated onto separately formed dies, and then these dies are bonded together. More specifically, the memory structure 502 can be formed on a single die, and some or all of the peripheral circuitry components (including one or more control circuits) can be formed on separate dies. For example, a memory die can be formed solely of memory elements, such as NAND flash memory, MRAM memory, PCM memory, ReRAM memory, or other memory cell arrays of other memory types. Some or all of the peripheral circuitry (even including components such as decoders and sense amplifiers) can then be moved to separate dies. This allows each die in the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without worrying about CMOS elements now moved to separate peripheral circuitry system dies that can be optimized for CMOS processing. This provides more space for peripheral elements, and additional capabilities that might not be easily combined can now be incorporated if peripheral elements are confined to the edges of the same die that houses the memory cell array. Two dies can then be bonded together in a bonded multi-die memory circuit, with an array on one die connected to peripheral elements on another memory circuit. For example, although the following description will focus on a combined memory circuit with one memory die and one peripheral circuit die, other implementations may use more dies, such as two memory dies and one peripheral circuit die.

[0045] Figure 6A and Figure 6B It shows Figure 5 An alternative arrangement to the arrangement can be implemented using wafer-to-wafer bonding to provide a pair of bonding dies for memory system 600. Figure 6A An example of a peripheral circuit system is shown, including control circuitry formed in a peripheral circuitry or control die 611, which is coupled to a memory structure 602 formed in a memory die 601. Figure 5 Similar to 502, memory die 601 may include multiple independently accessible arrays or "tiles". General components and Figure 5Similarly labeled (e.g., 502 is now 602, 510 is now 610, and so on). It can be seen that the system control logic unit 660, the row control circuitry system 620, and the column control circuitry system 610 (which can be formed using a CMOS process) are located in the control die 608. Additional components, such as functions from the controller 102, can also be moved to the control die 608. The system control logic unit 660, the row control circuitry system 620, and the column control circuitry system 610 can be formed using conventional processes (e.g., CMOS processes), such that adding components and functions more commonly found on the memory controller 102 may require few or no additional process steps (i.e., the same process steps used to manufacture the controller 102 can also be used to manufacture the system control logic unit 660, the row control circuitry system 620, and the column control circuitry system 610). Therefore, while removing such circuitry from a die (such as a memory die of memory system 500) can reduce the number of steps required to manufacture such a die, adding such circuitry to a die (such as control die 611) may not require any additional process steps.

[0046] Figure 6A A column control circuitry system 610 on a control die 611 is shown, which is coupled to a memory structure 602 on a memory die 601 via an electrical path 606. For example, electrical path 606 can provide electrical connections between a column decoder 612, a driver circuitry system 614, a block selector 616, and bit lines of the memory structure 602. The electrical path can extend from the column control circuitry system 610 in the control die 611 through pads on the control die 611 that bond to corresponding pads on the memory die 601 that connect to bit lines of the memory structure 602. Each bit line of the memory structure 602 can have a corresponding electrical path in electrical path 606, including a pair of bonded pads connected to the column control circuitry system 610. Similarly, a row control circuitry system 620 (including a row decoder 622, an array driver 624, and a block selector 626) is coupled to the memory structure 602 via an electrical path 608. Each electrical path in electrical path 608 may correspond to a word line, a dummy word line, or a selected gate line. Additional electrical paths may also be provided between the control die 611 and the memory die 601.

[0047] Figure 6BThis is a block diagram showing more details of the arrangement of an integrated memory assembly with connected die pairs 600. The memory die 601 contains a plane or array 602 of memory cells. The memory die 601 may have additional planes or arrays. For each plane or array 602, a representative bit line (BL) and a representative word line (WL) 666 are depicted. Each plane or array 602 may have thousands or tens of thousands of such bit lines. In one embodiment, the array or plane represents a set of connected memory cells sharing a common set of continuous word lines and continuous bit lines.

[0048] The control die 611 includes a plurality of bit line drivers 650. In some embodiments, each bit line driver 650 is connected to one bit line or may be connected to multiple bit lines. The control die 611 includes a plurality of word line drivers 660(1)–660(n). The word line drivers 660 are configured to provide voltage to word lines. In this example, each array or plane of memory cells has “n” word lines. In one embodiment, if the memory operation is programming or reading, one word line within the selected block is selected for the memory operation. In one embodiment, if the memory operation is erasing, all word lines within the selected block are selected for erasing. The word line drivers 660 provide voltage to the word lines in the memory die 601. As stated above regarding Figure 6A The control die 611 discussed may also include a charge pump, a voltage generator, and... Figure 6B Similar components not shown in the diagram may be used to provide voltage to word line driver 660 and / or bit line driver 650.

[0049] The memory die 601 has a plurality of bonding pads 670a, 670b on its first main surface 682. There may be “n” bonding pads 670a to receive voltage from the corresponding “n” word line drivers 660(1)–660(n). There may be one bonding pad 670b for each bit line associated with the array 602. The reference numeral 670 will be used generally to refer to the bonding pads on the main surface 682.

[0050] In some implementations, each data bit and each parity bit of the codeword are transmitted via different bonding pads 670b and 674b. The bits of the codeword can be transmitted in parallel via the bonding pads 670b and 674b. This provides a very efficient data transfer compared to, for example, transferring data between the memory controller 102 and the integrated memory component 600. For example, the data bus between the memory controller 102 and the integrated memory component 600 can provide, for example, 8 bits, 16 bits, or possibly 32 bits to be transmitted in parallel. However, the data bus between the memory controller 102 and the integrated memory component 600 is not limited to these examples. In some implementations, this ECC can be implemented on the memory die.

[0051] The control die 611 has a plurality of bonding pads 674a, 674b on its first main surface 684. There may be “n” bonding pads 674a to deliver voltage from the corresponding “n” word line drivers 660(1)–660(n) to the memory die 601. There may be one bonding pad 674b for each bit line associated with array 602. Reference numeral 674 will be used generally to refer to the bonding pads on the main surface 682. It should be noted that bonding pad pairs 670a / 674a and bonding pad pairs 670b / 674b may exist. In some embodiments, bonding pads 670 and / or 674 are flip-chip bonding pads.

[0052] In one embodiment, the pattern of bonding pad 670 matches the pattern of bonding pad 674. Bonding pad 670 is bonded (e.g., flip-chip bonding) to bonding pad 674. Therefore, bonding pads 670 and 674 electrically and physically couple memory die 601 to control die 611. Additionally, bonding pads 670 and 674 allow internal signal transmission between memory die 601 and control die 611. Thus, memory die 601 and control die 611 are bonded together using bonding pads. Although Figure 6A One control die 611 is depicted being coupled to a memory die 601, but in another embodiment, one control die 611 is coupled to multiple memory dies 601.

[0053] In this document, "internal signal transmission" means signal transmission between control die 611 and memory die 601. Internal signal transmission allows the circuitry on control die 611 to control memory operations in memory die 601. Therefore, bonding pads 670, 674 can be used for memory operation signal transmission. In this document, "memory operation signal transmission" refers to any signal related to memory operations in memory die 601. Memory operation signal transmission may include, but is not limited to, providing voltage, providing current, receiving voltage, receiving current, sensing voltage, and / or sensing current.

[0054] The bonding pads 670 and 674 can be formed of, for example, copper, aluminum, or their alloys. A pad may be present between the bonding pads 670 and 674 and the main surfaces (682, 684). The pad may be formed of, for example, titanium / titanium nitride stacks. The bonding pads 670 and 674 and the pad may be applied using vapor deposition and / or electroplating techniques. The bonding pads and pads together may have a thickness of 720 nm, but this thickness may be greater or less in other embodiments.

[0055] Metal interconnects and / or vias can be used to electrically connect various components in the die to bonding pads 670, 674. Several conductive paths that can be implemented using metal interconnects and / or vias are described. For example, a sense amplifier can be electrically connected to bonding pad 674b via path 664. Relative to Figure 6A Electrical path 606 can correspond to path 664, bonding pad 674b, and bonding pad 670b. There may be thousands of such sense amplifiers, paths, and bonding pads. Note that the BL is not necessarily directly connected to bonding pad 670b. The word line driver 660 can be electrically connected to bonding pad 674a via path 662. Relative to... Figure 6A Electrical path 608 may correspond to path 662, bonding pad 674a, and bonding pad 670a. Note that path 662 may include a separate conductive path for each word line driver 660(1)–660(n). Similarly, a separate bonding pad 674a may exist for each word line driver 660(1)–660(n). Word lines in block 2 of memory die 601 can be electrically connected to bonding pad 670a via path 664. Figure 6B In the block, for the corresponding "n" word lines, there are "n" paths 664. For each path 664, there can be a separate pair of bonding pads 670a and 674a.

[0056] Compared to Figure 5 , Figure 6A The on-die control circuitry may also include additional functions within its logic elements, including more general capabilities commonly found in memory controller 102, some CPU capabilities, and application-specific features.

[0057] In the following text, the system control logic unit 560 / 660, column control circuit system 510 / 610, row control circuit system 520 / 620 and / or controller 102 (or circuitry with equivalent function) are combined with Figure 5 The description or Figure 6A All or a subset of the other circuits on the control die 611, and Figure 5Similar elements can be considered as part of one or more control circuits that perform the functions described herein. Control circuits may consist solely of hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. Control circuits may include processors, FGAs, ASICs, integrated circuits, or other types of circuitry.

[0058] In the following discussion, Figure 5 and Figure 6A The memory arrays 502 / 602 will be discussed primarily in the context of crosspoint architecture, but much of the discussion can be applied more generally. In a crosspoint architecture, a first set of conductive lines or wires (such as word lines) extends relative to the underlying substrate along a first direction, and a second set of conductive lines or wires (such as bit lines) extends relative to the underlying substrate along a second direction. Memory cells are located at the intersections of word lines and bit lines. These memory cells at the crosspoints can be formed according to any of a variety of techniques (including those described above). The following discussion will focus primarily on implementations based on crosspoint architectures using MRAM memory cells.

[0059] Figure 7A An implementation of a memory array forming a cross-point architecture is depicted in oblique view. Figure 7A The memory arrays 502 / 602 are Figure 5 Memory array 502 or Figure 6A An example of a specific implementation of the memory array 602 is provided, wherein the memory die may include multiple such array structures. Bit lines BL1-BL5 are arranged along a first direction (indicated as extending into the page) relative to the lower substrate of the die (not shown), while word lines WL1-WL5 are arranged along a second direction perpendicular to the first direction. Figure 7A This is an example of a horizontal crossover structure, where both word lines WL1-WL5 and BL1-BL5 extend horizontally relative to the substrate, and memory cells (two of which are indicated by 701) are oriented such that the current through the memory cells (such as I) 单元 (As shown) flows vertically. In memory arrays with additional layers of memory cells, such as those described below... Figure 7D The discussion will involve corresponding additional layers for bit lines and word lines.

[0060] like Figure 7AThe depicted memory array 502 / 602 includes multiple memory cells 701. Memory cells 701 may include rewritable memory cells, such as those implemented using ReRAM, MRAM, PCM, FeRAM, or other materials with programmable resistors. The following discussion will focus on MRAM memory cells, but much of the discussion can be applied more generally. The current in the memory cells of the first memory level is shown as shown by arrow I. 单元 The direction indicated is upward, but the current can flow in either direction, as discussed in more detail below.

[0061] Figure 7B and Figure 7C They were presented respectively Figure 7A Side and top views of the intersection structure. Figure 7B The side view shows a bottom line or word line WL1 and a top line or bit line BL1-BL1. n MRAM memory cells 1201 are located at the intersections of each top and bottom line, but PCM, FeRAM, ReRAM or other technologies can be used. Figure 7C It displays M baselines WL1-WL M and N top lines BL1-BL N A top view of the intersection structure. In the binary implementation, the MRAM cell at each intersection can be programmed into one of two resistance states—a high-resistance state and a low-resistance state. Further details regarding implementation schemes for MRAM memory cell designs and their programming techniques are given below.

[0062] Figure 7A The cross-point array illustrates an implementation with a single layer of word lines and bit lines, where MRAM or other memory cells are located at the intersection of two sets of conductive lines. To increase the storage density of a memory die, multiple layers of such memory cells and conductive lines can be formed. A two-layer example is shown in... Figure 7D It is displayed in the middle.

[0063] Figure 7D An implementation of a portion of a two-level memory array forming a cross-point architecture is depicted in oblique view. (See diagram below.) Figure 7A As shown, Figure 7D The first layer 718 memory cell 701 of array 502 / 602 is shown, which is connected to the first layer word line WL. 1,1 -WL 1,4 At the intersection with bit lines BL1-BL5. The second-level memory cell 720 is formed above bit lines BL1-BL5 and at the intersection of these bit lines with the second set of word lines WL. 2,1 -WL 2,4 Between. Although Figure 7DTwo layers 718 and 720 of the memory cell are shown, but the structure can be extended upwards by additional alternating layers of word lines and bit lines. Depending on the implementation, Figure 7D The word lines and bit lines of the array can be biased for read or program operations, such that current in each layer flows from the word line layer to the bit line layer or circulates in the opposite direction. These two layers can be configured such that, for a given operation, current flows in the same direction in each layer, e.g., from the bit line to the word line for read, or current flows in opposite directions, e.g., from the word line to the bit line for layer 1 read, and from the bit line to the word line for layer 2 read.

[0064] The use of a crosspoint architecture allows for arrays with a small footprint, and several such arrays can be formed on a single die. The memory cell formed at each crosspoint can be a resistor-type memory cell, where data values ​​are encoded as different resistance levels. Depending on the implementation, the memory cell can be a binary value with a low-resistance state or a high-resistance state, or a multilayer cell (MLC) that may have an additional resistance between the low-resistance and high-resistance states. The crosspoint array described herein can be used as... Figure 4 The memory die 292 is used to replace the local memory 106, or both. Resistor-type memory cells can be formed according to many of the techniques mentioned above, such as ReRAM, FeRAM, PCM, or MRAM. The following discussion is presented primarily in the context of memory arrays using a cross-point architecture with binary-valued MRAM memory cells, but most of the discussion can be applied more generally.

[0065] Figure 8 An implementation scheme of the structure of an MRAM memory cell is shown. The voltage applied across the memory cell (between the corresponding word line and bit line of the memory cell) is represented as a voltage source V. 施加 813. The memory cell includes a bottom electrode 801, a pair of magnetic layers (reference layer 803 and free layer 807) separated by a separating layer or tunneling layer (in this example, magnesium oxide (MgO) 805), and then a top electrode 811 separated from the free layer 807 by a spacer 809. The state of the memory cell is based on the relative orientation of the magnetization of the reference layer 803 and the free layer 807: if the two layers are magnetized in the same direction, the memory cell will be in a parallel (P) low resistance state (LRS); and if they have opposite orientations, the memory cell will be in an antiparallel (AP) high resistance state (HRS). MLC implementations will include additional intermediate states. The orientation of the reference layer 803 is fixed, and... Figure 15 In the example, it is oriented upwards. Reference layer 803 is also called a fixing layer or pinning layer.

[0066] Data is written to the MRAM memory cell by programming the free layer 807 to have the same or opposite orientation. The reference layer 803 is formed such that it will maintain its orientation when the free layer 807 is programmed. The reference layer 803 can have a more complex design including a synthetic antiferromagnetic layer and additional reference layers. For simplicity, these additional layers are omitted in the figures and discussion, and only the fixed magnetic layer that is primarily responsible for the tunneling magnetoresistance in the cell is focused on.

[0067] Figure 9 An embodiment of an MRAM memory cell design implemented in a crosspoint array is shown in more detail. When placed in a crosspoint array, the top and bottom electrodes of the MRAM memory cell are two layers in adjacent conductor layers of the array, such as the top and bottom conductors of a two-level array or a dual-layer array. In the embodiment shown here, the bottom electrode is the word line 901 of the memory cell, and the top electrode is the bit line 911 of the memory cell; however, in some embodiments, these can be reversed by reversing the orientation of the memory elements. Between the word line 901 and the bit line 911 are a reference layer 903 and a free layer 907, which are also separated by an MgO barrier 905. Figure 9 In the illustrated embodiment, an MgO cladding layer 908 is also formed on top of the free layer 907, and a conductive spacer 909 is formed between the bit line 911 and the MgO cladding layer 908. The reference layer 903 is separated from the word line 901 by another conductive spacer 902. Neither side of the memory cell structure consists of liners 921 and 923, which may be part of the same structure, but... Figure 9 They appear separated in cross-section. A portion of the filling material 925, 927 used to fill the originally empty areas of the intersection structure is shown on either side of the linings 921, 923.

[0068] Regarding the free layer design 907, embodiments include a CoFe or CoFeB alloy with a thickness of approximately 1 nm to 2 nm, wherein an Ir layer may be dispersed within the free layer near the MgO barrier 905, and the free layer 907 may be doped with Ta, W, or Mo. Embodiments of the reference layer 903 may include a bilayer of CoFeB and CoPt multilayers coupled to Ir or Ru spacers 902. An MgO cladding layer 908 is optional but may be used to increase the anisotropy of the free layer 907. The conductive spacers may be conductive metals such as Ta, W, Ru, CN, TiN, and TaN, etc.

[0069] In order to sense the state of data stored in MRAM, a voltage V is applied across memory cells. 施加 The voltage is represented to determine its resistance state. To read an MRAM memory cell, the voltage difference V... 施加The bias can be applied in either direction; however, MRAM memory cells are directional, so in some cases, reading in one direction is preferred over reading in another. For example, the optimal current amplitude for writing a bit to AP (high resistance state, HRS) can be 50% or more larger than the optimal current amplitude for writing to P (low resistance state), so if AP (2AP) is read, the probability of bit error rate (read interference) is lower. Some of these cases and the resulting directionality of the read are discussed below. The directionality of the bias is particularly relevant to some implementations of MRAM memory cell programming, such as those concerning... Figure 10A and Figure 10B Further discussion is needed.

[0070] The following discussion will primarily focus on vertical spin-torque MRAM memory cells, in which... Figure 8 and Figure 9 The free layers 807 / 907 include switchable magnetization directions perpendicular to the plane of the free layer. Spin-transfer torque (“STT”) is the effect of modifying the magnetic layer orientation in a magnetic tunnel junction using a spin-polarized current. Charge carriers (such as electrons) have a property called spin, which is a small amount of angular momentum inherent to the charge carrier. The current is generally unpolarized (e.g., composed of 50% spin-up and 50% spin-down electrons). A spin-polarized current is a current with more electrons of either spin (e.g., a majority of spin-up electrons or a majority of spin-down electrons). A spin-polarized current can be generated by passing a current through a thick magnetic layer (the reference layer). If this spin-polarized current is directed into a second magnetic layer (the free layer), angular momentum can be transferred to that second magnetic layer, thereby changing the magnetization direction of the second magnetic layer. This is called spin-transfer torque. Figure 10A and Figure 10B This demonstrates the use of spin-torque magnetic random access memory (STT MRAM) for programming or writing. The advantages of STT MRAM are lower power consumption and better scalability compared to MRAM variants such as switchable MRAM. Compared to other MRAM implementations, STT switching technology requires relatively low power, which effectively eliminates the problem of adjacent bit interference and offers more favorable scaling for higher memory cell densities (reduced MRAM cell size). The latter also benefits STT MRAM, where the free layer magnetization and reference layer magnetization are oriented perpendicular to the film plane, rather than in-plane.

[0071] Because the STT phenomenon is easier to describe in terms of electron behavior, Figure 10A and Figure 10B The discussion is based on electronic current, where the direction of the writing current is defined as the direction of electron flow. Therefore, refer to... Figure 10A and Figure 10BThe term "write current" refers to electron current. When electrons are negatively charged, the electron current flows in the opposite direction to the conventionally defined current, causing the electron current to flow from a lower voltage level to a higher voltage level, instead of the conventional current flowing from a higher voltage level to a lower voltage level.

[0072] Figure 10A and Figure 10B This paper demonstrates writing to an MRAM memory cell using the STT mechanism, depicting a simplified schematic representation of an example of STT-switched MRAM memory cell 1000, where both the reference layer magnetization and the free layer magnetization are in the vertical direction. The memory cell 1000 includes a magnetic tunnel junction (MTJ) 1002 comprising an upper ferromagnetic layer 1010, a lower ferromagnetic layer 1012, and a tunnel barrier (TB) 1014, which acts as an insulating layer between the two ferromagnetic layers. In this example, the upper ferromagnetic layer 1010 is the free layer FL, and its magnetization direction can be switched. The lower ferromagnetic layer 1012 is the reference (or fixed) layer RL, and its magnetization direction cannot be switched. When the magnetization in the free layer 1010 is parallel to the magnetization in the reference layer RL 1012, the resistance across the memory cell 1000 is relatively low. The resistance across memory cell 1000 is relatively high when the magnetization in the free layer FL 1010 is antiparallel to the magnetization in the reference layer RL 1012. Data (“0” or “1”) in memory cell 1000 is read by measuring the resistance of memory cell 1000. For this purpose, electrical conductors 1006 / 1008 attached to memory cell 1000 are used to read MRAM data. By design, both the parallel and antiparallel configurations remain stable in the quiescent state and / or during read operations (at sufficiently low read current).

[0073] For both the reference layer RL 1012 and the free layer FL 1010, the magnetization direction is in the vertical direction (i.e., perpendicular to the plane defined by the free layer and perpendicular to the plane defined by the reference layer). Figure 10A and Figure 10B As shown, the magnetization direction of the reference layer RL 1012 is upward, and the magnetization direction of the free layer FL 1010 can switch between upward and downward, and it is also perpendicular to the plane.

[0074] In one embodiment, the tunnel barrier 1014 is made of magnesium oxide (MgO); however, other materials may also be used. The free layer 1010 is a ferromagnetic metal with the ability to change / switch its magnetization direction. Multilayers based on transition metals such as Co, Fe, and their alloys can be used to form the free layer 1010. In one embodiment, the free layer 1010 comprises an alloy of cobalt, iron, and boron. The reference layer 1012 can be made of many different types of materials, including (but not limited to) multilayers of cobalt and platinum and / or alloys of cobalt and iron.

[0075] In order to "set" the bit value of the MRAM memory cell (i.e., select the direction of free layer magnetization), an electronic write current 1050 is applied from conductor 1008 to conductor 1006, such as... Figure 10A As depicted. To generate the electron write current 1050, the top conductor 1006 is placed at a higher voltage level than the bottom conductor 1008 due to the negative charge of the electrons. Electrons in the electron write current 1050 become spin-polarized as they pass through the reference layer 1012, which is a ferromagnetic metal. When the spin-polarized electrons tunnel through the tunnel barrier 1014, the conservation of angular momentum can cause a spin-transfer torque to be applied to both the free layer 1010 and the reference layer 1012, but this transfer torque is insufficient (by design) to affect the magnetization direction of the reference layer 1012. Instead, if the initial magnetization orientation of the free layer 1010 is antiparallel (AP) to the reference layer 1012, this spin-transfer torque (by design) is sufficient to switch the magnetization orientation in the free layer 1010 to parallel (P) to the magnetization orientation of the reference layer 1012; this is called antiparallel to parallel (AP2P) writing. The parallel magnetization will then remain stable before and after this electron write current is turned off.

[0076] In contrast, if the magnetization of the free layer 1010 and the reference layer 1012 are initially parallel, the magnetization direction of the free layer 1010 can be switched to be antiparallel to the reference layer 1012 by applying an electron writing current in the opposite direction to the aforementioned case. For example, as Figure 10B As depicted, an electron writing current 1052 is applied from conductor 1006 to conductor 1008 by applying a higher voltage level across the lower conductor 1008. This writes the free layer 1010, which is in the P state, to the AP state, a process known as parallel-to-antiparallel (P2AP) writing. Therefore, via the same STT physics, the magnetization direction of the free layer 1010 can be deterministically set to either of two stable orientations by carefully selecting the direction (polarity) of the electron writing current.

[0077] Data ("0" or "1") in memory cell 1000 can be read by measuring the resistance of memory cell 1000. Low resistance typically indicates a "0" bit, and high resistance typically indicates a "1" bit, but sometimes alternative conventions apply. An electronic read current (e.g., ) is applied from conductor 1008 to conductor 1006. Figure 10A For the flow shown in 1050 (“AP2P direction”), a read current can be applied across memory cells (e.g., across magnetic tunnel junction 1002); alternatively, an electronic read current can be applied from conductor 1006 to conductor 1008, such as... Figure 10BThe flow is shown in Figure 1052 (“P2AP direction”). During a read operation, if the electronic write current is too high, it can interfere with the data stored in the memory cell and alter its state. For example, if the electronic read current uses… Figure 10B In the P2AP direction, excessively high current or voltage levels can switch any memory cell in the low-resistance P state to the high-resistance AP state. Therefore, although MRAM memory cells can be read in either direction, in various implementations, the directional nature of the write operation can make one read direction take precedence over another, such as the P2AP direction, because writing bits in that direction requires more current.

[0078] although Figure 10A and Figure 10B The discussion is conducted in the context of electronic currents for reading and writing currents, but unless otherwise specified, the subsequent discussion will be conducted in the context of normal currents.

[0079] Whether reading or writing Figures 7A to 7D In the array structure, the selected memory cells, corresponding to the bit lines and word lines of the selected memory cells, are biased to apply a voltage across the selected memory cells and induce electron flow, as per [reference to...]. Figure 10A or Figure 10B As shown, this will also apply voltage across the unselected memory cells of the array, which can induce current in the unselected memory cells. Although this wasted power consumption can be mitigated to some extent by designing the memory cells to have relatively high resistance levels for both high-resistance and low-resistance states, it will still result in increased current and power consumption, as well as additional design constraints on the design of the memory cells and the array.

[0080] One way to address this unwanted current leakage is to place the selector element in series with each MRAM or other resistive (e.g., ReRAM, PCM, and FeRAM) memory cell. For example, in Figures 7A to 7D In this configuration, the select transistor can be placed in series with each resistive memory cell element, making element 701 a composite of a selector and a programmable resistor. However, using transistors requires introducing additional control lines to enable the corresponding transistor for the selected memory cell. Furthermore, transistors typically do not scale in the same way as resistive memory elements, making the use of transistor-based selectors a limiting factor when memory arrays are moved to smaller sizes.

[0081] An alternative method for selecting elements is to use a threshold switch selector device connected in series with a programmable resistive element. A threshold switch selector has high resistance (in an off or non-conductive state) when biased to a voltage below its threshold voltage and low resistance (in a conducting or conductive state) when biased to a voltage above its threshold voltage. The threshold switch selector remains on until its current drops below the holding current, or the voltage drops below the holding voltage. When this occurs, the threshold switch selector returns to the off state. Therefore, to program a memory cell at a crossover point, a voltage or current sufficient to turn on the associated threshold switch selector and set or reset the memory cell is applied; and similarly, to read a memory cell, the threshold switch selector must be activated by turning on before the resistance state of the memory cell can be determined. One example of a threshold switch selector is a bidirectional threshold switch (OTS) material.

[0082] Figure 11A and Figure 11B An implementation scheme for incorporating a threshold switch selector into an MRAM memory array with a crosspoint architecture is demonstrated. Figure 11A and Figure 11B The example shows two MRAM cells in a two-layer crosspoint array, such as Figure 7D As shown, however, it is shown in a side view. Figure 11A and Figure 11B The diagram shows the lower first conductive line, i.e., word line 11100; the upper first conductive line, i.e., word line 2 1120; and the middle second conductive line, i.e., bit line 1110. In these figures, for ease of presentation, all these lines are shown extending from left to right across the entire page; they will be more accurately represented by an array of intersections, as shown below. Figure 7D The oblique view represents a scene where word lines or first conductive lines or wires extend in a direction parallel to the surface of the underlying substrate, and bit lines or second conductive lines or wires extend in a second direction parallel to the surface of the substrate, the second direction being substantially orthogonal to the first direction. MRAM memory cells are also represented in a simplified form, showing only the base layer, free layer, and intermediate tunnel barrier; however, in actual implementations, the above-described... Figure 9 The aforementioned additional structure.

[0083] An MRAM cell 1102, comprising a free layer 1101, a tunnel barrier 1103, and a reference layer 1105, is formed above a threshold switch selector 1109. This series combination of the MRAM device 1102 and the threshold switch selector 1109 forms a layer 1 cell between bit line 1110 and word line 11100. Aside from some voltage drop across the threshold switch selector 1109, the series combination of the MRAM device 1102 and the threshold switch selector 1109 largely behaves as described above when the threshold switch selector 1109 is on. Figure 10A and Figure 10B It operates as described. However, initially, it is necessary to apply a threshold voltage V higher than that of the threshold switch selector 1109. 阈值 The voltage is used to turn on the threshold switch selector 1109, and then the bias current or voltage needs to be maintained high enough to exceed the holding current or holding voltage of the threshold switch selector 1109 so that it remains on during subsequent read or write operations.

[0084] On the second layer, MRAM cell 1112 includes a free layer 1111, a tunnel barrier 1113, and a reference layer 1115 formed above a threshold switch selector 1119. The series combination of MRAM device 1112 and threshold switch selector 1119 forms a layer 2 cell between bit line 1110 and word line 2 1120. The layer 2 cell operates as a layer 1 cell, but the lower conductor now corresponds to bit line 1110, and the upper conductor is now the word line, i.e., word line 2 1120.

[0085] exist Figure 11A In one implementation, the threshold switch selector 1109 / 1119 is formed below the MRAM device 1102 / 1112; however, in another implementation, the threshold switch selector may be formed above the MRAM device for one or two layers. (See also: Regarding...) Figure 10A and Figure 10B The MRAM memory cells discussed are directional. Figure 11A In this embodiment, MRAM devices 1102 and 1112 have the same orientation, with free layers 1101 / 1111 above reference layers 1105 / 1115 (relative to a substrate not shown). Forming these layers between conductive lines having the same structure can have many advantages, especially for processing, because each of these two layers, as well as subsequent layers in embodiments with more layers, can be formed according to the same processing sequence.

[0086] Figure 11B Showing with Figure 11A A similar alternative implementation scheme, the difference being that in layer 2 units, the positions of the base layer and the free layer are reversed. More specifically, as... Figure 11AAs shown, between word line 11150 and bit line 1160, layer unit 1 includes MRAM structure 1152, which has a free layer 1151 formed above tunnel barrier 1153, which in turn is formed above base layer 1155, wherein MRAM structure 1152 is formed above threshold switch selector 1159. Figure 11B The second layer of the implementation also has an MRAM device 1162 formed between bit line 1160 and word line 2 1170 above threshold switch selector 1169, but relative to Figure 11A MRAM device 1162 is inverted such that base layer 1161 is now formed above tunnel barrier 1163 and free layer 1165 is now formed below tunnel barrier 1163.

[0087] Although Figure 11B The implementation scheme requires different processing sequences to form these layers, but in some implementation schemes, it can have advantages. Specifically, the orientation of the MRAM structure can make... Figure 11B The implementation is attractive because when writing or reading in the same direction (relative to the reference layer and the free layer), the bit line will be biased by the same amount for both the lower and upper layers, and the two word lines will also be biased by the same amount. For example, if both layer 1 memory cells and layer 2 memory cells are sensed in the P2AP direction (relative to the reference layer and the free layer), bit line layer 1160 will be biased as in the P2AP direction, bit line 1160 will be biased low (e.g., 0V) for both the upper and lower cells, and word line 1 1150 and word line 2 1170 will both be biased to a higher voltage level. Similarly, for writing, to write the high-resistance AP state, bit line 1160 is biased low (e.g., 0V) for both the upper and lower cells, and word lines 1 1150 and 2 1170 are both biased to higher voltage levels; and for writing the low-resistance P state, bit line 1160 is biased to a high voltage level, and word lines 1 1150 and 2 1170 are both biased to a low voltage level. In contrast, for Figure 11A In the implementation scheme, bit lines and word lines will need to have their bias levels reversed so that either of these operations can be performed relative to a lower level on a higher level.

[0088] Reading data from or writing data to an MRAM memory cell involves passing current through the memory cell. In embodiments where the threshold switch selector is placed in series with the MRAM device, sufficient voltage needs to be applied across the series combination of the threshold switch selector and the MRAM device to turn on the threshold switch selector before current can pass through the MRAM device. Figure 12 and Figure 13This activation of the threshold switch selector is considered in more detail within the context of the read operation.

[0089] Figure 12 and Figure 13 In the read operation, they are respectively used for Figure 11A and Figure 11B An implementation of a set of waveforms of current and voltage in layer 1 unit, wherein Figure 12 and Figure 13 The time axes are aligned and at the same scale. In this embodiment for the read operation, the read is performed in the P2AP direction, where word lines 1100 / 1150 are biased high and bit lines 1110 / 1160 are set low (e.g., 0V), causing (conventional) current to flow upwards, first through the reference layer 1105 / 1155, then through the free layer 1101 / 1151. (In terms of electron current, the electron flow will be the opposite of the conventional current, as follows...) Figure 10B As shown.

[0090] exist Figure 12 and Figure 13 In the implementation scheme, a forced current method is used, wherein the memory draws a read current I from the reference layer side using a current source from the driver circuitry system for the line. 读取 Driver. For example Figure 12 As shown by solid line 1201, the current increases to I. 读取 The value is retained for the duration of the current read operation. This current will move the supply current to the line of the selected memory cell, such as... Figure 11A Word lines 1 1100 / 1150 of the layer 1 memory cell in / B, and also support any leaks in the path. Figure 13 As shown at point 1251, when the threshold switch selector is in the off state, the current ramps up across the parallel combination of the threshold switch selector and the resistive MRAM element. Once the voltage across the threshold switch selector reaches the threshold voltage V of the threshold switch selector at point 1253... 阈值 The threshold switch selector will then be turned on and switched to a low resistance state.

[0091] Once the threshold switch selector is in the ON state, I 读取 Current will then flow through the selected memory cell. This is caused by... Figure 12 The dashed line 1203 illustrates that when the threshold switch selector is turned on at 1253, it retransmits the current through the memory cell, jumping from zero to I. 读取 When the current level remains fixed at I 读取At this time, the voltage across the memory cell will drop to a level dependent on the series resistance of the MRAM device and the on-state resistance of the threshold switch selector. For a binary implementation, the memory cell will have a high-resistance antiparallel state and a low-resistance parallel state. The resulting voltage across the series-connected MRAM device and threshold switch selector, as well as the series-connected decoder transistor, responds to the IS of the high-resistance state (HRS) and the low-resistance state (LRS). 读取 The current is directed to one of the N word lines and one of the N bit lines, shown as 1255 and 1253, respectively. The resulting voltage difference can then be measured by a sense amplifier to determine the state of the data stored in the memory cell. Although the discussion here is in the context of an MRAM-based memory cell placed in series with a threshold switch selector, this read technique can be similarly applied to other programmable resistive memory cells, such as PCM, FeRAM, or ReRAM devices.

[0092] Figure 13 The voltage is shown to be applied at 1251 in a ramp-up manner until it reaches V at 1253. 阈值 Then it drops to the high-resistance state at 1255 or the low-resistance state at 1253. In actual devices, due to resistance and capacitance, there will be some delay when the voltage spike at 1253 drops to 1255 or 1253. This is caused by... Figure 14 An example is shown for the low resistance state.

[0093] Figure 14 An example of the voltage across an MRAM device is shown when the threshold switch selector switches from an off state to an on state. Relative to Figure 13 , Figure 14 The voltage V across the MRAM device is shown only. MRAM ,and Figure 13 This represents the voltage across the series combination of the threshold switch selector and the MRAM device. Initially, before the threshold switch selector is turned on, the applied voltage ramps up to V. 阈值 The voltage across the MRAM device will be zero. Once the threshold switch selector is turned on, current begins to flow through the MRAM device, and the voltage across the MRAM device will spike to V. 阈值 Level minus the voltage drop V of the cross-threshold switch selector 保持 Therefore, V MRAM The jump will be from 0V to ΔV = (V 阈值 –V 保持 ), after which it will respond to the applied I 读取 This allows the voltage drop across the MRAM device to decay under low resistance conditions, V MRAM (LRS).

[0094] VMRAM The voltage drops to near the asymptotic V MRAM The rate of the (LRS) level depends on the "breakback voltage" ΔV (which is (V 阈值 –V 保持 The peak of the difference between V MRAM The magnitude of the LRS (Low Reduction Syndrome) and the rate at which charge can flow out of the device depend on the internal resistances of the MRAM and the selector when the selector is on, the RC characteristics of the memory cell and the wire connecting the memory cell therebetween. For lower capacitance and lower resistance, dissipation is faster. This behavior has some practical implications for the operation of the memory cell.

[0095] The first effect is that both the low-resistance and high-resistance states will experience attenuation, such as... Figure 14 As shown, where Figure 14 The low-resistance state is shown. The high-resistance state will exhibit similar behavior, but with a higher asymptotic state V ultimately determined by the path resistance ×I read. To distinguish between these two states, they need to be separated by a sufficient margin so that sensing operation can not be performed until a sufficient amount of time has elapsed, so that the two states have well-defined and distinguishable voltage levels.

[0096] Another impact is that spikes can interfere with data stored in memory cells. (For example, regarding...) Figure 10A and Figure 10B The discussed approach involves altering the state of an MRAM memory by allowing current to flow through the memory cell, such that if the voltage across the memory cell and / or the current through the memory cell is sufficiently high for a sufficiently long period, it will change from a parallel state to an antiparallel state (P2AP write) depending on the current direction. Figure 10B As shown, or changing the anti-parallel state to a parallel state (AP2P write), such as Figure 10A As shown. For example, Figure 12 and Figure 13 The reading process is described as being performed in the P2AP direction, making... Figure 14 Interference caused by the waveform can switch a low-resistance memory cell to a high-resistance state before the data state can be stored.

[0097] As described above, the threshold switch selector controls access to memory cells. Specifically, in order to apply voltage or current to a memory cell to change its resistance state, the corresponding selector must first apply a sufficiently high voltage (e.g., an amplitude higher than the operating threshold voltage V). 阈值 The selector switches to a conductive state by adjusting the voltage across it. When the selector is in a non-conductive state, for example, when the voltage across the selector is below the operating threshold voltage, the memory cell is isolated and maintains its existing resistive state.

[0098] Threshold voltage V of threshold switch selector 阈值 and holding voltage V 保持 The threshold voltage depends on both the inherent and non-inherent characteristics of the selector, including its material composition, thickness, electrode composition, lining material, heat dissipation, and cycling history. Chalcogenide selectors, constructed from binary, ternary, or quaternary alloys of Ge, Se, Te, and As and doped with B, C, Si, N, O, Zn, and / or In, can have a threshold voltage ranging from 0.5V to 6V and a holding voltage ranging from 0.5V to 3V. The exact voltage will depend on the thickness, with thicker selectors typically having a higher threshold voltage and possibly a slightly higher offset voltage. The V of a threshold switch selector... 阈值 The higher the value, the more effective the disconnection state, but the larger the spike, such as... Figure 13 As shown. Therefore, the choice of selector design is based on the decision of the specific memory application to which it will be applied.

[0099] One characteristic of materials used in threshold switch selectors (such as bidirectional threshold switches) is the threshold voltage V of the material. 阈值 This voltage can drift over time, becoming higher as the device ages, or more specifically, based on the time since the threshold switch selector was last turned on. This can lead to problems such as increased error rate (bit interference) and reduced durability, because it requires a higher voltage to turn on the threshold switch selector, making it possible for V to drift higher. 阈值 If the voltage becomes too high, the memory cell may become inaccessible unless the ability to generate a higher voltage level is available; and even if the memory device can turn on the threshold switch selector, this will result in... Figure 13 The voltage spikes are larger, which may increase the likelihood of data interference or damage to resistive memory cells.

[0100] The following discussion presents techniques for power-off recovery of memory devices using threshold switch selectors connected in series with resistive memory elements. Although presented in the context of MRAM-based crosspoint memory structures, these techniques can be more generally applied to other memory cells in which non-volatile elements (such as resistive PCM or ReRAM) are connected in series with threshold switch selectors, due to the focus on the characteristics of the threshold switch selectors. Therefore, the techniques disclosed in this invention are applicable to any form of crosspoint array in which memory cells are connected between orthogonal layer conductive lines (e.g., tungsten or copper wires).

[0101] As discussed above, series-connected threshold switch selectors (such as bidirectional threshold switches) have a voltage V 阈值 When this voltage is applied across the selector, the selector switches it to a lower V for the selected memory cell.保持 Voltage. In practice, when used in actual memory devices, these values ​​can vary with the processing involved in forming the device, such that, on a given device, V 阈值 The range varies depending on the processing method, for example, from 1.6V to 2.35V. 阈值 The value can increase over time due to "drift," such as from 10 mV to 50 mV every decade. Therefore, V 阈值 The drift in value can further increase V over a period of 10 decades. 阈值 A change of 500mV, for example, might result in a higher V. 阈值 The value increased to 2.85V. Although V 阈值 In some cases, drift may occur due to general aging or wear, but the amount of drift is primarily based on the time since the memory cell was last activated and the threshold switch selector was turned on. When the device is in use and powered on, techniques such as "loss leveling" algorithms can access each memory cell for a period of time (e.g., 10 hours). Through such mechanisms, V 阈值 Drift can be limited during operation, but such active management of drift is impossible during power outages, which can last for years.

[0102] V that can be processed 阈值 The maximum value is limited by the available power supply on the memory device. If excessive V occurs during a device power outage... 阈值 Drift, then V 阈值 This may exceed the voltage that the device can apply to the memory cell; this would be the power supply level minus any losses in the path to the memory cell (i.e., any leakage current multiplied by the path resistance). To overcome this problem, the available power supply level can be temporarily increased during power-up to ensure memory cell selection and V... 阈值 Reset. However, this may require the introduction of circuitry that is not normally available on memory devices, such as charge pumps and additional conditioning circuitry, which consumes area and increases complexity and power consumption.

[0103] Even if the required voltage is available, the threshold switch selector's V 阈值 Any increase will increase the "quick return" voltage ΔV = (V) upon switching on. 阈值 –V 保持 ), and the spike (such as Figure 14 (As shown) applied across MRAM devices connected in series (or more generally, other memory devices connected in series with a threshold switch selector). Due to the higher maximum V 阈值An increase in ΔV can increase the likelihood of bit switching in MRAM memory cells before the storage level is selected for reading. For example, reading a cascaded MRAM and threshold switch selector in the direction of writing to AP (P2AP) carries the risk of bits switching from P to AP, while bits already in the AP state are "safe." Since either bit state is possible at the start of a read, if ΔV is too large, the data content of the MRAM device may be lost due to the induced transient, resulting in irreversible damage to the stored user data. The mechanism can vary, but other forms of memory technology used with threshold switch selectors (ReRAM, PCM, etc.) may similarly experience data interference or damage from such large transients.

[0104] If data is stored in the device and then the power is turned off, the device time before power is applied and all bits are accessed may exceed the "power-on" time, for example, 10 hours between bit accesses during normal operation. This time-based access to all bits during power-on can be ensured, for example, through wear leveling, where each bit is accessed and / or relocated at a specific time. For embedded non-volatile memory (eNVM), the expected data retention period in the absence of power can be beyond 10 years. If V 阈值 Because the device was specified at 3 months and therefore excessively drifted, but customers store the device for longer periods without power, the device's data may need to be reloaded from storage rather than used directly from memory (e.g., "immediate power-on"). Therefore, the challenge is to determine V 阈值 Has the drift exceeded V? 阈值 The maximum allowed value, and the decision of whether to rely on the data stored in memory or to reload.

[0105] Figure 15 V is used to determine the threshold switch selector. 阈值 A high-level flowchart of an implementation of whether the data has drifted to an excessively high value and whether it should be reloaded into the memory device. Figures 16 to 18 A more detailed presentation of the implementation plan is provided. Figure 15 In this process, the procedure is used for the operation of a memory device that has been previously programmed and is in operation, and then powered off.

[0106] At step 1501, the memory device is powered down. This can be part of an appropriate shutdown, which may be in response to commands from the system's control circuitry, such as from system control logic unit 560 / 660, from controller 102, or host 120, or an inappropriate shutdown due to power loss. If the power down is an appropriate shutdown, in some embodiments, the time value of the power down may be stored in a register (such as register 561 / 661 or a register in controller 102). In some embodiments, system control logic unit 560 / 660 may maintain and periodically update a timestamp that can be referenced in the case of an appropriate or inappropriate shutdown.

[0107] At a later time, the device is powered on at step 1503, where the power-on command may originate from system control logic unit 560 / 660, from controller 102, or from host 120, such as as part of an access request. As part of the power-on procedure, step 1505 determines the V of the threshold switch selector. 阈值 Is it possible that the value has drifted to an excessively high level? According to this implementation, V can be inferred through testing procedures, by tracking device downtime, or a combination of these. 阈值 These are respectively from Figure 16 , Figure 17 and Figure 18 Further demonstration. If step 1505 determines V 阈值 The value does not appear to have drifted too far, and if the device is powered on to perform a read or other operation, that operation can be performed at step 1507.

[0108] If the steps are determined, V 阈值If the value exhibits excessive drift, remedial action, such as reloading the data stored in the device, is taken at step 1509 before the operation in step 1507 can be performed. The path from step 1509 is shown as a dashed line because in some embodiments, the operation may be canceled due to the time required for data reloading. The device may also send a notification to controller 102 or host 120 that the data should be reloaded. In some embodiments, the data can be reloaded from outside the device, such as from other non-volatile locations on the memory system or from a host used as a backup (e.g., from an HDD or SSD). For example, if MRAM crosspoint memory is used as local memory 106 by controller 102, the data may also be stored in a mass storage device (such as memory package 104) of the memory system from which it can be reloaded. In other cases, where data is stored redundantly (e.g., in a RAID configuration), data on one device within memory package 104 can be replaced from other locations within memory package 104. In other cases, data stored on the memory device can be recovered and erased, so that if the data can be read even under conditions of significant interference, the data content can be recovered and rewritten to the memory device via the controller's ECC capability.

[0109] In one set of implementations, the threshold voltage of the threshold switch selector is inferred during power-up as part of a test process to determine if drift is excessive. During the test, a subset of memory cells is read (or attempted to be read). The feasibility of this test depends on whether the memory interface allows for a power-on delay upon restart that is long enough to perform the test. One test is a simple on-detection test using the same selection circuitry system of the row control circuitry system 520 / 620 and the column control circuitry system 510 / 610, which selects… Figures 5 to 6B One or more memory cells in memory arrays (“blocks”) 502 / 602. Due to the resistance in the lines connecting the memory cells to the array drivers 524 / 624 of the row control circuitry system 520 / 620 to drive word lines and to the driver circuitry system 514 / 614 of the column control circuitry system 510 / 610 to drive bit lines, the voltage seen at the memory cell will differ from the voltage provided by the driver by an amount depending on the location of the memory cell. With this in mind, in some embodiments, the on-detection test can be performed by accessing the “farthest” memory cell along the line resistance (e.g., such as…). Figure 6B The effect is replicated by maximizing any IR voltage drop that may be seen on the array (top left corner of array 602). If the memory cell is turned on, V can be determined. 阈值 It wasn't too big.

[0110] During an alternative read test at power-up, a dedicated programming codeword (256 bits or longer) that is maintained during operation with a known set of values ​​can be stored in the memory array. At power-up, the known dedicated codeword can be read, and the read value can be compared to the stored known value to determine the number of bit errors. If the number of bit errors exceeds a given target (e.g., 1%), drift is determined to be excessive. For either power-up read test, to better ensure worst-case testing, both tests are run at sufficiently low supply voltages to ensure excessive drift is detected. If the array fails to pass V at a lower level... 阈值 If a read test is performed, one possible remedy is to then read the memory with a higher voltage to see if the data content can be extracted and erased.

[0111] Figure 16 It is used to determine V by using a read test as part of the power-on process. 阈值 A flowchart of one implementation of excessive drift. At step 1601, the memory device (such as...) Figure 5 The memory device 500, or Figure 6A and Figure 6B The memory die 601 or memory system 600 receives a power-on command. The power-on command can come from the system control logic unit 560 / 660, from the controller 102, or from the host 120, depending on the level at the time of the previous power failure.

[0112] At step 1603, the power-on sequence begins. In addition to the usual operations involved, a read test on a selected subset of memory cells is performed to determine if a significant V was present when the device was powered down. 阈值 Drift. Read tests can be performed as in the examples above, such as reading word lines or bit lines from one or more arrays on the device, such as by accessing the "far-off" memory cell furthest from drivers 524 / 624 and 514 / 614 along the conductive lines connecting the memory cells to the access circuitry, or such as by reading a set of memory cells storing known pattern data for that purpose. To ensure sufficient operational margin, for any of these read tests, the test can be performed using read voltage and / or current levels from array drivers 524 / 624 and driver circuitry 514 / 614 that are reduced relative to the levels used in standard data access read operations. In some embodiments, if the reduced voltage and / or current is insufficient to turn on some or all of the threshold switch selectors, standard read levels or even elevated read levels can be applied by array drivers 524 / 624 and driver circuitry 514 / 614 to see if this is sufficient to turn on the threshold switch selectors.

[0113] Such as about Figure 13 The threshold voltage of the drifting threshold switch selector discussed may exceed the maximum voltage applied during the selection process. In this case, the threshold switch selector will not turn on during the data reload process, and the user data on the chip will be corrupted. To ensure that the drifting threshold switch selector turns on, in some embodiments, the maximum available voltage can be temporarily increased. During the turn-on ramp performed by the control circuitry, the maximum available voltage can be increased by increasing the voltage available in the row control circuitry system 520 / 620, the column control circuitry system 510 / 610, or both. If the available voltage is limited by the supply voltage, the supply voltage can be temporarily increased by the circuitry system (e.g., a regulator or charge pump in the generator circuitry of the system control logic unit 560 / 660). A higher available voltage is selected to ensure a sufficiently low failure rate of the un-turned threshold switch selectors. For example, the increase in available voltage can be in the range of 0.1V to 1.0V. Once all the threshold switch selectors on the memory die have been cycled with the higher voltage, the available voltage returns to the normal value used in the data read, and the data can be reloaded from the memory device. If the data reload process cycles through all selectors on the chip, the need to cycle through all selectors before data reload can be avoided. A higher available supply voltage allows higher gate, source, and drain voltages to be applied to the transistors in the row control circuitry 520 / 620 and column control circuitry 510 / 610. Both have the effect of increasing the available voltage and current that can be supplied to the crosspoint array by the control circuitry. If the selection process is performed by circuitry capable of providing the requested current rather than the requested voltage, a higher available voltage enables the provision of a higher current, which in turn allows a higher voltage to be applied to the selected cell.

[0114] Step 1605 determines whether the device passes the test. The test can be performed, for example, by system control logic unit 560 / 660, while in other embodiments, it can be performed at a higher level within the system. For example, if the test involves decoding ECC codewords, the test can be performed at controller 102 to utilize ECC engine 226 / 256. For simple read operations, the test can simply be performed by detecting whether current flows through the memory cells at a low or high resistance level to see if a subset of memory cells or a certain threshold number of that subset fails to connect.

[0115] If the read test is used to read a set of memory cells storing a predetermined pattern, the test can be a comparison in system control logic 560 / 660 to compare only the read data with data of a known stored pattern. For example, system control logic 560 / 660 can maintain a copy of the data pattern in register 561 / 661. The determination in step 1605 can then be based on whether the read data matches the pattern or matches within a threshold bit error rate.

[0116] If one or more memory arrays pass V at step 1605 阈值 If the read test is successful, the power-up process can be completed, and the array read, programming, or other operations targeted by the power-up can be performed at step 1611. Conversely, if the test fails at step 1605, then at step 1607, the system control logic unit 560 / 660 can notify the controller 102 and / or the host 120 that there may be excessive V. 阈值 Drift. At step 1611, the data is then reloaded at step 1609, which can be done as described above regarding... Figure 15 The operation is performed as described in step 1509. According to the implementation, several variations are available at steps 1607 and 1609. For example, in response to a notification at step 1607, controller 102 or host 120 may instruct memory 500 / 600 to proceed and attempt to read or otherwise access the memory before or instead of reloading the data at step 1609. For example, if the test is performed using a reduced read voltage and / or current level, access may be attempted at a standard level or even an elevated level of voltage and / or current. Since reloading can take a significant amount of time, host 120 or controller 102 may decide to wait and continue the access at step 1611 once the data is reloaded, or may decide to cancel the operation or access the data from a redundant storage location (if available). In some implementations, reloading can be performed in a prioritized manner, where the data to be accessed is first reloaded and made available to the host, and then reloaded at a different address in an operation that may be a background operation.

[0117] In another set of embodiments, a power-down tracking method can be used. In this method, controller 102, system, or (if not power-down) control logic unit 560 / 660 can use its on-chip serial ID to track the "disconnect" time or the time the device is disabled, such as by maintaining and periodically updating timestamps, to track the duration of the disconnect time to determine if the power-off time is excessive. In other embodiments, the power-down time can be recorded, such as in register 561 / 661 on the system control logic unit 560 / 660 of the memory device or at the level of the system or controller 102, and read as a mode register upon power-up to determine if the power-down time is excessive. If the time since the previous power-down exceeds a certain threshold, such as 3 months, controller 102, host 120, or system control logic unit 560 / 660 can determine V 阈值 Is it possible that the data has been over-increased, and a decision has been made to reload the data instead of relying on the stored data, because the bit error rate (BER) of the data may have increased excessively and cannot be recovered unless reloaded?

[0118] Figure 17 It is used to determine whether there is excessive V based on the amount of time the memory device is powered down using a power-down tracking method. 阈值 A flowchart of one implementation scheme for drifting. Step 1701 can be related to... Figure 16 Step 1601 is largely the same, and a more typical portion of the power-on sequence in step 1703 can also be so. The difference between step 1703 and step 1603 will lie in how the memory determines V. 阈值 Is it possible that the value has drifted too much?

[0119] More specifically, in step 1703, a power-off tracking method is used. As discussed in the previous two paragraphs, controller 102, the system, or (if not powered down) control logic unit 560 / 660 can track "disconnect" times by maintaining and periodically updating timestamps or by recording power-on times (e.g., using register 561 / 661 or at the system or controller 102 level), and reading them as mode registers upon power-up to determine if the power-off time was excessive. Step 1705 determines whether the device passes a test, which can be performed, for example, by system control logic unit 560 / 660, while in other embodiments, it can be performed at a higher level in the system. Figure 17 In this implementation, the test is based on the time since the previous power outage and determines whether it exceeds a certain threshold, such as 3 months. At step 1705, controller 102, host 120, or system control logic unit 560 / 660 can determine the V of the elapsed time. 阈值Has the value exceeded the threshold? Based on the result of step 1705, the process can continue to steps 1707, 1709, and 1711, which can be performed as described above. Figure 16 As described in steps 1607, 1609 and 1611.

[0120] Figure 18 It is a combination Figure 16 and Figure 17 The flowchart illustrates the implementation scheme of the method. Memory systems may sometimes have a specified amount of time allocated to the power protocol. Figure 16 The process involves reading a portion of the memory cells on the array, which is typically more time-consuming than determining the amount of time since the last access to the memory device. Figure 18 In the mixing method, first check Figure 17 The time-based method is used, and if the actual time consumed exceeds a threshold, a read-based test is performed.

[0121] exist Figure 18 In the process, steps 1801, 1803, and 1805 can be as described above regarding steps 1701, 1703, and 1705, except that if the test in step 1805 passes, the process proceeds to step 1815 (which can be as described above regarding...). Figure 16 Step 1611 or Figure 17 (as described in step 1711), and if the test fails, the process proceeds to step 1807. Read-based tests are performed in steps 1807 and 1809. At step 1807, a selected set of memory cells is read, which can be done as described above regarding... Figure 17 This part of the power-on sequence in step 1703 is discussed. Step 1809 performs a read-based test, which can be performed as described above regarding... Figure 16 As described in step 1605. As discussed above, in some embodiments, in response to determining that the threshold voltage of the threshold switch selector has drifted to an excessively high value, the available voltage for turning on the threshold switch selector increases from a first maximum value to a second maximum value, all selectors on the memory die cycle, the available voltage for turning on the selectors returns to the first maximum value, and the data is reloaded into the array. If the test in step 1809 passes, the process can proceed to step 1815; if the test in step 1809 fails, the process proceeds to steps 1811 and 1813, which can proceed as described above regarding... Figure 16 As described in steps 1607 and 1609.

[0122] According to the first aspect, the device includes control circuitry configured to be connected to one or more arrays of a plurality of non-volatile memory cells, each memory cell including a programmable resistive element connected in series with a threshold switch selector configured to become conductive in response to an applied voltage level exceeding a corresponding threshold voltage. The control circuitry is configured to: power on one or more arrays for an access operation; perform an access operation on one or more memory cells in the arrays after powering on the one or more arrays; and power off the one or more arrays. The control circuitry is further configured to, following a previous power-off of the one or more arrays before powering on the one or more arrays for the purpose of performing an access operation, determine whether a threshold voltage of a threshold selection device exhibits excessive drift; and, in response to determining that the threshold voltage of the threshold selection device exhibits excessive drift, reload data into the one or more arrays.

[0123] In an additional aspect, the method includes powering down a memory array comprising a plurality of memory cells, each memory cell including a programmable resistive element connected in series with a threshold switch selector configured to become conductive in response to an applied voltage level exceeding a corresponding threshold voltage. The method also includes subsequently powering up the memory array, the power-up including determining whether the threshold voltage of the threshold switch selector has drifted to an excessively high value. In response to determining that the threshold voltage of the threshold switch selector has drifted to an excessively high value, data stored in the memory array is reloaded.

[0124] In another aspect, the non-volatile memory device includes a memory array and one or more control circuits connected to the memory array. The memory array has a cross-point architecture, with memory cells located at each cross-point of the array. Each of these memory cells includes a magnetoresistive random access memory (MRAM) device connected in series with a threshold switch selector, which is configured to become conductive in response to the application of a voltage level exceeding a corresponding threshold voltage. One or more control circuits are configured, as part of a power-on process, to determine whether the threshold voltage of the threshold switch selector has drifted to an excessively high value, and in response to determining that the threshold voltage of the threshold switch selector has drifted to an excessively high value, to reload the data stored in the memory array.

[0125] For the purposes of this document, the terms “implementation scheme,” “one implementation scheme,” “some implementation schemes,” or “another implementation scheme” used in the specification may be used to describe different implementation schemes or the same implementation scheme.

[0126] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is mentioned as being connected or coupled to another element, that element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is mentioned as being directly connected to another element, there is no intermediary element between that element and the other element. If two devices are directly or indirectly connected, the two devices are “communicating”, enabling them to communicate electronic signals between them.

[0127] For the purposes of this document, the term “based on” may be understood as “at least partially based on”.

[0128] For the purposes of this document, the use of numerical terms such as “first” object, “second” object, and “third” object without additional context may not imply an ordering of objects, but may be used for identification purposes to distinguish different objects.

[0129] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0130] The detailed description above has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the precise forms disclosed in the invention. Many modifications and variations are possible based on the teachings above. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and various modifications suitable for the specific intended use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. An apparatus comprising: control circuitry configured to connect to a plurality of arrays each comprising a plurality of non-volatile memory cells each comprising a programmable resistive element connected in series with a threshold switch selector configured to become conductive in response to application of a voltage level exceeding a corresponding threshold voltage, the control circuitry configured to: power up a first one or more of the plurality of arrays for an access operation; after powering up the first one or more arrays, perform the access operation on one or more of the memory cells of the first one or more arrays; power down the first one or more arrays; determine whether the threshold voltages of the threshold switch selectors of the first one or more arrays exhibit excessive drift after powering down the first one or more arrays storing data content, prior to powering up the first one or more arrays for performance of an access operation, and prior to performance of the access operation; and in response to determining that the threshold voltages of the threshold switch selectors of the first one or more arrays exhibit excessive drift, reload the stored data content from another one or more of the plurality of arrays to the first one or more arrays, the data content being redundantly stored in the another one or more arrays.

2. The apparatus of claim 1, wherein the control circuitry is formed on a control die, the apparatus further comprising: a memory die comprising the first one or more arrays of non-volatile memory cells, the memory die being separately formed from and bonded to the control die.

3. The apparatus of claim 1, wherein each of the plurality of arrays comprises: one or more first conductive lines; one or more second conductive lines; and the plurality of memory cells each connected between a corresponding one of the first conductive lines and one of the second conductive lines.

4. The apparatus of claim 3, wherein: the resistive elements are magnetoresistive random access memory (MRAM) memory devices.

5. The apparatus of claim 3, wherein: the resistive elements are resistive random access memory (ReRAM) memory devices.

6. The apparatus of claim 3, wherein: the resistive elements are phase change memory (PCM) memory devices.

7. The apparatus of claim 3, wherein the control circuitry is further configured to: apply a first read voltage to a selected plurality of the memory cells in the first one or more arrays; determine whether the selected plurality of the memory cells are conductive in response to the applied first read voltage; and determine whether the threshold voltages of the threshold switch selectors of the first one or more arrays exhibit excessive drift based on whether the selected plurality of the memory cells are conductive in response to the applied first read voltage. ​ ​ 8. The apparatus of claim 7, wherein the first read voltage is a lower voltage level than a voltage level used in a read operation to determine a data state stored in the memory cell.

9. The apparatus of claim 7, wherein the first read voltage is a higher voltage level than a voltage level used in a read operation to determine a data state stored in the memory cell.

10. The apparatus of claim 3, wherein the control circuit is further configured to: perform a read operation on a subset of the memory cells of the first one or more arrays; compare data read from the subset of the memory cells to a known pattern; and determine whether the threshold voltage of the threshold switch selector exhibits excessive drift based on comparing the data read from the subset of the memory cells to the known pattern.

11. The apparatus of claim 3, wherein the control circuit is further configured to: determine a time value of a time between powering up the first one or more arrays for performing an access operation and a previous time of powering down the first one or more arrays; and determine whether the threshold voltage of the threshold switch selector exhibits excessive drift based on the determined time value.

12. The apparatus of claim 1, wherein the control circuit is further configured to: in response to determining that the threshold voltage of the threshold switch selector of the first one or more arrays exhibits excessive drift, notify a host connected with the apparatus that the threshold switch selector exhibits excessive drift, and wherein the reloading of the stored data content from another one or more of the plurality of arrays to the first one or more arrays is in response to a host command, the host command being in response to the host being notified that the threshold switch selector exhibits excessive drift.

13. A method comprising: powering down a first memory array in a memory system including a plurality of memory arrays, the first memory array including a plurality of memory cells each including a programmable resistive element connected in series with a threshold switch selector configured to become conductive in response to a voltage level applied that exceeds a corresponding threshold voltage; subsequently powering up the first memory array, the powering up including: determining whether the threshold voltage of the threshold switch selector of the first memory array has drifted to a value that is too high; and in response to determining that the threshold voltage of the threshold switch selector of the first memory array has drifted to a value that is too high, reloading data content stored in the first memory array from another one or more of the plurality of memory arrays in which the data content is redundantly stored.

14. The method of claim 13, wherein determining whether the threshold voltage of the threshold switch selector of the first memory array has drifted to a value that is too high includes: ​ applying a read voltage to a subset of the memory cells of the first memory array; determining a number of the subset of the memory cells that conduct in response to the read voltage; and based on the number of the subset of the memory cells that conduct in response to the read voltage, determining whether the threshold voltage of the threshold switch selector of the first memory array has drifted to a too high value.

15. The method of claim 13, wherein determining whether the threshold voltage of the threshold switch selector of the first memory array has drifted to a too high value comprises: reading a predetermined subset of the memory cells of the first memory array; performing a comparison of a result of reading the predetermined subset of the memory cells to a known pattern; and based on the comparison, determining whether the threshold voltage of the threshold switch selector of the first memory array has drifted to a too high value.

16. The method of claim 13, wherein determining whether the threshold voltage of the threshold switch selector of the first memory array has drifted to a too high value comprises: determining a time value of a time between a power up procedure of the first memory array and a previous power down; determining whether the time value exceeds a threshold value; and based on whether the time value exceeds the threshold value, determining whether the threshold voltage of the threshold switch selector of the first memory array has drifted to a too high value.

17. A non-volatile memory device comprising: a plurality of memory arrays including a first memory array having a cross-point architecture, a memory cell at each cross-point of the array, each of the memory cells including a magnetoresistive random access memory (MRAM) memory device connected in series with a threshold switch selector configured to become conductive in response to a voltage level applied that exceeds a corresponding threshold voltage; and one or more control circuits connected to the first memory array and configured to determine, as part of a power up procedure, whether the threshold voltage of the threshold switch selector of the first memory array has drifted to a too high value, and in response to determining that the threshold voltage of the threshold switch selector of the first memory array has drifted to a too high value, to reload data content stored in the first memory array from another one or more of the plurality of memory arrays in which the data content is redundantly stored.

18. The non-volatile memory device of claim 17, wherein the one or more control circuits are further configured to: apply a read voltage to a subset of the memory cells of the first memory array; determine a number of the subset of the memory cells that conduct in response to the read voltage; and based on the number of the subset of the memory cells that conduct in response to the read voltage, determine whether the threshold voltage of the threshold switch selector of the first memory array has drifted to a too high value.

19. The non-volatile memory device of claim 17, wherein the one or more control circuits are further configured to: read a predetermined subset of the memory cells of the first memory array; perform a comparison of a result of reading the predetermined subset of the memory cells with a known pattern; and determine whether the threshold voltage of the threshold switch selector of the first memory array has drifted to a too high value based on the comparison.

20. The non-volatile memory device of claim 17, wherein the one or more control circuits are further configured to: determine a time value of a time between a power up of the first memory array and a previous power down; determine whether the time value exceeds a threshold value; and determine whether the threshold voltage of the threshold switch selector of the first memory array has drifted to a too high value based on whether the time value exceeds the threshold value.

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