Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate having a material layer to be etched formed thereon; forming a plurality of mutually separated sacrificial layers and a first protective layer on the material layer to be etched, the first protective layer being on the sacrificial layers and having first openings between adjacent sacrificial layers; forming a mask material layer on a bottom and sidewall surface of the first openings, the mask material layer covering a top and sidewall surface of the first protective layer and a sidewall surface of the sacrificial layers; removing the mask material layer on the bottom surface of the first openings and the top surface of the first protective layer; removing the first protective layer and the sacrificial layers to form second openings in the remaining mask material layer; and removing the material layer to be etched exposed by the first openings and the second openings to form a target pattern layer. The method improves the pattern accuracy of the second openings and thus improves the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.

[0003] In the development of integrated circuits, the functional density (i.e. the number of interconnects in each chip) usually increases gradually while the geometric size (i.e. the smallest component size that can be produced by process steps) gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] Currently, as technology nodes continue to shrink, the performance of the resulting semiconductor structures is relatively poor. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure, which is beneficial to improving the performance of the semiconductor structure.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a material layer to be etched is formed on the substrate; forming a plurality of mutually discrete sacrificial layers and a first protective layer on the material layer to be etched, wherein the first protective layer is located on the sacrificial layers and a first opening is formed between adjacent sacrificial layers; forming a mask material layer on the bottom and sidewall surfaces of the first opening, wherein the mask material layer covers the top and sidewall surfaces of the first protective layer and the sidewall surfaces of the sacrificial layers; removing the mask material layer on the bottom surface of the first opening and the top surface of the first protective layer; removing the first protective layer and the sacrificial layer, thereby forming a second opening within the remaining mask material layer; and removing the material layer to be etched exposed by the first and second openings to form a target pattern layer.

[0007] Optionally, the step of forming a plurality of mutually discrete sacrificial layers and a first protective layer on the material layer to be etched includes: forming a sacrificial material layer on the material layer to be etched; forming a first protective material layer on the sacrificial material layer; forming a patterned layer on the first protective material layer, the patterned layer having a patterned opening, the patterned opening corresponding to the position and size of the first opening; implanting doped ions into a portion of the first protective material layer and the sacrificial material layer using the patterned layer as a mask; removing the implanted doped first protective material layer and the sacrificial material layer to form mutually discrete sacrificial layers and a first protective layer; and removing the patterned layer.

[0008] Optionally, the process for forming the first protective material layer includes chemical vapor deposition or atomic layer deposition.

[0009] Optionally, before forming the first protective material layer on the sacrificial material layer, the method further includes forming a second protective material layer on the surface of the sacrificial material layer.

[0010] Optionally, the sacrificial material layer is oxidized to form the second protective material layer; the process parameters of the oxidation treatment include: providing oxygen, wherein the oxygen flow rate is 100-200 sccm and the temperature is 30-50°C.

[0011] Optionally, the steps of removing the first protective layer and the sacrificial layer include: removing the first protective layer using a first etching process, and then removing the sacrificial layer using a second etching process.

[0012] Optionally, the first etching process is a wet etching process; the parameters of the wet etching process include: the etching solution includes a diluted hydrofluoric acid solution, wherein the volume ratio of hydrofluoric acid to water in the diluted hydrofluoric acid solution is less than or equal to 1:500.

[0013] Optionally, the second etching process is a wet etching process; the parameters of the wet etching process include: the etching solution includes ammonia.

[0014] Optionally, the material of the first protective layer includes silicon oxide or silicon nitride.

[0015] Optionally, the material of the sacrificial layer includes amorphous silicon, amorphous carbon, or polycrystalline silicon.

[0016] Optionally, the material layer to be etched may include a single material layer or multiple stacked material layers.

[0017] Optionally, the material of the mask material layer includes titanium oxide, titanium nitride, silicon nitride, silicon oxide, or silicon oxynitride.

[0018] Optionally, the process for forming the mask material layer includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0019] Optionally, the doped ions include carbon ions, boron ions, arsenic ions, gallium ions, or indium ions.

[0020] Optionally, the process for removing the first protective material layer and sacrificial material layer after implantation of doped ions is a dry etching process.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0022] Several mutually independent sacrificial layers and a first protective layer are formed on the material layer to be etched, with the first protective layer located on the sacrificial layer. The first protective layer is used to cover the top surface of the sacrificial layer to prevent the top surface of the sacrificial layer from being exposed to air and causing atomic aggregation, thereby reducing the formation of trenches on the surface of the sacrificial layer. When forming the mask material layer, the mask material layer is located on the top surface of the first protective layer to prevent the mask material layer from being deposited in the trenches on the surface of the sacrificial layer. This prevents the sacrificial layer from remaining in the second opening when the sacrificial layer is removed to form the second opening, ensuring the pattern morphology of the formed second opening, improving the accuracy of pattern transfer, and thus helping to improve the performance of the formed semiconductor structure. Attached Figure Description

[0023] Figures 1 to 4 This is a schematic diagram of a semiconductor structure formation method in one embodiment;

[0024] Figures 5 to 12 This is a schematic diagram of the structure corresponding to each step of the semiconductor structure formation method in one embodiment of the present invention. Detailed Implementation

[0025] As the background technology shows, the performance of current semiconductor structures is relatively poor. The reasons for this poor performance will now be analyzed in conjunction with specific accompanying figures.

[0026] refer to Figure 1 A layer 100 to be etched is provided; a sacrificial layer 101 is formed on the layer 100 to be etched; a patterned layer 102 is formed on the sacrificial layer 101, the patterned layer 102 exposing a portion of the surface of the sacrificial layer 101; and ion implantation is performed on the exposed sacrificial layer.

[0027] refer to Figure 2 Remove the patterned layer 102; remove the ion-implanted sacrificial layer 101, and form a first opening 103 in the remaining sacrificial layer 101, the first opening 103 exposing the surface of the layer 100 to be etched.

[0028] refer to Figure 3A sidewall material layer 104 is formed at the bottom and sidewall surface of the first opening 103, and the sidewall material layer 104 covers the top and sidewall surface of the sacrificial layer 101.

[0029] refer to Figure 4 Remove the sidewall material layer 104 from the bottom surface of the first opening 103 and the top surface of the sacrificial layer 101; remove the remaining sacrificial layer 101, and form a second opening 105 within the remaining sidewall material layer 104.

[0030] The inventors discovered that when forming a semiconductor structure using the above-described method, after removing the patterned layer 102, the unimplanted sacrificial layer 101 is exposed to air. The sacrificial layer 101 is typically made of amorphous silicon. Amorphous silicon exposed to air is prone to silicon agglomeration, resulting in a rough surface and trenches on the sacrificial layer 101. When depositing a sidewall material layer on the surface of the sacrificial layer 101, the material of the sidewall material layer easily deposits into the trenches (see reference). Figure 3 The thickening of the sidewall material layer (as shown in the middle circle) leads to localized thickening of the sidewall material layer. When removing the sidewall material layer on the top surface of the sacrificial layer 101, the excessive thickness of the local sidewall material layer prevents complete removal of the sidewall material layer 104. Consequently, when removing the unimplanted sacrificial layer 101, some sacrificial layer 102 remains in the formed second opening 105. Subsequently, when etching the layer to be etched using the remaining sidewall material layer 104 as a mask, the residual sacrificial layer 101 in the second opening 105 disrupts the stability of pattern transfer. This results in poor morphology of the target pattern layer formed within the layer to be etched 100, incomplete patterns, and incomplete trench opening, affecting the performance of the final semiconductor structure.

[0031] To address the aforementioned problems, this invention provides a method for forming a semiconductor structure. A plurality of mutually discrete sacrificial layers and a first protective layer are formed on a material layer to be etched, with the first protective layer located on the sacrificial layers. The first protective layer prevents the surface of the sacrificial layer from directly contacting air, reducing atomic aggregation on the surface of the sacrificial layer. Furthermore, when forming the mask material layer, a portion of the mask material layer is located on the top surface of the first protective layer, preventing the mask material layer from entering the trenches on the surface of the sacrificial layer. This solves the problem of sacrificial layer residue in the second opening when removing the sacrificial layer to form the second opening. Subsequent etching of the layer to be etched along the first and second openings results in higher stability of pattern transfer, improving the morphology of the formed target pattern layer and benefiting the performance of the final semiconductor structure.

[0032] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Figures 5 to 12This is a schematic diagram of the structure corresponding to each step of the semiconductor structure formation method in one embodiment of the present invention.

[0034] refer to Figure 5 A substrate 200 is provided, on which a material layer 210 to be etched is formed.

[0035] The substrate 200 is used to provide a process platform for subsequent processes. In this embodiment, taking a planar transistor as an example of the formed semiconductor structure, the substrate 200 includes a substrate.

[0036] In this embodiment, the substrate is a silicon substrate; in other embodiments, the substrate material can also be germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium, etc., and the substrate can also be a silicon substrate on an insulator or a germanium substrate on an insulator, etc.

[0037] In other embodiments, when the formed semiconductor structure is a fin field-effect transistor, the substrate 200 may accordingly include a substrate and fins protruding from the substrate.

[0038] The substrate 200 may also include other structures, such as gate structures, doped regions, shallow trench isolation structures, etc.

[0039] The material layer 210 to be etched can be a single-layer material layer or a multi-layer stacked material layer, specifically including dielectric materials, metallic materials or hard mask materials, etc.

[0040] In this embodiment, the material layer 210 to be etched is a multi-layered stacked material layer, including: a first material layer (not shown in the figure) located on the surface of the substrate 200, and a second material layer (not shown in the figure) located on the surface of the first material layer.

[0041] The material of the first material layer includes: the k-th dielectric material (k is less than or equal to 3.9).

[0042] The second material layer is a hard mask layer, which includes one or more stacked layers of SiC, SiN, BD, tetraethyl orthosilicate (TEOS), and TiN.

[0043] The second material layer serves two purposes: firstly, it acts as an etching stop layer; secondly, the material of the second material layer is a hard mask layer material, which results in less etching loss during subsequent etching processes and higher stability of pattern transfer.

[0044] After forming the material layer 210 to be etched on the substrate 200, a plurality of mutually independent sacrificial layers and a first protective layer are formed on the material layer 210 to be etched. The first protective layer is located on the sacrificial layer and has a first opening between adjacent sacrificial layers.

[0045] In this embodiment, the steps of forming several mutually independent sacrificial layers and a first protective layer specifically include:

[0046] refer to Figure 6 A sacrificial material layer 220 is formed on the material layer 210 to be etched.

[0047] In this embodiment, the sacrificial material layer 220 is used to subsequently form discrete sacrificial layers.

[0048] Subsequent processes include patterning the sacrificial material layer 220, thus achieving a high etching selectivity between the sacrificial material layer 220 and the material layer 210 to be etched, thereby enabling selective etching in subsequent processes. In this embodiment, the sacrificial material layer 220 and the material layer 210 to be etched are made of different materials.

[0049] The material of the sacrificial material layer 220 includes amorphous silicon, amorphous carbon, or polycrystalline silicon. In this embodiment, the material of the sacrificial material layer 220 is amorphous silicon.

[0050] The process for forming the sacrificial material layer 220 includes chemical vapor deposition (CVD) or atomic layer deposition (ALD). In this embodiment, the process for forming the sacrificial material layer 220 is CVD.

[0051] Continue to refer to Figure 6 A first protective material layer 230 is formed on the sacrificial material layer 220.

[0052] In this embodiment, the first protective material layer 230 is used to form the first protective layer subsequently.

[0053] In this embodiment, a first protective material layer 230 is formed on the sacrificial material layer 220. The first protective material layer 230 can protect the sacrificial material layer 220 and prevent the sacrificial material layer 220 from being exposed to air and causing silicon agglomeration.

[0054] The first protective material layer 230 is made of silicon oxide or silicon nitride. In this embodiment, the first protective material layer 230 is made of silicon oxide.

[0055] The process for forming the first protective material layer 230 includes chemical vapor deposition (CVD) or atomic layer deposition (ALD). In this embodiment, the process for forming the first protective material layer 230 is CVD. Using CVD can yield a first protective material layer 230 with good density, which is beneficial for better protecting the sacrificial material layer 220.

[0056] The thickness range of the first protective material layer 230 is If the thickness of the first protective material layer 230 is less than Then it cannot effectively protect the sacrificial material layer 220; if the thickness of the first protective material layer 230 is greater than This will result in the first protective layer not being completely removed during subsequent removal processes.

[0057] In this embodiment, before forming the first protective material layer 230, the method further includes forming a second protective material layer 240 on the surface of the sacrificial material layer 220, wherein the first protective material layer 230 is located on the surface of the second protective material layer 240.

[0058] In other embodiments, the second protective material layer 240 may not be formed.

[0059] In this embodiment, the second protective material layer 240 is also used to protect the sacrificial material layer 220. Through double protection, the sacrificial material layer 220 can be prevented from being exposed to the air to the greatest extent, so as to prevent grooves from appearing on the surface of the sacrificial material layer 220 and improve the surface roughness of the sacrificial material layer 220.

[0060] In this embodiment, the method for forming the second protective material layer 240 includes: oxidizing the sacrificial material layer 220 to form the second protective material layer 240 on the surface of the sacrificial material layer 220.

[0061] In this embodiment, the parameters of the oxidation treatment include: introducing oxygen, the oxygen flow rate being 100-200 sccm, and the process temperature being 30-50℃.

[0062] In this embodiment, since the material of the sacrificial material layer 220 is amorphous silicon, the material of the second protective material layer 240 formed after oxidation treatment includes silicon oxide.

[0063] refer to Figure 7 A patterned layer 250 is formed on the first protective material layer 230. The patterned layer 250 has a patterned opening 251, which defines the position and size of the first opening to be formed.

[0064] In this embodiment, the patterning layer 250 is a patterned photoresist layer.

[0065] Continue to refer to Figure 7 Using the patterned layer 250 as a mask, doped ions are implanted into a portion of the first protective material layer 230 and the sacrificial material layer 220.

[0066] In this embodiment, doped ions are specifically injected into the first protective material layer 230 exposed by the patterned opening 251 and the sacrificial material layer 220 below it.

[0067] In this embodiment, doping ions are also implanted into a portion of the second protective material layer 240.

[0068] In this embodiment, dopant ions are implanted into a portion of the first protective material layer 230, the second protective material layer 240, and the sacrificial material layer 220. This is suitable for increasing the removal selectivity ratio between the first protective material layer 230, the second protective material layer 240, and the sacrificial material layer 220 without dopant ions and the first protective material layer 230, the second protective material layer 240, and the sacrificial material layer 220 with dopant ions. This helps to increase the process window of the removal process when removing the first protective material layer 230, the second protective material layer 240, and the sacrificial material layer 220 with dopant ions, thereby ensuring the pattern accuracy of the first opening formed subsequently.

[0069] The dopant ions include carbon ions, boron ions, arsenic ions, gallium ions, or indium ions. In this embodiment, the dopant ion is a boron ion.

[0070] In this embodiment, the process parameters for implanting dopant ions include: implantation energy of 5–11 keV and implantation dose of 1E15–2E15 atoms / cm. 2 .

[0071] refer to Figure 8 The first protective material layer 230 and the sacrificial material layer 220, which are implanted with doped ions, are removed. A sacrificial layer 221 and a first protective layer 231, which are mutually independent, are formed on the material layer 210 to be etched. The first protective layer 231 is located on the sacrificial layer 221. A first opening 261 is provided between adjacent sacrificial layers 221. The bottom of the first opening 261 exposes the surface of the material layer 210 to be etched.

[0072] In this embodiment, the method further includes: removing the second protective material layer 240 from which doped ions are implanted to form a second protective layer 241, wherein the second protective layer 241 is located on the surface of the sacrificial layer 221 and the first protective layer 231 is located on the surface of the second protective layer 241.

[0073] In this embodiment, the process for removing the first protective material layer 230, the second protective material layer 240, and the sacrificial material layer 220 implanted with doped ions is a dry etching process.

[0074] In this embodiment, a first dry etching process is used to remove the first material layer 230 and the second protective material layer 240 implanted with doped ions until the surface of the sacrificial material layer 220 is exposed. Then, a second dry etching process is used to remove the sacrificial material layer 220 implanted with doped ions. The parameters of the first dry etching process include: an etching atmosphere comprising a mixed gas of CF4, CHF3, and He; a power of 1000–1500 W; a pressure of 5–15 mTorr; a temperature of 30–50 °C; and a time of 5–10 s. The parameters of the second dry etching process include: an etching atmosphere comprising a mixed gas of Cl2, HBr, CF4, and O2; an etching power of 500–1000 W; a pressure of 5–8 mTorr; a temperature of 30–50 °C; and a time of 20–40 s.

[0075] In this embodiment, after the sacrificial layer 221 is formed, the patterned layer 250 is removed by an ashing process.

[0076] In this embodiment, after removing the patterning layer 250, since the top of the sacrificial layer 221 is covered by the second protective layer 241 and the first protective layer 231, silicon agglomeration of the sacrificial layer 221 when exposed to air can be avoided, and the formation of trenches on the surface of the sacrificial layer 221 can be improved. When the mask material layer is subsequently formed, part of the mask material layer is formed on the top surface of the first protective material layer 231, avoiding the deposition of the mask material layer into the trenches on the surface of the sacrificial layer 221. This solves the problem of residual sacrificial layer 221 when it is removed, which is beneficial to improve the accuracy of pattern transfer and improve the morphology of the final target pattern.

[0077] refer to Figure 9 A mask material layer 270 is formed on the bottom surface and sidewall surface of the first opening 261, and the mask material layer 270 covers the top and sidewall surfaces of the first protective layer 231 and the sidewall surface of the sacrificial layer 221.

[0078] In this embodiment, the mask material layer 270 also covers the sidewall surface of the second protective layer 241.

[0079] The process for forming the mask material layer 270 includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this embodiment, atomic layer deposition is used to form the mask material layer 270.

[0080] The atomic layer deposition process forms a mask material layer 270 with good thickness uniformity, which makes the thickness of the mask material layer 270 located on the bottom surface and side wall surface of the first opening 261 more consistent with the thickness of the mask material layer 270 located on the top surface of the first protective layer 231. This is beneficial for exposing the material layer 210 to be etched at the bottom of the first opening 261 and the top surface of the first protective layer 231 when the mask material layer 270 is subsequently etched.

[0081] The mask material layer 270 is made of titanium oxide, titanium nitride, silicon nitride, silicon oxide, or silicon oxynitride. In this embodiment, the mask material layer 270 is made of titanium oxide.

[0082] refer to Figure 10 Remove the mask material layer 270 from the bottom surface of the first opening 261 and the top surface of the first protective layer 231.

[0083] The process for removing the mask material layer 270 from the bottom surface of the first opening 261 and the top surface of the first protective layer 231 includes one or a combination of dry etching and wet etching processes.

[0084] The etching process has a high etching selectivity for the material layer 210 to be etched, the first protective layer 231, and the mask material layer 270. That is, the etching rate of the material layer 210 to be etched and the first protective layer 231 is much lower than the etching rate of the mask material layer 270. When part of the mask material layer 270 is etched away, the material layer 210 to be etched and the first protective layer 231 are less damaged by etching. As a result, the sacrificial layer 221 covered by the first protective layer 231 is less damaged by etching, which helps to improve the stability of pattern transfer and thus improves the performance of the formed semiconductor structure.

[0085] refer to Figure 11 Remove the first protective layer 231 and the sacrificial layer 221 to form a second opening 262 in the remaining mask material layer 270.

[0086] In this embodiment, the second protective layer 241 is also removed.

[0087] In this embodiment, the steps of removing the first protective layer 231, the second protective layer 241 and the sacrificial layer 221 include: removing the first protective layer 231 and the second protective layer 241 using a first etching process, and removing the sacrificial layer 221 using a second etching process.

[0088] In this embodiment, the first etching process is a wet etching process, and the parameters of the wet etching process include: the etching solution includes a diluted hydrofluoric acid solution, and the volume ratio of hydrofluoric acid to water in the diluted hydrofluoric acid solution is less than or equal to 1:500.

[0089] The first etching process helps to ensure that the second protective layer 241 and the first protective layer 231 on the sacrificial layer 221 are completely removed, avoiding residue.

[0090] The first etching process has a high etching selectivity for the mask material layer 270 and the first protective layer 231 and the second protective layer 241. That is, the etching rate of the first etching process for the mask material layer 270 is much lower than the etching rate for the first protective layer 231 and the second protective layer 241. Therefore, the mask material layer 270 is less damaged by etching, which ensures the integrity of the remaining mask material layer 270 pattern and helps to improve the stability of pattern transfer.

[0091] In this embodiment, the second etching process is a wet etching process, and the parameters of the wet etching process include: the etching solution includes ammonia.

[0092] The second etching process has a high etching selectivity for the mask material layer 270 and the sacrificial layer 221. That is, the etching rate of the second etching process for the mask material layer 270 is much lower than the etching rate for the sacrificial layer 221. Therefore, the mask material layer 270 is less damaged by etching, which ensures that the sacrificial layer 221 is completely removed while the pattern of the remaining mask material layer 270 remains intact, which is beneficial to improving the stability of pattern transfer.

[0093] In this embodiment, the presence of the first protective layer 231 and the second protective layer 241 reduces silicon agglomeration and void formation on the top surface of the sacrificial layer 221, improves the surface roughness of the sacrificial layer 221, and prevents the mask material layer 270 from being formed on the top surface of the sacrificial layer 221, thus avoiding the deposition of the mask material layer in the voids. This solves the problem of residual sacrificial layer in the second opening 262 when forming the second opening 262, ensuring the morphology of the formed first opening 261 and second opening 262. When etching the material layer 210 to be etched along the first opening 261 and second opening 262, the stability and accuracy of pattern transfer are improved, which in turn helps to improve the performance of the formed semiconductor.

[0094] refer to Figure 12 Remove the material layer 210 to be etched exposed by the first opening 261 and the second opening 262 to form the target pattern layer 211.

[0095] After removing the material layer 210 to be etched exposed by the first opening 261 and the second opening 262, the patterns of the first opening 261 and the second opening 262 are transferred to the target pattern layer 211, where a first trench 281 corresponding to the first opening 261 and a second trench 282 corresponding to the second opening 262 are formed. The first opening 261 and the second opening 262 have better morphology and higher pattern accuracy, which improves the pattern accuracy of the first trench 281 and the second trench 282, and improves the quality of the metal interconnect structure subsequently formed in the first trench 281 and the second trench 282, thereby improving the performance of the semiconductor structure.

[0096] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a layer of material to be etched is formed; A sacrificial material layer is formed on the material layer to be etched, and the sacrificial material layer is oxidized to form a second protective material layer; A first protective material layer is formed on the second protective material layer; Remove a portion of the sacrificial material layer, the second protective material layer, and the first protective material layer to form a plurality of mutually independent sacrificial layers, second protective layers, and first protective layers on the material layer to be etched. The second protective layer is located on the sacrificial layer, the first protective layer is located on the second protective layer, and there is a first opening between adjacent sacrificial layers. A masking material layer is formed on the bottom and sidewall surfaces of the first opening, and the masking material layer covers the top and sidewall surfaces of the first protective layer as well as the sidewall surfaces of the sacrificial layer and the second protective layer; Remove the mask material layer from the bottom surface of the first opening and the top surface of the first protective layer; Remove the first protective layer, the second protective layer, and the sacrificial layer to form a second opening within the remaining mask material layer; Remove the material layer to be etched exposed by the first and second openings to form the target pattern layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a plurality of mutually discrete sacrificial layers, second protective layers, and first protective layers on the material layer to be etched includes: forming a sacrificial material layer on the material layer to be etched; forming a patterned layer on the first protective material layer, the patterned layer having patterned openings, the patterned openings corresponding to the position and size of the first opening; using the patterned layer as a mask, implanting doped ions into a portion of the first protective material layer, the second protective material layer, and the sacrificial material layer; removing the implanted doped first protective material layer, the second protective material layer, and the sacrificial material layer to form mutually discrete sacrificial layers, second protective layers, and first protective layers; and removing the patterned layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process for forming the first protective material layer includes chemical vapor deposition or atomic layer deposition.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for the oxidation treatment include: providing oxygen, wherein the oxygen flow rate is 100~200 sccm and the temperature is 30~50℃.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps of removing the first protective layer, the second protective layer and the sacrificial layer include: removing the first protective layer and the second protective layer using a first etching process, and then removing the sacrificial layer using a second etching process.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The first etching process is a wet etching process; the parameters of the wet etching process include: the etching solution includes a diluted hydrofluoric acid solution, wherein the volume ratio of hydrofluoric acid to water in the diluted hydrofluoric acid solution is less than or equal to 1:

500.

7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The second etching process is a wet etching process; the parameters of the wet etching process include: the etching solution includes ammonia.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first protective layer includes silicon oxide or silicon nitride.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the sacrificial layer includes amorphous silicon, amorphous carbon, or polycrystalline silicon.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material layer to be etched includes a single material layer or multiple stacked material layers.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the mask material layer includes titanium oxide, titanium nitride, silicon nitride, silicon oxide, or silicon oxynitride.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the mask material layer includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

13. The method for forming a semiconductor structure as described in claim 2, characterized in that, The doped ions include carbon ions, boron ions, arsenic ions, gallium ions, or indium ions.

14. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process for removing the implanted doped ions from the first protective material layer, the second protective material layer, and the sacrificial material layer is a dry etching process.

Images