Method for forming semiconductor structure

Abstract

The present application provides a method for forming a semiconductor structure, the method comprising: providing a semiconductor substrate, the surface of the semiconductor substrate comprising a plurality of sacrificial layers and channel layers stacked in sequence; forming a dummy gate layer on top of the sacrificial layers and channel layers; etching the sacrificial layers and channel layers on both sides of the dummy gate layer until the surface of the semiconductor substrate is exposed, while forming a recess in the sidewalls of the sacrificial layer below the dummy gate layer; forming an oxide layer on the sidewalls of the sacrificial layer and channel layer, wherein the oxide layer located on the sidewalls of the sacrificial layer maintains the shape of the recess; and forming an inner sidewall within the recess in the oxide layer on the sidewalls of the sacrificial layer. By utilizing the difference in etching and oxidation rates between the sacrificial layer and the channel layer, a recess is formed on the sidewalls of the sacrificial layer, and finally, an inner sidewall is formed within the recess. This simplifies the process for forming the inner sidewall, reduces damage to the surface of the silicon channel, improves the quality of the source and drain electrodes, and thereby improves device reliability.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] As the size of CMOS semiconductor structures becomes smaller and smaller, the current FinFET device structure faces many problems below the 3-nanometer core size. Therefore, a new gate all around (GAA) Nanosheet device structure has emerged to achieve the continuous reduction of the size of CMOS semiconductor structures.

[0003] GAA Nanosheet not only has excellent electrostatic performance (short channel effect), but its process is also compatible with FinFET technology to the greatest extent possible. In the GAA Nanosheet process, an inner spacer is formed outside the sacrificial SiGe layer to reduce the parasitic capacitance from the gate to the source and drain.

[0004] However, the current inner spacer process is complex, and the inner spacer determines the gate length, posing a significant challenge to gate length uniformity. Furthermore, etching the inner spacer cavity requires a very high-efficiency process, which also damages the silicon channel surface, affecting the quality of subsequent source and drain epitaxy. Therefore, a more effective and reliable technical solution is needed. Summary of the Invention

[0005] The present application provides a method for forming a semiconductor structure, which can simplify the process of forming inner sidewalls, reduce damage to the surface of the silicon channel, improve the quality of the source and drain, and thus improve the reliability of the device.

[0006] The present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein the surface of the semiconductor substrate comprises a plurality of sacrificial layers and channel layers stacked in sequence; forming a dummy gate layer on top of the sacrificial layers and the channel layers; etching the sacrificial layers and the channel layers on both sides of the dummy gate layer until the surface of the semiconductor substrate is exposed, while forming a recess in the sidewall of the sacrificial layer below the dummy gate layer; forming an oxide layer on the sidewalls of the sacrificial layer and the channel layer, wherein the oxide layer located on the sidewall of the sacrificial layer maintains the shape of the recess; and forming an inner sidewall in the recess in the oxide layer on the sidewall of the sacrificial layer.

[0007] In some embodiments of the present application, the material of the sacrificial layer includes silicon germanium, and the material of the channel layer includes silicon.

[0008] In some embodiments of the present application, the method of forming the plurality of sequentially stacked sacrificial layers and channel layers includes an epitaxial growth process.

[0009] In some embodiments of the present application, the method of forming the oxide layer on the sidewalls of the sacrificial layer and the channel layer includes a wet oxidation method.

[0010] In some embodiments of the present application, the process parameters of the wet oxidation method include: an oxidation temperature of 500 degrees Celsius to 900 degrees Celsius, and an oxidation time of 15 minutes to 25 minutes.

[0011] In some embodiments of the present application, the method for forming an inner sidewall on the surface of the recess of the oxide layer includes: forming an inner sidewall material layer on the sidewall of the oxide layer; etching and removing the sidewall material layer on the surface of the oxide layer on the sidewall of the channel layer to expose the oxide layer on the sidewall of the channel layer.

[0012] In some embodiments of the present application, the method of etching and removing the spacer material layer located on the surface of the oxide layer on the sidewall of the channel layer includes anisotropic dry etching.

[0013] In some embodiments of the present application, the method for forming the semiconductor structure also includes: etching and removing the oxide layer on the sidewalls of the channel layer until the sidewalls of the channel layer are exposed; and forming a source and a drain on the surface of the semiconductor substrate and the sidewalls of the channel layer and the inner sidewalls.

[0014] In some embodiments of the present application, the method of etching and removing the oxide layer on the sidewall of the channel layer to expose the sidewall of the channel layer comprises wet etching.

[0015] In some embodiments of the present application, the method of forming the source and the drain on the surface of the semiconductor substrate and the sidewalls of the channel layer and the inner sidewall includes an epitaxial growth process.

[0016] The method for forming a semiconductor structure described in the present application utilizes the difference in etching rates between the sacrificial layer and the channel layer to form a recess on the sidewall of the sacrificial layer, then utilizes the difference in oxidation rates between the sacrificial layer and the channel layer to further deepen the recess, and finally forms an inner sidewall in the recess. This can simplify the process of forming the inner sidewall, reduce damage to the surface of the silicon channel, improve the quality of the source and drain, and thus improve device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following figures describe in detail exemplary embodiments disclosed in this application. Identical reference numerals denote similar structures in several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the same inventive intent as described in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0018] Figures 1 to 11 Schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0020] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.

[0021] An embodiment of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein the surface of the semiconductor substrate includes a plurality of sacrificial layers and channel layers stacked in sequence; forming a dummy gate layer on the top surfaces of the sacrificial layers and the channel layers; etching the sacrificial layers and the channel layers on both sides of the dummy gate layer until the surface of the semiconductor substrate is exposed, while forming a recess on the sidewall of the sacrificial layer below the dummy gate layer; forming an oxide layer on the sidewalls of the sacrificial layer and the channel layer, wherein the oxide layer located on the sidewall of the sacrificial layer maintains the shape of the recess; and forming an inner sidewall in the recess of the oxide layer on the sidewall of the sacrificial layer.

[0022] Figures 1 to 11 Schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present application. Figure 1 For a three-dimensional image, Figures 2 to 11 For the Figure 1 The following describes in detail the method for forming the semiconductor structure according to the embodiment of the present application in conjunction with the accompanying drawings.

[0023] refer to Figure 1 As shown, a semiconductor substrate 100 is provided, and a surface of the semiconductor substrate 100 includes a plurality of sacrificial layers 110 and channel layers 120 stacked in sequence.

[0024] In some embodiments of the present application, the bottom layer is a sacrificial layer 110, and the top layer is also a sacrificial layer 110. In other embodiments of the present application, the bottom layer is a sacrificial layer 110, and the top layer may also be a channel layer 120. Any structure that can achieve the gate-all-around (GAA) structure feature is sufficient.

[0025] In addition, it should be noted that in the embodiments of the present application, Figure 1 Only two channel layers 120 and three sacrificial layers 110 are used as an example, but this is not a limitation of the present application. The number of the channel layers 120 and the sacrificial layers 110 can also be other numbers, as long as the feature of the metal gate surrounding the silicon channel in the fully surrounded gate structure can be achieved. Specifically, the number of the channel layers 120 and the sacrificial layers 110 can be designed according to the difficulty of the process and the thickness of the overall structure. When the thickness of the overall structure cannot be too thick, more layers can be set if the process allows to increase the efficiency of electron migration.

[0026] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination thereof. In addition, the semiconductor substrate 100 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 100 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0027] In some embodiments of the present application, the material of the sacrificial layer 110 includes silicon germanium, and the material of the channel layer 120 includes silicon.

[0028] In some embodiments of the present application, when the material of the sacrificial layer 110 is silicon germanium and the material of the channel layer 120 is silicon, the method for forming the plurality of sequentially stacked sacrificial layers 110 and channel layers 120 includes an epitaxial growth process. In other embodiments of the present application, the plurality of sequentially stacked sacrificial layers 110 and channel layers 120 may also be formed by any other suitable method (e.g., a vapor deposition process).

[0029] refer to Figures 2 to 3 As shown, a dummy gate layer 130 is formed on the top surface of the sacrificial layer 110 and the channel layer 120. The dummy gate layer 130 is used to define the position of the metal gate, and in subsequent processes, the dummy gate layer 130 will be replaced by a metal gate.

[0030] In some embodiments of the present application, the method for forming the dummy gate layer 130 on the top surfaces of the sacrificial layer 110 and the channel layer 120 includes: referring to Figure 2 , forming a dummy gate material layer 130a on the top surface of the sacrificial layer 110 and the channel layer 120; Figure 3 , etching the dummy gate material layer 130 a to form the dummy gate layer 130 .

[0031] In some embodiments of the present application, a method for forming the dummy gate material layer 130 a on the top surfaces of the sacrificial layer 110 and the channel layer 120 includes a chemical vapor deposition process or a physical vapor deposition process.

[0032] In some embodiments of the present application, a method of etching the dummy gate material layer 130 a to form the dummy gate layer 130 includes wet etching or dry etching.

[0033] In some embodiments of the present application, the material of the dummy gate layer 130 is a sacrificial material that is not easily oxidized, such as silicon nitride.

[0034] refer to Figure 4 The sacrificial layer 110 and the channel layer 120 on both sides of the dummy gate layer 130 are etched until the surface of the semiconductor substrate 100 is exposed, and a recess 111 is formed in the sidewall of the sacrificial layer 110 below the dummy gate layer 130. Since the sacrificial layer 110 and the channel layer 120 are made of different materials, their different etching rates can be utilized to select an etching solution that etches the sacrificial layer 110 faster. In this way, due to the difference in etching rates, the recess 111 is etched in the sidewall of the sacrificial layer 110, while the etching amount of the sidewall of the channel layer 120 is extremely small, or even negligible.

[0035] In some methods for forming a semiconductor structure, the sacrificial layer 110 and the channel layer 120 on both sides of the dummy gate layer 130 are first etched until the surface of the semiconductor substrate 100 is exposed; then an etching solution with an extremely high etching selectivity for the sacrificial layer 110 and the channel layer 120 is selected to etch the sacrificial layer 110 alone. This not only requires more process steps, but also places high demands on the etching solution and may damage the channel layer 120. In the method for forming a semiconductor structure described in the embodiment of the present application, a conventional ordinary etching solution can be used to form the recess 111 through a single etching, which can simplify the process and reduce damage to the channel layer 120. In subsequent processes, the recess 111 is further expanded to achieve the formation of the inner sidewall.

[0036] In some embodiments of the present application, the sacrificial layer 110 and the channel layer 120 on both sides of the dummy gate layer 130 are etched until the surface of the semiconductor substrate 100 is exposed, and at the same time, a recess 111 is formed on the sidewall of the sacrificial layer 110 below the dummy gate layer 130. The etching solution used can be a conventional dry anisotropic etching solution or an atomic layer etching solution, etc., which can etch silicon germanium.

[0037] refer to Figure 5 As shown, an oxide layer 140 is formed on the sidewalls of the sacrificial layer 110 and the channel layer 120 , and an oxide layer 140 is also formed on the dummy gate layer 130 and the surface of the semiconductor substrate 100 , wherein the oxide layer 140 located on the sidewalls of the sacrificial layer 110 maintains the shape of the recess 111 .

[0038] In some embodiments of the present application, the process parameters of the wet oxidation method include: an oxidation temperature of 500 degrees Celsius to 900 degrees Celsius, for example, 550 degrees Celsius, 600 degrees Celsius, 650 degrees Celsius, 700 degrees Celsius, 750 degrees Celsius, 800 degrees Celsius or 850 degrees Celsius, etc.; an oxidation time of 15 minutes to 25 minutes, for example, 18 minutes, 20 minutes or 23 minutes, etc.

[0039] In some embodiments of the present application, the oxidizing gas of the wet oxidation method includes: oxygen, hydrogen and nitrogen, and the ratio of oxygen, hydrogen and nitrogen is (1-3): (1-3): (12-20).

[0040] A thin oxide layer 140 is formed on the side walls of the sacrificial layer 110 and the channel layer 120 by oxidation. Since the oxidation rate of the sacrificial layer 110 is lower than the oxidation rate of the channel layer 120, that is, the oxide layer on the side wall of the sacrificial layer 110 is thinner than the oxide layer on the side wall of the channel layer 120, the recess 111 can be further deepened to form an inner sidewall.

[0041] In some embodiments of the present application, the method for forming the oxide layer on the sidewalls of the sacrificial layer 110 and the channel layer 120 includes a wet oxidation method, which requires a relatively low process temperature (generally below 900 degrees Celsius) and does not cause germanium ion diffusion.

[0042] refer to Figures 6 and 7 An inner sidewall 150 is formed in the recess 111 of the oxide layer 140 on the sidewall of the sacrificial layer 110. The inner sidewall 150 can reduce the parasitic capacitance between the metal gate and the source and drain.

[0043] In some embodiments of the present application, the method for forming the inner sidewall 150 on the surface of the recess 111 of the oxide layer 140 includes referring to Figure 6, forming an inner sidewall material layer 150a on the sidewall of the oxide layer 140; Figure 7 The spacer material layer 150a located on the surface of the oxide layer 140 on the sidewalls of the channel layer 120 is etched away, exposing the oxide layer 140 on the sidewalls of the channel layer 120. The remaining material in the recesses on both sides of the sacrificial layer 110 serves as the inner spacer 150. Simultaneously, the spacer material layer 150a on the oxide layer 140 on the surface of the semiconductor substrate 100 and on the top surface of the dummy gate 130 is also removed.

[0044] In some embodiments of the present application, forming the inner spacer material layer 150 a on the sidewall of the oxide layer 140 includes a chemical vapor deposition process or a physical vapor deposition process.

[0045] In some embodiments of the present application, the method for etching and removing the spacer material layer 150a located on the surface of the oxide layer 140 on the sidewalls of the channel layer 120 includes anisotropic dry etching. The anisotropic dry etching can only remove the portion of the spacer material layer protruding from the sidewalls of the channel layer 120, without removing the spacer material layer on the sidewalls of the sacrificial layer 110.

[0046] refer to Figure 8 As shown, in some embodiments of the present application, the method for forming the semiconductor structure further includes etching away the oxide layer 140 on the sidewalls of the channel layer 120 until the sidewalls of the channel layer 120 are exposed. Since the oxide layer 140 on the sidewalls of the channel layer 120 is not protected by the inner sidewall 150 and is completely exposed, it can be etched away. At the same time, the oxide layer 140 on the surface of the semiconductor substrate 100 and the oxide layer 140 on the top surface of the dummy gate 130 are also removed.

[0047] In some embodiments of the present application, the method of etching and removing the oxide layer 140 on the sidewalls of the channel layer 120 until the sidewalls of the channel layer 120 are exposed includes wet etching.

[0048] refer to Figure 9 As shown, a source 160 and a drain 170 are formed on the surface of the semiconductor substrate 100 and on the sidewalls of the channel layer 120 and the inner spacer 150. The positions of the source 160 and the drain 170 can be arbitrary, and the source 160 can be located on the left side, or the drain 170 can be located on the right side.

[0049] In some embodiments of the present application, the method of forming the source 160 and the drain 170 on the surface of the semiconductor substrate 110 and the sidewalls of the channel layer 120 and the inner spacer 150 includes an epitaxial growth process.

[0050] In some embodiments of the present application, the method for forming the semiconductor structure further includes: referring to Figure 10As shown, the dummy gate layer 130 and the sacrificial layer 110 are removed to form a cavity 180; Figure 11 As shown, a metal gate 190 is formed in the cavity 180 .

[0051] In some embodiments of the present application, the method of removing the dummy gate layer 130 and the sacrificial layer 110 to form the cavity 180 includes wet etching.

[0052] In some embodiments of the present application, the method of forming the metal gate 190 in the cavity 180 includes a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or the like.

[0053] In some embodiments of the present application, the material of the metal gate 190 includes aluminum or other work function metals.

[0054] Continue to refer Figure 11 In some embodiments of the present application, the oxide layer 140 on the sidewall of the metal gate 190 and the remaining spacer material layer on the surface of the oxide layer 140 on the sidewall of the metal gate 190 can collectively serve as the outer sidewall of the metal gate 190. In other embodiments of the present application, the top surface and oxide layer of the sidewall of the metal gate 190, as well as the remaining gate material layer on the surface of the oxide layer on the top surface of the sidewall of the metal gate 190, can also be removed to independently form the outer sidewall of the metal gate 190.

[0055] The method for forming a semiconductor structure described in the present application saves the complex process of inner spacer recess etching, is achieved through a simple process of thin film deposition, and is compatible with conventional GAA processes. Specifically, by utilizing the slight difference in etching rates of SiGe and Si materials, a SiGe recess is simultaneously formed as the starting end of the inner spacer during the back etching of the source and drain electrodes; then, by utilizing the difference in oxidation rates of SiGe and Si materials, a distance difference between the outer side of SiGe and the protrusion of the Si surface is further formed, forming the required size of the inner spacer; finally, a sidewall material layer is deposited on all surfaces, and by utilizing the height difference of the protrusion of the Si surface sidewall material layer, the Si surface sidewall material layer is completely etched away using anisotropic dry etching to expose the oxide layer, while the SiGe and other surfaces are wrapped by the sidewall material layer. By utilizing the difference in wet etching of the oxide layer and the sidewall material layer, the oxide layer on the surface of the channel layer is removed, exposing the channel layer required for epitaxy, and simultaneously forming the inner sidewall structure.

[0056] The method for forming a semiconductor structure described in the present application utilizes the difference in etching rates between the sacrificial layer and the channel layer to form a recess on the sidewall of the sacrificial layer, then utilizes the difference in oxidation rates between the sacrificial layer and the channel layer to further deepen the recess, and finally forms an inner sidewall in the recess. This can simplify the process of forming the inner sidewall, reduce damage to the surface of the silicon channel, improve the quality of the source and drain, and thus improve device reliability.

[0057] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0058] It should be understood that the term "and / or" used in this embodiment includes any and all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present.

[0059] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" indicates the absence of intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0060] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0061] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein a surface of the semiconductor substrate includes a plurality of sacrificial layers and channel layers stacked in sequence; forming a dummy gate layer on top surfaces of the sacrificial layer and the channel layer; Etching the sacrificial layer and the channel layer on both sides of the dummy gate layer until the surface of the semiconductor substrate is exposed, and simultaneously forming a recess on the sidewall of the sacrificial layer below the dummy gate layer; forming an oxide layer on the sidewalls of the sacrificial layer and the channel layer by a wet oxidation method, wherein the oxide layer on the sidewalls of the sacrificial layer maintains the shape of the recess and the oxide layer on the sidewalls of the sacrificial layer is thinner than the oxide layer on the sidewalls of the channel layer; Forming an inner sidewall in the recess of the oxide layer on the sidewall of the sacrificial layer, comprising: forming an inner sidewall material layer on the sidewall of the oxide layer; The sidewall material layer located on the surface of the oxide layer on the sidewall of the channel layer is removed by etching to expose the oxide layer on the sidewall of the channel layer. The remaining material in the recesses on both sides of the sacrificial layer is the inner sidewall.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the sacrificial layer includes silicon germanium, and the material of the channel layer includes silicon.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming the plurality of sacrificial layers and channel layers stacked in sequence includes an epitaxial growth process.

4. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of the wet oxidation method include: an oxidation temperature of 500 degrees Celsius to 900 degrees Celsius, and an oxidation time of 15 minutes to 25 minutes.

5. The method for forming a semiconductor structure according to claim 1, wherein: The method of etching and removing the spacer material layer on the surface of the oxide layer on the sidewall of the channel layer includes anisotropic dry etching.

6. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Etching and removing the oxide layer on the sidewall of the channel layer until the sidewall of the channel layer is exposed; A source electrode and a drain electrode are formed on the surface of the semiconductor substrate, the sidewall of the channel layer, and the sidewall of the inner spacer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The method of etching and removing the oxide layer on the sidewall of the channel layer to expose the sidewall of the channel layer includes wet etching.

8. The method for forming a semiconductor structure according to claim 6, wherein: The method of forming the source and the drain on the surface of the semiconductor substrate and the sidewalls of the channel layer and the inner sidewall includes an epitaxial growth process.

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