Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method for fabricating the same are disclosed. The method for fabricating the semiconductor device includes forming a gate structure on a substrate, forming a contact hole etching stop layer on the gate structure, forming an interlayer dielectric layer on the contact hole etching stop layer, performing a solidification fabrication process to make the oxygen concentration of the contact hole etching stop layer different from the oxygen concentration of the interlayer dielectric layer, and performing a metal gate replacement fabrication process to convert the gate structure into a metal gate.

Description

[0001] This application is a divisional application of the invention patent application filed on September 22, 2017, with application number 201710865297.1 and title "Semiconductor Component and Method of Manufacturing Thereof". Technical Field

[0002] This invention relates to a method for fabricating semiconductor devices, and more particularly to a method for reducing the capacitance overlap (C) between the gate structure and the source / drain regions using a curing process after forming an interlayer dielectric layer. ov The method. Background Technology

[0003] In the current semiconductor industry, polysilicon is widely used in semiconductor devices such as metal-oxide-semiconductor (MOS) transistors as the standard gate fill material. However, as the size of MOS transistors continues to shrink, traditional polysilicon gates suffer from problems such as reduced device performance due to the boron penetration effect and the unavoidable depletion effect. This leads to an increase in the equivalent gate dielectric layer thickness, a decrease in gate capacitance, and consequently, a decline in device drive capability. Therefore, the semiconductor industry is exploring new gate fill materials, such as work function metals, to replace traditional polysilicon gates as control electrodes to match high-k gate dielectric layers.

[0004] However, in the current manufacturing process of metal gate transistors, since components such as spacers and contact hole etch stop layers are usually made of materials with high dielectric constants, the overlap capacitance (C) between the gate structure and the source / drain regions is high. ov The inability to control these factors within an optimal range negatively impacts component performance. Therefore, improving current manufacturing processes to address these issues is a crucial task today. Summary of the Invention

[0005] One embodiment of the present invention discloses a method for fabricating a semiconductor device. First, a gate structure is formed on a substrate. Then, a contact hole etch stop layer is formed on the gate structure, and an interlayer dielectric layer is formed on the contact hole etch stop layer. Afterward, a curing process is performed to make the oxygen concentration of the contact hole etch stop layer different from the oxygen concentration of the interlayer dielectric layer. Finally, a metal gate replacement process is performed to convert the gate structure into a metal gate.

[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a gate structure disposed on a substrate, a spacer surrounding the gate structure, a contact hole etch stop layer disposed next to the spacer, and an interlayer dielectric layer surrounding the contact hole etch stop layer, wherein the oxygen concentration of the contact hole etch stop layer is different from the oxygen concentration of the interlayer dielectric layer. Attached Figure Description

[0007] Figures 1 to 5 This is a schematic diagram of a method for fabricating a semiconductor device according to a preferred embodiment of the present invention.

[0008] Explanation of main component symbols

[0009] 12 Basement 14 Fin-like structure

[0010] 16 Gate structure 18 Gate dielectric layer

[0011] 20 Gate material layer 22 First hard mask

[0012] 24 Second hard mask 26 Gap wall

[0013] 28 Offset spacer wall; 30 Main spacer wall

[0014] 32 Source / Drain Region 34 Epitaxial Layer

[0015] 36 Contact hole etch stop layer 38 Interlayer dielectric layer

[0016] 40 Gate dielectric layer 42 High dielectric constant dielectric layer

[0017] 44 Work function metal layer 46 Low impedance metal layer

[0018] 48 Metal gate 50 Hard mask

[0019] 52 Contact plug Detailed Implementation

[0020] Please refer to Figures 1 to 5 , Figures 1 to 5 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to a preferred embodiment of the present invention. Figure 1As shown, a substrate 12, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, is first provided, on which a transistor region, such as a PMOS transistor region or an NMOS transistor region, can be defined. The substrate 12 has at least one fin structure 14 and an insulating layer (not shown), wherein the bottom of the fin structure 14 is covered by the insulating layer, such as silicon oxide, to form a shallow trench isolation. It should be noted that although this embodiment uses the fabrication of a non-planar field-effect transistor, such as a fin structure field-effect transistor, as an example, it is not limited thereto. The present invention can also be applied to general planar field-effect transistors, and this embodiment is also within the scope of the present invention.

[0021] According to one embodiment of the present invention, the fin structure 14 is preferably fabricated using sidewall image transfer (SIT) technology. The procedure generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on the substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layers. The patterned sacrificial layers are then removed, and etching is performed under the cover of the spacers, transferring the pattern formed by the spacers into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0022] In addition, the formation of the fin structure 14 may also include first forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 through an etching process to form the fin structure. Alternatively, the fin structure may be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial fabrication process to grow a semiconductor layer, such as silicon-germanium, on the substrate 12 exposed above the patterned hard mask layer. This semiconductor layer can then serve as the corresponding fin structure. These embodiments of forming fin structures are all within the scope of this invention.

[0023] Next, at least one gate structure 16 or a dummy gate can be formed on the substrate 12. In this embodiment, the gate structure 16 can be fabricated in a manner that meets the requirements of the fabrication process, such as a gate-first fabrication process, a high-k-first fabrication process for the gate-last fabrication process, or a high-k-last fabrication process for the gate-last fabrication process. Taking the high dielectric constant dielectric layer fabrication process of this embodiment as an example, a gate dielectric layer 18 or dielectric layer, a gate material layer 20 composed of polysilicon, a first hard mask 22 and a second hard mask 24 can be sequentially formed on the substrate 12. A patterned photoresist (not shown) is used as a mask to perform a pattern transfer fabrication process. In a single etching or successive etching step, part of the second hard mask 24, part of the first hard mask 22, part of the gate material layer 20 and part of the gate dielectric layer 18 are removed. Then the patterned photoresist is stripped to form a gate structure 16 composed of the patterned gate dielectric layer 18, the patterned gate material layer 20, the patterned first hard mask 22 and the patterned second hard mask 24 on the substrate 12.

[0024] Then, at least one spacer wall 26 is formed on the sidewall of the gate structure 16. A source / drain region 32 and / or epitaxial layer 34 are formed in the fin structure 14 and / or the substrate 12 on both sides of the spacer wall 26. A metal silicide (not shown) is selectively formed on the surface of the source / drain region 32 and / or the epitaxial layer 34, and a contact hole etch stop layer 36 is formed on the surface of the substrate 12 and the gate structure 16. In this embodiment, the spacer wall 26 can be a single spacer wall or a composite spacer wall, for example, it can include a bias spacer wall 28 and a main spacer wall 30. The bias spacer wall 28 and the main spacer wall 30 can contain the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride (SiON), and silicon carbide (SiCN). The source / drain region 32 can contain different dopants depending on the conductivity type of the transistor, for example, it can contain P-type dopants or N-type dopants. The contact hole etch stop layer 36 preferably contains silicon nitride or silicon carbide nitride, but is not limited to these.

[0025] Then as Figure 2As shown, an interlayer dielectric layer 38 composed of silicon dioxide or silicon oxycarbide (SiOC) is first formed on the contact hole etch stop layer 36, and then a curing process is performed to improve the strength of the main spacer wall 30. In detail, the curing process performed in this embodiment is preferably an extreme ultraviolet (EUV) curing process, wherein the curing process preferably involves introducing ozone (O3) while performing ultraviolet irradiation and a heat treatment process, thereby changing the dielectric constant of the spacer wall 26 and the contact hole etch stop layer 36 and simultaneously reducing the capacitance overlap (C) value generated between the gate structure 16 and the source / drain region 32. ov ).

[0026] It is worth noting that, in this embodiment, the main spacer wall 30 and the contact hole etch stop layer 36 are preferably made of materials with high dielectric constants before the curing process, such as silicon carbide (SiCN). Since this embodiment primarily uses heat treatment to drive oxygen atoms from ozone into the main spacer wall 30, the contact hole etch stop layer 36, and the interlayer dielectric layer 38 during the curing process, these materials are preferably converted to materials with lower dielectric constants after the extreme ultraviolet (EUV) curing process. More specifically, the main spacer wall 30 and the contact hole etch stop layer 36, originally made of silicon carbide, are preferably converted to silicon oxycarbonate (SiOCN) with even lower dielectric constants after the oxygen atoms are driven in, while the interlayer dielectric layer 38, made of silicon oxycarbide (SiOC), retains its original material.

[0027] Furthermore, the dielectric constants of the main spacer wall 30, the contact hole etch stop layer 36, and the interlayer dielectric layer 38 are slightly adjusted during the curing process. For example, the main spacer wall 30, originally composed of silicon carbide with a dielectric constant of approximately 5.0, is preferably converted to silicon oxynitride with a dielectric constant of approximately 4.6; the contact hole etch stop layer 36, originally composed of silicon carbide with a dielectric constant of approximately 5.0 or slightly higher, is preferably converted to silicon oxynitride with a dielectric constant of approximately 4.6; and the interlayer dielectric layer, originally composed of silicon carbide with a dielectric constant of approximately 4.6, maintains the same material and dielectric constant. In other words, the main spacer wall 30, the contact hole etch stop layer 36, and the interlayer dielectric layer 38, which originally had different dielectric constants, are preferably converted into materials with the same dielectric constant but possibly different materials after the aforementioned curing process. The offset spacer 28, which is originally made of silicon carbide, is located closer to the gate structure 16 and is less likely to be driven into oxygen atoms during the curing process, thus reducing its dielectric constant. Therefore, its dielectric constant value is still slightly higher than that of the main spacer 30 after the curing process, for example, about 5.0.

[0028] Furthermore, although the foregoing embodiments use silicon carbide as an example to describe the main spacer wall 30 and the contact hole etch stop layer 36, they are not limited thereto. According to one embodiment of the present invention, one or both of the main spacer wall 30 and the contact hole etch stop layer 36 may be selected to be made of silicon nitride with a dielectric constant of about 6.5 before the curing process. In this case, after oxygen atoms are driven into the main spacer wall 30 and the contact hole etch stop layer 36 during the curing process, it is preferable to convert silicon nitride to silicon oxynitride (SiON) respectively. Moreover, after the dielectric constant of both is reduced by the curing process, it can be approximately equal to the dielectric constant value of the interlayer dielectric layer 38. This embodiment is also within the scope of the present invention.

[0029] Furthermore, from another perspective, since this embodiment preferably utilizes a heat treatment process to drive oxygen atoms from ozone into the main spacer wall 30, the contact hole etch stop layer 36, and the interlayer dielectric layer 38 during the curing process, the oxygen concentration of the contact hole etch stop layer 36 is preferably different from the oxygen concentration of the interlayer dielectric layer 38 after the curing process. For example, the oxygen concentration of the interlayer dielectric layer 38 is preferably higher than the oxygen concentration of the contact hole etch stop layer 36 after the curing process, or, from a more detailed perspective, the oxygen concentration on the surface of the contact hole etch stop layer 36 is preferably higher than the oxygen concentration inside the contact hole etch stop layer 36.

[0030] In this embodiment, the heat treatment temperature in the UV curing process is preferably between 500°C and 800°C, the curing pressure is preferably between 1 Torr and 760 Torr, and the curing time is between 50 minutes and 70 minutes, or preferably about 60 minutes.

[0031] like Figure 3 As shown, a planarization process is then performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 32 and part of the contact hole etching stop layer 30, exposing the second hard mask 24, so that the upper surface of each second hard mask 24 is flush with the upper surface of the interlayer dielectric layer 32. It is worth noting that although this embodiment preferably performs the aforementioned curing process before the planarization process, it is not limited to this order. According to one embodiment of the present invention, the aforementioned curing process can also be performed after the planarization process, for example, after the upper surface of the second hard mask 24 is aligned with the upper surface of the interlayer dielectric layer 38. This embodiment is also within the scope of the present invention.

[0032] like Figure 4 As shown, a metal gate replacement fabrication process is then performed to convert each gate structure 16 into a metal gate. For example, a selective dry or wet etching process can be performed first, such as using an etching solution such as ammonia (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the second hard mask 24, the first hard mask 22, the gate material layer 20, and even the gate dielectric layer 18 in the gate structure 16, to form a groove (not shown) in the interlayer dielectric layer 38. Then, a selective dielectric layer or gate dielectric layer 40, a high dielectric constant dielectric layer 42, a work function metal layer 44, and a low impedance metal layer 46 are sequentially formed in the groove. Then, a planarization process is performed, such as using CMP to remove part of the low impedance metal layer 46, part of the work function metal layer 44, and part of the high dielectric constant dielectric layer 42 to form a gate structure composed of a metal gate 48. Taking the gate structure fabricated using the high dielectric constant dielectric layer fabrication process in this embodiment as an example, each metal gate 48 preferably includes a dielectric layer or gate dielectric layer 40, a U-shaped high dielectric constant dielectric layer 42, a U-shaped work function metal layer 44, and a low impedance metal layer 46.

[0033] In this embodiment, the high dielectric constant dielectric layer 42 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. lead zirconate titanate (SrBi₂Ta₂O₉, SBT) and lead zirconate titanate (PbZr) x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x The group consisting of TiO3, BST, or combinations thereof.

[0034] The work function metal layer 44 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 44 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto; if the transistor is a P-type transistor, the work function metal layer 44 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 44 and the low impedance metal layer 46. The material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low impedance metal layer 46 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof.

[0035] Subsequently, as Figure 5 As shown, a portion of the low-impedance metal layer 46, a portion of the work function metal layer 44, and a portion of the high dielectric constant dielectric layer 42 can be removed to form a groove (not shown). Then, a hard mask 50 made of, for example, silicon nitride is filled into the groove, and the upper surface of the hard mask 50 is aligned with the upper surface of the interlayer dielectric layer 38.

[0036] A pattern transfer fabrication process can then be performed. For example, a patterned mask can be used to remove a portion of the interlayer dielectric layer 38 next to the metal gate 48 and a portion of the contact hole etching stop layer 36 to form multiple contact holes (not shown) and expose the underlying source / drain regions 32. Then, the desired metal material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. A planarization fabrication process is then performed, for example, by chemical mechanical polishing to remove a portion of the metal material to form contact plugs 52 in each contact hole to electrically connect the source / drain regions 32. This completes the fabrication of the semiconductor device according to the preferred embodiment of the present invention.

[0037] Please continue to refer to Figure 5 , Figure 5 A schematic diagram of the structure of a semiconductor device according to the present invention is also disclosed. For example... Figure 5As shown, the semiconductor device mainly includes a gate structure or metal gate 48 disposed on the substrate 12 or fin structure 14, a spacer 26 surrounding the gate structure, a contact hole etch stop layer 36 disposed next to the spacer 26, and an interlayer dielectric layer 38 surrounding the contact hole etch stop layer 36. The spacer 26 further includes a bias spacer 28 and a main spacer 30.

[0038] In this embodiment, since oxygen atoms are driven into the main spacer wall 30, the contact hole etch stop layer 36, and the interlayer dielectric layer 38 by heat treatment during the curing process as described above, the oxygen concentration of the contact hole etch stop layer 36 is preferably different from the oxygen concentration of the interlayer dielectric layer 38, or more specifically, the oxygen concentration of the interlayer dielectric layer 38 is preferably higher than the oxygen concentration of the contact hole etch stop layer 36, and the oxygen concentration on the surface of the contact hole etch stop layer 36 is higher than the oxygen concentration inside the contact hole etch stop layer 36.

[0039] Furthermore, from the viewpoint of dielectric constant, the contact hole etch stop layer 36 and the interlayer dielectric layer 38 preferably have the same dielectric constant after the curing process, or according to an embodiment of the present invention, the main sidewall 30, the contact hole etch stop layer 36, and the interlayer dielectric layer 38 are all converted to the same dielectric constant after the curing process. The dielectric constant of the offset spacer wall 28 is preferably greater than that of the main sidewall 30, the contact hole etch stop layer 36, and the interlayer dielectric layer 38 after the curing process.

[0040] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor element comprising: The gate structure is disposed on a substrate; An offset spacer wall surrounds the gate structure; A main spacer wall surrounds the offset spacer wall; A contact hole etching stop layer is disposed adjacent to the main gap wall, wherein the dielectric constant of the offset gap wall is greater than the dielectric constant of the contact hole etching stop layer surface; and Interlayer dielectric layer, etch stop layer surrounding the contact hole, The contact hole etching stop layer and the interlayer dielectric layer have the same dielectric constant.

2. The semiconductor device of claim 1, wherein the oxygen concentration of the interlayer dielectric layer is higher than the oxygen concentration of the contact hole etch stop layer.

3. The semiconductor device of claim 1, wherein the oxygen concentration on the surface of the contact hole etch stop layer is higher than the oxygen concentration inside the contact hole etch stop layer.

4. The semiconductor device of claim 1, wherein the main spacer wall and the contact hole etch stop layer comprise the same material.

5. The semiconductor device of claim 1, wherein the offset spacer wall is SiCN and the main spacer wall is SiOCN.

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