Mim capacitor structure

Abstract

An integrated circuit structure is provided. The integrated circuit structure includes a back end of line (BEOL) wiring layer including metal lines and a first region between the metal lines. The integrated circuit structure also includes a metal-insulator-metal (MIM) capacitor formed in the first region. The MIM capacitor includes a first electrode, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, a second dielectric layer formed on the second electrode, a third electrode formed on the second dielectric layer, a third dielectric layer formed on the third electrode, a fourth electrode formed on the third dielectric layer, a first metal interconnect electrically connecting the first electrode and the third electrode, and a second metal interconnect electrically connecting the second electrode and the fourth electrode.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of electrical, electronic and computer engineering. In particular, the present disclosure relates to metal-insulator-metal (MIM) capacitors having different plate structures. BACKGROUND

[0002] Generally, MIM capacitors have a sandwich structure and can be described as parallel plate capacitors. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating dielectric layer.

[0003] Metal-insulator-metal (MIM) capacitors can be used in high performance applications of complementary metal-oxide-semiconductor (CMOS) technology. For example, MIM capacitors have been used in functional circuits, such as mixed signal circuits, analog circuits, radio frequency (RF) circuits, dynamic random access memory (DRAM), embedded DRAM, and logic operation circuits. In system-on-chip (SOC) applications, different capacitors for different functional circuits must be integrated on the same chip for different purposes. For example, in mixed signal circuits, capacitors are used as decoupling capacitors and high frequency noise filters. For DRAM and embedded DRAM circuits, capacitors are used for memory storage. However, for RF circuits, capacitors are used in oscillators and phase shift networks for coupling and / or bypass purposes. For microprocessors, capacitors can be used for decoupling. High frequency and low power of semiconductor chips can require a large number of decoupling capacitors. MIM capacitors have been used for decoupling in these applications. SUMMARY

[0004] Certain embodiments relate to an integrated circuit structure. The integrated circuit structure includes a back end of line (BEOL) wiring layer including metal lines and a first region between the metal lines. The integrated circuit structure also includes a metal-insulator-metal (MIM) capacitor formed in the first region. The MIM capacitor includes a first electrode, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, a second dielectric layer formed on the second electrode, a third electrode formed on the second dielectric layer, a third dielectric layer formed on the third electrode, a fourth electrode formed on the third dielectric layer, a first metal interconnect electrically connecting the first electrode and the third electrode, and a second metal interconnect electrically connecting the second electrode to the fourth electrode.

[0005] Other embodiments of the disclosure relate to a method of manufacturing an integrated circuit structure. The method includes forming a back end of line (BEOL) wiring layer including metal lines and a first region between the metal lines. The method also includes forming a metal-insulator-metal (MIM) capacitor in the first region by forming a first electrode, forming a first dielectric layer on the first electrode, forming a second electrode on the first dielectric layer, forming a second dielectric layer on the second electrode, forming a third electrode on the second dielectric layer, forming a third dielectric layer on the third electrode, forming a fourth electrode on the third dielectric layer, forming a first metal interconnect to electrically connect the first electrode and the third electrode, and forming a second metal interconnect to electrically connect the second electrode to the fourth electrode.

[0006] The above summary is not intended to describe each illustrated embodiment or every implementation of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings, which are included in the disclosure and form a part of the disclosure, illustrate embodiments of the disclosure and, together with the description, explain the principles of the disclosure. The drawings merely illustrate certain embodiments and are not intended to limit the disclosure.

[0008] FIG. 1A is a cross-sectional view of an example semiconductor device showing the use of dummy electrodes in empty regions between metal lines.

[0009] FIG. 1B is a plan view of the example semiconductor device of FIG. 1A

[0010] FIG. 2A is a plan view of an example shape of a bottom electrode of a multi-plate MIM capacitor device in empty regions between metal lines according to an embodiment.

[0011] FIG. 2B ​is a plan view of another example shape of a bottom electrode of a multi-plate MIM capacitor according to an embodiment.

[0012] FIG. 2C is a plan view of another example shape of a bottom electrode of a multi-plate MIM capacitor according to an embodiment.

[0013] FIG. 3A is a cross-sectional view depicting a multi-plate MIM capacitor device at an intermediate stage of a manufacturing process according to an embodiment.

[0014] FIG. 3B is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment. FIG. 3A is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment.

[0015] FIG. 3C is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment. FIG. 3B is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment.

[0016] FIG. 3D is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment. FIG. 3C is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment.

[0017] FIG. 3E is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment. FIG. 3D is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment.

[0018] FIG. 3F is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment. FIG. 3E is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment.

[0019] FIG. 3G is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment. FIG. 3F is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment.

[0020] FIG. 3H is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment. FIG. 3G is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment.

[0021] FIG. 3I is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment. FIG. 3H is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment.

[0022] FIG. 3J is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment. FIG. 3I is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment.

[0023] FIG. 3K is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment. FIG. 3JCross-sectional view of a multi-plate MIM capacitor device after an additive manufacturing operation.

[0024] FIG. 3L is according to an embodiment FIG. 3K Cross-sectional view of a multi-plate MIM capacitor device after an additive manufacturing operation.

[0025] FIG. 3M is according to an embodiment FIG. 3L Cross-sectional view of a multi-plate MIM capacitor device after an additive manufacturing operation.

[0026] FIG. 4 is a cross-sectional view depicting a multi-plate MIM capacitor device according to an embodiment.

[0027] FIG. 5 is a cross-sectional view depicting a multi-plate MIM capacitor device according to an embodiment.

[0028] It is to be understood that the elements in the figures are shown for the purpose of simplicity and clarity. Conventional elements related to semiconductor devices have not been shown in order to avoid obscuring the subject matter of the present disclosure. DETAILED DESCRIPTION

[0029] The present disclosure describes metal-insulator-metal (MIM) capacitor devices and methods of manufacturing MIM capacitor devices. In particular, the present disclosure describes MIM capacitor devices that are located in a region between trace metal lines of a semiconductor device and that include at least four or five MIM plates (i.e., alternating metal and insulator layers).

[0030] Various embodiments of the present disclosure are described herein with reference to the associated drawings. Alternative embodiments can be devised without departing from the scope of the present disclosure. Note that the various connections and positional relationships (e.g., above, below, right, left, lateral, longitudinal, back, etc.) depicted in the drawings have been represented for purposes of clarity and are not necessarily drawn to scale. Unless otherwise noted, connections and / or positional relationships between elements are direct connections and / or direct positional relationships. The present disclosure is not intended to be limited in scope to the depictions of the various embodiments, and the present disclosure is not intended to be limited in scope to the depictions of the various embodiments, and the various embodiments are not intended to be limited in scope to the depictions of the various embodiments. Thus, the coupling between entities can be direct or indirect, and the positional relationships between entities can be direct or indirect. As an example of indirect positional relationships, references in this specification to forming a layer “on” or “under” another layer can include instances where one or more intervening layers (e.g., layers “C”) are disposed between the two layers, so long as the relevant properties and functions of the two layers are substantially unchanged by the intervening layer(s).

[0031] The following definitions and abbreviations are to be used for interpretation of the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains" or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, a process, a method, an article, or an apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0032] For the purposes of the description hereinafter, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figure. The terms "overlying", "atop", "on top of", "positioned on" or "positioned on top of" mean that the first element (such as first structure) is present on the second element (such as second structure), wherein intervening elements (such as interfacial structures) can be present between the first element and the second element. The term "direct contact" means that the first element (such as first structure) and the second element (such as second structure) are connected without any intermediate conductive, insulating or semiconductor layers at the interface of the two elements. It should be noted that the term "selective to" (such as, for example, "a first element is selective to a second element") means that the first element can be etched and the second element can act as an etch stop.

[0033] For the sake of brevity, conventional techniques related to semiconductor devices and integrated circuit (IC) fabrication can or can not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well-known and, as such, have been omitted or described in a simple manner.

[0034] Generally, the various processes used to form the microchips that will be packaged into ICs are divided into four general categories, namely, film deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0035] Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. Another deposition technique is plasma-enhanced chemical vapor deposition (PECVD), which is a process that uses energy within a plasma to initiate reactions at the wafer surface that would otherwise require higher temperatures associated with conventional CVD. The high-energy ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0036] Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry), chemical mechanical planarization (CMP), etc. One example of a removal process is ion beam etching (IBE). Generally, IBE (or milling) refers to a dry plasma etching method that utilizes a remote broad-beam ion / plasma source to remove substrate material by physical inert gas and / or chemical reactive gas means. Similar to other dry plasma etching techniques, IBE has benefits such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching (RIE). Generally, RIE uses a chemically reactive plasma to remove material deposited on a wafer. With RIE, a plasma is generated by electromagnetic fields at low pressure (vacuum). High-energy ions from the RIE plasma attack the wafer surface and react with it to remove material.

[0037] Semiconductor doping is the alteration of electrical properties by doping, e.g., transistor source and drain (typically by diffusion and / or by ion implantation). These doping processes are followed by in-furnace annealing or rapid thermal annealing ("RTA"). Annealing is used to activate the implanted dopants. Films of conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be altered with the application of voltage. By forming structures of these various components, millions of transistors can be constructed and wired together to form the complex circuitry of modern microelectronic devices.

[0038] Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern onto the substrate. In semiconductor lithography, the pattern is formed from a light-sensitive polymer known as photoresist. To construct the complex structures that make up a transistor and the many wiring of millions of transistors that make up an electrical circuit, the lithography and etch pattern transfer steps are repeated many times. Each pattern printed on the wafer is aligned with the previously formed pattern, and gradually the conductors, insulators, and selectively doped regions are built up to form the final device.

[0039] Turning now to a more particular overview of the technology with which aspects of the present disclosure are more closely related, generally, MIM capacitors refer to capacitors having a stacked structure, such as including a bottom electrode, a top electrode, and an insulator therebetween. More particularly, MIM capacitors are often used in high performance applications of CMOS technology. Generally, MIM capacitors have a sandwich structure and can be described as parallel plate capacitors. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating dielectric layer. Both the two parallel plates are typically formed of TiN, which is patterned and etched using several photolithography mask steps. The thin insulating dielectric layer is typically made of silicon oxide, silicon nitride, or high-K dielectric material (such as AI2O3, HfO2, ZrO2, or combinations thereof) deposited, for example, by chemical vapor deposition (CVD). Certain embodiments of the present invention describe MIM capacitors having more than the traditional three plates (i.e., a first metal layer, an insulator layer, and a second metal layer). For example, certain embodiments of the present invention describe MIM capacitors of four and five plates.

[0040] As discussed herein, high frequency and low power of semiconductor chips can require a large number of decoupling capacitors. MIM capacitors have been used for decoupling in these applications. These capacitors can take up valuable chip area and impact the overall size of the chip.

[0041] Certain areas of a semiconductor wafer, such as metal fill shape areas between metal wiring, can typically utilize dummy metal fill shapes. These dummy metal fill shapes do not contribute to the performance of the device in any way and are primarily used to meet the uniform metal density requirements for effective chemical mechanical planarization (CMP), patterning, and etching. In other words, if there are areas with little metal object, the CMP performance is degraded. Without meeting the uniform metal density requirements, metal dishing and / or dielectric erosion can occur, which can undesirably result in surface topography after CMP (i.e., instead of planarization). Certain embodiments of the present invention place MIM capacitors in these metal fill shape areas instead of using dummy metal fill shapes. In this way, it is beneficial to use decoupling capacitors in areas that typically do not function. Furthermore, the MIM capacitors include metal layers that can help meet the uniform metal density requirements for CMP and other processes.

[0042] Referring now to the drawings in which like numerals refer to like or similar elements throughout the several views, first reference is made to FIG. 1A and 1B showing an example semiconductor device 100 including dummy electrodes 106 (i.e., metal fill shapes). In this example, a semiconductor wafer or substrate 102 is provided. Several back end of line (BEOL) wiring layers of a semiconductor integrated circuit are shown. In this example, dummy electrodes 106 are provided between the BEOL wiring layers. In this example, the dummy electrodes 106 are metal fill shapes that do not contribute to the performance of the device in any way and are primarily used to meet the uniform metal density requirements for effective chemical mechanical planarization (CMP), patterning, and etching. In other words, if there are areas with little metal object, the CMP performance is degraded. Without meeting the uniform metal density requirements, metal dishing and / or dielectric erosion can occur, which can undesirably result in surface topography after CMP (i.e., instead of planarization). Certain embodiments of the present invention place MIM capacitors in these metal fill shape areas instead of using dummy metal fill shapes. In this way, it is beneficial to use decoupling capacitors in areas that typically do not function. Furthermore, the MIM capacitors include metal layers that can help meet the uniform metal density requirements for CMP and other processes. FIG. 1Alower wiring lines 104 and dummy electrodes 106 are formed in the lower portion. A capping layer 108 is formed over the lower wiring lines 104 and dummy electrodes 106. The capping layer 108 can be formed of, for example, AIN, SiN, SiCN, combinations thereof, or any other suitable dielectric material. An interlayer dielectric layer 110 is formed over the lower capping layer 108, and several metal interconnects 112 extend upward through the dielectric layer 110 to contact upper wiring lines 114. An upper capping layer 116 is formed over the upper wiring lines 114. The upper capping layer 116 can be made of the same or similar material as the lower capping layer 116. Because the dummy electrodes 106 do not function in the semiconductor device, they are not connected with the lower wiring lines (not shown) or the upper wiring lines 114. However, as noted above, they do have the effect of increasing the metal density in the additional “empty” areas between the active metal lines (e.g., the combination of the upper wiring lines 114, metal interconnects 112, and lower wiring lines 104). This allows for an improvement in the performance of the CMP process, but the dummy electrodes 106 utilize valuable space on the semiconductor wafer.

[0043] Referring now to FIG. 1B , this figure illustrates FIG. 1A a plan view of the semiconductor device 100 taken along the cut line A-A. FIG. 1B One example of the placement pattern of the dummy electrodes 106 and how much space they can occupy in the empty areas between adjacent lower wiring lines 104 is shown.

[0044] Referring now to FIG. 2A to FIG. 2C , several example shapes of the bottom electrode (or first electrode 202) of a MIM capacitor device 200 are shown, in accordance with certain embodiments. In each of these figures, the first electrode 202 has a different shape with different patterns of openings 204. It should be appreciated that the first electrode 202 can have any suitable shape that meets the uniform metal density requirements of CMP and optimizes the MIM capacitor density over the semiconductor wafer substrate 102.

[0045] Referring now to FIG. 3A to FIG. 3M , first referring to FIG. 3A , example embodiments illustrating a method of fabricating a quad plate MIM capacitor (MIMCap) device 300 are shown. As shown in FIG. 3A , a substrate 302 is provided. In certain embodiments, the substrate can be an interlayer dielectric layer deposited over different BEOL layers (not shown). In FIG. 3A , a first (lower) wiring layer 304 of an example semiconductor device is shown after several BEOL processing steps (e.g., etching, deposition, metal filling, planarization, etc.) are completed. In certain embodiments, a first electrode 306 (or bottom electrode) of the MIMCAP device 300 is formed instead of a dummy electrode 106 as described above with respect toFIG. 1A and 1B The dummy electrode is formed as described. FIG. 3B As shown, a capping layer or first insulating layer 308 is formed on top of the first wiring layer 304, the first electrode 306, and the surrounding ILD layer or substrate 302. The first electrode 306 is the bottommost plate of the MIM capacitor. The capping layer (or first insulating layer 308) can be formed of, for example, AIN, SiN, SiCN, combinations thereof, or any other suitable dielectric material.

[0046] Referring now to FIG. 3C A metal plate 310 is formed on top of the first insulating layer 308. Although not shown in FIG. 3C , the metal plate 310 can be initially formed by a thick metal plate deposition process, which is subsequently patterned into the desired shape. In certain embodiments, the metal plate 310 is composed of at least one of TiN, TaN, Al, or any other suitable electrode material. As shown, FIG. 3C The position of the metal plate 310 is slightly offset to the left relative to the position of the first electrode 306. In particular, the right side of the metal plate 310 is more to the left than the right side of the first electrode 306, and the left side of the metal plate 310 is also more to the left than the left side of the first electrode 306. In certain embodiments, the metal plate 310 can be aligned with the first electrode 306.

[0047] Referring now to FIG. 3D , after the metal plate 310 is patterned in FIG. 3C , a first ILD layer 312 is formed to cover the surface of the first insulating layer 308 and the metal plate 310. The surface of the first ILD layer 312 is then planarized using a CMP process or the like and the upper surface of the metal plate 310 is exposed.

[0048] Referring now to FIG. 3E , a second electrode 314 is formed on the metal plate 310 by a deposition and patterning process. In certain embodiments, the size and position of the second electrode 314 are approximately the same as the size and position of the thick metal plate 310. It can also be considered that the combination of the metal plate 310 and the second electrode 314 is effectively the second electrode of the MIMCAP device 300. In certain embodiments, the second electrode 314 is composed of TiN, TaN, or any other suitable electrode material. The material of the second electrode 314 can be the same as or different from the material of the underlying metal plate 310. It should be understood that in the case where the material of the second electrode 314 is the same as the material of the underlying metal plate 310, the two layers can be formed in a single step and considered to be a single layer.

[0049] Referring now to FIG. 3FA first high-K dielectric layer 316 is conformally deposited over the entire surface of the wafer. The conformal first high-K dielectric layer 316 includes a high-K dielectric material. In general, the term high-K refers to a material that has a high dielectric constant (kappa, kappa) compared to silicon dioxide. High-K dielectric materials are used in semiconductor manufacturing processes where they are often used to replace a silicon dioxide gate dielectric or another dielectric layer of a device. Thus, as used herein, the term high-K refers to a material that has a relative dielectric constant K that is much higher than that of silicon dioxide (e.g., for hafnium dioxide (Hf02), the dielectric constant kappa = 25, as opposed to a dielectric constant of 4 for silicon dioxide). Examples of suitable high-K gate dielectric materials include, but are not limited to, Hf02, AI2O3, Zr02, and / or lanthanum oxide (La203). As a result of the conformal coating of the first high-K dielectric layer 316, the surface has a degree of topography, with the upper layer of the high-K dielectric layer 316 being higher in the area of the second electrode 314. However, it will be appreciated that in other embodiments, the first high-K dielectric layer 316 can be deposited thicker and then planarized using CMP (which would require an additional processing step).

[0050] Referring now to FIG. 3G A third electrode 318 is formed on top of the first high-K dielectric layer 316. Although FIG. 3G not shown in FIG. 3, the third electrode 318 can initially be formed by a deposition process followed by patterning to form the desired shape. In certain embodiments, the third electrode 318 is composed of at least one of TiN, TaN, Al, or any other suitable electrode material. As FIG. 3G shown, the position of the third electrode 318 is slightly offset to the right relative to the position of the second electrode 314. In particular, the right side of the third electrode 318 is further to the right than the right side of the second electrode 314, and the left side of the third electrode 318 is also further to the right than the left side of the second electrode 314. In the example embodiment shown, the position of the right side of the third electrode 318 corresponds approximately to the position of the right side of the first electrode 306. This approximate alignment will allow for a subsequent electrical connection between the first electrode 306 and the third electrode 318, as discussed in detail below. FIG. 3G

[0051] Referring now to FIG. 3H A second high-K dielectric layer 320 is conformally deposited over the entire surface of the wafer. The conformal second high-K dielectric layer 320 includes a high-K dielectric material, which can be the same or different than the material of the first high-K dielectric layer 316. Again, as a result of the conformal coating of the first high-K dielectric layer 316 and the second high-K dielectric layer 320, as well as the formation of the second electrode 314 and the third electrode 318, the surface has a degree of topography.

[0052] Referring now to FIG. 3I ​A fourth electrode 322 is formed on the second high-K dielectric layer 320 by a deposition and patterning process. The material of the fourth electrode 322 can be the same or different from the material of the underlying electrode layer. In some embodiments, the size and position of the fourth electrode 322 is substantially the same as the size and position of the thick metal plate 310 and the second electrode 314, but this is not strictly required. The substantial alignment of the fourth electrode 322 will allow for a subsequent electrical connection between the second electrode 314 and the fourth electrode 322, as discussed in detail below.

[0053] Referring now to FIG. 3J A second interlayer dielectric layer 324 is formed over the entire surface of the wafer to cover the fourth electrode 322 and the second high-K dielectric layer 320. A CMP process is then performed on the second interlayer dielectric layer 324 to planarize the surface of the layer.

[0054] In this example, the fourth electrode 322 has a stepped surface profile corresponding to the surface profile of the underlying second high-K dielectric layer 320 (i.e., because the second high-K dielectric layer 320 was conformally formed over all surfaces), and the third electrode 318 has a stepped surface profile corresponding to the surface profile of the underlying first high-K dielectric layer 316 (i.e., because the first high-K dielectric layer 316 was conformally formed over all surfaces).

[0055] Referring now to FIG. 3K An etching process (e.g., RIE) is performed on the wafer to create spaces to form subsequent metal interconnects and upper metal wiring lines of the BEOL layer. At the same time, etching is performed in the vicinity of the MIMCap device 300 to allow for subsequent electrical connections of the individual MIMCap electrodes.

[0056] Referring now to FIG. 3L Metal interconnects 328A and 328B and a second wiring layer 326 (i.e., an upper layer of wiring lines) are formed. In regions that do not correspond to the MIMCAP device 300, the metal interconnects 328A electrically connect the first wiring layer 304 to an upper layer or second wiring layer 326 of the BEOL layer. However, in regions that correspond to the MIMCAP device 300, the metal interconnects 328B electrically connect the individual electrodes together. Specifically, the right-hand metal interconnects of the metal interconnects 328B electrically connect the first electrode 306 to the third electrode 318, and the left-hand metal interconnects of the metal interconnects 328B electrically connect the second electrode 314 to the fourth electrode 322.

[0057] In certain embodiments, all of the electrodes (i.e., 306, 310, 314, 318, and 322) are vertically aligned. In this case, a via hole larger than the via hole size is needed on the electrodes with no contact between the electrode and the via hole to allow the via hole 328 to pass through. In these embodiments, a via hole is formed where contact between the electrode and the via hole is needed.

[0058] Referring now to FIG. 3M , another cap layer or second insulating layer 330 is formed on top of the second wiring layer 326 and surrounding second interlayer dielectric layer 324. Thus, a four plate MIMcap device 300 is formed where two of the four electrodes are connected together on the right side and the other two of the electrodes are connected together on the left side. In addition, in certain embodiments, only one additional mask (i.e., for forming the metal plate 310) is needed and only four additional process steps are needed to structure the MIMCAP device 300 into the empty space between the wires in the BEOL layer. In other embodiments, more than one additional mask can be needed where in addition to patterning the metal plate 310, the third electrode 318 and the second high K dielectric layer 320 must also be patterned. In these embodiments, there can be more than four additional processing steps.

[0059] Referring now to FIG. 4 , an example embodiment illustrating a method of fabricating a five plate MIM capacitor (MIMCAP) device 400 is shown. FIG. 4 Many of the processes in the fabrication of the MIMCAP device 400 in FIG. 3A to FIG. 3M are the same as described above with respect to FIG. 3A to FIG. 3M and will not be repeated here. However, there are certain differences. First, the location of the metal plate 310 is shifted to the right relative to the embodiment of . Second, a portion of the first interlayer dielectric layer 312 is inserted between the metal plate 310 and the second electrode 314 to electrically isolate these layers from each other. Third, the etch depth of the metal interconnect 428 is different in the region corresponding to the MIMCAP device 400. In particular, the metal interconnect 428 on the left side of the MIMCAP device is formed down to a depth corresponding to the upper surface of the first electrode 306, thereby electrically connecting the first electrode 306, the second electrode 314, and the fourth electrode 322. In addition, the metal interconnect 428 on the right side of the MIMCAP device 400 is formed down to a depth corresponding to the upper surface of the metal plate 310, thereby electrically connecting the metal plate 310 to the third electrode 318. Thus, there are a total of five conductive layers in this MIMCAP device 400, three on the left side and two on the right side. In this embodiment, the metal plate 310 can be considered to be a fifth electrode.

[0060] In this example, the fourth electrode 322 has a stepped surface profile corresponding to the surface profile of the underlying second high-K dielectric layer 320 (i.e., because the second high-K dielectric layer 320 is conformally formed over all surfaces), and the third electrode 318 has a stepped surface profile corresponding to the surface profile of the underlying first high-K dielectric layer 316 (i.e., because the first high-K dielectric layer 316 is conformally formed over all surfaces).

[0061] Reference is now made to FIG. 5 , which shows an example embodiment illustrating a method of fabricating another five-plate MIM capacitor (MIMCap) device 500. FIG. 5 Many of the processes in the fabrication of the MIMCAP device 500 in FIG. 4 are the same as described above with respect to FIG. 5 , and will not be repeated here. However, there are certain differences. In particular, a third high-K dielectric layer 502 is formed between the metal plate 310 and the first interlayer dielectric layer 312. In certain embodiments, the second high-K dielectric layer 502 is formed on top of the metal plate 310, and they are subsequently patterned together. In other embodiments, the second high-K dielectric layer 502 is not patterned, and it covers the entire surface, similar to other high-K dielectric layers described herein. Thus, in the embodiment shown in FIG. 5 , there is a bilayer dielectric structure between the metal plate 310 and the second electrode 314, and this bilayer dielectric structure includes both the first interlayer dielectric layer 312 and the third high-K dielectric layer 502.

[0062] The description of the various embodiments has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An integrated circuit structure comprising: a lower back-end-of-the-line (BEOL) wiring layer including a lower metal line and an upper BEOL wiring layer including an upper metal line, the lower metal line being connected to the upper metal line via an interconnect, the lower metal line and the upper metal line extending in a first direction in a plan view and defining a filled-shape region between the lower metal lines in the plan view, the filled-shape region not including elements of the lower BEOL wiring layer; as well as a metal-insulator-metal (MIM) capacitor formed in the fill-shaped region, the fill-shaped region extending at least partially from the lower BEOL wiring layer to the upper BEOL wiring layer along the thickness direction of the integrated circuit structure and not overlapping the lower metal line or the upper metal line in the plan view, The first electrode of the MIM capacitor is formed in the same layer as the lower metal line in the thickness direction, and all remaining portions of the MIM capacitor are formed between the lower metal line and the upper metal line in the thickness direction.

2. The integrated circuit structure of claim 1 , wherein the MIM capacitor comprises: the first electrode; a first dielectric layer formed on the first electrode; a second electrode formed on the first dielectric layer; a second dielectric layer formed on the second electrode; a third electrode formed on the second dielectric layer; a third dielectric layer formed on the third electrode; a fourth electrode formed on the third dielectric layer; a first metal interconnection electrically connecting the first electrode and the third electrode; as well as A second metal interconnection electrically connecting the second electrode to the fourth electrode wherein right sides of the first electrode and the third electrode extend further to the right than right sides of the second electrode and the fourth electrode, and The left sides of the second electrode and the fourth electrode extend further to the left than the left sides of the first electrode and the third electrode. 3 . The integrated circuit structure of claim 2 , wherein the first dielectric layer is a capping layer comprising at least one material selected from the group consisting of AlN, SiN, and SiCN.

4. The integrated circuit structure of claim 2 , wherein the third electrode has a stepped surface profile corresponding to a surface profile of the underlying second dielectric layer, and the fourth electrode has a stepped surface profile corresponding to a surface profile of the underlying third dielectric layer.

5. The integrated circuit structure of claim 2 , wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer each comprise: At least one material selected from the group consisting of HfO 2 , Al 2 O 3 , ZrO 2 and lanthanum oxide La 2 O 3 .

6. The integrated circuit structure according to claim 2, wherein the first metal interconnection vertically extends through the third dielectric layer, the third electrode, the second dielectric layer, and the first dielectric layer to contact the first electrode, and The second metal interconnection vertically extends through the fourth electrode, the third dielectric layer and the second dielectric layer to contact the second electrode.

7. The integrated circuit structure according to claim 1, The MIM capacitor comprises: the first electrode; a first dielectric layer formed on the first electrode; a second electrode formed on the first dielectric layer; an interlayer dielectric layer formed on the second electrode; a third electrode formed on the interlayer dielectric layer; a second dielectric layer formed on the third electrode; a fourth electrode formed on the second dielectric layer; a third dielectric layer formed on the fourth electrode; a fifth electrode formed on the third dielectric layer; a first metal interconnection electrically connecting the first electrode, the third electrode, and the fifth electrode; as well as A second metal interconnection electrically connects the second electrode and the fourth electrode. 8 . The integrated circuit structure according to claim 7 , further comprising a fourth dielectric layer formed between the second electrode and the interlayer dielectric layer.

9. The integrated circuit structure according to claim 7, wherein the left sides of the first electrode, the third electrode, and the fifth electrode extend further to the left than the left sides of the second electrode and the fourth electrode, and The right sides of the second electrode and the fourth electrode extend further to the right than the right sides of the third electrode and the fifth electrode.

10. The integrated circuit structure of claim 7, wherein the first dielectric layer is a capping layer comprising at least one material selected from the group consisting of AlN, SiN, and SiCN.

11. The integrated circuit structure of claim 7, wherein the fourth electrode has a stepped surface profile corresponding to a surface profile of the second dielectric layer, and the fifth electrode has a stepped surface profile corresponding to a surface profile of the third dielectric layer.

12. The integrated circuit structure according to claim 7, wherein the first dielectric layer, the second dielectric layer, the interlayer dielectric layer, and the third dielectric layer each comprise: At least one material selected from the group consisting of HfO 2 , Al 2 O 3 , ZrO 2 and lanthanum oxide La 2 O 3 .

13. The integrated circuit structure according to claim 7, wherein the first metal interconnection vertically extends through the fifth electrode, the third dielectric layer, the second dielectric layer, the third electrode, the interlayer dielectric layer, and the first dielectric layer to contact the first electrode, and The second metal interconnection vertically extends through the third dielectric layer, the fourth electrode, the third dielectric layer, and the interlayer dielectric layer to contact the second electrode.

14. A method of manufacturing an integrated circuit structure, the method comprising: forming a lower back-end-of-the-line (BEOL) wiring layer including lower metal lines and an upper BEOL wiring layer including upper metal lines, the lower metal lines being connected to the upper metal lines via interconnects, the lower metal lines and the upper metal lines extending in a first direction in a plan view, and the lower metal lines defining a filled-shape region between the lower metal lines in the plan view, the filled-shape region not including elements of the lower BEOL wiring layer; as well as forming a metal-insulator-metal (MIM) capacitor in the fill-shaped region, the fill-shaped region extending at least partially from the lower BEOL wiring layer to the upper BEOL wiring layer along the thickness direction of the integrated circuit structure and not overlapping the lower metal line in the plan view, The first electrode of the MIM capacitor is formed in the same layer as the lower metal line in the thickness direction, and all remaining portions of the MIM capacitor are formed between the lower metal line and the upper metal line in the thickness direction.

15. The method of claim 14, further comprising forming the MIM capacitor by: forming a first electrode; forming a first dielectric layer on the first electrode; forming a second electrode on the first dielectric layer; forming a second dielectric layer on the second electrode; forming a third electrode on the second dielectric layer; forming a third dielectric layer on the third electrode; forming a fourth electrode on the third dielectric layer; forming a first metal interconnection to electrically connect the first electrode to the third electrode; as well as forming a second metal interconnection to electrically connect the second electrode to the fourth electrode, wherein right sides of the first electrode and the third electrode extend further to the right than right sides of the second electrode and the fourth electrode, and The left sides of the second electrode and the fourth electrode extend further to the left than the left sides of the first electrode and the third electrode.

16. The method of claim 15, wherein the third electrode has a stepped surface profile corresponding to a surface profile of the underlying second dielectric layer, and the fourth electrode has a stepped surface profile corresponding to a surface profile of the underlying third dielectric layer.

17. The method according to claim 15, wherein the first metal interconnect is formed to vertically extend through the third dielectric layer, the third electrode, the second dielectric layer, and the first dielectric layer to contact the first electrode, and The second metal interconnection is formed to vertically extend through the fourth electrode, the third dielectric layer, and the second dielectric layer to contact the second electrode.

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