Memory array and method for forming a memory array including strings of memory cells

Abstract

This application relates to memory arrays and methods for forming memory arrays including strings of memory cells. A memory array includes laterally spaced-apart memory blocks that respectively include vertical stacks including alternating insulative levels and conductive levels. Strings of channel material of memory cells extend through the insulative levels and the conductive levels. Intervening material is laterally between and longitudinally along laterally-adjacent ones of the memory blocks. The intervening material in a lowermost portion of the conductive levels includes intervening portion material. Bridges laterally extend between the laterally-adjacent memory blocks. The bridges include bridging material having a different composition than the intervening portion material. The bridges are longitudinally spaced apart along the laterally-adjacent memory blocks by the intervening portion material and laterally extend into the laterally-adjacent memory blocks. Other embodiments including methods are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to memory arrays and methods for forming memory arrays comprising strings of memory cells. Background Technology

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines electrically interconnect memory cells along columns of the array, and access lines electrically interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is typically specified as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of milliseconds or less. In any case, memory cells are configured to retain or store memory in at least two different optional states. In binary systems, states are considered to be "0" or "1". In other systems, at least some individual memory cells can be configured to store information in more than two levels or states.

[0004] A field-effect transistor (FET) is a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is greatly prevented. FETs may also include additional structures, such as a reversible programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory widely used in modern computers and devices. For example, modern personal computers store the BIOS on flash memory chips. As another example, it is increasingly common for computers and other devices to use flash memory, in the form of solid-state drives, instead of traditional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and allows manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND can be a basic architecture for integrated flash memory. A NAND cell device includes at least one selection device series-coupled with a series combination of memory cells (and said series combination is generally referred to as a NAND string). NAND architectures can be configured in a three-dimensional arrangement, comprising vertically stacked memory cells, each vertically stacked memory cell individually including a reversibly programmable vertical transistor. Control components or other circuitry may be formed beneath the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells individually including transistors.

[0007] Memory arrays can be arranged in memory pages, memory blocks, and portions of blocks (e.g., sub-blocks) and memory planes, as shown and described, for example, in any of U.S. Patent Application Publications Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. A memory block can at least partially define the longitudinal profile of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines can occur in so-called “step structures” at the ends or edges of the array of vertically stacked memory cells. A step structure includes individual “steps” (alternatively referred to as “steps” or “staircases”) defining contact areas for individual word lines, with vertically extending conductive vias contacting said contact areas to provide electrical access to the word lines. Summary of the Invention

[0008] In some embodiments, a method for forming a memory array comprising strings of memory cells includes forming a conductor layer comprising a conductor material on a substrate. A lower portion of a stack comprising vertically alternating first and second layers is formed above the conductor layer. The stack comprises laterally spaced memory block regions. The material of the first layer has a different composition than the material of the second layer. The lowermost portion of the first layer comprises a sacrificial material. Bridging portions extend laterally between laterally adjacent memory block regions. The bridging portions comprise a bridging material with a different composition than the sacrificial material. The bridging portions are longitudinally spaced along the laterally adjacent memory block regions by the sacrificial material and extend laterally into the laterally adjacent memory block regions. The vertically alternating first and second layers of the upper portion of the stack are formed above the lower portion. A channel material string is formed, passing through the first and second layers in the upper portion and extending to the lowermost first layer in the lower portion. Horizontally extending trenches are formed into the stack, the trenches being located between laterally adjacent memory block regions and extending to the sacrificial material and the bridging portion in the bottommost first layer. The sacrificial material is selectively and isotropically etched relative to the bridging material from the bottommost first layer through the trenches. Following the etching, a conductive material is formed around the bridging portion in the bottommost first layer. This conductive material directly electrically couples the channel material of the individual channel material strings to the conductive material of the conductor layer.

[0009] In some embodiments, a memory array includes laterally spaced memory blocks, each comprising a vertical stack, the vertical stack including alternating insulating and conductive layers. Channel material strings of memory cells extend through the insulating and conductive layers. Intermediate material is laterally positioned between laterally adjacent memory blocks and longitudinally extends along the laterally adjacent memory blocks. The intermediate material in the lowermost portion of the conductive layer includes intermediary portion material. Bridging portions extend laterally between the laterally adjacent memory blocks. The bridging portions include a bridging material with a different composition from the intermediary portion material. The bridging portions are longitudinally spaced along the laterally adjacent memory blocks by the intermediary portion material and extend laterally into the laterally adjacent memory blocks.

[0010] In some embodiments, a memory array includes a conductor layer comprising a conductive material. Laterally spaced memory blocks each comprise a vertical stack, the vertical stack comprising alternating insulating and conductive layers directly above the conductor layer. Channel material strings of memory cells extend through the insulating and conductive layers. The conductive material at the bottom of the conductive layer directly electrically couples the channel material of the individual channel material strings to the conductive material of the conductor layer. Intermediate materials are laterally located between laterally adjacent memory blocks and longitudinally extend along the laterally adjacent memory blocks. The intermediate material in the bottom conductive layer comprises an intermediary portion material. Bridging portions extend laterally between the laterally adjacent memory blocks. The bridging portions comprise a bridging material with a different composition from the intermediary portion material. The bridging portions are longitudinally spaced along the laterally adjacent memory blocks by the intermediary portion material and extend laterally into the laterally adjacent memory blocks. Attached Figure Description

[0011] Figure 1 This is a schematic cross-sectional view of a portion of the substrate during processing according to an embodiment of the present invention, which is through... Figure 2 and 3 The line 1-1 in the middle is cut off.

[0012] Figure 2 Is it through Figure 1 A schematic diagram of the cross-section taken from line 2-2 in the diagram.

[0013] Figure 3 Is it through Figure 1 A schematic diagram of the cross-section taken from line 3-3 in the diagram.

[0014] Figure 4-24 This is a process according to some embodiments of the present invention. Figure 1-3 Schematic continuous cross-sectional views, unfolded views, enlarged views and / or partial views of the structure or its parts or alternative embodiments. Detailed Implementation

[0015] Embodiments of the present invention cover methods for forming memory arrays comprising strings of memory cells, such as NAND arrays or arrays of other memory cells that may have at least one array-level peripheral control circuitry system (e.g., array-level CMOS). Embodiments of the present invention cover so-called "back-gate" or "replacement gate" processes, so-called "front-gate" processes, and other processes, whether existing or future developments, that are independent of the formation timing of transistor gates. Embodiments of the present invention also cover existing or future integrated circuit systems comprising memory arrays, including strings of memory cells independent of the manufacturing process, such as NAND architectures. Reference Figure 1-24The first example method embodiment is described, which can be considered as a "post-gate" or "replacement gate," and from... Figure 1-3 start.

[0016] Figure 1-3 The diagram illustrates a configuration 10 having an array or array region 12 in which vertically extending strings of transistors and / or memory cells will be formed. Configuration 10 includes a substrate 11 having any one or more of the following materials: conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, or insulating / insulator / insulator (i.e., electrically) materials. The various materials are vertically formed above the substrate 11. The materials may be... Figure 1-3 The material depicted is adjacent to, vertically inward, or vertically outward. For example, components for other parts or all of the integrated circuit system may be provided somewhere above, around, or inside the base substrate 11. Control and / or other peripheral circuitry systems for operating components within an array (e.g., array 12) of vertically extending strings of memory cells may also be fabricated, and these systems may or may not be entirely or partially within the array or subarrays. Furthermore, multiple subarrays may be fabricated and operated relatively independently of each other, sequentially, or otherwise. In this document, "subarray" may also be considered as an array.

[0017] In some embodiments, and as shown, a conductor layer 16 comprising conductor material 17 has been formed over substrate 11. As an example, conductor material 17 comprises an upper conductor material 43 (e.g., n-type or p-type conductive doped polysilicon) with a lower conductor material 44 (e.g., WSi) having a different composition from the upper conductor material 43. x Directly above (e.g., directly against). Conductor layer 16 may include portions of a control circuitry (e.g., peripheral array under-circuit system and / or common source line or board) for controlling read and write access to transistors and / or memory cells to be formed within array 12.

[0018] The lower portion 18L of the stack 18* is formed over the substrate 11 and the conductor layer 16 (* is used as a suffix to include all such components that may or may not have other suffixes and are specified with the same numerical value). The stack 18* will include vertically alternating conductive layers 22* and insulating layers 20*, wherein the material of layer 22* has a different composition than the material of layer 20*. The stack 18* includes laterally spaced memory block regions 58, which will include laterally spaced memory blocks 58 in the finished circuit system construction. In this document, "block" generally includes "sub-block". The memory block regions 58 and the resulting memory blocks 58 (not shown) can be considered as longitudinally extended and oriented, for example, along direction 55. The memory block regions 58 may be indistinguishable at this processing point.

[0019] The conductive layer 22* (alternatively referred to as the first layer) may not include conductive material, and the insulating layer 20* (alternatively referred to as the second layer) may not include insulating material or may be insulating when combined with the “back gate” or “alternate gate” example method embodiments described herein. In one embodiment, the lower portion 18L includes the lowermost portion 20z of the second layer 20* located directly above (e.g., directly abutting) the conductive material 17. The lowermost second layer 20z is insulating (e.g., comprises a material 24 having silicon dioxide) and may be sacrificial.

[0020] The lowest part 22z of the first layer 22* is directly above (e.g., directly abutting) the lowest second layer 20z. The lowest first layer 22z includes a sacrificial material 77 and a bridging portion 62 extending laterally between laterally adjacent memory block regions 58. The bridging portion 62 includes a bridging material 81 with a composition different from that of the sacrificial material 77. The bridging portion 62 is longitudinally spaced along the laterally adjacent memory block regions 58 by the sacrificial material 77 and extends laterally into the laterally adjacent memory block regions 58. The sacrificial material 77 may include any suitable insulating, conductive, and / or semiconductive material. Similarly, the bridging material 81 may include any suitable insulating, conductive, and / or semiconductive material (regardless of such electrical properties of the sacrificial material 77). By way of example only, the example insulating material 81 includes alumina, silicon dioxide, silicon oxynitride, and silicon nitride. The example conductive material 81 includes elemental metals, elemental metal alloys, conductive doped semiconductive materials (e.g., polycrystalline silicon), and metal compounds (e.g., metal nitrides, metal silicides, etc.). In several preferred embodiments, the sacrificial material 77 comprises polycrystalline silicon or silicon nitride, and the bridging material 81 comprises the same polycrystalline silicon or silicon nitride but has been doped with one or more of the following: C, N, B, Ga, As, Sb, Bi, Li, Al, In, Group 18 elements, or a metallic material (e.g., at a concentration sufficient to achieve selective isotropic etching of the sacrificial material 77 relative to the bridging material 81; e.g., at least 1 × 10⁻⁶). 12 One atom per cubic centimeter, but even a little less would be sufficient.

[0021] In one embodiment, the bridging portion 62 extends laterally to each of its two laterally adjacent memory blocks 58 at equal lateral distances relative to each other (e.g., D1). However, and in one embodiment, the bridging portion 62 extends laterally to each of its two laterally adjacent memory blocks 58 at a distance less than the lateral distance between the two laterally adjacent memory blocks 58 (e.g., D2). In one embodiment, the nearest longitudinal ends 79 of the laterally adjacent bridging portions 62 are spaced apart from each other (e.g., along a common long axis of each such bridging portion). Example laterally adjacent bridging portions 62 are shown as longitudinally aligned relative to each other between different pairs of adjacent memory blocks 58. Alternatively, they may not be aligned in this way (e.g., periodically staggered longitudinally and not shown). In one embodiment, the bridging portion 62 is insulating; in another embodiment, it is conductive; and in yet another embodiment, it is semi-conductive.

[0022] The bridging portion 62 can be formed by any suitable process. As an example, a blanket of sacrificial material 77 is formed in the lowermost first layer 22z. Subsequently, regions of the blanket (e.g., using one or more of C, N, B, Ga, As, Sb, Bi, Li, Al, In, Group 18 elements, or metallic materials) are ion-implanted to form bridging material 81 and bridging portion 62 (e.g., using an ion-implantation mask over the blanket of sacrificial material 77). As another example, after forming the blanket of sacrificial material 77 in the lowermost first layer 22z, such a blanket is subtractively patterned (e.g., using photolithography and etching) to form void spaces therein (e.g., corresponding to the desired location of bridging portion 62). Thereafter, bridging material 81 is formed in such void spaces to form bridging portion 62 (e.g., by depositing bridging material 81 to overfill such void spaces and planarizing bridging material 81 back at least to the top surface of sacrificial material 77). In another example, a blanket of bridging material 81 is formed in the bottommost first layer 22z. The blanket is then subtractively patterned (e.g., using photolithography and etching) to form the bridging portion 62. Subsequently, a sacrificial material 77 is formed around the bridging portion 62 (e.g., by depositing sacrificial material 77 to fill the remaining volume of the first layer 22z, and then planarizing the sacrificial material 77 back at least to the top surface of the bridging portion 62).

[0023] In one embodiment, the next lowermost portion 20x of the second layer 20* is directly above the lowermost first layer 22z (e.g., comprising material 24). In one embodiment, a conductive material layer 21 comprising conductive material 47 (e.g., conductive doped polysilicon) is directly above the next lowermost second layer 20x. In any case, the ion implantation of the above-mentioned examples, when used, can occur before or after the formation of either layer 20x or 21. In one embodiment, and as shown, the bridging portion 62 is respectively vertically positioned between and directly abutting the insulating layers (e.g., material 24 of layers 20x and 20z).

[0024] refer to Figure 4-8 Vertically alternating first layers 22 and second layers 20 of the upper portion 18U of the stack 18* are formed above the lower portion 18L. The first layers 22 and second layers 20 each comprise different constituent materials 26 and 24 (e.g., silicon nitride and silicon dioxide). The upper portion 18U is shown in an example where the second layer 20 is above the lower portion 18L, but alternatively it may begin with the first layer 22 (not shown). Additionally, and by way of example, the lower portion 18L may be formed with one or more first and / or second layers on its top. In any case, only a small number of layers 20 and 22 are shown; more likely, the upper portion 18U (and consequently the stack 18*) includes tens, hundreds, or more layers 20 and 22. Furthermore, other circuitry, which may or may not be part of the peripheral and / or control circuitry system, may be located between the conductor layer 16 and the stack 18*. By way of example only, multiple vertically alternating layers of conductive and insulating materials in such circuit systems may be located below the lowest part of conductive layer 22* and / or above the highest part of conductive layer 22*. For example, one or more select gate layers (not shown) may be located between conductor layer 16 and the lowest conductive layer 22*, and one or more select gate layers may be located above the highest part of conductive layer 22*. Alternatively or additionally, at least one of the depicted uppermost and lowermost conductive layers 22* may be a select gate layer.

[0025] A channel opening 25 has been formed (e.g., by etching) through the second layer 20 and the first layer 22 in the upper portion 18U to reach the conductor layer 16 (e.g., at least to the lowermost first layer 22z). The channel opening 25 may gradually narrow radially inward (not shown) to extend deeper into the stack 18. In some embodiments, the channel opening 25 may enter the conductor material 17 of the conductor layer 16 as shown or may stop at the top (not shown). Alternatively, as an example, the channel opening 25 may stop at the top or within the lowermost second layer 20z. The reason for extending the channel opening 25 at least to the conductor material 17 of the conductor layer 16 is to provide an anchoring effect on the material within the channel opening 25.

[0026] Horizontally extending trenches 40 have been formed (e.g., by anisotropic etching) into the stack 18* and are located between laterally adjacent memory block regions 58. For the sake of simplicity and by way of example, channel openings 25 are shown arranged in groups or columns of staggered rows of four and five channel openings 25 per row. Trenches 40 are typically wider than channel openings 25 (e.g., 10 to 20 times wider, but such extent is not shown for simplicity). Any alternative existing or future-developed arrangements and configurations may be used. Trenches 40 and channel openings 25 may be formed in any order relative to each other.

[0027] The trench 40 has been formed in the lowermost first layer 22z to extend to the sacrificial material 77 and the bridging portion 62. As an example, the trench 40 may initially be formed by etching materials 24, 26, and 47 (possibly using different anisotropic etching chemicals) and terminate on or within the material 24 of the next lowermost second layer 20x (if present). A thin sacrificial liner 78 (e.g., hafnium oxide, alumina, etc.) may then be formed, followed by punch etching through this to expose the material 24, and subsequently punch etching through the material 24 to expose the sacrificial material 77. Alternatively, and only by way of example, sacrificial etch termination lines (not shown) having the same generally horizontal profile as the trench 40 may be formed in the conductive layer 21 (if present) to be directly above and in contact with the material 24 of the next lowermost second layer 20x (or to reach and / or into the bridging portion 62) before the formation of the upper portion 18U. The trench 40 can then be formed by the following steps: etching materials 24 and 26 to stop on or within the material of the individual sacrificial lines, then excavating the remaining material of such lines, and then forming a thin sacrificial liner 78.

[0028] Transistor channel material can be formed vertically along the insulating and conductive layers in individual channel openings, thus including individual channel material strings directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of an example memory array in formation may include a gate region (e.g., a control gate region) and a memory structure laterally located between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge-blocking region, a storage material (e.g., a charge storage material), and an insulating charge-transfer material. The storage material of the individual memory cell (e.g., a floating gate material, such as doped or undoped silicon, or a charge-trapping material, such as silicon nitride, metal dots, etc.) is formed vertically along the individual charge-blocking region. The insulating charge-transfer material (e.g., a bandgap-engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulating oxides (e.g., silicon dioxide) is laterally located between the channel material and the storage material.

[0029] Figure 4-8One embodiment is shown in which charge blocking material 30, storage material 32, and charge transport material 34 are formed vertically along insulating layer 20 and conductive layer 22 in individual channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed, for example, by depositing corresponding thin layers of the transistor materials above stack 18* and within individual openings 25 and subsequently planarizing such transistor materials back at least to the top surface of stack 18*.

[0030] The channel material 36, serving as the channel material string 53, is also vertically formed in the channel opening 25 along the insulating layer 20 and the conductive layer 22. Therefore, the channel material string 53 extends through the first layer 20* and the second layer 22* in the upper portion 18U and extends to the sacrificial material 77 in the lowermost first layer 22z. Due to proportions, materials 30, 32, 34, and 36 in… Figure 4-6 The material 37 is shown and designated only in the diagram. Example channel material 36 comprises a suitably doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called Group III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). The thickness of each of materials 30, 32, 34, and 36 is typically 25 to 100 angstroms. Punch etching may be performed to remove materials 30, 32, and 34 from the substrate of the channel opening 25 to expose the conductor layer 16, such that the channel material 36 directly abuts the conductor material 17 of the conductor layer 16. Such punch etching may occur individually with respect to each of materials 30, 32, and 34 (as shown), or may occur only with respect to some of them (not shown). Alternatively, and by way of example only, punch etching may not be performed, and the channel material 36 may be directly electrically coupled to the conductor material 17 of the conductor layer 16 (also not shown) only via separate conductive interconnects. Regardless, a sacrificial etch-stop plug (not shown) may be formed horizontally in the lower portion 18L, wherein the channel opening 25 will precede the formation of the upper portion 18U and be used in a manner similar to the sacrificial etch-stop line described above when forming the channel opening 25. A radially centered solid dielectric material 38 (e.g., spin-coated dielectric, silicon dioxide, and / or silicon nitride) is shown in the channel opening 25. Alternatively, and by way of example only, the radially centered portion within the channel opening 25 may contain void spaces (not shown) and / or lack solid material (not shown).

[0031] refer to Figure 9-11The sacrificial material 77 (not shown) has been isotropically etched from the lowest first layer 22z through trench 40 (e.g., using liquid or gaseous H3PO4 as the primary etchant, where material 77 is silicon nitride, or using tetramethylammonium hydroxide [TMAH], where material 77 is polycrystalline silicon). This isotropic etching is selectively performed relative to the bridging material 81 of the bridging portion 62, and in one such embodiment, the selectivity relative to it is at least 5:1 (as would occur with H3PO4 or TMAH versus all the aforementioned examples of bridging material 81).

[0032] In the lowest first layer, a conductive material is formed that directly electrically couples the channel material of individual channel materials to the conductive material of the conductor layer. In one embodiment, such conductive material is formed directly against the bottom of the conductive material of the conductive layer and directly against the top of the conductive material of the conductor layer. For example, and first referring to... Figure 12 and 13 The illustration shows a subsequent processing step where, in one embodiment, material 30 (e.g., silicon dioxide), material 32 (e.g., silicon nitride), and material 34 (e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) have been etched in layer 20z to expose the sidewalls 41 of the channel material 36 of the channel material string 53 in the lowermost first layer 22z. Any of materials 30, 32, and 34 in layer 22z can be considered as a sacrificial material. As an example, consider an embodiment where the liner 78 is one or more insulating oxides (other than silicon dioxide), and the memory cell materials 30, 32, and 34 are one or more of silicon dioxide and silicon nitride layers, respectively. In this example, the depicted structure can be produced by selectively etching silicon dioxide and silicon nitride sequentially relative to another chemical substance using modified or different chemical substances. As an example, a 100:1 (by volume) water to HF solution will selectively etch silicon dioxide relative to silicon nitride, while a 1000:1 (by volume) water to HF solution will selectively etch silicon nitride relative to silicon dioxide. Therefore, and in such examples, these etching chemicals can be used alternately, where the desired effect is achieved by… Figure 12 and 13 The example structure shown. Those skilled in the art can select other chemicals for etching other different materials, where it is necessary to... Figure 12 and 13 The structure shown. Insulating material from layers 20x and 20z (e.g., 24, and in...) Figure 12 and 13 Some or all of the material (not shown in the image) may be removed when other materials are removed, may be removed individually, or may be retained in whole or in part.

[0033] refer to Figure 14-16Conductive material 42 (e.g., conductive doped polysilicon) has been formed around the bridging portion 62 in the lowermost first layer 22z, thereby directly electrically coupling the channel material 36 of the individual channel material strings 53 to the conductor material 17 of the conductor layer 16. In one embodiment, and as shown, such material has been formed directly against the bottom of the conductive material 47 of the conductive layer 21 and directly against the top of the conductor material 43 of the conductor layer 16, thereby directly electrically coupling the channel material 36 of the individual channel material strings 53 to the conductor material 43 of the conductor layer 16 and the conductive material 47 of the conductive layer 21.

[0034] refer to Figure 17 and 18 Furthermore, by way of example, the conductive material 42 has been removed from the trench 40 by anisotropic etching. The sacrificial liner 78 (not shown) has also been removed. The sacrificial liner 78 may be removed before the conductive material 42 (not shown) is formed.

[0035] refer to Figure 19-24 For example, material 26 (not shown) of the conductive layer 22* is removed by isotropically etching it through trench 40 with an ideal selectivity relative to other exposed materials (e.g., using liquid or gaseous H3PO4 as the primary etchant, where material 26 is silicon nitride and other materials include one or more oxides or polysilicon). In an exemplary embodiment, material 26 (not shown) in the conductive layer 22* is sacrificial and has been replaced with conductive material 48 and subsequently removed from trench 40, thus forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56.

[0036] A thin insulating liner (e.g., Al2O3, not shown) may be formed prior to the formation of the conductive material 48. The approximate orientation of the transistor and / or memory cell 56 is... Figure 23 Parentheses are used to indicate this, while some are in Figure 19 , 21 In 22 and 24, the transistors and / or memory cells 56 are indicated by dashed outlines, where they are substantially annular or ring-shaped in the depicted examples. Alternatively, the transistors and / or memory cells 56 may not completely surround the individual channel openings 25, such that each channel opening 25 may have two or more vertically extending strings 49 (e.g., in an individual conductive layer, multiple transistors and / or memory cells surround an individual channel opening, where there may be multiple word lines per channel opening in the individual conductive layer, and these are not shown). The conductive material 48 can be considered as having ends 50 corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56. Figure 23In the depicted embodiment, the control gate region 52 includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 can be viewed as a memory structure 65 laterally located between the control gate region 52 and the channel material 36. In one embodiment, and as shown relative to the example “back gate” processing, the conductive material 48 of the conductive layer 22* is formed after the channel opening 25 and / or trench 40 is formed. Alternatively, for example, relative to the “front gate” processing, the conductive material of the conductive layer may be formed before the channel opening 25 and / or trench 40 (not shown).

[0037] A charge blocking region (e.g., charge blocking material 30) is located between the storage material 32 and each control gate region 52. The charge blocking member in the memory cell may function to prevent charge carriers from flowing out of the storage material (e.g., floating gate material, charge trapping material, etc.) to the control gate in programming mode, and to prevent charge carriers from flowing from the control gate into the charge storage material in erase mode. Therefore, the charge blocking member can be used to block charge migration between the control gate region and the storage material of an individual memory cell. As illustrated, the charge blocking region includes an insulating material 30. By other examples, the charge blocking region may include a lateral (e.g., radial) outer portion of the storage material (e.g., material 32), wherein this storage material is insulating (e.g., in the absence of any different compositional material between the insulating storage material 32 and the conductive material 48). In any case, as an additional example, the interface between the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region in the absence of any single-component insulating material 30. Furthermore, the interface between the conductive material 48 and the insulating material 30 (if present) can together serve as a charge-blocking region, and alternatively or additionally serve as a lateral outer region of an insulating storage material (e.g., silicon nitride material 32). Example materials 30 are one or more of hafnium oxide and silicon dioxide.

[0038] In one embodiment, as shown, the lowermost surface of the channel material 36 of the channel material string 53 never directly abuts against any of the conductor materials 17 of the conductor layer 16. In one embodiment, as shown, the conductive material 42 directly abuts against the sidewall 41 of the channel material string 53.

[0039] Intermediate material 57 is formed in trench 40, and thus lies laterally between laterally adjacent memory blocks 58, and longitudinally along the memory blocks. Intermediate material 57 provides lateral electrical isolation (insulation) between laterally adjacent memory blocks. Such material may comprise one or more of insulating, semiconductive, and conductive materials, and in any case, helps prevent short circuits between conductive layers 22 in the finished circuit system construction. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. In this document, "undoped polysilicon" refers to impurities with increasing conductivity ranging from 0 atoms / cm³ to 1 × 10⁻⁶. 12 Polycrystalline silicon with atoms per cubic centimeter. "Doped polycrystalline silicon" refers to polycrystalline silicon with impurities exceeding 1 × 10⁻⁶ atoms per cubic centimeter. 12 Polycrystalline silicon with atoms per cubic centimeter, and "conductively doped polycrystalline silicon" is polycrystalline silicon with at least 1 × 10⁻⁶ atoms in impurities that increase conductivity. 18 Polycrystalline silicon with atoms per cubic centimeter. Intermediate material 57 may contain through-hole arrays (not shown).

[0040] Any other attributes or aspects shown and / or described herein with reference to other embodiments may be used in the embodiments shown and described above.

[0041] Alternative embodiments may be constructed from the method embodiments described above or otherwise. In any case, embodiments of the invention cover memory arrays independent of the manufacturing method. Nevertheless, such memory arrays may have any of the properties described herein in the method embodiments. Similarly, the method embodiments described above may incorporate having, forming, and / or having any of the properties described relative to the device embodiments.

[0042] In one embodiment, an integrated circuit system comprising a memory array (e.g., 12) having strings (e.g., 49) of memory cells (e.g., 56) includes laterally spaced memory blocks (e.g., 58), each memory block individually comprising a vertical stack (e.g., 18*) comprising alternating insulating layers (e.g., 20*) and conductive layers (e.g., 22*). Strings (e.g., 49) of memory cells (e.g., 56) including channels (e.g., 53) extend through the insulating and conductive layers. Intermediate materials (e.g., 57 and 81) are laterally positioned between laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks. The intermediate material in the lowermost portion (e.g., 22z) of the conductive layer includes intermediary portion material (e.g., the portion of 57 located between bridging portions 62 along direction 55) and bridging portions (e.g., 62) extending laterally between laterally adjacent memory blocks. The bridging portions include bridging materials (e.g., 81) with a different composition from the intermediary portion material. The bridging portion is longitudinally spaced along the laterally adjacent memory blocks by intervening material and extends laterally into the laterally adjacent memory blocks. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0043] In one embodiment, an integrated circuit system comprising a memory array (e.g., 12) having strings (e.g., 49) of memory cells (e.g., 56) includes a conductor layer (e.g., 16) having a conductor material (e.g., 17). The memory array includes laterally spaced memory blocks (e.g., 58), each memory block comprising a vertical stack (e.g., 18*), the vertical stack comprising alternating insulating layers (e.g., 20*) and conductive layers (e.g., 22*). Strings (e.g., 49) of memory cells (e.g., 56) including strings of channel material (e.g., 53) extend through the insulating and conductive layers. The conductive material (e.g., 42) of the lowest portion (e.g., 22z) of the conductive layer directly electrically couples the channel material (e.g., 36) of the individual string of channel material to the conductor material of the conductor layer. Intermediate materials (e.g., 57 and 81) are laterally positioned between laterally adjacent memory blocks within the memory blocks and longitudinally along the laterally adjacent memory blocks. The intervening material in the lowest conductive layer includes intervening portion material (e.g., the portion at 57 between bridging portions 62 along direction 55) and bridging portions (e.g., 62) extending laterally between laterally adjacent memory blocks. The bridging portions include bridging materials (e.g., 81) with a different composition than the intervening portion material. The bridging portions are longitudinally spaced apart by the intervening portion material along laterally adjacent memory blocks and extend laterally into the laterally adjacent memory blocks. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0044] The above-described processing or construction can be viewed as an array of components formed as a single stack or group of such components, or within a single stack or group, which is above or part of an underlying substrate (but a single stack / group may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array can also be formed as part of the final construction, and in some embodiments may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / groups may be provided or fabricated above and / or below the stacks / groups shown in the diagram or described above. Furthermore, the arrays of components in different stacks / groups may be the same or different from each other, and the different stacks / groups may have the same or different thicknesses relative to each other. Intermediate structures (e.g., additional circuitry and / or dielectric layers) may be provided between vertically adjacent stacks / groups. And, the different stacks / groups may be electrically coupled relative to each other. Multiple stacks / groups can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / groups can be manufactured substantially simultaneously.

[0045] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can contain multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0046] In this document, unless otherwise indicated, “vertical,” “higher,” “upper,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” refers to a generally relative direction (i.e., within 10 degrees) along the surface of the main substrate, where the substrate is processed during manufacturing, and which is generally orthogonal to vertical. “Just horizontal” is a generally relative direction (i.e., not at an angle) along the surface of the main substrate. Furthermore, “vertical” and “horizontal” as used herein are generally perpendicular to each other and independent of the orientation of the substrate in three-dimensional space. Additionally, “vertically extending” and “vertically extending” refer to a direction deviating at least 45° from just horizontal. Furthermore, “vertically extending,” “vertically extending,” “horizontally extending,” “horizontally extending,” etc., relative to a field-effect transistor, refer to the orientation of the transistor’s channel length along which current flows between the source / drain regions during operation. For bipolar junction transistors, terms such as "vertically extending," "vertically extending," "horizontally extending," and "horizontally extending" refer to the orientation of the substrate length along which current flows between the emitter and collector during operation. In some embodiments, any vertically extending component, feature, and / or region extends vertically or within a vertical 10°.

[0047] Furthermore, "directly above," "directly below," and "directly below" require that the two stated areas / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. Moreover, using "above" without the preceding "direct" only requires that a portion of the stated area / material / component above the other stated area / material / component extends vertically outward from the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, using "below" and "under" without the preceding "direct" only requires that a portion of the stated area / material / component below / under the other stated area / material / component extends vertically inward from the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0048] Any of the materials, regions, and structures described herein may be homogeneous or non-homogeneous, and in any event may be continuous or discontinuous over any material covering them. When one or more example compositions are provided for any material, the material may comprise, consist primarily of, or consist of such one or more compositions. Furthermore, unless otherwise stated, any suitable existing or future-developed techniques may be used to form each material, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0049] Additionally, the term “thickness” (without a directional adjective) used alone is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions with different compositions, passing through a given material or region. Furthermore, the various materials or regions described herein may have substantially constant thickness or variable thickness. If variable thickness is present, then unless otherwise indicated, the thickness refers to the average thickness, and the material or region will have a minimum thickness and a maximum thickness due to the variable thickness. As used herein, “different compositions” only requires that the portions of two stated materials or regions that can directly contact each other are chemically and / or physically different, for example, in cases where such materials or regions are not homogeneous. If two stated materials or regions are not directly contacting each other, then in cases where such materials or regions are not homogeneous, “different compositions” only requires that the portions of two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when a stated material, region, or structure is in at least some physical contact with each other, one material, region, or structure “directly contacts” another material, region, or structure. In contrast, the words "over," "on," "near," "along," and "against" without the preceding "positive" encompass "direct contact" and constructions in which the intervening material, area, or structure causes the stated material, area, or structure to have no physical contact with each other.

[0050] In this context, if, during normal operation, current can flow continuously from one zone-material-component to another, and this flow is primarily accomplished by the movement of said subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated, then the zone-material-components are “electrically coupled” relative to each other. Another electronic component may be electrically coupled between and to the zone-material-components. In contrast, when zone-material-components are referred to as “directly electrically coupled,” there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled zone-material-components.

[0051] Any use of the terms "row" and "column" in this document is for the convenience of distinguishing one series or orientation of features from another series or orientation of features, and for components that have been or may be formed along said "row" and "column". "Row" and "column" are used synonymously with any series of areas, components, and / or features, regardless of function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns may be the same. Furthermore, rows and columns may intersect each other at 90° or at one or more other angles (i.e., other than straight angles).

[0052] The components of any of the conductive / conductor / conductive materials mentioned herein may be metallic materials and / or conductive-doped semiconducting / semiconductor / semiconductive materials. "Metallic material" means any elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds.

[0053] In this document, any use of "selective" in relation to etching, removal, deposition, formation, and / or shaping is an action in which a stated material is acted relative to another stated material at a volume ratio of at least 2:1. Additionally, any use of selective deposition, selective growth, or selective formation is the deposition, growth, or formation of one material relative to one or more stated materials at a volume ratio of at least 2:1, up to a minimum of 75 angstroms.

[0054] Unless otherwise indicated, the use of "or" in this document covers either one or both.

[0055] in conclusion

[0056] In some embodiments, a method for forming a memory array comprising strings of memory cells includes forming a conductor layer comprising a conductor material on a substrate. A lower portion of a stack comprising vertically alternating first and second layers is formed above the conductor layer. The stack includes laterally spaced memory block regions. The material of the first layer has a different composition than the material of the second layer. The lowermost portion of the first layer includes a sacrificial material. Bridging portions extend laterally between laterally adjacent memory block regions. The bridging portions include a bridging material with a different composition than the sacrificial material. The bridging portions are longitudinally spaced along the laterally adjacent memory block regions by the sacrificial material and extend laterally into the laterally adjacent memory block regions. The vertically alternating first and second layers of the upper portion of the stack are formed above the lower portion. A string of channel material is formed, passing through the first and second layers in the upper portion and extending to the lowermost first layer in the lower portion. Horizontally extending trenches are formed into the stack, the horizontally extending trenches being respectively between the laterally adjacent memory block regions and extending to the sacrificial material and the bridging portions in the lowermost first layer. The sacrificial material is selectively and isotropically etched relative to the bridging material through the trench from the bottom first layer. Following the etching, a conductive material is formed around the bridging portion in the bottom first layer. This conductive material directly electrically couples the channel material of individual channel material strings in the channel material strings to the conductive material of the conductor layer.

[0057] In some embodiments, a memory array includes laterally spaced memory blocks, each of which comprises a vertical stack including alternating insulating and conductive layers. Channel material strings of memory cells extend through the insulating and conductive layers. Intermediate materials are laterally positioned between laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks. The intermediate material at the bottom of the conductive layer includes an intermediary portion material. Bridging portions extend laterally between the laterally adjacent memory blocks. The bridging portions include a bridging material with a different composition from the intermediary portion material. The bridging portions are longitudinally spaced along the laterally adjacent memory blocks by the intermediary portion material and extend laterally into the laterally adjacent memory blocks.

[0058] In some embodiments, the memory array includes a conductor layer comprising a conductive material. Laterally spaced memory blocks are individually included in a vertical stack directly above the conductor layer, the vertical stack comprising alternating insulating and conductive layers. Channel material strings of memory cells extend through the insulating and conductive layers. The conductive material at the bottom of the conductive layer directly electrically couples the channel material of the individual channel material strings to the conductive material of the conductor layer. Intermediate materials are laterally located between laterally adjacent memory blocks and longitudinally extend along the laterally adjacent memory blocks. The intermediate material in the bottom conductive layer includes an intermediary portion material. Bridging portions extend laterally between the laterally adjacent memory blocks. The bridging portions include a bridging material with a different composition from the intermediary portion material. The bridging portions are longitudinally spaced along the laterally adjacent memory blocks by the intermediary portion material and extend laterally into the laterally adjacent memory blocks.

[0059] As per the regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writings and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. A method for forming a memory array comprising strings of memory cells, comprising: A conductor layer comprising a conductor material is formed on a substrate; A lower portion is formed above the conductor layer, comprising a stack of vertically alternating first and second layers, the stack including laterally spaced memory block regions, wherein the material of the first layer has a different composition than that of the second layer, and the lowermost portion of the first layer includes: Sacrificial materials; and A bridging portion extending laterally between laterally adjacent memory block regions, the bridging portion comprising a bridging material having a different composition from the sacrificial material, the bridging portions being longitudinally spaced apart by the sacrificial material and extending laterally into the laterally adjacent memory block regions, the bridging portions having opposing ends and opposing sides extending between the opposing ends, each opposing end terminating within one of the two laterally adjacent memory block regions, the sacrificial material completely surrounding each bridging portion and located laterally adjacent to the opposing ends and the opposing sides of each bridging portion; The stacked upper portion forms vertically alternating first and second layers above the lower portion, and forms a channel material string that extends through the first and second layers in the upper portion to the lowermost part of the first layer in the lower portion. Horizontally extending trenches are formed into the stack, the horizontally extending trenches being respectively between the laterally adjacent memory block regions and extending to the sacrificial material and the bridging portion in the bottom part of the first layer; The sacrificial material is selectively and isotropically etched relative to the bridging material from the lowest part of the first layer through the trench; and After the etching, a conductive material is formed around the bridging portion in the lowermost part of the first layer. The conductive material is located laterally beside the opposite ends and opposite sides of each of the bridging portions. The conductive material directly electrically couples the channel material of the individual channel material strings to the conductor material of the conductor layer.

2. The method of claim 1, further comprising forming in the lower portion the channel material string extending through the lowermost portion of the first layer.

3. The method of claim 1, wherein the sacrificial material and the bridging material comprise polysilicon, and the isotropic etching comprises using tetramethylammonium hydroxide.

4. The method of claim 1, wherein the bridging portion is formed by a process comprising the following steps: A blanket layer of the sacrificial material is formed in the lowest part of the first layer; and Ion implantation is performed on the area of ​​the blanket covering layer of the sacrificial material to form the bridging material and the bridging portion.

5. The method according to claim 4, wherein the ion implantation is targeted at one or more of C, N, B, Ga, As, Sb, Bi, Li, Al, In, Group 18 elements or metallic materials.

6. The method according to claim 4, wherein, The sacrificial material includes polycrystalline silicon or silicon nitride; The ion implantation is targeted at one or more of the following elements: C, N, B, Ga, As, Sb, Bi, Li, Al, In, Group 18 elements, or metallic materials; and The isotropic etching includes the use of tetramethylammonium hydroxide or phosphoric acid.

7. The method of claim 1, wherein the bridging portion is formed by a process comprising the following steps: A blanket layer of the sacrificial material is formed in the lowest part of the first layer; The sacrificial material blanket overlay is subtractively patterned to form void spaces therein; and The bridging material is formed in the void space.

8. The method of claim 1, wherein the bridging portion is formed by a process comprising the following steps: A blanket layer of the bridging material is formed in the lowest part of the first layer; The blanket covering of the bridging material is subtractively patterned to form the bridging portion; and The sacrificial material is formed around the bridging portion.

9. The method of claim 1, wherein the bridging portion extends laterally into its two laterally adjacent memory block regions, and the lateral distances into each of the laterally adjacent memory block regions are equal.

10. The method of claim 1, wherein the bridging portion extends laterally to each of its two laterally adjacent memory block regions by a lateral distance less than the lateral distance between the two laterally adjacent memory block regions.

11. The method of claim 10, wherein the bridging portion extends laterally into its two laterally adjacent memory block regions, and the lateral distances into each of the laterally adjacent memory block regions are equal.

12. The method of claim 1, wherein the nearest longitudinal ends of the laterally adjacent bridging portions are spaced apart from each other.

13. The method according to claim 1, wherein the bridging portion is insulated.

14. The method of claim 1, wherein the bridging portion is conductive.

15. The method of claim 1, wherein the bridging portion is semi-conductive.

16. The method of claim 1, wherein the bridging portions are vertically positioned between a pair of insulating layers and directly abut against the pair of insulating layers.

17. The method of claim 1, wherein the isotropic etching of the sacrificial material through the trench from the lowermost part of the first layer is selective relative to the bridging material at a ratio of at least 5:

1.

18. A memory array comprising: The memory block regions extend longitudinally along a first direction and are spaced apart from each other in a second direction orthogonal to the first direction. Each memory block region includes a vertical stack, the vertical stack including alternating insulating and conductive layers, and a channel material string of memory cells extends through the insulating and conductive layers. and Intermediate material, situated between the memory block regions adjacent in the second direction, the intermediate material extending longitudinally along the memory block regions adjacent in the second direction in the first direction, the intermediate material in the lowermost part of the conductive layer comprising: Intermediary materials; and A bridging portion extending in a second direction between memory block regions adjacent in a second direction, the bridging portion comprising a bridging material having a different composition from the intervening portion material, the bridging portion being spaced apart in a first direction by the intervening portion material and extending in the second direction into the memory block regions adjacent in the second direction, the bridging portion having an end in a relative second direction and a side in a relative first direction extending between the ends in the relative second direction, each end in the relative second direction terminating within one of the two memory block regions adjacent in the second direction.

19. The memory array of claim 18, wherein the bridging portions extend laterally to each other in two adjacent memory block regions in a second direction at equidistant lateral distances.

20. The memory array of claim 18, wherein the bridging portion extends laterally to each of its two second-direction adjacent memory block regions by a lateral distance less than the lateral distance between the two second-direction adjacent memory block regions.

21. The memory array of claim 20, wherein the bridging portion extends laterally into two adjacent memory block regions in a second direction, and the lateral distances into each adjacent memory block region in the second direction are equal.

22. The memory array of claim 18, wherein the nearest second-direction ends of the bridging portions adjacent in the second direction are spaced apart from each other.

23. The memory array of claim 18, wherein the intervening material is conductive.

24. The memory array of claim 18, wherein the intervening material is insulating.

25. The memory array of claim 18, wherein the intervening material is semi-conductive.

26. The memory array of claim 18, wherein the bridging portion is insulated.

27. The memory array of claim 18, wherein the bridging portion is conductive.

28. The memory array of claim 18, wherein the bridging portion is semi-conductive.

29. The memory array of claim 18, wherein the bridging material comprises non-conductive doped polysilicon.

30. The memory array of claim 18, wherein the bridging material comprises one or more of a metal material having C, N, B, Ga, As, Sb, Bi, Li, Al, In, Group 18 elements or metals thereof.

31. The memory array of claim 18, wherein the bridging portions are respectively vertically positioned between a pair of insulating layers and directly abut against the pair of insulating layers.

32. The memory array of claim 18, comprising NAND.

33. The memory array of claim 18, wherein all the channel material strings in the memory block regions adjacent to each other in the second direction are spaced apart at various points.

34. A memory array comprising: The conductor layer includes conductor materials; The memory block regions extend longitudinally along a first direction and are spaced apart from each other in a second direction orthogonal to the first direction. Each memory block region includes a vertical stack, which includes alternating insulating and conductive layers directly above the conductor layer. Channel material strings of memory cells extend through the insulating and conductive layers. The conductive material at the bottom of the conductive layer directly electrically couples the channel material of the individual channel material strings and the conductor material of the conductor layer together. and Intermediate material, situated between memory block regions adjacent in a second direction, the intermediate material extending longitudinally in the first direction along the memory block regions adjacent in the second direction, the intermediate material in the lowermost portion of the conductive layer comprising: Intermediary materials; and A bridging portion extending in a second direction between memory block regions adjacent in a second direction, the bridging portion comprising a bridging material having a different composition from the intervening portion material, the bridging portion being spaced apart in a first direction by the intervening portion material and extending in the second direction into the memory block regions adjacent in the second direction, the bridging portion having an end in a relative second direction and a side in a relative first direction extending between the ends in the relative second direction, each end in the relative second direction terminating within one of the two memory block regions adjacent in the second direction.

35. The memory array of claim 34, wherein the lowermost surface of the channel material of the channel material string does not directly abut against any of the conductor materials of the conductor layer.

36. The memory array of claim 34, comprising a string of channel material formed in the lower portion extending through the conductive layer at the lowermost portion.

37. The memory array of claim 34, wherein all the channel material strings in the memory block regions adjacent to each other in the second direction are spaced apart at various points.

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