Memory array and method for forming a memory array including strings of memory cells

Abstract

Embodiments of the present application relate to memory arrays and methods for forming memory arrays including strings of memory cells. A memory array includes a conductor level having an upper conductor material directly above and electrically coupled to a lower conductor material. The upper and lower conductor materials include different compositions relative to each other. Laterally spaced-apart memory blocks individually include a vertical stack including alternating insulative and conductive levels. Strings of channel material of memory cells extend through the insulative and conductive levels and through the upper conductor material into the lower conductor material. The channel material of the strings of channel material is directly electrically coupled to the upper and lower conductor materials of the conductor level. An intervening material is laterally between and longitudinally along laterally-adjacent memory blocks. Other embodiments including methods are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to memory arrays and methods for forming memory arrays comprising strings of memory cells. Background Technology

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines electrically interconnect memory cells along columns of the array, and access lines electrically interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is typically specified as memory with a retention period of at least approximately 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention period of milliseconds or less. In any case, memory cells are configured to retain or store memory in at least two different optional states. In binary systems, states are considered to be "0" or "1". In other systems, at least some individual memory cells can be configured to store information in more than two levels or states.

[0004] Field-effect transistors (FETs) are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region therebetween. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is greatly prevented. FETs may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory widely used in modern computers and devices. For example, modern personal computers store the BIOS on flash memory chips. As another example, it is increasingly common for computers and other devices to use flash memory, in the form of solid-state drives, instead of conventional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and allows manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND can be the basic architecture of an integrated flash memory. A NAND cell device includes at least one select device coupled in series with a series combination of memory cells (and the series combination is commonly referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement that includes vertically stacked memory cells that individually include a vertically transistor that is reversibly programmable. Control circuitry or other circuitry can be formed under the vertically stacked memory cells. Other volatile or non-volatile memory array architectures can also include vertically stacked memory cells that individually include a transistor.

[0007] Memory arrays can be arranged in memory pages, memory blocks, and partial blocks (e.g., sub-blocks), and memory planes, for example, as shown and described in any of U.S. Patent Application Publication Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. A memory block can at least partially define a longitudinal profile of individual word lines in individual word line levels of vertically stacked memory cells. Connections to these word lines can occur in so-called “staircase structures” at ends or edges of an array of vertically stacked memory cells. A staircase structure includes individual “steps” (alternatively referred to as “rungs” or “staircases”) that define contact regions of individual word lines, which are contacted by vertically extending conductive vias to provide electrical access to the word lines. SUMMARY

[0008] According to one embodiment of the present invention, a method is provided for forming a memory array including strings of memory cells. The method includes forming a conductor level including an upper conductor material directly over and electrically coupled with a lower conductor material, the upper and lower conductor materials including different compositions relative to each other; forming a stack including vertically alternating first and second levels over the conductor level, the stack including laterally spaced apart memory block regions, a material of the first levels having a different composition than a material of the second levels; forming strings of channel material extending through the first and second levels and through the upper conductor material to the lower conductor material; and forming intervening material laterally between and longitudinally along laterally adjacent ones of the memory block regions.

[0009] According to another embodiment of the present invention, there is provided a method for forming a memory array including strings of memory cells. The method includes forming a conductor level including an upper conductor material directly above and directly electrically coupled to a lower conductor material, the upper and lower conductor materials including different compositions relative to each other; forming a lower portion of a stack including vertically alternating first and second levels above the conductor level, the stack including laterally spaced apart memory block regions, a material of the first levels having a different composition than a material of the second levels, a lowermost of the first levels including a sacrificial material, a lowermost of the second levels being below the lowermost first level; forming the vertically alternating first and second levels of an upper portion of the stack above the lower portion and forming strings of channel material extending through the first levels and the second levels and through the upper conductor material into the lower conductor material; forming horizontally elongated trenches into the stack, the horizontally elongated trenches individually between laterally immediately adjacent ones of the memory block regions and extending to the lowermost first levels; isotropically etching the sacrificial material from the lowermost first levels through the trenches; removing a lowermost second level after the isotropic etching; forming conductive material in the lowermost first levels directly electrically coupling together the channel material of the individual strings of channel material and the conductor level after removing the lowermost second level; and forming intervening material laterally between laterally immediately adjacent ones of the memory block regions and longitudinally along laterally immediately adjacent ones of the memory block regions.

[0010] According to yet another embodiment of the present invention, there is provided a memory array. The memory array includes a conductor level including an upper conductor material directly above and directly electrically coupled to a lower conductor material, the upper and lower conductor materials including different compositions relative to each other; laterally spaced apart memory blocks each including a vertical stack, the vertical stack including alternating insulative and conductive levels, strings of channel material of memory cells extending through the insulative and conductive levels and through the upper conductor material into the lower conductor material, the channel material of the strings of channel material being directly electrically coupled to the upper and lower conductor materials of the conductor level; and intervening material laterally between laterally immediately adjacent ones of the memory blocks and longitudinally along laterally immediately adjacent ones of the memory blocks.

[0011] According to yet another embodiment of the present invention, a memory array is provided. The memory array comprises: a conductor level comprising an upper conductor material directly above and in direct electrical coupling with a lower conductor material, the upper and lower conductor materials comprising different compositions relative to each other; laterally spaced-apart memory blocks each comprising a vertical stack comprising alternating insulative levels and conductive levels, a channel material string of memory cells extending through the insulative levels and the conductive levels, the channel material of the channel material string being directly electrically coupled to the upper and lower conductor materials of the conductor level; dummy pillars extending through the insulative levels and the conductive levels and through the upper conductor material into the lower conductor material; and intervening material laterally between and longitudinally along laterally-adjacent ones of the memory blocks. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a cross-sectional schematic view of a portion of a substrate in processing according to embodiments of the present invention, taken across line 1-1 in Figure 2 .

[0013] Figure 2 is a cross-sectional schematic view taken across line 2-2 in Figure 1 .

[0014] Figures 3-23 is a schematic continuous cross-sectional view, exploded view, magnified view, and / or partial view of a construction of Figure 1 and 2 in processing according to some embodiments of the present invention, or portions or alternative embodiments thereof. DETAILED DESCRIPTION

[0015] Embodiments of the present invention encompass methods for forming a memory array comprising strings of memory cells, such as a NAND array or other array of memory cells that can have at least some array- below peripheral control circuitry (e.g., array- below CMOS). Embodiments of the present invention encompass so-called “gate-last” or “replacement gate” processing, so-called “gate-first” processing, and other processing that is independent of the timing of formation of transistor gates, whether existing or future-developed. Embodiments of the present invention also encompass integrated circuitry comprising a memory array comprising strings of memory cells independent of fabrication method, such as comprising a NAND architecture, whether existing or future-developed. Reference is made to Figures 1-22 and from Figure 1 and 2 A first example method embodiment is described starting with

[0016] Figure 1 and2 A construction 10 is shown having an array or array region 12 in which arrays of vertically extending strings of transistors and / or memory cells are to be formed. The construction 10 includes a base substrate 11 having any one or more of conductive / conductor / conductivity, semiconductive / semiconductor / semiconductivity, or insulative / insulator / insulativity (i.e., electrically, herein) material. Various materials are formed vertically above the base substrate 11. The materials can be provided to the side of, vertically inward of, or vertically outward of the materials depicted. For example, other portions or all of the fabrication of the integrated circuitry can be provided somewhere above, around, or internal to the base substrate 11. Control and / or other peripheral circuitry for operating components within the array of memory cell vertically extending strings (e.g., array 12) can also be fabricated, and can or can not be wholly or partially within the array or subarray. Further, multiple subarrays can also be fabricated and operated independently of one another, sequentially, or otherwise. A "subarray" can also be considered an array in this document. Figure 1 and 2 The depicted materials can be to the side of, vertically inward of, or vertically outward of. For example, other portions or all of the fabrication of the integrated circuitry can be provided somewhere above, around, or internal to the base substrate 11. Control and / or other peripheral circuitry for operating components within the array of memory cell vertically extending strings (e.g., array 12) can also be fabricated, and can or can not be wholly or partially within the array or subarray. Further, multiple subarrays can also be fabricated and operated independently of one another, sequentially, or otherwise. A "subarray" can also be considered an array in this document.

[0017] A conductor level 16 including a conductor material 17 has been formed above the substrate 11. The conductor material 17 includes an upper conductor material 43 directly above and in direct electrical coupling (e.g., directly against) a lower conductor material 44, which has a different composition than the upper conductor material 43. In one embodiment, the upper conductor material 43 includes a conductively doped semiconductive material (e.g., n-type doped or p-type doped polysilicon). In one embodiment, the lower conductor material 44 includes a metallic material (e.g., a metal silicide, such as WSi x ). The conductor level 16 can include portions of control circuitry (e.g., peripheral array- under circuitry and / or common source lines or plates) for controlling read and write access to the transistors and / or memory cells to be formed within the array 12.

[0018] In one embodiment, a lower portion 18L of a stack 18* has been formed above the substrate 11 and the conductor level 16 (* as a suffix for containing all such components that can or can not have other suffixes designated with the same numerical value). The stack 18* will include vertically alternating conductive levels 22* and insulative levels 20*, with the material of levels 22* having a different composition than the material of levels 20*. The stack 18* includes laterally spaced apart memory block regions 58, which will include laterally spaced apart memory blocks 58 in the finished circuitry construction. A "block" generally contains a "subblock" in this document. The memory block regions 58 and resulting memory blocks 58 (not yet shown) can be considered to be longitudinally elongated and oriented, for example, along direction 55. The memory block regions 58 can not be discernible at this point in processing.

[0019] The conductive tier 22* (alternatively referred to as a first tier) can not include a conductive material, and the insulative tier 20* (alternatively referred to as a second tier) can not include an insulative material or be insulative when incorporated in the “gate-last” or “replacement gate” example method embodiments initially described herein. In one embodiment, the lower portion 18L includes a lowermost tier 20z of the second tier 20* that is directly over (e.g., directly against) the conductor material 17. The lowermost second tier 20z is insulative (e.g., includes a material 24 having silicon dioxide) and can be sacrificial. A lowermost 22z of the first tier 22* is directly over (e.g., directly against) the lowermost second tier 20z. The lowermost first tier 22z includes a sacrificial material 77 (e.g., silicon nitride or polysilicon). In one embodiment, a next lowermost tier 20x of the second tier 20* is directly over the lowermost first tier 22z (e.g., includes a material 24). In one embodiment, a conductive tier 21 including a conductive material 47 (e.g., conductively doped polysilicon) is directly over the next lowermost second tier 20x.

[0020] In one embodiment, sacrificial pillars 60 have been formed in the conductor level 16 and in one such embodiment, in material above the conductor level 16. The sacrificial pillars 60 are horizontally positioned (i.e., in x, y coordinates) where individual strings of channel material are to be formed. In one embodiment, dummy pillars (not shown yet) are to be formed extending through the first level 20* and the second level 22* and through the upper conductor material 43 to the lower conductor material 44. In this document, a "dummy pillar" is a pillar that is not used as a string of memory cells. In one such embodiment, sacrificial pillars 64 have been formed in the conductor level 16 and in one such embodiment, in material above the conductor level 16. The sacrificial pillars 64 are horizontally positioned (i.e., in x, y coordinates) where individual dummy pillars are to be formed. By way of example and for simplicity only, the sacrificial pillars 60 and 64 are shown arranged in groups or columns of interleaved rows of four and five pillars 60 / 64 per row. In one embodiment, the sacrificial pillars 60 / 64 comprise material 24 (e.g., silicon dioxide) and material 15 (e.g., polysilicon, or a thin TiN liner with elemental tungsten in a radially inward manner). The pillars 60 / 64 can taper radially inwardly (not shown), moving deeper into the lower stack portion 18L. In one embodiment, horizontally elongated sacrificial lines 13 have been formed in the conductor level 16 and in one such embodiment, in material above the conductor level 16. The sacrificial lines 13 are individually between laterally adjacent memory block regions 58. An example sacrificial line 13 comprises material 24 and 15. The sacrificial lines 13 can taper laterally inwardly (not shown), moving deeper into the lower stack portion 18L. In embodiments where pillars 60, pillars 64, and / or lines 13 are formed, they can be formed simultaneously or at different times.

[0021] Reference is made to Figure 3 and 4The vertically alternating first tiers 22 and second tiers 20 of the upper portion 18U of the stack 18* have been formed over the lower portion 18L. The first tiers 22 and second tiers 20 include different constituent materials 26 and 24, respectively (e.g., silicon nitride and silicon dioxide). The example upper portion 18U is shown as beginning with a second tier 20 over the lower portion 18L, though it could alternatively begin with a first tier 22 (not shown). Also, and by way of example, the lower portion 18L can be formed with one or more first and / or second tiers at its top. Regardless, only a small number of tiers 20 and 22 are shown, though it is more likely that the upper portion 18U (and, in turn, the stack 18*) includes tens, hundreds, or more, etc. tiers 20 and 22. Also, other circuitry, which can or can not be part of the peripheral and / or control circuitry, can be between the conductor tiers 16 and the stack 18*. By way of example only, a plurality of vertically alternating tiers of conductive and insulative material of such circuitry can be below the lowermost of the conductive tiers 22* and / or above the uppermost of the conductive tiers 22*. For example, one or more select gate tiers (not shown) can be between the conductor tiers 16 and the lowermost conductive tiers 22*, and one or more select gate tiers can be above the uppermost of the conductive tiers 22*. Alternatively or additionally, at least one of the depicted uppermost and lowermost conductive tiers 22* can be a select gate tier.

[0022] Channel openings 25 and dummy openings 76 have been formed (e.g., by etching) through the second tiers 20 and first tiers 22, respectively, in the upper portion 18U to the sacrificial pillars 60 and 64. In this document, a "dummy opening" is an opening in which a dummy pillar has been or will be formed. The openings 25 / 76 can taper radially inwardly, moving deeper into the stack 18 (not shown).

[0023] Figure 5 The pillars 60 and 64 (not shown) are shown removed through the openings 25 and 76, respectively, extending the openings 25 and 76 into the lower conductor material 44 of the conductor tiers 16. In one embodiment, some or all of the material 24 can remain (not shown) in the extended openings 25 and / or 76. If the pillars 60 and / or 64 are not formed, the openings 25 and / or 76 can be formed into the material 44 as shown in Figure 5 from the start.

[0024] Transistor channel materials can be formed vertically in individual channel openings along insulative and conductive tiers, thus including individual strings of channel material directly electrically coupled with conductive material in the conductor tiers. Individual memory cells of an example memory array being formed can include a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulative charge transport material. The storage material (e.g., a floating gate material, such as doped or undoped silicon, or a charge trapping material, such as silicon nitride, metal dots, etc.) of the individual memory cells is vertically along the individual charge blocking regions. The insulative charge transport material (e.g., a bandgap engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulator oxides [e.g., silicon dioxide]) is laterally between the channel material and the storage material.

[0025] Figures 6-9 One embodiment is shown in which charge blocking material 30, storage material 32, and charge transport material 34 have been formed vertically in individual openings 25 / 76 along insulative tiers 20 and conductive tiers 22. Transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed by, for example, depositing respective thin layers of such transistor materials over stack 18* and within individual openings 25 / 76, and then planarizing such transistor materials back at least to a top surface of stack 18*.

[0026] Channel material 36, as an operative channel material string 53, has also been formed vertically in channel opening 25 along insulative tiers 20 and conductive tiers 22. Thus, operative channel material string 53 extends through first and second tiers 20* and 22* in upper portion 18U and through upper conductor material 43 into lower conductor material 44. In addition, dummy pillar 87 has been formed extending through first and second tiers 20* and 22* in upper portion 18U and through upper conductor material 43 into lower conductor material 44. Thus, and in one embodiment, dummy pillar 87 can have the same material and construction as operative channel material string 53 (as shown) or can have a different material or construction or different materials and construction (not shown). Due to scale, materials 30, 32, 34, and 36 are not shown in the same scale as materials 20, 22, 44, and 43. Figure 6 and 7Commonly exhibited and designated only as material 37. Example channel material 36 includes a suitably doped crystalline semiconductor material, such as one or more of silicon, germanium, and so-called Group III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 Angstroms. A punch etch can be performed to remove materials 30, 32, and 34 from the base of channel opening 25 to expose conductor level 16 such that channel material 36 is directly against conductor material 17 of conductor level 16. Such a punch etch can occur separately with respect to each of materials 30, 32, and 34 (as shown), or can occur only with respect to some of them (not shown). Alternatively, and by way of example only, no punch etch can be performed, and channel material 36 can be directly electrically coupled to conductor material 17 of conductor level 16 only through a separate conductive interconnect (not yet shown). Radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride) is shown in openings 25 / 76. Alternatively, and by way of example only, the radially central portion within openings 25 / 76 can include void space (not shown) and / or be free of solid material (not shown).

[0027] Referring to Figure 10 and 11 A horizontally elongated trench 40 has been formed into stack 18* (e.g., by anisotropic etching), and individually between laterally immediately adjacent memory block regions 58 and extending to line 13 (when present) between the memory block regions.

[0028] Referring to Figure 12 and 13 Trench 40 has optionally been lined with a liner material 78 (e.g., hafnium oxide, aluminum oxide, silicon dioxide, silicon nitride, etc., not shown). Liner material 78 can be partially or completely sacrificial, and desirably has a composition other than that of materials 24 and 26. After deposition of liner material 78, the liner material has been substantially removed from the horizontal surfaces to expose material 15, e.g., by maskless anisotropic spacer-like etching thereof. Subsequently, material 15 (not shown) and material 24 (not shown) of line 13 (not shown) have been removed through trench 40 (e.g., isotropic etching by using a mixture of ammonia and hydrogen peroxide or a mixture of sulfuric acid and hydrogen peroxide if material 15 includes W, and isotropic etching by using HF if material 15 includes silicon dioxide).

[0029] In the lowermost first level, conductive material is formed that directly electrically couples together the channel material of the individual channel material strings with the conductor material of the conductor level. For example, and first referring to Figure 14 and15 which shows an example follow-up process in which the sacrificial material 77 (not shown) has been isotropically etched from the lowermost first level 22z through the trench 40 (e.g., using liquid or gaseous H3PO4 as the primary etchant, where the material 77 is silicon nitride, or using tetramethylammonium hydroxide [TMAH], where the material 77 is polysilicon). Thereafter, in one embodiment, the material 30 (e.g., silicon dioxide), the material 32 (e.g., silicon nitride), and the material 34 (e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) have been etched in the level 20z to expose the sidewall 41 of the channel material 36 of the channel material string 53 in the lowermost first level 22z. Any of the materials 30, 32, and 34 in the level 22z can be considered a sacrificial material therein. By way of example, consider an embodiment in which the liner 78 is one or more insulative oxides (other than silicon dioxide), and the memory cell materials 30, 32, and 34 are individually one or more of a silicon dioxide and a silicon nitride layer. In such an example, the depicted construction can be produced by sequentially etching the silicon dioxide and the silicon nitride selectively with respect to the other using modified or different chemistries. By way of example, a 100: 1 (by volume) solution of water to HF will etch silicon dioxide selectively with respect to silicon nitride, while a 1000: 1 (by volume) solution of water to HF will etch silicon nitride selectively with respect to silicon dioxide. Thus, and in such an example, such etching chemistries can be used in an alternating fashion to achieve the example construction shown by Figure 14 and 15 A person of skill in the art is able to select other chemistries for etching other different materials to achieve the construction shown by Figure 14 and 15 A person of skill in the art is able to select other chemistries for etching other different materials to achieve the construction shown by Figure 14 and 15 Some or all (when present, and not shown as having been removed) of the insulative material (e.g., 24, and not shown in

[0030] Referring to Figure 16 and 17 the conductive material 42 (e.g., conductive doped polysilicon) has been formed in the lowermost first level 22z and in turn directly electrically couples the channel material 36 of the individual operative channel material string 53 with the conductor material 17 of the conductor level 16 together. Subsequently and by way of example, the conductive material 42 has been removed from the trench 40, as has the sacrificial liner 78 (not shown). The sacrificial liner 78 can be removed prior to formation of the conductive material 42 (not shown).

[0031] Referring to Figures 18-22material 26 (not shown) of conductive level 22* is removed, e.g., by isotropically etching away material 26 with respect to other exposed materials desirably selectively (e.g., using liquid or gaseous H3PO4 as a primary etchant, where material 26 is silicon nitride, and other materials include one or more oxides or polysilicon). In an example embodiment, material 26 (not shown) in conductive level 22* is sacrificial, and has been replaced with conductive material 48, and thereafter removed from trench 40, thus forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56.

[0032] A thin insulating liner (e.g., Al2O3, not shown) can be formed prior to forming conductive material 48. The approximate orientation of transistors and / or memory cells 56 is indicated in brackets in Figure 21 , while some of the approximate orientations are indicated with dashed outlines in Figures 18-20 and 22, where transistors and / or memory cells 56 are substantially annular or ring-shaped in the depicted examples. Alternatively, transistors and / or memory cells 56 can not be completely annular with respect to individual channel openings 25, such that each channel opening 25 can have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells around individual channel openings in individual conductive levels, where there can be multiple word lines per channel opening in individual conductive levels, not shown). Conductive material 48 can be considered to have ends 50 Figure 21 corresponding to control gate regions 52 of individual transistors and / or memory cells 56. In the depicted embodiment, control gate regions 52 include individual portions of individual conductive lines 29. Materials 30, 32, and 34 can be considered to be memory structures 65 laterally between control gate regions 52 and channel material 36. In one embodiment and as shown with respect to example "gate last" processing, conductive material 48 of conductive level 22* is formed after forming openings 25 / 27 and / or trench 40. Alternatively, e.g., with respect to "gate first" processing, conductive material of a conductive level can be formed prior to forming channel openings 25 and / or trench 40 (not shown).

[0033] A charge-blocking region (e.g., charge-blocking material 30) is between the storage material 32 and the respective control gate region 52. The charge-blocking can have the following function in a memory cell: in a program mode, the charge-blocking can prevent charge carriers from flowing out of the storage material (e.g., floating gate material, charge-trapping material, etc.) to the control gate, and in an erase mode, the charge-blocking can prevent charge carriers from flowing from the control gate into the storage material. Thus, the charge-blocking can be used to block charge migration between the control gate region and the storage material of an individual memory cell. The example charge-blocking region includes insulator material 30 as shown. By way of other examples, the charge-blocking region can include a laterally (e.g., radially) outer portion of the storage material (e.g., material 32), where such storage material is insulative (e.g., in the absence of any differently-composed material between the insulative storage material 32 and the conductive material 48). Regardless, by way of additional examples, the interface of the storage material and the conductive material of the control gate can be sufficient to act as a charge-blocking region in the absence of any separate composition of the insulator material 30. Moreover, the interface of the conductive material 48 and the material 30 (if present) in combination with the insulator material 30 can together act as a charge-blocking region, and alternatively or additionally, can act as a laterally-outer region of the insulative storage material (e.g., silicon nitride material 32). Example material 30 is one or more of hafnium oxide and silicon dioxide.

[0034] In one embodiment and as shown, the lowermost surface of the channel material 36 of the operative channel material string 53 is not directly against any of the conductor materials 17 of the conductor layer 16. In one embodiment and as shown, the conductive material 42 is directly against the sidewall 41 of the channel material string 53.

[0035] The intervening material 57 has been formed in the trench 40, and thereby laterally between the laterally-adjacent memory blocks 58, and longitudinally along the memory blocks. The intervening material 57 can provide lateral electrical isolation (insulation) between laterally-adjacent memory blocks. Such material can include one or more of insulative, semiconductive, and conductive materials, and regardless, can help to prevent shorting of the conductive layer 22 relative to one another in the finished circuit system construction. Example insulative materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. In this document, "undoped polysilicon" is polysilicon having from 0 atoms per cubic centimeter to 1 x 1019atoms per cubic centimeter of an impurity that increases the electrical conductivity. "Doped polysilicon" is polysilicon having greater than 1 x 1019atoms per cubic centimeter of an impurity that increases the electrical conductivity, and "conductively-doped polysilicon" is polysilicon having at least 1 x 1020atoms per cubic centimeter of an impurity that increases the electrical conductivity. 12 12 18 The intervening material 57 can include through-array vias (not shown).​​

[0036] Any other attribute or aspect as shown and / or described herein with respect to other embodiments can be used in reference to the embodiments shown and described above.

[0037] Alternative embodiment constructions can be implemented by or otherwise result from the method embodiments described above. Regardless, embodiments of the invention encompass memory arrays independent of fabrication methods. Nonetheless, such memory arrays can have any of the attributes as described herein in the method embodiments. Likewise, the method embodiments described above can incorporate, form, and / or have any attribute described with respect to the device embodiments.

[0038] In one embodiment, a memory array (e.g., 12) includes a conductor level (e.g., 16) having an upper conductor material (e.g., 43) directly above and electrically coupled to a lower conductor material (e.g., 44). The upper and lower conductor materials include different compositions relative to each other. The array includes laterally spaced-apart memory blocks (e.g., 58) each including a vertical stack (e.g., 18) of alternating insulative levels (e.g., 20) and conductive levels (e.g., 22). A channel material string (e.g., 53) of a memory cell (e.g., 56) extends through the insulative and conductive levels and through the upper conductor material into the lower conductor material. A channel material (e.g., 36) of the channel material string is directly electrically coupled to the upper and lower conductor materials of the conductor level. An intervening material (e.g., 57) is laterally between and longitudinally along laterally-adjacent memory blocks. Any other attribute or aspect as shown and / or described herein with respect to other embodiments can be used.

[0039] In one embodiment, a memory array (e.g., 12) includes a conductor level (e.g., 16) having an upper conductor material (e.g., 43) directly above and electrically coupled to a lower conductor material (e.g., 44). The upper and lower conductor materials include different compositions relative to each other. The array includes laterally spaced-apart memory blocks (e.g., 58) each including a vertical stack (e.g., 18) of alternating insulative levels (e.g., 20) and conductive levels (e.g., 22). A channel material string (e.g., 53) of a memory cell (e.g., 56) extends through the insulative and conductive levels. A channel material (e.g., 36) of the channel material string is directly electrically coupled to the upper and lower conductor materials of the conductor level. Dummy pillars (e.g., 87) extend through the insulative and conductive levels and through the upper conductor material into the lower conductor material. An intervening material (e.g., 57) is laterally between and longitudinally along laterally-adjacent memory blocks. In one embodiment, the channel material string extends through the upper conductor material into the lower conductor material.

[0040] In one embodiment, the dummy pillars and the channel material strings have the same composition and structure as the conductive levels in which the memory cells reside. In one such embodiment, a lowermost portion of individual dummy pillars has a different composition and structure than individual channel material strings, and in one such embodiment, the different composition includes polysilicon. For example, and by way of example only, Figure 23 An alternative embodiment construction 10a is shown. Certain construction differences are indicated with the same numerals as the above-described embodiments, with a suffix "a" or with different numerals, as appropriate. The lowermost portions of individual dummy pillars 87a are the same as the lowermost portions of pillars 64 of Figure 2 and, in one embodiment, include polysilicon (e.g., material 15). By way of example only, such structures can be produced using the methods as described above, but with the openings 76 masked when the sacrificial pillars 60 are removed from the openings 25.

[0041] Any other property or aspect as shown and / or described herein with respect to other embodiments can be used.

[0042] The above-described processes or configurations can be considered with respect to an array of components formed as a single stack or single deck of such components or within a single stack or single deck, the stack or deck being over or part of an underlying base substrate (but a single stack / deck can have multiple levels). Control and / or other peripheral circuitry for operating or accessing such components within the array can also be formed as part of the final configuration in any location, and in some embodiments, can be under the array (e.g., under-array CMOS). Regardless, one or more additional such stacks / decks can be provided or fabricated over and / or under the stack / deck shown in the figures or described above. Further, the array of components can be the same or different in different stacks / decks relative to each other, and different stacks / decks can have the same or different thicknesses relative to each other. Intervening structures can be provided between vertically adjacent stacks / decks (e.g., additional circuitry and / or dielectric layers). Also, different stacks / decks can be electrically coupled relative to each other. Multiple stacks / decks can be fabricated individually and sequentially (e.g., one on top of the other), or two or more stacks / decks can be fabricated substantially simultaneously.

[0043] The assemblies and structures discussed above can be used in integrated circuits / circuitry and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multilayer, multichip modules. The electronic systems can be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0044] In this document, unless otherwise indicated, "vertical," "higher," "upper," "lower," "top," "over," "bottom," "above," "below," "under," "up," and "down" refer generally to upright directions in the vertical orientation. "Horizontal" refers to a general direction along a major substrate surface that a substrate can be relatively during processing (i.e., within 10 degrees), and vertical is a direction generally normal thereto. "Exactly horizontal" refers to a direction along a major substrate surface (i.e., no angle thereto). Also, as used herein, "vertical" and "horizontal" are generally perpendicular directions with respect to each other, and are independent of the orientation of a substrate in three-dimensional space. In addition, "vertically extending" and "extends vertically" refer to a direction that is at least 45° from exactly horizontal. Furthermore, "vertically extending," "vertically extends," "horizontally extending," "extends horizontally," etc. with respect to a field effect transistor refer to the orientation of the channel length of the transistor, along which current flows between source / drain regions in operation. For bipolar junction transistors, "vertically extending," "vertically extends," "horizontally extending," "extends horizontally," etc. refer to the orientation of the base length, along which current flows between the emitter and collector in operation. In some embodiments, any component, feature, and / or region that extends vertically extends vertically or within 10° of vertical.

[0045] Furthermore, "directly above," "directly below," and "directly under" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components with respect to each other. Also, the use of "above" without the "directly" preceding it only requires that some portion of the stated region / material / component above the other stated region / material / component extends vertically outward from the other stated region / material / component (i.e., independent of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, the use of "below" and "under" without the "directly" preceding it only requires that some portion of the stated region / material / component below / under the other stated region / material / component extends vertically inward from the other stated region / material / component (i.e., independent of whether there is any lateral overlap of the two stated regions / materials / components).

[0046] Any of the materials, regions, and structures described herein can be uniform or non-uniform, and whether or not continuous over any material on which it is over. When one or more example compositions are provided for any material, the material can comprise, consist essentially of, or consist of such one or more compositions. In addition, unless otherwise indicated, each material can be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0047] In addition, "thickness" (without a directional adjective preceding it) used alone is defined as the average straight-line distance normal through a given material or region from the closest surface of an immediately adjacent material or region of different composition. In addition, various materials or regions described herein can have a substantially constant thickness or a variable thickness. If having a variable thickness, unless otherwise indicated, the thickness refers to the average thickness, and the material or region will have some minimum thickness and some maximum thickness due to the variable thickness. As used herein, "different composition" only requires that those portions of two stated materials or regions that can be directly against one another are chemically and / or physically different, e.g., if such materials or regions are not uniform. If two stated materials or regions are not directly against one another, "different composition" only requires that those portions of two stated materials or regions that are closest to one another are chemically and / or physically different, e.g., if such materials or regions are not uniform. In this document, a material, region, or structure is "directly against" another material, region, or structure when there is at least some physical contact between the stated materials, regions, or structures relative to one another. In contrast, "over," "on," "adjacent," "along," and "against" without the "the" in front of them encompass both "directly against" and configurations where intervening materials, regions, or structures are such that the stated materials, regions, or structures are not in physical contact relative to one another.

[0048] Herein, zone-material-assemblies are "electrically coupled" relative to one another if, in normal operation, current is able to flow continuously from one zone-material-assembly to another, and the flow is primarily through movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic assembly can be between and electrically coupled to the zone-material-assemblies. In contrast, when zone-material-assemblies are said to be "directly electrically coupled," there are no intervening electronic assemblies (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled zone-material-assemblies.

[0049] Any use of "row" and "column" herein is to facilitate distinguishing one series or orientation of features from another series or orientation of features, and assemblies have been or can be formed along the "rows" and "columns." "Row" and "column" are used synonymously with respect to any series of zones, assemblies, and / or features, regardless of function. Regardless, rows can be straight and / or curved and / or parallel and / or non-parallel relative to one another, as can columns. In addition, rows and columns can intersect at 90° or at one or more other angles (i.e., other than a right angle) relative to one another.

[0050] The components of any of the conductive / conductor / conducting materials herein can be metallic materials and / or electrically conductive doped semiconductive / semiconductor / semiconducting materials. A "metallic material" is any one or a combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more electrically conductive metal compounds.

[0051] In this document, any use of "or" means any one and both of the stated alternatives. In this document, any use of "and" means both of the stated alternatives.

[0052] Unless otherwise indicated herein, the use of "or" in this document encompasses any one and both of the stated alternatives.

[0053] Conclusion

[0054] In some embodiments, a method for forming a memory array including strings of memory cells includes forming a conductor level including an upper conductor material directly above and in direct electrical coupling with a lower conductor material. The upper and lower conductor materials include different compositions relative to one another. Forming a stack including vertically alternating first and second levels above the conductor level. The stack includes laterally spaced apart memory block regions. A material of the first levels has a different composition than a material of the second levels. Forming strings of channel material extending through the first and second levels and through the upper conductor material to the lower conductor material. Forming intervening material laterally between and longitudinally along laterally adjacent ones of the memory block regions.

[0055] In some embodiments, a method for forming a memory array including strings of memory cells includes forming a conductor level including an upper conductor material directly above and directly electrically coupled with a lower conductor material. The upper and lower conductor materials include different compositions relative to each other. Forming a lower portion of a stack including vertically alternating first and second levels above the conductor level. The stack includes laterally spaced apart memory block regions. A material of the first levels has a different composition than a material of the second levels. A lowermost of the first levels includes a sacrificial material. A lowermost of the second levels is below the lowermost first level. Vertically alternating first and second levels of an upper portion of the stack are formed above the lower portion. Forming strings of channel material extending through the first and second levels and through the upper conductor material to the lower conductor material. Forming horizontally elongated trenches into the stack that are individually between laterally immediately adjacent memory block regions and extend to the lowermost first levels. Etching the first sacrificial material isotropically from the lowermost first levels through the trenches. Removing the lowermost second levels after the isotropic etching. Forming conductive material in the lowermost first levels that directly electrically couples the channel material of the individual strings of channel material together with the conductor level after removing the lowermost second levels. Forming intervening material laterally between the laterally immediately adjacent memory block regions and longitudinally along the laterally immediately adjacent memory block regions.

[0056] In some embodiments, a memory array includes a conductor level having an upper conductor material directly above and directly electrically coupled with a lower conductor material. The upper and lower conductor materials include different compositions relative to each other. Laterally spaced apart memory blocks individually include a vertical stack including alternating insulative and conductive levels. Strings of channel material of memory cells extend through the insulative and conductive levels and through the upper conductor material to the lower conductor material. The channel material of the strings of channel material is directly electrically coupled to the upper and lower conductor materials of the conductor level. Intervening material is laterally between laterally immediately adjacent the memory blocks and longitudinally along laterally immediately adjacent the memory blocks.

[0057] In some embodiments, a memory array includes a conductor level having an upper conductor material directly above and directly electrically coupled to a lower conductor material. The upper and lower conductor materials include different compositions relative to each other. Laterally spaced-apart memory blocks individually include a vertical stack of alternating insulative levels and conductive levels. Strings of channel materials of memory cells extend through the insulative levels and the conductive levels. The channel materials of the strings of channel materials are directly electrically coupled to the upper and lower conductor materials of the conductor level. Dummy pillars extend through insulative levels and conductive levels and through the upper conductor material into the lower conductor material. An intervening material is laterally between and longitudinally along laterally-adjacent ones of the memory blocks.

[0058] In accordance with the provisions of the patent statutes, the subject matter disclosed herein has been described in its preferred form, with specific reference to structural and methodological features set forth and / or illustrated herein. It is to be understood, however, that the words used are merely descriptive, rather than limiting, and that changes may be made in the function and / or construction of the various features disclosed and / or illustrated herein without departing from the scope of the disclosure. Accordingly, the claims are not limited to the specific features set forth and / or illustrated herein, but encompass all changes that come within the true spirit and scope of the claims, even though these changes may not have been forceably enumerated by the claims.

Claims

1. A method for forming a memory array comprising strings of memory cells, comprising: forming a conductor level comprising an upper conductor material, the upper conductor material being directly above and electrically coupled with a lower conductor material, the upper and lower conductor materials comprising different compositions relative to one another; forming a stack comprising vertically-alternating first and second levels above the conductor level, the stack comprising laterally-spaced memory block regions, a material of the first levels having a different composition than a material of the second levels; forming strings of channel material extending through the first and second levels and through the upper conductor material to the lower conductor material; and forming intervening material laterally between and longitudinally along laterally-adjacent ones of the memory block regions.

2. The method of claim 1 wherein the upper conductor material comprises electrically- conductively-doped semiconductive material.

3. The method of claim 2 wherein the electrically-conductively-doped semiconductive material comprises electrically-conductively-doped polysilicon.

4. The method of claim 1 wherein the lower conductor material comprises metallic material.

5. The method of claim 4 wherein the metallic material comprises metal silicide.

6. The method of claim 1 wherein the upper conductor material comprises electrically- conductively-doped semiconductive material and the lower conductor material comprises metallic material.

7. The method of claim 6 wherein the upper conductor material comprises electrically- conductively-doped polysilicon and the lower conductor material comprises metal silicide.

8. The method of claim 7 wherein the metal silicide comprises tungsten silicide.

9. The method of claim 1 wherein forming the strings of channel material comprises: forming sacrificial pillars in the conductor level, the sacrificial pillars individually horizontally positioned where individual strings of channel material are to be formed; forming channel openings into the stack and individually extending to individual ones of the sacrificial pillars; removing the sacrificial pillars through the channel openings to extend the channel openings into the lower conductor material of the conductor level; and forming the strings of channel material in the elongated channel openings and in void spaces created therein by the removing.

10. The method of claim 1 comprising forming dummy pillars extending through the first and second levels and through the upper conductor material to the lower conductor material.

11. The method of claim 10 wherein forming the dummy pillars comprises: forming sacrificial pillars in the conductor level, the sacrificial pillars individually horizontally positioned where individual dummy pillars are to be formed; forming dummy openings into the stack and individually extending to individual ones of the sacrificial pillars; removing the sacrificial pillars through the dummy openings to extend the dummy openings into the lower conductor material of the conductor level; and forming the dummy pillars in the elongated dummy openings and in void spaces created therein by the removing.

12. A method for forming a memory array comprising strings of memory cells, comprising: forming a conductor level comprising an upper conductor material directly over and in electrical coupling with a lower conductor material, the upper and lower conductor materials comprising different compositions relative to one another; forming a lower portion of a stack comprising vertically-alternating first and second levels over the conductor level, the stack comprising laterally-spaced memory block regions, a material of the first levels having a different composition than a material of the second levels, a lowermost of the first levels comprising a sacrificial material, a lowermost of the second levels being below the lowermost first level; forming the vertically-alternating first and second levels of an upper portion of the stack over the lower portion and forming strings of channel material extending through the first and second levels and through the upper conductor material into the lower conductor material; forming horizontally-elongated trenches into the stack, the horizontally-elongated trenches individually between laterally-adjacent ones of the memory block regions and extending to the lowermost first levels; isotropically etching the sacrificial material from the lowermost first levels through the trenches; removing a lowermost second level after the isotropic etching; forming conductive material in the lowermost first levels after removing the lowermost second level that directly electrically couples together the channel material of the individual strings of channel material with the conductor level; and forming intervening material laterally between laterally-adjacent ones of the memory block regions and longitudinally along laterally-adjacent ones of the memory block regions.

13. The method of claim 12 wherein the upper conductor material comprises a conductively-doped semiconductive material and the lower conductor material comprises a metallic material.

14. The method of claim 12 wherein forming the strings of channel material comprises: forming sacrificial pillars in the lower portion of the stack and in the conductor level, the sacrificial pillars individually horizontally positioned where the individual strings of channel material are to be formed; forming channel openings into the stack and individually extending to individual ones of the sacrificial pillars; removing the sacrificial pillars through the channel openings to extend the channel openings into the lower conductor material of the conductor level; and forming the strings of channel material in the elongated channel openings and in void spaces created therein by the removing.

15. The method of claim 12 comprising forming dummy pillars extending through the first and second levels, through the lower portion and through the upper conductor material to the lower conductor material.

16. The method of claim 15 wherein forming the dummy pillars comprises: forming sacrificial pillars in the lower portion of the stack and in the conductor level, the sacrificial pillars individually horizontally positioned where the individual dummy pillars are to be formed; forming dummy openings into the stack and individually extending to individual ones of the sacrificial pillars; removing the sacrificial pillars through the dummy openings to extend the dummy openings into the lower conductor material of the conductor level; and forming the dummy pillars in the extended dummy openings and in void spaces created therein by the removing.

17. A memory array, comprising: a conductor level including an upper conductor material directly above and directly electrically coupled to a lower conductor material, the upper and lower conductor materials including different compositions relative to each other; laterally spaced-apart memory blocks each including a vertical stack including alternating insulative levels and conductive levels, strings of channel materials of memory cells extending through the insulative levels and the conductive levels and through the upper conductor material into the lower conductor material, the channel materials of the strings of channel materials directly electrically coupled to the upper and lower conductor materials of the conductor level; and interstitial material laterally between and longitudinally along laterally-adjacent ones of the memory blocks.

18. The memory array of claim 17, wherein the upper conductor material comprises a conductively-doped semiconductive material.

19. The memory array of claim 18, wherein the conductively-doped semiconductive material comprises conductively-doped polysilicon.

20. The memory array of claim 17, wherein the lower conductor material comprises a metallic material.

21. The memory array of claim 20, wherein the metallic material comprises a metal silicide.

22. The memory array of claim 21, wherein the upper conductor material comprises a conductively-doped semiconductive material and the lower conductor material comprises a metallic material.

23. The memory array of claim 22, wherein the upper conductor material comprises conductively-doped polysilicon and the lower conductor material comprises a metal silicide.

24. The memory array of claim 23, wherein the metal silicide comprises tungsten silicide.

25. A memory array, comprising: a conductor level including an upper conductor material directly above and directly electrically coupled to a lower conductor material, the upper and lower conductor materials including different compositions relative to each other; laterally spaced-apart memory blocks each including a vertical stack including alternating insulative levels and conductive levels, strings of channel materials of memory cells extending through the insulative levels and the conductive levels, the channel materials of the strings of channel materials directly electrically coupled to the upper and lower conductor materials of the conductor level; dummy pillars extending through the insulative levels and the conductive levels and through the upper conductor material into the lower conductor material; and interstitial material laterally between and longitudinally along laterally-adjacent ones of the memory blocks.

26. The memory array of claim 25, wherein the channel material string extends through the upper conductor material into the lower conductor material.

27. The memory array of claim 25, wherein the dummy pillars and the channel material strings have the same composition and structure as the electrically conductive levels in which the memory cells reside.

28. The memory array of claim 27, wherein a lowermost portion of individual dummy pillars has a different composition and structure than the lowermost portion of individual channel material strings.

29. The memory array of claim 28, wherein the different composition comprises polysilicon.

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