Co-integrated high voltage (HV) and medium voltage (MV) field effect transistors with anti-defect structures

Abstract

The present invention relates to co-integrated high-voltage (HV) and medium-voltage (MV) field-effect transistors and defect-preventing structures. The present disclosure relates to semiconductor structures, and more particularly to co-integrated high-voltage and medium-voltage devices and defect-preventing structures and manufacturing methods. The structure includes: a semiconductor-on-insulator (SOI) region and a bulk region integrated in a single substrate; at least one active device located in the bulk region; at least one active device located in the SOI region; and a defect-preventing structure located at the boundary of the SOI region.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to co-integrated high-voltage and medium-voltage devices with anti-defect structures and manufacturing methods. Background Art

[0002] Silicon-on-insulator (SOI) substrates, including fully depleted SOI (FDSOI) or radio frequency SOI (RFSOI), are used for various integrated circuit (IC) applications. The SOI substrate includes a thin surface crystalline layer or silicon layer separated from the bulk substrate by a buried oxide (BOX).

[0003] Typically, IC applications include high-voltage (HV) transistors, such as extended drain metal oxide semiconductor (EDMOS) transistors. However, the thin surface substrate of the SOI substrate is not suitable for providing high-voltage transistors, such as EDMOS. This makes it difficult to integrate HV transistors with other devices (such as SOI devices) on the SOI substrate. For example, conventional techniques for integrating HV transistors on the SOI substrate require performing complex processing to make these HV transistors compatible with other devices. But the complex processing results in increased costs. In addition, when forming the gate oxide for HV or medium-voltage (MV) transistors, due to oxygen diffusion, such an integration scheme causes defects in the active Si regions (such as the channel region) of the SOI devices. Summary of the Invention

[0004] In one aspect of the present disclosure, a structure includes: a semiconductor-on-insulator (SOI) region and a bulk region integrated in a single substrate; at least one active device located in the bulk region; at least one active device located in the SOI region; and an anti-defect structure located at the border of the SOI region.

[0005] In one aspect of the present disclosure, a structure includes: a semiconductor-on-insulator (SOI) region including at least one active SOI device; a bulk region integrated with the SOI region and including at least one active bulk device different from the at least one active SOI device; and a guard ring structure including bulk semiconductor material located at the border of the SOI region and configured to prevent oxygen diffusion into the active channels of the SOI devices in the SOI region.

[0006] In one aspect of the present disclosure, a method includes: forming a semiconductor-on-insulator (SOI) region and a bulk region from a single substrate; forming at least one active device in the bulk region; forming at least one active device in the SOI region; and forming an anti-defect structure located at the border of the SOI region. Description of the Drawings

[0007] In the following detailed description, the present disclosure is described with reference to the several figures mentioned, by way of non-limiting examples of exemplary embodiments of the present disclosure.

[0008] Figure 1 Shown are a substrate with a defect prevention structure among other features, according to some aspects of the present disclosure, and a corresponding manufacturing process.

[0009] Figure 2 Shown are SOI technology and bulk technology from the same substrate among other features, according to some aspects of the present disclosure, and a corresponding manufacturing process.

[0010] Figure 3 Shown are a first gate dielectric material and a bird's beak in a defect prevention structure among other features, according to some aspects of the present disclosure, and a corresponding manufacturing process.

[0011] Figure 4 Shown are a second gate dielectric material and bulk technology on a patterned first gate dielectric material among other features, according to some aspects of the present disclosure, and a corresponding manufacturing process.

[0012] Figure 5 Shown is a patterned second dielectric material among other features, according to some aspects of the present disclosure, and a corresponding manufacturing process.

[0013] Figure 6 Shown are gate materials on SOI technology and bulk technology for forming a gate among other features, according to some aspects of the present disclosure, and a corresponding manufacturing process.

[0014] Figure 7 Shown are patterned gate materials on SOI technology and bulk technology among other features, according to some aspects of the present disclosure, and a corresponding manufacturing process.

[0015] Figure 8 Shown are different devices with partially silicided raised source and drain regions on SOI technology and bulk technology among other features, according to some aspects of the present disclosure, and a corresponding manufacturing process.

[0016] Figures 9A to 9C A top-down view schematically shows different configurations of a defect prevention structure, according to some aspects of the present disclosure. Detailed Description

[0017] The present disclosure relates to semiconductor structures, and more particularly to co-integrated high-voltage and medium-voltage devices with anti-defect structures and manufacturing methods. More specifically, the present disclosure relates to the co-integration of HV and MV field-effect transistors (FETs) with fully depleted silicon-on-insulator (FDSOI) technology, and structures for preventing defects in the active regions of FDSOI technology (i.e., SOI / cSiGe devices). Advantageously, this integration scheme prevents defects in the active regions of SOI devices during the gate oxide process of HV and / or MV FETs, thereby allowing applications and / or circuits to migrate from legacy technologies to current technology nodes.

[0018] In an embodiment, HV FETs and MV FETs can be integrated on the same die (in a bulk technology) with fully depleted MOSFET devices. More specifically, for example, HV and MV FETs can be integrated with SOI technology on a bulk technology. In an example of this integration scheme, an anti-defect structure composed of bulk material (e.g., Si material) can be provided at the boundary between the fully depleted MOSFET device and the MV FET and / or HV FET. When viewed from a top-down view, the bulk material (e.g., the anti-defect structure) appears as a protection ring that surrounds the fully depleted MOSFET device or a cluster of HV FET and / or MV FET devices. During the formation of the gate oxide of the HV FET and / or MVFET, the anti-defect structure (e.g., bulk Si material) prevents oxygen diffusion corrosion (e.g., resulting in defects) of the active region of the fully depleted MOSFET device.

[0019] The devices of the present disclosure can be fabricated in a variety of different ways using a variety of different tools. However, generally speaking, these methods and tools are used to form structures on the micron and nanometer scales. The methods (i.e., techniques) used to fabricate the devices of the present disclosure have been adopted from integrated circuit (IC) technology. For example, these structures are built on wafers and realized in patterned material films by performing a lithography process on top of the wafers. In particular, the fabrication of these devices uses three basic building blocks: (i) depositing a thin film of material on a substrate, (ii) applying a patterned mask on top of the film by lithographic imaging, and (iii) selectively etching the film with respect to the mask.

[0020] Figure 1 A substrate with an anti-defect structure and a corresponding manufacturing process are shown, among other features. More specifically, Figure 1The structure 10 includes a substrate 12 incorporating SOI technology. For example, the substrate 12 can be a fully depleted p-doped substrate. In an embodiment, for illustrative purposes, the substrate 12 includes four separate regions: (i) a region 100 for hybrid devices; (ii) a region 200 for SOI / cSiGe devices; (iii) a region 300 for MV FET devices; (iv) a region 400 for HV FET devices. As further described below, the substrate 12 of regions 100, 300, and 400 can be modified to a bulk wafer implementation, with a defect prevention structure 15 at the boundaries of region 200 and / or region 300 and / or region 400, depending on device fabrication (e.g., if region 300 is excluded). In an embodiment, and as an illustrative and non-limiting example, the MV FET device can be an 8V FET; while the HV FET device can be a 20V FET.

[0021] In SOI technology, the substrate 12 includes a semiconductor material 12c bonded or attached to an insulator layer 12b, and the insulator layer 12b is bonded to a bulk wafer 12a, such as a bulk semiconductor material. The semiconductor material 12c can be bonded to the insulator layer 12b by using wafer bonding techniques and / or other suitable methods. The insulator layer 12b can also be formed by any suitable process, such as by separation by implanted oxygen (SIMOX), oxidation, deposition, and / or other suitable processes. The semiconductor materials 12a, 12c can include any suitable semiconductor materials, such as Si, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. The insulator layer 12b also includes any suitable materials, including silicon oxide, sapphire, other suitable insulating materials, and / or combinations thereof. An exemplary insulator layer 12b is a buried oxide layer (BOX) with a thickness of about 10 - 30 nm.

[0022] Still referring to Figure 1 , in region 200, a condensation process is performed on a portion of the semiconductor material 12c to form a channel region 14 of a different semiconductor material. For example, the channel region 14 can be SiGe produced by a SiGe condensation process. The condensation process can be any condensation process known in the art. For example, one-step or two-step wet oxidation of germanium implanted into the semiconductor material 12c can be used to demonstrate germanium condensation. Also, those skilled in the art should understand that the diffusion and accumulation of Ge will vary with gas flow rate and temperature. In an embodiment, the SiGe channel region 14 is for pFET devices (such as cSiGe).

[0023] Figure 1A plurality of shallow trench isolation structures 16 are also shown. In an embodiment, the shallow trench isolation structures 16 can be formed by conventional lithography, etching, and deposition methods known to those skilled in the art. For example, a resist formed over the semiconductor material 12c is exposed to energy (light) to form a pattern (opening). An etching process with selective chemical action (e.g., reactive ion etching (RIE)) can be used to form one or more trenches in the substrate 12 through the opening of the resist, and these trenches extend into the bulk semiconductor material 12a. After removing the resist by a conventional oxygen ashing process or other known strippers, an insulator material, such as an oxide, can be deposited by any conventional deposition process (e.g., chemical vapor deposition (CVD) process). Any residual material on the surfaces of the semiconductor materials 12c, 14 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0024] A defect prevention structure 15 can be provided at the boundary between the SOI region 200 and adjacent bulk regions (e.g., MV / HV device regions 300, 400). In a more specific embodiment, the defect prevention structure 15 can be a structure that extends through the shallow trench isolation structure 16 and reaches the bulk Si material of the underlying substrate 12a. In an alternative embodiment, the defect prevention structure 15 can be any semiconductor material that can consume oxides.

[0025] The defect prevention structure 15 can be fabricated by using conventional lithography, etching, and deposition methods known to those skilled in the art as already described herein. For example, a resist formed over the structure is exposed to energy (light) to form a pattern (opening) over the shallow trench isolation structure 16. An etching process with selective chemical action (e.g., reactive ion etching (RIE)) will be used to provide a trench through the shallow trench isolation structure 16. The semiconductor material of the defect prevention structure 15 can be deposited in the trench by any conventional deposition process, including an epitaxial growth process, while other portions of the structure are still covered by a masking material to prevent epitaxial growth in undesired regions of the structure. Other known deposition processes can also be considered herein. Any excess material can be removed by a planarization process (e.g., chemical mechanical polishing (CMP)).

[0026] Viewed from a top-down view, the defect prevention structure 15 presents as a guard ring structure surrounding the SOI device region 200 or the MV FET device region 300 and / or the HV FET device region 400, providing an oxygen diffusion barrier. For example, in these different configurations, the defect prevention structure 15 (e.g., semiconductor material) prevents oxygen from diffusing through the shallow trench isolation structure 16 and into the active channel region 14 of the devices within the region 200. Thus, the active channel region 14 and / or 12a will not be corroded (become defective) during the formation of the gate oxide of the devices in the regions 300, 400.

[0027] Still referring toFigure 1 An ion implantation process can be performed on the substrate 12 to form wells, particularly in regions 300 and 400. For example, region 300 for the MV FET device can be subjected to an ion implantation process to create an N well; while region 400 for the HV FET device can be subjected to an ion implantation process to create both an N well and a P well. In an embodiment, the P well can be doped or implanted with a p-type dopant, such as boron (B), and the N well can be doped or implanted with an n-type dopant, such as arsenic (As), phosphorus (P), and Sb, and other suitable examples.

[0028] In an embodiment, wells can be formed by introducing a certain concentration of different dopants of opposite conductivity types into the substrate 12. In an embodiment, corresponding patterned implantation masks can be used to define the selected regions exposed for implantation. The implantation mask for selecting the regions exposed for well formation is stripped after implantation and before the implantation masks for forming other wells of different types. The implantation mask can include a photosensitive material layer, such as an organic photoresist layer, which is applied by a spin coating process, pre-baked, exposed to light projected through a photomask, post-exposure baked, and developed with a chemical developer. Each implantation mask has a thickness and blocking ability sufficient to block the masked regions from receiving a certain dose of implanted ions. Those skilled in the art will understand that annealing can be performed after the implantation process to drive in the dopants.

[0029] In Figure 2 , a removal process (such as an etching process) is performed on the substrate 12 to form a bulk semiconductor implementation in regions 100, 300, and 400. For example, after removing the implantation mask (and / or other masks), a photolithography and etching process can be performed on the substrate 12 to remove the semiconductor material 12c and the insulator layer 12b in regions 100, 300, and 400. These processes will expose the bulk semiconductor material 12a, creating a bulk implementation for the hybrid device, MV FET, and HV FET. In an embodiment, a defect prevention structure 15, such as bulk Si material, can be fabricated before or after the etching process for forming the bulk semiconductor implementation in regions 100, 300, and 400.

[0030] To form a bulk semiconductor implementation in regions 100, 300, and 400, the resist formed over semiconductor material 12c is exposed to energy (light) to form a pattern (opening) over regions 100, 300, and 400. A process with selective chemistry (e.g., RIE) is used to remove semiconductor material 12c and insulator layer 12b in regions 100, 300, and 400 while protecting region 200 (including channel region 14), thereby exposing the bulk semiconductor material 12a in regions 100, 300, and 400. In this way, devices in regions 100, 300, and 400 can be fabricated in a bulk implementation, while devices in region 200 are fabricated using SOI technology. The resist can be removed by a conventional oxygen ashing process or other known strippers.

[0031] After the etching process, channel and extension region implants can be fabricated in regions 300 and 400. During the channel and extension region implants, regions 100 and 200 can be protected by a hard mask and / or a stack of resist materials. In this way, the implant process will not be performed on regions 100 and 200. As is well known in the art, after the implant process, the stack of resist materials can be removed. Regions 300 and 400 can also be cleared of any masking materials to expose the surface of the bulk semiconductor material 12a. However, as Figure 3 shown, the hard mask 18 can remain on the semiconductor materials 12c, 14 in regions 100 and 200 during the cleaning process.

[0032] Figure 3 Shown is the resulting bird's beak 15a and the first gate dielectric material in the defect prevention structure 15 among other features. More specifically, in Figure 3 , an insulator material 20 is formed over the bulk semiconductor material 12a in regions 300 and 400 and over the hard mask 18 in regions 100 and 200. Before depositing the insulator material 20, the exposed surface of the semiconductor material 12c can be cleaned by a wet process (e.g., HF chemistry) known to those skilled in the art. The hard mask 18 will protect the surfaces of regions 100 and 200 during the cleaning process. In an embodiment, the insulator material 20 can be a gate oxide material for HV FET devices (e.g., region 400).

[0033] The insulator material 20 can be formed (e.g., deposited) by any conventional deposition method for gate oxides (e.g., CVD, plasma vapor deposition (PVD), etc.). After the deposition process, a rapid thermal annealing process known in the art can be performed on the insulator material 20. In an embodiment, the bottom surface of the insulator material 20 can be aligned with the bottom surface of the insulator layer 12b. The insulator material 20 can be deposited to about The thickness; however, other dimensions may be considered herein. In a preferred embodiment, the insulator material 20 may be deposited to a thickness greater than the thickness of the insulator layer 12b.

[0034] Those skilled in the art should understand that the insulator deposition process results in oxygen diffusion, which can corrode the active channel regions 14 and / or 12a of, for example, pFET or other MOSFET devices (such as cSiGe). Noting this, the defect prevention structure 15 (such as a bulk semiconductor material) eliminates the oxygen diffusion path into the active channel regions of the SOI device, thereby preventing corrosion (defects) of the channel material (such as Si, SiGe, etc.). For example, the semiconductor material of the defect prevention structure 15 consumes oxygen during the oxidation process, forming a bird's beak 15a (such as an oxide region) extending inward from the shallow trench structure 16. In this way, the oxygen consumption of the defect prevention structure 15 effectively prevents any corrosion or defects of the semiconductor material in the active channel regions 14 and / or 12a of the SOI device in region 200.

[0035] In Figure 4 it, the insulator material 20 undergoes a patterning process, and then an insulator material 22 for, for example, MV FET devices in region 300 is formed (such as deposited). More specifically, as Figure 4 shown, the insulator material 20 is removed from regions 100, 200, and 300 by conventional lithography and etching processes (such as dry and wet etching processes). The insulator material 20 is also partially removed from region 400, leaving the patterned insulator material 20 for the HV FET device. After resist removal, the exposed surface can be cleaned with, for example, an HF solvent, where the hard mask 18 serves as an HF etch stop layer.

[0036] After the cleaning process, an insulator material 22 is formed (such as deposited) on the exposed surface of the insulator material 20 in region 400, on the exposed surface of the bulk semiconductor material 12a in regions 300 and 400, and above the hard mask material 18 in regions 100 and 200. In an embodiment, the insulator material 22 can surround the top and side surfaces of the insulator material 20 in region 400 for the HV FET device. In addition, the bottom surfaces of both the insulator material 22 and the insulator material 20 can be aligned with the insulator layer 12b (such as the buried oxide layer of SOI technology). In an embodiment, the insulator material 22 is the gate oxide material for the MVFET device in region 300.

[0037] It is also expected that the defect prevention structure 15 (such as a bulk semiconductor material) can block the oxygen diffusion path into the active regions 14 and / or 12a during the gate oxidation process. Again, the defect prevention structure 15 can consume oxygen, thereby forming a bird's beak structure 15a composed of oxide material; while the active channel regions 14 and / or 12a will not be affected by the oxygen diffusion process.

[0038] The combination of the insulator material 22 and the insulator material 20 in the region 400 can be thicker than the insulator layer 12b (such as the buried oxide layer of SOI technology). For example, the insulator material 22 can have a thickness of about ; but other dimensions can be considered herein. The insulator material 22 can be deposited by any conventional deposition method for gate oxide (such as CVD, PVD, etc.), and then a rapid thermal annealing process well-known in the art is performed.

[0039] In Figure 5 , the insulator material 22 undergoes a patterning process for MV FET devices in the region 300, for example, and then the hard mask in the regions 100 and 200 is removed. More specifically, as Figure 5 shown, the insulator material 22 can be completely removed from the regions 100 and 200, while being patterned in the regions 300 and 400 by using conventional lithography and etching processes (such as dry and wet etching processes). Those skilled in the art should understand that the patterning of the insulator materials 20 and 22 in the regions 300 and 400 is the result of the patterning of the resist material, that is, the removal of the insulator materials 20 and 22 in the regions 300 and 400 is prevented.

[0040] In the region 300, the insulator material 22 can be partially removed, leaving the insulator material 22 for the MV FET device. Additionally, in the region 400, the insulator material 22 can be retained on the side and top surfaces of the insulator material 20 for the HV FET device. It should be understood that due to the resist patterning, the insulator material 22 for the HV FET device in the region 400 can form a stepped feature or pattern 23 (as Figure 5 shown), and is also retained on the partially exposed surface of the bulk semiconductor material 12a.

[0041] Figure 5 The removal of the hard mask 18 in the regions 100 and 200 is also shown. The hard mask 18 can be removed. Additionally, in an embodiment, the exposed surfaces (such as the semiconductor materials 12c, 14) can undergo a pre-cleaning process, such as resist stripping, to remove any native oxide on the surfaces of the semiconductor materials 12c, 14.

[0042] In Figure 6Therein, the gate patterning process is started for the hybrid devices, SOI devices, MV FET devices, and HV FET devices in each region. Advantageously, each gate material can be fabricated for each device in the same processing step. For example, the gate dielectric material 28 is deposited over the insulator material 22 for the MV FET devices and HV FET devices, and also over the semiconductor materials 12c, 14 for the hybrid devices and SOI devices. In an embodiment, the gate dielectric material 28 can be a high-k dielectric material, such as HfO2, Al2O3, Ta2O3, TiO2, La2O3, SrTiO3, LaAlO3, ZrO2, Y2O3, Gd2O3, and combinations including multiple layers thereof.

[0043] Still referring to Figure 6 , the gate conductor material 30 can be deposited on the gate dielectric material 28. In an embodiment, the gate conductor material 30 can include a work function metal for the pre-gate process and an optional Si layer that can be silicided later. Examples of work function materials for p-channel FETs include Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co. Examples of work function materials for n-channel FETs include TiN, TaN, TaAlC, TiC, TiAl, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC. The work function materials can be formed by CVD, PVD, including sputtering, atomic layer deposition (ALD), or other suitable methods. A capping material (e.g., SiN) 32 is deposited on the gate conductor material 30 using any conventional deposition method. Those skilled in the art should understand that the capping material 32 will serve as a sidewall spacer.

[0044] In Figure 7 , the gate structure will undergo a patterning process to form, for example, hybrid devices 36, SOI devices 38, MV FET devices 40, and HV FET 42. For example, the capping material 32, the gate conductor material 30, and the gate dielectric material 28 are removed from the horizontal surface of the device, thereby exposing the semiconductor materials 12a, 12c, 14. In this gate patterning process, after the gate patterning process, another capping material 33 can remain on the sidewalls of each device 36, 38, 40, 42. This patterning process can define the devices 36, 38, 40, 42.

[0045] After defining each of the devices 36, 38, 40, 42, source and drain regions 34 can be formed on the exposed semiconductor materials 12a, 12c, 14. In an embodiment, the source and drain regions 34 can be raised source and drain regions, which are formed by performing a doped epitaxial growth process directly on the corresponding exposed semiconductor materials 12a (for hybrid devices 36, MV FET devices 40, and HV FET devices 42) and semiconductor materials 12c, 14 (for SOI devices 38). The capping material 32 is then removed to expose the gate conductor material 30.

[0046] As Figure 8 As further shown, a liner 43 is deposited over the capping material 32, the exposed conductor material 30, and the source and drain regions 34. In an embodiment, the liner is a silicide blocking material that prevents the formation of silicide on the top surface of the source and drain regions 34. After partially removing the liner 43 to expose the side surfaces of the source and drain regions 34 and the conductor material 30, a silicide 44 is formed on the exposed conductor material 30 and the source and drain regions 34.

[0047] Those skilled in the art should understand that the silicide process begins with depositing a thin transition metal layer, such as nickel, cobalt, or titanium, on a fully formed and patterned semiconductor device (e.g., doped or ion implanted source and drain regions and corresponding devices). After depositing the material, the structure is heated to allow the transition metal to react with the exposed silicon (or other semiconductor materials described herein) in the active regions of the semiconductor device (e.g., source, drain, gate contact regions), thereby forming a low-resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts 44 in the active regions of the device. Those skilled in the art should understand that when the gate structure is composed of a metal material, silicide contacts are not required on the device.

[0048] In addition to the source and drain regions 34, a liner 46 is also deposited over each of the devices 36, 38, 40, 42. In an embodiment, the liner 46 can be a tensile stress liner composed of a tensile material (e.g., nitride). An interlayer dielectric material 48 is deposited by CVD and then subjected to a CMP process. Although not shown in this view, contacts to the devices 36, 38, 40, 42 and the source and drain regions 34 are formed using conventional lithography, etching, and deposition processes, which are well known to those skilled in the art and thus the present disclosure can be fully understood without further explanation.

[0049] Figure 8It is also shown that each of the devices 36, 38, 40, and 42 includes a different absolute height. This is caused by the different materials and manufacturing processes for constructing these different devices. For example, device 42 includes two layers of gate oxide materials 20, 24; device 40 includes one layer of gate oxide material 20, while device 36 does not include any gate oxide. Additionally, device 38 is constructed on an SOI wafer 12 (such as semiconductor materials 12a, 14) without using gate oxide material; while devices 36, 40, and 42 are constructed on a bulk wafer.

[0050] Figures 9A to 9C A top - down view schematically shows different configurations of the anti - defect structure 15. More specifically, in Figure 9A the anti - defect structure 15 is shown surrounding an SOI device, namely, region 200 for an SOI / cSiGe device. In Figure 9B the anti - defect structure 15 is shown surrounding region 300 for an MV FET device. In Figure 9C the anti - defect structure is shown surrounding both region 300 for an HV FET device and region 400. It should be understood that regions 200, 300, 400 represent single devices or clusters of devices. Additionally, it should be understood that the anti - defect structure 15 can be located at the boundary of any combination of regions 300 and 400 and region 200. And, in each of these different configurations, the anti - defect structure 15 acts as a guard ring located at the boundary of region 200, such that the oxygen diffusion path is blocked, thereby preventing the active channel region 14 of the devices in region 200, such as Si, SiGe, etc., from being corroded during the gate oxide manufacturing process of the devices in regions 300, 400.

[0051] The devices described herein can be utilized in system - on - a - chip (SoC) technology. Those skilled in the art should understand that an SoC is an integrated circuit (also referred to as a “chip”) that integrates all components of an electronic system on a single chip or substrate. Since the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area compared to a multi - chip design with equivalent functionality. Therefore, SoCs are becoming a dominant force in the mobile computing (such as smartphones) and edge - computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0052] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in the form of single-chip packages (e.g., plastic carriers with leads fixed to a motherboard or other higher-level carrier) or multi-chip packages (e.g., ceramic carriers with surface and / or buried interconnections). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with a display, keyboard, or other input device and a central processing unit.

[0053] The description of the various embodiments of the present disclosure has been given for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to a person of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: a semiconductor-on-insulator (SOI) region and a bulk region integrated in a single substrate; at least one active device located in the bulk region; at least one active device located in the SOI region; and a defect prevention structure located at the boundary of the SOI region and at least between the SOI region and the bulk region, wherein the defect prevention structure includes bulk semiconductor material extending within a shallow trench isolation structure.

2. The structure according to claim 1, wherein the bulk semiconductor material extends through the shallow trench isolation structure and reaches the same semiconductor material of the SOI region and the bulk region.

3. The structure according to claim 2, wherein the bulk semiconductor material is bulk Si material.

4. The structure according to claim 1, further comprising a shallow trench isolation structure located between the SOI region and the bulk region.

5. The structure according to claim 1, wherein the defect prevention structure includes an oxidized bird's beak.

6. The structure according to claim 1, wherein the defect prevention structure includes a guard ring surrounding the SOI region.

7. The structure according to claim 1, wherein the defect prevention structure includes a guard ring surrounding the bulk region.

8. The structure according to claim 1, wherein the at least one device in the bulk region includes at least one high-voltage transistor, and the defect prevention structure includes a guard ring surrounding the at least one high-voltage transistor.

9. The structure according to claim 1, wherein the at least one device in the bulk region includes at least one medium-voltage transistor, and the defect prevention structure includes a guard ring surrounding the at least one medium-voltage transistor.

10. The structure according to claim 1, wherein the at least one device in the bulk region includes at least one medium-voltage transistor and at least one high-voltage transistor, and the defect prevention structure includes a guard ring surrounding both the at least one medium-voltage transistor and the at least one high-voltage transistor.

11. A semiconductor structure, comprising: a semiconductor-on-insulator (SOI) region including at least one active SOI device; a bulk region integrated with the SOI region and including at least one active bulk device different from the at least one active SOI device; and a guard ring structure including bulk semiconductor material located at the boundary of the SOI region and at least between the SOI region and the bulk region and configured to prevent oxygen from diffusing into the active channel of the SOI device in the SOI region, wherein the guard ring structure includes bulk semiconductor material extending within a shallow trench isolation structure.

12. The structure according to claim 11, wherein the bulk semiconductor material extends through the shallow trench isolation structure located at the boundary of the SOI region and the bulk region.

13. The structure according to claim 12, wherein the bulk semiconductor material includes bulk Si material.

14. The structure according to claim 13, wherein the guard ring structure includes a bird's beak formed of an oxide.

15. The structure according to claim 11, wherein the guard ring structure surrounds the at least one active SOI device.

16. The structure according to claim 11, wherein the guard ring structure surrounds the at least one active bulk device.

17. The structure according to claim 11, wherein the at least one bulk device includes a high-voltage transistor and a medium-voltage transistor, and the guard ring structure surrounds both the high-voltage transistor and the medium-voltage transistor.

18. The structure according to claim 11, wherein the bulk semiconductor material is positioned and configured to prevent oxygen diffusion through the shallow trench isolation structure to the at least one active SOI device.

19. A method of forming a semiconductor structure, comprising: forming a semiconductor-on-insulator (SOI) region and a bulk region from a single substrate; forming at least one active device in the bulk region; forming at least one active device in the SOI region; and forming a defect-preventing structure located at a boundary of the SOI region and at least between the SOI region and the bulk region, wherein the defect-preventing structure includes bulk semiconductor material extending within a shallow trench isolation structure.

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