Semiconductor devices

Abstract

A semiconductor device capable of improving the conduction performance of a parasitic diode is obtained. A plurality of first control electrodes (8) extend in a first direction when viewed from above, and a plurality of second control electrodes (11) extend in a second direction when viewed from above. The sum of the lengths in the first direction of the boundary lines between the second semiconductor layer (3) and the plurality of third semiconductor layers (4) on the surface of the semiconductor substrate (1) opposite to the plurality of first control electrodes (8) is set as the first gate total width (ΣG1W). The sum of the lengths in the second direction of the boundary lines between the fourth semiconductor layer (5) and the plurality of fifth semiconductor layers (6) on the surface of the semiconductor substrate (1) opposite to the plurality of second control electrodes (11) is set as the second gate total width (ΣG2W). The gate width ratio (ΣG2W / ΣG1W) obtained by dividing the second gate total width (ΣG2W) by the first gate total width (ΣG1W) is greater than or equal to 1.0.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] In the case of an IGBT, an emitter electrode (cathode) is provided on the surface, and a collector electrode (electrode) (anode) is provided on the back surface. A double-sided gate structure IGBT is proposed in which a first gate electrode is provided on the surface and a second gate electrode is also provided on the back surface (for example, refer to Patent Document 1).

[0003] When the second gate electrode is turned off, a signal is applied to the second gate electrode, and a channel connecting the N base layer and the N collector layer is formed near the second gate electrode. In addition, the P base layer and the N base layer function as a PN diode. Thus, a current path from the emitter electrode to the collector electrode is formed, which is composed of the emitter electrode, the P base layer, the N base layer, the back side channel region, the N collector layer, and the collector electrode. Since the excess electrons accumulated in the N base layer are discharged through this path, the turn-off loss can be greatly reduced without sacrificing the on-voltage.

[0004] If the parasitic diode built into the double-gate structure IGBT has a sufficient current-carrying function, it will function in the same manner as a flyback diode connected in reverse parallel to the IGBT. Therefore, the flyback diode can be a small-capacity flyback diode or can be omitted.

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 01-057674

[0006] However, the existing double-sided gate structure IGBT focuses on reducing the cut-off loss of the IGBT, and does not focus on making the function of the parasitic diode fully exerted. Therefore, the current-carrying capacity of the parasitic diode has not been improved. In addition, the higher the withstand voltage, the thicker the thickness of the N base layer needs to be. For example, in the case of a 1000V-level IGBT, the thickness of the N base layer is set to about 120 microns, in the case of a 3000V-level IGBT, it is set to about 350 microns, and in the case of a 6000V-level IGBT, it is set to about 650 microns. Therefore, the higher the withstand voltage, the longer the current path becomes, so the current-carrying performance of the diode is worse. Therefore, it is impossible to set the freewheeling diode connected in reverse parallel to the IGBT to a small-capacity freewheeling diode, nor can the freewheeling diode be omitted. Summary of the invention

[0007] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device capable of improving the current-carrying performance of a parasitic diode.

[0008] The semiconductor device of the present invention is characterized in that it comprises: a semiconductor substrate having a first and a second main surface opposite to each other; a first semiconductor layer of a first conductivity type, which is arranged between the first main surface and the second main surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type, which is arranged between the first semiconductor layer and the first main surface; a plurality of third semiconductor layers of the first conductivity type, which are selectively arranged on the surface of the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is arranged between the first semiconductor layer and the second main surface; a plurality of fifth semiconductor layers of the first conductivity type, which are selectively arranged on the surface of the fourth semiconductor layer; a first main electrode, which is arranged on the first main surface and connected to the second and third semiconductor layers; a second main electrode, which is arranged on the second main surface and connected to the fourth and fifth semiconductor layers; and a plurality of first control electrodes, which respectively control the first semiconductor layer and the fourth semiconductor layer in response to electrical signals. The invention relates to a gate electrode for switching conduction and non-conduction between multiple third semiconductor layers; and a second control electrode, which switches conduction and non-conduction between the first semiconductor layer and the multiple fifth semiconductor layers respectively in response to an electrical signal, the multiple first control electrodes are in the shape of strips extending in the first direction when viewed from above, and the multiple second control electrodes are in the shape of strips extending in the second direction when viewed from above, and the sum of the lengths of the boundary lines between the second semiconductor layer and the multiple third semiconductor layers at the surface of the semiconductor substrate opposite to the multiple first control electrodes in the first direction is set as the first gate total width, and the sum of the lengths of the boundary lines between the fourth semiconductor layer and the multiple fifth semiconductor layers at the surface of the semiconductor substrate opposite to the multiple second control electrodes in the second direction is set as the second gate total width, and the gate width ratio obtained by dividing the second gate total width by the first gate total width is greater than or equal to 1.0.

[0009] Effects of the Invention

[0010] In the present invention, the plurality of first control electrodes extend in the first direction when viewed from above, and the plurality of second control electrodes extend in the second direction when viewed from above. The sum of the lengths in the first direction of the boundary lines between the second semiconductor layer and the plurality of third semiconductor layers at the surface of the semiconductor substrate opposite to the plurality of first control electrodes is set as the first gate total width. The sum of the lengths in the second direction of the boundary lines between the fourth semiconductor layer and the plurality of fifth semiconductor layers at the surface of the semiconductor substrate opposite to the plurality of second control electrodes is set as the second gate total width. The gate width ratio obtained by dividing the second gate total width by the first gate total width is greater than or equal to 1.0. Thus, the conduction performance of the parasitic diode can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0012] Figure 2 This is a plan view of the semiconductor device according to Embodiment 1 as viewed from the emitter side.

[0013] Figure 3 This is a plan view of the semiconductor device according to Embodiment 1 as viewed from the collector side.

[0014] Figure 4 Yes Figure 2 An enlarged plan view of the area enclosed by the dotted line.

[0015] Figure 5 is along Figure 4 A cross-sectional view of the emitter layer and its surrounding area of ​​II′.

[0016] Figure 6 Yes Figure 3 An enlarged plan view of the area enclosed by the dotted line.

[0017] Figure 7 Yes Figure 6 An enlarged plan view of the area enclosed by the dotted line.

[0018] Figure 8 This is a diagram showing simulation results of the relationship between the gate width ratio and the forward voltage drop of the parasitic diode of a double-gate structure IGBT with a withstand voltage of 1 kV class.

[0019] Fig. 9 This is a diagram showing simulation results of the relationship between the gate width ratio and the forward voltage drop of the parasitic diode of a double-gate structure IGBT with a withstand voltage of 3 kV class.

[0020] Fig.10 The diagram shows a typical motor control inverter for inductive (L) load application.

[0021] Fig.11 This is a diagram showing the simulation results of the on-voltage of a double-sided gate IGBT having a trench gate structure on the front and back sides and a withstand voltage of 3 kV class.

[0022] Fig.12 It is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0023] Fig.13 This is a plan view of a portion of the semiconductor device according to Embodiment 2 as viewed from the emitter side.

[0024] Fig.14 This is a plan view of a portion of the semiconductor device according to the second embodiment as viewed from the collector side.

[0025] Fig.15 is along Fig.14 A cross-sectional view of the collector layer and its surrounding area along II-II′.

[0026] Fig.16 This is a plan view of a portion of the semiconductor device according to the third embodiment as viewed from the collector side.

[0027] Fig.17 is along Fig.16 A cross-sectional view of the collector layer and its surroundings along line I-I'. DETAILED DESCRIPTION

[0028] The semiconductor device according to the embodiment will be described with reference to the drawings. The same reference numerals are given to the same or corresponding components, and duplicate description may be omitted.

[0029] Implementation method 1.

[0030] Figure 1 1 is a cross-sectional view showing a semiconductor device according to Embodiment 1. The semiconductor device is a double-sided gate structure IGBT having a trench gate structure on the front side and a planar gate structure on the back side. Figure 1 The horizontal direction is set as the X direction, and the vertical direction is set as the Y direction.

[0031] The semiconductor substrate 1 has a front surface and a back surface facing each other. The N base layer 2 is provided between the front surface and the back surface of the semiconductor substrate 1. The P base layer 3 is provided between the N base layer 2 and the surface of the semiconductor substrate 1. A plurality of N emitter layers 4 are selectively provided on the surface of the P base layer 3. A plurality of P collector layers 5 are provided between the N base layer 2 and the back surface of the semiconductor substrate 1. A plurality of N collector layers 6 are selectively provided on the surface of the P collector layer 5.

[0032] A plurality of trenches 7 are formed on the surface side of the semiconductor substrate 1 so as to penetrate the N emitter layer 4 and the P base layer 3 and reach the N base layer 2. A surface-side gate electrode 8 is formed inside the plurality of trenches 7 via a surface-side gate insulating film 9. The surface-side interlayer film 10 covers the surface-side gate electrode 8. A back-side gate electrode 11 is formed on the back side of the semiconductor substrate 1 via a back-side gate insulating film 12 so as to face the N base layer 2, the P collector layer 5, and the N collector layer 6. The back-side interlayer film 13 covers the back-side gate electrode 11.

[0033] The emitter electrode 14 is provided on the surface of the semiconductor substrate 1 and connected to the P base layer 3 and the N emitter layer 4 . The collector electrode 15 is provided on the back surface of the semiconductor substrate 1 and connected to the P collector layer 5 and the N collector layer 6 .

[0034] The surface area of ​​the semiconductor substrate 1 is divided into a plurality of mesa portions by the grooves 7 of the plurality of surface-side gate electrodes 8. The plurality of mesa portions include: a unit portion including an N emitter layer 4 connected to the emitter electrode 14; and a dummy unit portion not including the N emitter layer 4 connected to the emitter electrode 14 or not including the N emitter layer 4. The unit portion and the dummy unit portion form an emitter-side IGBT region. The interval between adjacent unit portions is referred to as a cell pitch CP. The shortest distance from the P base layer 3 to the P collector layer 5, that is, the thickness Tn of the N base layer 2, determines the withstand voltage performance.

[0035] When an electric signal is applied to the surface side gate electrode 8, a surface side gate channel 16 is formed in a region of the P base layer 3 that faces the surface side gate electrode 8 via the surface side gate insulating film 9. The N emitter layer 4 and the N base layer 2 are conductively connected through the surface side gate channel 16. Therefore, the plurality of surface side gate electrodes 8 respectively switch between conductive and non-conductive states between the N base layer 2 and the plurality of N emitter layers 4 in accordance with the electric signal.

[0036] When an electric signal is applied to the back side gate electrode 11, a back side gate channel 17 is formed in a region of the P collector layer 5 that faces the back side gate electrode 11 via the back side gate insulating film 12. The N collector layer 6 and the N base layer 2 are connected through the back side gate channel 17. Therefore, the back side gate electrode 11 switches between the conduction and non-conduction between the N base layer 2 and the plurality of N collector layers 6 in response to the electric signal.

[0037] Figure 2 This is a plan view of the semiconductor device according to Embodiment 1 as viewed from the emitter side. Figure 2 The extending direction of the surface side gate electrode 8 is set as the Z direction. When viewed from above perpendicular to the surface of the semiconductor substrate 1, the plurality of surface side gate electrodes 8 are strip-shaped and extend in the Z direction, and are arranged in parallel with each other. The surface side gate wiring 18 is connected to the surface side gate electrode 8. The surface side gate wiring 18 is connected to the surface side gate electrode pad 19. In order to maintain the withstand voltage characteristics, a peripheral electrode 20 and an N + The peripheral area of ​​the layer 21. The peripheral area is covered by a peripheral protective film.

[0038] Figure 3 This is a plan view of the semiconductor device according to Embodiment 1 as viewed from the collector side. The plurality of back-side gate electrodes 11 are strip-shaped and extend in the Z direction when viewed from above perpendicular to the back surface of the semiconductor substrate 1, and are arranged in parallel with each other. The back-side gate wiring 22 is connected to the back-side gate electrode 11. The back-side gate wiring 22 is connected to the back-side gate electrode pad 23. The back-side gate wiring 22 and a portion of the back-side gate electrode pad 23 are covered by a protective film 24.

[0039] The front side gate insulating film 9 and the back side gate insulating film 12 are usually made of SiO 2 The surface side gate electrode 8 and the back side gate electrode 11 are composed of polysilicon doped with N-type impurities. The surface side interlayer film 10 and the back side interlayer film 13 are composed of silicate glass (BPSG) containing boron and phosphorus. The emitter electrode 14, the collector electrode 15, the surface side gate wiring 18, the surface side gate electrode pad 19, the collector electrode 15, the back side gate wiring 22 and the back side gate electrode pad 23 are composed of aluminum containing silicon.

[0040] Figure 4 Yes Figure 2 An enlarged plan view of the area enclosed by the dotted line. Figure 5 is along Figure 4 1 is a cross-sectional view of the emitter layer and the vicinity of II′. The emitter electrode 14 and the surface-side interlayer film 10 are omitted. The length G1W in the Z direction of the boundary line between the P base layer 3 and the N emitter layer 4 at the surface (YZ plane) of the semiconductor substrate 1 opposite to the surface-side gate electrode 8 is the width of the surface-side gate channel 16. The sum of the lengths G1W of the plurality of N emitter layers 4 is set to the first gate total width ΣG1W.

[0041] Figure 6 Yes Figure 3 An enlarged plan view of the area enclosed by the dotted line. Figure 7 Yes Figure 6 An enlarged plan view of the area enclosed by the dotted line. Figure 1 Along with Figure 4 and Figure 6 The back side gate electrode 11, the back side gate insulating film 12, the back side interlayer film 13, and the collector electrode 15 are omitted. The length G2W in the Z direction of the boundary line between the P collector layer 5 and the N collector layer 6 at the surface (XZ plane) of the semiconductor substrate 1 opposite to the back side gate electrode 11 is the width of the back side gate channel 17. The sum of the lengths G2W of the plurality of N collector layers 6 is set to the second gate total width ΣG2W.

[0042] In this embodiment, the gate width ratio (ΣG2W / ΣG1W) obtained by dividing the second gate total width ΣG2W by the first gate total width ΣG1W is designed to be greater than or equal to 1.0. The upper limit of the gate width ratio (ΣG2W / ΣG1W) is about 10.

[0043] The rated withstand voltage of the gates on the front and back sides is the same as that of the gate of a scaling IGBT with a scaling factor (k) of 3, which is ±7 V. The threshold voltage of the gates on the front and back sides is also the same as that of the scaling IGBT, which is about +1.7 V. In order to make the gate channel low-resistance and operate stably, the gate voltage applied to the gates on the front and back sides is also about 3 times the threshold voltage, that is, +5 V, which is the same as the gate voltage of the scaling IGBT.

[0044] Table 1 shows the voltage blocking and current conduction states of the operation of such a double-sided gate structure IGBT. A collector voltage that is positive or negative relative to the ground potential of the emitter electrode 14 is applied. A gate voltage that is positive relative to the ground potential of the emitter electrode 14 is applied to the surface side gate electrode 8. A gate voltage that is positive relative to the potential of the collector electrode 15 is applied to the back side gate electrode 11. The operation state is any of voltage blocking, forward current conduction, and reverse current conduction, and does not include the state of leakage current and the breakdown state of the junction. In the case of voltage blocking, no current flows from the collector electrode 15 to the emitter electrode 14. In the case of forward current conduction, current flows from the collector electrode 15 to the emitter electrode 14. In the case of reverse current conduction, current flows from the emitter electrode 14 to the collector electrode 15.

[0045] [Table 1]

[0046]

[0047] Next, the on-off operation is described. First, the collector voltage V CE The on state (operation mode 2 in Table 1) in which a large current flows from the collector electrode 15 to the emitter electrode 14 is described. A predetermined collector voltage V is applied between the emitter electrode 14 and the collector electrode 15. CE No gate voltage is applied between the collector electrode 15 and the back side gate electrode 11, or a negative voltage (reverse bias) is applied to the back side gate electrode 11 relative to the collector electrode 15. A positive voltage (forward bias) V is applied to the surface side gate electrode 8 relative to the emitter electrode 14. G1E. In this case, the area near the surface-side gate electrode 8 of the P base layer 3 is inverted to N type to form a first surface-side gate channel 16. A current path is formed in the N emitter layer 4, the surface-side gate channel 16, and the N base layer 2. Electrons with negative charge are injected from the emitter electrode 14 to the N base layer 2 through this path. Due to the injected electrons, the N base layer 2 is charged with negative polarity, and the PN junction formed by the P collector layer 5 and the N base layer 2 is forward biased. As a result, holes with positive charge are injected from the collector electrode 15 through the P collector layer 5 into the N base layer 2. As a result, the density of holes existing in the N base layer 2 increases, causing conductivity modulation, and the resistance component of the N base layer 2 is greatly reduced. Therefore, by a low collector voltage V CE , a large collector current also flows from the collector electrode 15 to the emitter electrode 14. At this time, the voltage drop between the collector and the emitter of the double-sided gate structure IGBT is the on-state voltage V CEsat .

[0048] Next, the cut-off switching action of the double-sided gate structure IGBT from the on state to the off state is described. A zero potential or a negative potential is applied to the surface side gate electrode 8, and the application of a positive voltage relative to the emitter electrode 14 is stopped. As a result, the region of the P base layer 3 that is inverted to the N type and located near the surface side gate electrode 8 is restored to the P type. Since the first N channel disappears, the flow path of electrons from the N emitter layer 4 to the N base layer 2 disappears. Therefore, the injection of electrons from the emitter electrode 14 to the N base layer 2 stops, the forward bias of the PN junction formed by the P collector layer 5 and the N base layer 2 is eliminated, and the injection of holes from the collector electrode 15 via the P collector layer 5 to the N base layer 2 stops. The conductivity modulation of the N base layer 2 is eliminated, and the resistance of the N base layer 2 returns to the state before the conductivity modulation occurs. The PN junction formed by the P base layer 3 and the N base layer 2 is depleted and shows voltage blocking characteristics. As a result, the state changes to an OFF state (voltage blocking) in which no current flows from the collector electrode 15 to the emitter electrode 14 .

[0049] In the off switching operation, immediately before or substantially simultaneously with the stopping of the application of the positive voltage to the emitter electrode 14 to the front side gate electrode 8, a positive voltage V is applied to the collector electrode 15 to the back side gate electrode 11. G2C. As a result, the area near the back side gate electrode 11 is inverted to N type to form the back side gate channel 17. A current path consisting of the N base layer 2, the back side gate channel 17, and the N collector layer 6 is formed. Through this path, electrons are discharged from the N base layer 2 to the collector electrode 15, and thus the electron density of the N base layer 2 begins to decrease. The decrease in the electron density weakens the forward bias of the PN junction formed by the P collector layer 5 and the N base layer 2, and reduces the hole injection from the P collector layer 5 to the N base layer 2. In this condition, if the positive gate voltage V applied to the surface side gate electrode 8 is G1E When switched to zero volt or reverse bias, the surface gate channel 16 that has reversed to N type returns to P type, and the electron injection from the emitter electrode 14 stops. The electrons accumulated in the N base layer 2 are discharged to the collector electrode 15 through the back side gate channel 17 and the N collector layer 6. The holes accumulated in the N base layer 2 are discharged to the emitter electrode 14 through the P base layer 3. Due to the depletion layer electric field generated by the PN junction composed of the P base layer 3 and the N base layer 2 being depleted, the electrons accumulated in the N base layer 2 are quickly discharged to the collector electrode 15, and the holes are quickly discharged to the emitter electrode 14.

[0050] Immediately before stopping the application of the positive voltage with respect to the emitter electrode 14 to the front side gate electrode 8, a positive voltage V with respect to the collector electrode 15 is applied to the back side gate electrode 11. G2C As a result, the electron accumulation in the N base layer 2 is reduced, and the hole density is also reduced to satisfy the charge neutrality. Therefore, the time until the excess charge accumulated in the N base layer 2 disappears is shortened, and the loss of switching on and off is also reduced.

[0051] Figure 8 This is a graph showing the simulation results of the relationship between the gate width ratio and the forward voltage drop of the parasitic diode of a double-gate structure IGBT with a withstand voltage of 1kV. The horizontal axis is the gate width ratio (ΣG2W / ΣG1W). The vertical axis is the forward voltage drop of the parasitic diode @150A / cm 2 Relative value. Scaling design technology is applied to the surface side gate structure. The distance from the P collector layer 5 to the P base layer 3, that is, the thickness of the N base layer 2 is set to 115 microns. The cell pitch CP is set to 12 microns. The depth of the surface side groove 7 is set to 2.5 microns. The gate rated voltage of the surface side gate and the back side gate is set to ±7V, and the threshold voltage is set to 1.6V to 1.8V. 0V is applied to the surface side gate electrode 8, and 5V is applied to the back side gate electrode 11. The temperature is 150°C, which is the rated temperature of a normal IGBT. The flowing current is converted into current density, eliminating the cause of the size of the double-sided gate structure IGBT.

[0052] It is known that if the gate width ratio (ΣG2W / ΣG1W) is less than 1.0, the forward voltage drop of the parasitic diode exceeds the level of error and increases significantly, and the current carrying capacity of the diode decreases. Here, if the gate width ratio is small, the gate width G2W of the back side gate electrode 11 that becomes the current path becomes narrower, and the back side gate channel 17 becomes narrower. Therefore, the resistance of the back side gate channel 17 increases, and the forward voltage drop of the parasitic diode increases sharply.

[0053] Fig. 9 This is a graph showing the simulation results of the relationship between the gate width ratio and the forward voltage drop of the parasitic diode of a double-gate structure IGBT with a withstand voltage of 3kV. The horizontal axis is the gate width ratio (ΣG2W / ΣG1W). The vertical axis is the forward voltage drop of the parasitic diode @50A / cm 2 Relative value. The thickness of the N base layer 2, which is the distance from the P collector layer 5 to the P base layer 3, is set to 350 microns. The cell pitch CP is set to 12 microns. The depth of the surface side groove 7 is set to 6 microns. The thickness of the surface side gate insulating film 9 and the back side gate insulating film 12 is set thick, the gate rated voltage of the surface side gate and the back side gate is set to ±20V, and the threshold voltage is set to +5V to +6V. The applied voltage for driving is +15V. 0V is applied to the surface side gate electrode 8, and 15V is applied to the back side gate electrode 11. The temperature is 150°C, which is the rated temperature of a normal IGBT. The flowing current is converted into current density, eliminating the cause of the size of the double-sided gate structure IGBT.

[0054] It is known that if the gate width ratio (ΣG2W / ΣG1W) is less than 1.0, the forward voltage drop of the parasitic diode exceeds the level of error and increases significantly, similar to the 1kV-class double-sided gate structure IGBT, and the current carrying capacity of the diode decreases. Therefore, it is confirmed that even in a double-sided gate structure IGBT with different ratings and characteristics, the current carrying capacity of the parasitic diode can be improved by setting the gate width ratio (ΣG2W / ΣG1W) to be greater than or equal to 1.0.

[0055] As described above, the present embodiment is a double-sided gate structure IGBT, that is, the structure design of the emitter side IGBT region for realizing the low on-voltage of the IGBT is maintained, and a back side gate electrode 11 is provided for reducing the turn-off loss. In addition, by setting the first gate total width ΣG1W on the front side to be the same as that of the existing double-sided gate structure IGBT and adjusting the second gate total width ΣG2W on the back side, the gate width ratio (ΣG2W / ΣG1W) is designed to be greater than or equal to 1.0. As a result, the current carrying capacity of the reverse parasitic diode built into the IGBT can be improved.

[0056] Fig.10This is a diagram showing a motor control inverter as a representative of inductive (L) load applications. Two IGBT units 26 are connected in series to form a bridge arm in each of the three phases of the DC-AC inverter that drives the motor 25. Each IGBT unit 26 has an IGBT 27 and a freewheeling diode 28 (FWD: Free Wheeling Diode) connected in reverse parallel to the IGBT 27.

[0057] The driving power is supplied to the motor 25 from the series connection part of the IGBT unit 26. The IGBT 27 whose cathode is connected to the series connection part is called the P-side (high potential side) IGBT. The IGBT 27 whose anode is connected to the series connection part is called the N-side (low potential side) IGBT. The P-side IGBT and the N-side IGBT connected in series to form the bridge arm are controlled in such a way that they do not become turned on at the same time (bridge arm short circuit). As for the IGBT 27 constituting the bridge arm, the ON / OFF time width is adjusted and controlled while repeating ON / OFF to supply driving power to the motor. Due to the current flowing through the IGBT 27, energy is accumulated in the L load. When the IGBT 27 is turned off, the FWD flows a reverse current (reverse current in the IGBT 27 but forward current in the FWD) and consumes energy.

[0058] The IGBT 27 of the inverter applies the double-sided gate structure IGBT involved in this embodiment. In the double-sided gate structure IGBT, by turning on the back side gate, the N base layer 2 and the collector electrode 15 can be turned on, and the conduction of the N base layer 2 and the collector electrode 15 can make the PN junction formed by the P base layer 3 and the N base layer 2 function as a diode. By turning on the back side gate and turning on the surface side gate to make the N base layer 2 and the emitter electrode 14 conductive, the emitter electrode 14 and the collector electrode 15 can be turned on and a reverse current can flow. Therefore, by controlling the back side gate, the double-sided gate structure IGBT can also have a function of built-in FWD. Therefore, the freewheeling diode 28 can be set to a small-capacity freewheeling diode or the freewheeling diode can be omitted. As a result, a significant miniaturization of the inverter can be achieved.

[0059] In addition, in the present embodiment, the back side gate electrode 11 has a planar gate structure, so that the trench forming step can be omitted, and thus the manufacturing becomes easy and the productivity is improved.

[0060] In addition, the thickness Tn of the N base layer 2 and the cell pitch CP have an optimal relationship in the scaled IGBT. Fig.11This is a diagram showing the simulation results of the on-voltage of a double-sided gate structure IGBT with a trench gate structure on the surface and back sides and a withstand voltage of 3kV level. The horizontal axis is the ratio of the cell pitch CP to Tn, CP / Tn. The vertical axis is the on-voltage after normalization with the minimum value set to 1. The gate width ratio (ΣG2W / ΣG1W) is set to 1.0. The rated gate voltage of the surface side gate and the back side gate is set to ±20V, and the threshold voltage is set to 5V to 6V. 15V is applied to the surface side gate electrode 8, and 0V is applied to the back side gate electrode 11. The temperature is 150°C, which is the rated temperature of a normal IGBT. As a result of the simulation, it can be seen that in the area where CP / Tn is 1 / 40 to 1 / 20, the change in the on-voltage is small and converges to within plus 1.0% of the error level. Therefore, in this embodiment, CP / Tn is designed within the range of 1 / 40 to 1 / 20. In this way, the on-voltage of the IGBT can be reduced by defining the cell pitch on the surface side by the thickness of the N base layer 2 .

[0061] Implementation method 2.

[0062] Fig.12 It is a cross-sectional view showing a semiconductor device according to the second embodiment. Fig.13 This is a plan view of a portion of the semiconductor device according to Embodiment 2, viewed from the emitter side. The emitter electrode 14 and the surface-side interlayer film 10 are omitted. Fig.14 This is a plan view of a portion of the semiconductor device according to Embodiment 2 viewed from the collector side. The collector electrode 15 and the back-side interlayer film 13 are omitted. Fig.12 Along with Fig.13 and Fig.14 II′ corresponds to the cross-sectional view. Fig.15 is along Fig.14 A cross-sectional view of the collector layer and its surrounding area along II-II′.

[0063] The structure of the emitter side of this embodiment is the same as that of Embodiment 1, but the structure of the collector side is different. A plurality of grooves 29 are formed on the back side of the semiconductor substrate 1 in such a manner that the N collector layer 6 and the P collector layer 5 are penetrated and reach the N base layer 2. A back side gate electrode 11 is formed inside the plurality of grooves 29 via a back side gate insulating film 12. A back side interlayer film 13 covers the back side gate electrode 11.

[0064] In this way, since the back side gate electrode 11 is a trench gate structure, the pitch of the back side gate electrode 11 can be designed to be about 6 microns. Therefore, compared with a planar gate structure with a pitch of about 12 microns, the interval between the back side gate electrodes 11 can be designed to be narrow and the back side gate electrodes 11 can be arranged at a high density.

[0065] In addition, in order to improve the on-voltage of the IGBT, the electron injection enhancement effect is usually used. Therefore, the surface-side gate electrode 8 cannot reduce the cell pitch using a groove structure. As for the groove 7, since it is required to be formed at as uniform an interval as possible, a dummy cell portion that does not have an N emitter layer 4 and is not connected to the emitter electrode 14 is provided to increase the cell pitch. On the other hand, since there is no such restriction on the back-side gate electrode 11, the N collector layer 6 can be configured on all the terraces between the grooves 29.

[0066] Therefore, since the back side gate electrode 11 is a trench gate structure, the total width ΣG2W of the second gate on the back side can be set large. Therefore, it is easy to make the gate width ratio (ΣG2W / ΣG1W) greater than or equal to 1.0. Therefore, the conduction performance of the parasitic diode can be improved and the forward voltage drop of the parasitic diode can be reduced.

[0067] Implementation method 3.

[0068] Fig.16 This is a plan view of a portion of the semiconductor device according to Embodiment 3 as viewed from the collector side. The collector electrode 15 and the back-side interlayer film 13 are omitted. Fig.17 is along Fig.16 The structure of the emitter side of this embodiment is the same as that of the first embodiment, and the length direction of the surface side gate electrode 8 is the Z-axis direction. On the other hand, the length direction of the back side gate electrode 11 is the X-axis direction, which is different from the length direction of the surface side gate electrode 8.

[0069] Here, in the case where the surface-side gate electrode 8 is a trench gate structure, there is no JFET resistance region in the electron injection path from the N emitter layer 4 to the N base layer 2. The resistance of the injection path is reduced, and accordingly, the electron injection into the N base layer 2 increases. As a result, the amount of electrons accumulated in the N base layer 2 increases and the amount of electrons becomes uneven. In addition, since the overlapping and non-overlapping parts of the surface-side gate electrode 8 for injecting electrons and the back-side gate electrode 11 for discharging electrons appear locally, sometimes in the transient operation of turning off and on, the distribution of electrons in the N base layer 2 will produce uneven growth, resulting in current concentration and damage.

[0070] In contrast, in the present embodiment, the extension direction of the back side gate electrode 11 is different from the extension direction of the surface side gate electrode 8. As a result, the situation where the portion where electrons are easily accumulated by the surface side gate electrode 8 and the portion away from the back side gate electrode 11 where the electrons are discharged slowly is locally repeated is eliminated. Therefore, the uniformity of the operation can be improved in transient operations such as switching on and off. In addition, it is preferred that the extension direction of the back side gate electrode 11 is orthogonal to the extension direction of the surface side gate electrode 8. As a result, the in-plane fluctuation of the performance of the IGBT unit area becomes smaller.

[0071] In addition, the semiconductor substrate 1 is not limited to being formed by silicon, and can also be formed by a wide bandgap semiconductor having a larger bandgap than silicon. Wide bandgap semiconductors are, for example, silicon carbide, gallium nitride-based materials, or diamond. As for semiconductor devices formed by such wide bandgap semiconductors, they can be miniaturized due to their high voltage resistance and allowable current density. By using the miniaturized semiconductor device, a semiconductor module assembled with the semiconductor device can also be miniaturized and highly integrated. In addition, since the semiconductor device has high heat resistance, the heat dissipation fins of the radiator can be miniaturized, and the water cooling part can be air-cooled, so the semiconductor module can be further miniaturized. In addition, since the semiconductor device has low power loss and high efficiency, the semiconductor module can be made efficient.

[0072] The technical concept of the present invention is not limited to the above-mentioned embodiment, and it is needless to say that the present invention can be changed to a double-sided gate structure IGBT in which the surface side gate structure is a planar gate structure, a CIGBT (Clustered IGBT) having the same function as the IGBT, etc. without departing from the gist of the present invention.

[0073] Description of the label

[0074] 1 semiconductor substrate, 2N base layer (first semiconductor layer), 3P base layer (second semiconductor layer), 4N emitter layer (third semiconductor layer), 5P collector layer (fourth semiconductor layer), 6N collector layer (fifth semiconductor layer), 8 surface side gate electrode (first control electrode), 11 back side gate electrode (second control electrode), 14 emitter electrode (first main electrode), 15 collector electrode (second main electrode)

Claims

1. A semiconductor device, It is characterized in that have: A semiconductor substrate having first and second main surfaces facing each other; A first semiconductor layer of a first conductivity type, which is disposed between the first main surface and the second main surface of the semiconductor substrate; A second semiconductor layer of a second conductivity type, disposed between the first semiconductor layer and the first main surface; A plurality of third semiconductor layers of the first conductivity type, which are selectively disposed on the surface of the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, disposed between the first semiconductor layer and the second main surface; A plurality of fifth semiconductor layers of the first conductivity type, which are selectively disposed on the surface of the fourth semiconductor layer; A first main electrode, which is disposed on the first main surface and connected to the second and third semiconductor layers; A second main electrode, which is disposed on the second main surface and connected to the fourth and fifth semiconductor layers; a plurality of first control electrodes, which respectively switch the conduction and non-conduction between the first semiconductor layer and the plurality of third semiconductor layers in response to electrical signals; as well as a plurality of second control electrodes, which respectively switch the conduction and non-conduction between the first semiconductor layer and the plurality of fifth semiconductor layers in response to electrical signals, The plurality of first control electrodes are strip-shaped extending in the first direction when viewed from above, The plurality of second control electrodes are strip-shaped extending in the second direction when viewed from above, The sum of the lengths of the boundary lines between the second semiconductor layer and the third semiconductor layers at the surface of the semiconductor substrate opposite to the first control electrodes in the first direction is set as a first gate total width, The sum of the lengths of the boundary lines between the fourth semiconductor layer and the fifth semiconductor layers at the surface of the semiconductor substrate opposite to the second control electrodes in the second direction is set as the second gate total width, A gate width ratio obtained by dividing the second gate total width by the first gate total width is greater than or equal to 1.0, The plurality of first control electrodes are of trench gate structure, The region on the first main surface side of the semiconductor substrate is divided into a plurality of mesa portions by the grooves of the plurality of first control electrodes. The plurality of mesa portions include: a unit portion including the third semiconductor layer connected to the first main electrode; and a dummy unit portion not including the third semiconductor layer connected to the first main electrode or not including the third semiconductor layer, The interval between the adjacent unit portions is one fortieth to one twentieth of the shortest distance from the second semiconductor layer to the fourth semiconductor layer.

2. The semiconductor device according to claim 1, It is characterized in that The second control electrode is a planar gate structure.

3. The semiconductor device according to claim 1, It is characterized in that The second control electrode has a trench gate structure.

4. The semiconductor device according to any one of claims 1 to 3, It is characterized in that The first control electrode is a trench gate structure, The second direction is different from the first direction.

5. The semiconductor device according to claim 4, It is characterized in that The second direction is orthogonal to the first direction.

6. The semiconductor device according to any one of claims 1 to 3, It is characterized in that The semiconductor substrate is formed of a wide bandgap semiconductor.

7. The semiconductor device according to claim 4, It is characterized in that The semiconductor substrate is formed of a wide bandgap semiconductor.

8. The semiconductor device according to claim 5, It is characterized in that The semiconductor substrate is formed of a wide bandgap semiconductor.

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