Tunneling field effect transistor and method of forming the same

Abstract

The application provides a tunnel field effect transistor and a forming method thereof. The tunnel field effect transistor comprises a semiconductor substrate, a metal gate structure located on the surface of the semiconductor substrate, a side wall located on the side wall of the metal gate structure, a source and a drain respectively located in the semiconductor substrate on both sides of the metal gate structure, and a heavily doped region located in the semiconductor substrate below the channel of the tunnel field effect transistor. The doping type of the heavily doped region is the same as that of the source, and the doping concentration of the heavily doped region is higher than that of the source. The tunnel field effect transistor and the forming method thereof can significantly improve the driving current of the tunnel field effect transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a tunneling field-effect transistor and a method for forming the same. Background Technology

[0002] Tunnel field-effect transistors (TFETs) have excellent subthreshold characteristics and their operating voltage is significantly lower than that of complementary metal-oxide-semiconductor (CMOS), making them suitable for ultra-low leakage current and ultra-low power consumption applications.

[0003] Traditional TFET devices have low drive current, which depends on the band-to-band tunneling probability and the area of ​​the tunneling region. Traditional TFET tunneling only occurs at the junction between the p-type doped region and the substrate region, and is limited to a small area that can be controlled by the gate electric field. Summary of the Invention

[0004] The technical problem addressed by this application is the low drive current of existing TFET devices.

[0005] To address the aforementioned technical problems, this application provides a tunneling field-effect transistor, comprising: a semiconductor substrate; a metal gate structure located on the surface of the semiconductor substrate; sidewalls located on the sidewalls of the metal gate structure; a source and a drain located on opposite sides of the metal gate structure in the semiconductor substrate; and a heavily doped region located in the semiconductor substrate below the channel of the tunneling field-effect transistor, wherein the doping type of the heavily doped region is the same as that of the source, and the doping concentration of the heavily doped region is higher than that of the source.

[0006] In this embodiment, the surface of the heavily doped region is lower than the top surfaces of the source and the drain, and the heavily doped region is adjacent to the source but does not contact the drain.

[0007] In this embodiment, the height difference between the surface of the heavily doped region and the top surfaces of the source and drain electrodes is 5 nm to 100 nm.

[0008] In this embodiment, the absolute value of the depth difference between the bottom surface of the heavily doped region and the bottom surface of the source and drain electrodes does not exceed 50 nm.

[0009] In this embodiment, the width of the heavily doped region is greater than the depth of the source electrode and less than the width of the metal gate structure.

[0010] In this embodiment, the width difference between the heavily doped region and the metal gate structure is 20 nm to 100 nm.

[0011] In this embodiment, the semiconductor substrate includes an epitaxial layer located between the metal gate structure and the heavily doped region, and connecting the source and the drain, serving as the channel of the tunnel field-effect transistor.

[0012] In this embodiment of the application, the tunneling field-effect transistor further includes an interlayer dielectric layer, which is located on the sidewall of the sidewall and covers the surfaces of the source and the drain.

[0013] In this embodiment, the tunneling field-effect transistor further includes: an intermetallic dielectric layer located on the surface of the intermetallic dielectric layer and the metal gate structure; a metal silicide layer located in the intermetallic dielectric layer and covering a portion of the surface of the source and the drain; and a conductive layer located on the surface of the metal silicide layer, wherein the top surfaces of the conductive layer and the intermetallic dielectric layer are coplanar.

[0014] This application also provides a method for forming a tunnel field-effect transistor, comprising: providing a semiconductor substrate, wherein a dummy gate structure is formed on the surface of the semiconductor substrate, sidewalls are formed on the sidewalls of the dummy gate structure, and a source and a drain are formed in the semiconductor substrate on both sides of the dummy gate structure, respectively; forming an interlayer dielectric layer on the surface of the semiconductor substrate on both sides of the sidewalls; removing the dummy gate structure to expose the surface of the semiconductor substrate; etching a portion of the semiconductor substrate in the channel region of the tunnel field-effect transistor until the surface of the semiconductor substrate is lower than the top surfaces of the source and the drain; and etching the semiconductor substrate in the tunnel field-effect transistor. A heavily doped region is formed in the substrate. The doping type of the heavily doped region is the same as that of the source electrode, and the doping concentration of the heavily doped region is higher than that of the source electrode. The heavily doped region is adjacent to the source electrode but does not contact the drain electrode. An epitaxial layer is grown on the surface of the heavily doped region and on the exposed surface of the semiconductor substrate. The surface of the epitaxial layer is coplanar with the top surfaces of the source electrode and the drain electrode. The epitaxial layer is the channel of the tunnel field-effect transistor. A metal gate structure is formed on the surface of the epitaxial layer, and the surface of the metal gate structure is coplanar with the top surface of the interlayer dielectric layer.

[0015] In this embodiment of the application, after etching the semiconductor substrate, the height difference between the surface of the semiconductor substrate and the top surfaces of the source and drain electrodes is 5nm to 100nm.

[0016] In this embodiment, the heavily doped region is formed using a tilted ion implantation process.

[0017] In this embodiment, the ion implantation direction is towards the source electrode, the incident angle of the ion implantation is 7° to 60°, and the ion implantation energy is 5keV to 50keV.

[0018] In this embodiment, the absolute value of the depth difference between the bottom surface of the heavily doped region and the bottom surface of the source and drain electrodes does not exceed 50 nm.

[0019] In this embodiment, the width of the heavily doped region is greater than the depth of the source electrode and less than the width of the metal gate structure.

[0020] In this embodiment, the width difference between the heavily doped region and the metal gate structure is 20 nm to 100 nm.

[0021] In this embodiment, the epitaxial layer is formed using a selective epitaxial growth process, and the temperature of the selective epitaxial growth process does not exceed 700°C.

[0022] In this embodiment, the epitaxial layer is made of the same material as the semiconductor substrate.

[0023] In this embodiment of the application, after forming the metal gate structure, the method further includes: forming an intermetallic dielectric layer on the surface of the interlayer dielectric layer and the metal gate structure; etching the intermetallic dielectric layer and the interlayer dielectric layer to expose a portion of the source and drain surfaces to form a contact hole; forming a metal silicide layer on the bottom surface of the contact hole; and forming a conductive layer on the surface of the metal silicide layer, wherein the top surfaces of the conductive layer and the intermetallic dielectric layer are coplanar.

[0024] The tunneling field-effect transistor and its formation method disclosed in this application form a heavily doped region in a semiconductor substrate below the tunneling field-effect transistor channel. The doping type of the heavily doped region is the same as that of the source electrode, and the doping concentration of the heavily doped region is higher than that of the source electrode. This improves the conventional vertical tunneling junction surface to a horizontal tunneling junction surface, thereby increasing the area of ​​the tunneling region and significantly improving the driving current of the tunneling field-effect transistor. Attached Figure Description

[0025] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0026] Figure 1 This is a schematic diagram of the structure of a tunneling field-effect transistor;

[0027] Figure 2 This is a schematic flowchart illustrating a method for forming a tunneling field-effect transistor according to an embodiment of this application.

[0028] Figures 3 to 11 This is a schematic diagram of the structure corresponding to each step of the method for forming a tunnel field-effect transistor according to an embodiment of this application. Detailed Implementation

[0029] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0030] refer to Figure 1 A tunneling field-effect transistor includes a semiconductor substrate 10, on the surface of which a metal gate structure 13 is formed. A source electrode 11 and a drain electrode 12 are formed in the semiconductor substrate 10 on both sides of the metal gate structure 13, respectively. The tunneling junction A between the source electrode 11 and the semiconductor substrate 10 is the main site for tunneling. Since the area of ​​the tunneling junction A is small, the driving current of the tunneling field-effect transistor is small.

[0031] In view of this, the technical solution of this application adds a heavily doped region in the semiconductor substrate below the tunnel field-effect transistor channel, so that the doping type of the heavily doped region is the same as the doping type of the source, and the doping concentration of the heavily doped region is higher than that of the source, thereby changing the vertical tunnel junction surface to a horizontal tunnel junction surface, thereby increasing the area of ​​the tunneling region and effectively improving the driving current of the tunnel field-effect transistor.

[0032] The technical solution of this application will be described in detail below with reference to the embodiments and accompanying drawings.

[0033] refer to Figure 2 The method for forming a tunneling field-effect transistor according to an embodiment of this application includes:

[0034] Step S1: Provide a semiconductor substrate, on the surface of which a dummy gate structure is formed, the sidewalls of which are formed, and the source and drain electrodes are formed in the semiconductor substrate on both sides of the dummy gate structure, respectively.

[0035] Step S2: Form an interlayer dielectric layer on the surface of the semiconductor substrate on both sides of the sidewall;

[0036] Step S3: Remove the dummy gate structure to expose the surface of the semiconductor substrate;

[0037] Step S4: Etch a portion of the semiconductor substrate in the channel region of the tunnel field-effect transistor until the surface of the semiconductor substrate is lower than the top surfaces of the source and the drain.

[0038] Step S5: A heavily doped region is formed in the semiconductor substrate. The doping type of the heavily doped region is the same as that of the source electrode, and the doping concentration of the heavily doped region is higher than that of the source electrode. The heavily doped region is adjacent to the source electrode but does not contact the drain electrode.

[0039] Step S6: An epitaxial layer is grown on the surface of the heavily doped region and the exposed semiconductor substrate surface. The surface of the epitaxial layer is coplanar with the top surfaces of the source and the drain. The epitaxial layer is the channel of the tunnel field-effect transistor.

[0040] Step S7: A metal gate structure is formed on the surface of the epitaxial layer, and the surface of the metal gate structure is coplanar with the top surface of the interlayer dielectric layer.

[0041] refer to Figure 2 and Figure 3 A semiconductor substrate 100 is provided. The material of the semiconductor substrate 100 may be (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above. Furthermore, the semiconductor substrate 100 may be doped (e.g., a P-type semiconductor substrate or an N-type semiconductor substrate). In some embodiments of this application, the semiconductor substrate 100 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic). When the tunneling field-effect transistor is N-type, the semiconductor substrate 100 may be intrinsically doped or weakly N-type doped; when the tunneling field-effect transistor is P-type, the semiconductor substrate 100 may be intrinsically doped or weakly P-type doped.

[0042] A dummy gate structure 110 is formed on the surface of the semiconductor substrate 100. The dummy gate structure 110 can be a single-layer structure or a multilayer structure. In this embodiment, the dummy gate structure 110 includes a dummy gate dielectric layer and a dummy gate layer located on the surface of the dummy gate dielectric layer. The dummy gate dielectric layer can be a single-layer structure or a multilayer structure. The material of the dummy gate dielectric layer can include oxide materials, such as silicon oxide. The material of the dummy gate layer can include polysilicon. The process of forming the dummy gate structure 110 can include: sequentially depositing the dummy gate dielectric layer and the dummy gate layer on the surface of the semiconductor substrate 100 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition; forming a patterned hard mask (not shown) on the surface of the dummy gate layer; etching the dummy gate dielectric layer and the dummy gate layer using dry etching, wet etching, or a combination thereof to form the dummy gate structure 110. The patterned mask layer can be removed or left on the surface of the dummy gate layer of the dummy gate structure 110 to protect the dummy gate layer in subsequent processes.

[0043] The dummy gate structure 110 also has sidewalls 120 formed on its sidewalls. The method for forming the sidewalls 120 may include: depositing sidewall material on the sidewalls and surface of the dummy gate structure 110 and on the surface of the semiconductor substrates 100 on both sides of the dummy gate structure 110 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes; etching the sidewall material to leave only the sidewall material of the dummy gate structure sidewalls, thus forming the sidewalls 120. The sidewall material is one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The sidewalls 120 can be a single-layer structure or a multilayer structure, and during subsequent ion implantation to form the source and drain electrodes, the sidewalls 120 can protect the dummy gate structure 110 from being affected.

[0044] refer to Figure 4 A source electrode 130 and a drain electrode 140 are formed in the semiconductor substrates 100 on both sides of the dummy gate structure 110, respectively. The formation steps of the source electrode 130 and the drain electrode 140 may include doping the semiconductor substrates 100 on both sides of the dummy gate structure 110 with different types of dopant ions to form the source electrode 130 and the drain electrode 140. When the formed transistor is a P-type tunneling field-effect transistor, the source electrode 130 is doped with N-type ions, and the drain electrode 140 is doped with P-type ions; when the formed transistor is an N-type tunneling field-effect transistor, the source electrode 130 is doped with P-type ions, and the drain electrode 140 is doped with N-type ions. In some embodiments, the doping process may be an ion implantation process or an in-situ doping process.

[0045] refer to Figure 5An interlayer dielectric layer 150 is formed on the surface of the semiconductor substrate 100 on both sides of the sidewall 120. The process steps for forming the interlayer dielectric layer 150 may include: depositing an interlayer dielectric layer material on the surface of the semiconductor substrate 100 on both sides of the sidewall 120 and on the surface of the gate structure 110. The process for depositing the interlayer dielectric layer material may be atomic layer deposition, low-pressure chemical vapor deposition, or plasma-enhanced chemical vapor deposition. The deposited interlayer dielectric layer material may be a single layer or a multilayer structure, for example, forming two interlayer dielectric layer materials, wherein the interlayer dielectric layer material near the semiconductor substrate 100 is formed using atomic layer deposition, and the other interlayer dielectric layer material is formed using plasma-enhanced chemical vapor deposition. The interlayer dielectric layer material includes, but is not limited to, silicon oxide, silicon oxynitride, or silicon hydroxide; in this embodiment, it is silicon oxide. The interlayer dielectric layer material is planarized so that the surface of the interlayer dielectric layer material and the top surface of the gate structure 110 are coplanar, forming the interlayer dielectric layer 150. The process for planarizing the interlayer dielectric layer material may be chemical mechanical polishing or physical mechanical polishing. The interlayer dielectric layer 150 and the sidewall 120 define the location of the metal grid structure to be formed subsequently.

[0046] refer to Figure 6 The dummy gate structure 110 is removed to expose the surface of the semiconductor substrate 100. The process for removing the dummy gate structure 110 is a dry etching process; the dry etching process is an anisotropic etching process or an isotropic etching process. In other embodiments, the process for removing the dummy gate structure 110 can also be a wet etching process.

[0047] Continue to refer to Figure 6 The semiconductor substrate 100 of the tunnel field-effect transistor is etched to a depth where the surface of the semiconductor substrate 100 is below the top surfaces of the source 130 and the drain 140. The etching process for the semiconductor substrate 100 can be a dry etching process or a wet etching process, and can be anisotropic or isotropic. The height of the etched semiconductor substrate 100 depends on the location of the subsequently formed heavily doped region. In some embodiments, after etching the semiconductor substrate 100, the height difference between the surface of the semiconductor substrate 100 and the top surfaces of the source 130 and the drain 140 is 5 nm to 100 nm.

[0048] refer to Figure 7A heavily doped region 160 is formed in the semiconductor substrate 100. The doping type of the heavily doped region 160 is the same as that of the source 130. If the formed tunneling field-effect transistor (TFET) is N-type, the dopant ions in the heavily doped region 160 are P-type; if the formed TFET is P-type, the dopant ions in the heavily doped region 160 are N-type. The doping concentration of the heavily doped region 160 should be higher than that of the source 130. This allows tunneling to preferentially occur on the surface of the heavily doped region 160, rather than on the sidewalls of the source 130 above the heavily doped region 160, thus changing the existing vertically distributed tunneling junction surface to a horizontally distributed tunneling junction surface.

[0049] The heavily doped region 160 is adjacent to the source 130 but does not contact the drain 140 to meet the channel performance requirements of the tunneling field-effect transistor. In some embodiments, the absolute value of the depth difference between the bottom surface of the heavily doped region 160 and the bottom surfaces of the source 130 and the drain 140 does not exceed 50 nm. That is, the depth of the bottom surface of the heavily doped region 160 can be greater than the depth of the bottom surfaces of the source 130 and the drain 140, but the depth difference is not greater than 50 nm; or, the depth of the bottom surface of the heavily doped region 160 is less than the depth of the bottom surfaces of the source 130 and the drain 140, and the depth difference is also not greater than 50 nm. For example, the depth difference between the heavily doped region 160 and the source 130 and the drain 140 can be 10 nm, 20 nm, 30 nm, 40 nm, or 50 nm, as long as tunneling mainly occurs on the surface of the heavily doped region 160. The width of the heavily doped region 160 is greater than the depth of the source 130 and less than the width of the dummy gate structure 110. That is, the width of the heavily doped region 160 is less than the width of the subsequently formed metal gate, meaning the width of the heavily doped region 160 should be less than the straight-line distance between the source 130 and the drain 140. In some embodiments, the width difference between the heavily doped region 160 and the dummy gate structure 110 is between 20 nm and 100 nm, meaning the straight-line distance between adjacent sidewalls of the heavily doped region 160 and the drain 140 is between 20 nm and 100 nm.

[0050] The heavily doped region 160 can be formed using a tilted ion implantation process, with the ion implantation direction facing the source 130. The ion implantation angle of the tilted ion implantation process is crucial for forming the heavily doped region 160. If the incident angle α is too large, the width of the formed heavily doped region 160 will be too small, resulting in a small tunneling region area and an insignificant effect on improving the driving current. If the incident angle α is too small, the distance between the heavily doped region 160 and the drain 140 will be too small, failing to meet the device performance requirements. In some embodiments of this application, the incident angle α of ion implantation is set to 7°–60°, and the ion implantation energy is set to 5keV–50keV to ensure that the heavily doped region 160 is adjacent to the source 130 and has a reasonable distance from the drain 140, which can significantly improve the driving current. In the embodiments of this application, the "incident angle α" refers to the angle α between the ion implantation path and the normal to the surface of the semiconductor substrate 100.

[0051] refer to Figure 8 An epitaxial layer 170 is grown on the surface of the heavily doped region 160 and the exposed semiconductor substrate 100. The surface of the epitaxial layer 170 is coplanar with the top surfaces of the source 130 and the drain 140, meaning that the epitaxial layer 170 fills the semiconductor substrate etched away in step S4. The epitaxial layer 170 serves as the channel of the tunnel field-effect transistor. The material of the epitaxial layer 170 can be (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above. Furthermore, the epitaxial layer 170 can also be doped (e.g., P-type doping or N-type doping). In some embodiments, the epitaxial layer 170 can be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic). When the tunneling field-effect transistor is N-type, the epitaxial layer 170 can be intrinsically doped or weakly N-type doped; when the tunneling field-effect transistor is P-type, the epitaxial layer 170 can be intrinsically doped or weakly P-type doped. The materials of the epitaxial layer 170 and the semiconductor substrate 100 can be the same or different.

[0052] The epitaxial layer 170, grown using a selective epitaxial growth process, allows epitaxial material to be grown only on the surfaces of the heavily doped region 160 and the exposed semiconductor substrate 100, without growing epitaxial material on the surface of the interlayer dielectric layer 150, thus eliminating the step of removing the epitaxial material from the surface of the interlayer dielectric layer 150. The selective epitaxial growth process is performed at a low temperature to avoid impurity diffusion in the heavily doped region 160. In this embodiment, the temperature of the selective epitaxial growth process does not exceed 700°C.

[0053] In this embodiment, the epitaxial layer 170 serves as the channel of the tunneling field-effect transistor (TFET). Specifically, the channel of the TFET is located on the surface of the epitaxial layer 170, which is covered by the metal gate structure 180. Since the ion concentration of the heavily doped region 160 is higher than that of the source 130, tunneling mainly occurs at the adjacent surface B between the epitaxial layer 170 and the heavily doped region 160. That is, the adjacent surface B is the tunneling junction of the TFET, which is horizontally distributed. The aforementioned tunneling junction A is the adjacent surface between the source and the semiconductor substrate, perpendicular to the surface of the semiconductor substrate. Clearly, the area of ​​the adjacent surface B is much larger than the area of ​​the tunneling junction A, thus significantly increasing the driving current of the TFET.

[0054] refer to Figure 9 A metal gate structure 180 is formed on the surface of the epitaxial layer 170, and the surface of the metal gate structure 180 is coplanar with the top surface of the interlayer dielectric layer 150. The metal gate structure 180 may include a gate dielectric layer and a metal gate located on the surface of the gate dielectric layer. The material of the gate dielectric layer may be silicon nitride, silicon oxynitride, or some high-k materials, wherein the high-k material is a material with a relative permittivity greater than that of silicon oxide. In this embodiment, the high-k material is HfO2. In other embodiments, the high-k material may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3. The process for forming the gate dielectric layer may be chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this embodiment, atomic layer deposition is used to form the gate dielectric layer. The material of the metal gate may include at least one of Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0055] Combination Figure 10 and Figure 11 After forming the metal grid structure 180, the following process steps are also included:

[0056] An intermetallic dielectric layer 190 is formed on the surfaces of the interlayer dielectric layer 150 and the metal gate structure 180. The material of the intermetallic dielectric layer 190 may include at least one of SiOCN, SiOC, SiO2, SiN, and SiON. The intermetallic dielectric layer 190 and the interlayer dielectric layer 150 are etched to expose portions of the surfaces of the source electrode 130 and the drain electrode 140, forming contact holes. A metal silicide layer (not shown) is formed on the bottom surface of the contact holes. A conductive layer 200 is formed on the surface of the metal silicide layer, and the top surface of the conductive layer 200 and the intermetallic dielectric layer 190 are coplanar. This embodiment of the application avoids the damage to the silicide structure and performance caused by high-temperature processes through a post-silicide last process.

[0057] The method for forming a tunnel field-effect transistor according to the embodiments of this application forms a heavily doped region below the channel of the tunnel field-effect transistor, and the doping concentration of the heavily doped region is higher than that of the source. This causes tunneling to preferentially occur at the adjacent surface between the heavily doped region and the channel layer, thereby increasing the area of ​​the tunneling region and improving the driving current of the tunnel field-effect transistor.

[0058] refer to Figure 9 This application also provides a tunneling field-effect transistor, comprising: a semiconductor substrate 100; a metal gate structure 180 located on the surface of the semiconductor substrate 100; a sidewall 120 located on the sidewall of the metal gate structure 180; a source 130 and a drain 140 respectively located in the semiconductor substrate 100 on both sides of the metal gate structure 180; and a heavily doped region 160 located in the semiconductor substrate 100 below the channel of the tunneling field-effect transistor, wherein the doping type of the heavily doped region 160 is the same as the doping type of the source 130, and the doping concentration of the heavily doped region 160 is higher than that of the source 130.

[0059] The semiconductor substrate 100 may be made of (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above. The semiconductor substrate 100 may be a P-type semiconductor substrate or an N-type semiconductor substrate. For example, the semiconductor substrate 100 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic). When the tunneling field-effect transistor is N-type, the semiconductor substrate 100 may be intrinsically doped or weakly N-type doped; when the tunneling field-effect transistor is P-type, the semiconductor substrate 100 may be intrinsically doped or weakly P-type doped.

[0060] The metal gate structure 180 is a stacked structure, including a gate dielectric layer and a metal gate located on the surface of the gate dielectric layer. The material of the gate dielectric layer can be silicon nitride, silicon oxynitride, or some high-k materials, wherein the high-k material is a material with a relative permittivity greater than that of silicon oxide. In some embodiments, the high-k material can also be HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3, and the material of the metal gate can include at least one of Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0061] The sidewall 120 is located on the side wall of the metal grid structure 180. The sidewall 120 can be a single-layer structure or a multi-layer structure. The material of the sidewall 120 can include one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0062] The surface of the heavily doped region 160 is lower than the top surfaces of the source 130 and the drain 140, and the heavily doped region 160 is adjacent to the source 130 but does not contact the drain 140, so as to meet the performance requirements of the tunnel field-effect transistor for the channel.

[0063] In some embodiments, the height difference between the surface of the heavily doped region 160 and the top surfaces of the source 130 and the drain 140 is 5 nm to 100 nm. The absolute value of the depth difference between the bottom surface of the heavily doped region 160 and the bottom surfaces of the source 130 and the drain 140 does not exceed 50 nm. That is, the depth of the bottom surface of the heavily doped region 160 can be greater than the depth of the bottom surfaces of the source 130 and the drain 140, but the depth difference is not greater than 50 nm; or, the depth of the bottom surface of the heavily doped region 160 is less than the depth of the bottom surfaces of the source 130 and the drain 140, and the depth difference is also not greater than 50 nm. The width of the heavily doped region 160 is greater than the depth of the source 130 and less than the width of the metal gate structure 180, and the width difference between the heavily doped region 160 and the metal gate structure 180 is 20 nm to 100 nm.

[0064] The semiconductor substrate 100 includes an epitaxial layer 170 located between the metal gate structure 180 and the heavily doped region 160, and connecting the source 130 and the drain 140, serving as the channel of the tunnel field-effect transistor. In some embodiments, the tunnel field-effect transistor further includes an interlayer dielectric layer 150 located on the sidewall of the sidewall 120 and covering the surfaces of the source 130 and the drain 140.

[0065] refer to Figure 11The tunneling field-effect transistor further includes an intermetallic dielectric layer 190 located on the surface of the intermetallic dielectric layer 150 and the metal gate structure 180; a metal silicide layer (not shown) located in the intermetallic dielectric layer 150 and covering a portion of the surface of the source 130 and the drain 140; and a conductive layer 200 located on the surface of the metal silicide layer, wherein the top surfaces of the conductive layer 200 and the intermetallic dielectric layer 190 are coplanar.

[0066] This application embodiment changes the conventional tunneling field-effect transistor structure by adding a heavily doped region with a doping concentration greater than that of the source. As a result, the tunneling site of the tunneling field-effect transistor mainly occurs at the interface between the heavily doped region and the channel layer. Since the width of the heavily doped region is greater than the depth of the source, the tunneling area is increased, thereby improving the driving current.

[0067] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0068] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0069] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0070] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0071] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A tunneling field-effect transistor, characterized in that, include: Semiconductor substrate; A metal gate structure is located on the surface of the semiconductor substrate; Sidewalls, located on the side walls of the metal grid structure; The source and drain are located in the semiconductor substrates on both sides of the metal gate structure, respectively; The heavily doped region is located in the semiconductor substrate below the channel of the tunnel field-effect transistor. The surface of the heavily doped region is lower than the top surfaces of the source and the drain. The doping type of the heavily doped region is the same as that of the source, and the doping concentration of the heavily doped region is higher than that of the source. The width of the heavily doped region is greater than the depth of the source and less than the width of the metal gate structure. The width difference between the heavily doped region and the metal gate structure is 20 nm to 100 nm.

2. The tunneling field-effect transistor according to claim 1, characterized in that, The heavily doped region is adjacent to the source but does not contact the drain.

3. The tunneling field-effect transistor according to claim 1, characterized in that, The height difference between the surface of the heavily doped region and the top surfaces of the source and drain electrodes is 5 nm to 100 nm.

4. The tunneling field-effect transistor according to claim 1, characterized in that, The absolute value of the depth difference between the bottom surface of the heavily doped region and the bottom surface of the source and drain electrodes does not exceed 50 nm.

5. The tunneling field-effect transistor according to claim 1, characterized in that, The semiconductor substrate includes an epitaxial layer located between the metal gate structure and the heavily doped region, and connecting the source and the drain, serving as the channel of the tunnel field-effect transistor.

6. The tunneling field-effect transistor according to claim 1, characterized in that, It also includes an interlayer dielectric layer, which is located on the sidewall of the sidewall and covers the surfaces of the source and the drain.

7. The tunneling field-effect transistor according to claim 6, characterized in that, Also includes: An intermetallic dielectric layer is located on the surface of the intermetallic dielectric layer and the metal gate structure; A metal silicide layer is located in the interlayer dielectric layer and covers a portion of the surface of the source and the drain. A conductive layer is located on the surface of the metal silicide layer, and the top surfaces of the conductive layer and the intermetallic dielectric layer are coplanar.

8. A method for forming a tunneling field-effect transistor, characterized in that, include: A semiconductor substrate is provided, wherein a dummy gate structure is formed on the surface of the semiconductor substrate, sidewalls are formed on the sidewalls of the dummy gate structure, and source and drain electrodes are formed in the semiconductor substrate on both sides of the dummy gate structure, respectively. An interlayer dielectric layer is formed on the surface of the semiconductor substrate on both sides of the sidewall; Remove the dummy gate structure to expose the surface of the semiconductor substrate; Etch a portion of the semiconductor substrate in the channel region of the tunnel field-effect transistor until the surface of the semiconductor substrate is lower than the top surfaces of the source and the drain. A heavily doped region is formed in the semiconductor substrate. The doping type of the heavily doped region is the same as that of the source electrode, and the doping concentration of the heavily doped region is higher than that of the source electrode. The heavily doped region is adjacent to the source electrode but does not contact the drain electrode. The surface of the heavily doped region is lower than the top surface of the source electrode and the drain electrode. An epitaxial layer is grown on the surface of the heavily doped region and the exposed semiconductor substrate surface, wherein the surface of the epitaxial layer is coplanar with the top surfaces of the source and the drain, and the epitaxial layer is the channel of the tunnel field-effect transistor. A metal gate structure is formed on the surface of the epitaxial layer, and the surface of the metal gate structure and the top surface of the interlayer dielectric layer are coplanar. The width of the heavily doped region is greater than the depth of the source electrode and less than the width of the metal gate structure. The width difference between the heavily doped region and the metal gate structure is 20 nm to 100 nm.

9. The method for forming a tunneling field-effect transistor according to claim 8, characterized in that, After etching the semiconductor substrate, the height difference between the surface of the semiconductor substrate and the top surfaces of the source and drain electrodes is 5 nm to 100 nm.

10. The method for forming a tunneling field-effect transistor according to claim 8, characterized in that, The heavily doped region is formed using a tilted ion implantation process.

11. The method for forming a tunneling field-effect transistor according to claim 10, characterized in that, The ion implantation direction is towards the source electrode, and the incident angle of the ion implantation is 7° to 60°, and the ion implantation energy is 5keV to 50keV.

12. The method for forming a tunneling field-effect transistor according to claim 8, characterized in that, The absolute value of the depth difference between the bottom surface of the heavily doped region and the bottom surface of the source and drain electrodes does not exceed 50 nm.

13. The method for forming a tunneling field-effect transistor according to claim 8, characterized in that, The epitaxial layer is formed using a selective epitaxial growth process, wherein the temperature of the selective epitaxial growth process does not exceed 700°C.

14. The method for forming a tunneling field-effect transistor according to claim 8, characterized in that, The epitaxial layer is made of the same material as the semiconductor substrate.

15. The method for forming a tunneling field-effect transistor according to claim 8, characterized in that, After forming the metal grid structure, it also includes: An intermetallic dielectric layer is formed on the surfaces of the interlayer dielectric layer and the metal gate structure; Etch the intermetallic dielectric layer and the interlayer dielectric layer to expose part of the source and drain surfaces, forming contact holes; A metal silicide layer is formed on the bottom surface of the contact hole; A conductive layer is formed on the surface of the metal silicide layer, and the top surfaces of the conductive layer and the intermetallic dielectric layer are coplanar.

Images