Pixel driving circuit and driving method thereof, display panel and display device

Abstract

A pixel driving circuit and a driving method thereof, a display panel and a display device, the pixel driving circuit being used for driving a light emitting unit (OLED), the pixel driving circuit comprising: a driving circuit (1), a compensation circuit (2), a control circuit (3), and a data writing circuit (4), the driving circuit (1) being connected with a first node (N1), a second node (N2), and a third node (N3), and being used for inputting a driving current to the third node (N3) through the second node (N2) according to a voltage signal of the first node (N1); the compensation circuit (2) being connected with the first node (N1), the third node (N3), and a gate driving signal end (Gate), and being used for connecting the first node (N1) and the third node (N3) in response to a signal of the gate driving signal end (Gate); the control circuit (3) being connected with the second node (N2), a first power supply end (VDD), the third node (N3), a first electrode of the light emitting unit (OLED), and a first enable signal end (EM1), and being used for connecting the first power supply end (VDD) and the second node (N2) in response to a signal of the first enable signal end (EM1), and being used for connecting the third node (N3) and the first electrode of the light emitting unit (OLED) in response to the signal of the first enable signal end (EM1); and the data writing circuit (4) being connected with the second node (N2), a data signal end (Da), and a second enable signal end (EM2), and being used for transmitting a signal of the data signal end (Da) to the second node (N2) in response to a signal of the second enable signal end (EM2). In at least part of a period in which the gate driving signal end (Gate) outputs an invalid level, the first enable signal end (EM1) alternately outputs a valid level and an invalid level, the second enable signal end (EM2) alternately outputs the valid level and the invalid level, and a valid level period of the second enable signal end (EM2) is located in an invalid level period of the first enable signal end (EM1), and a valid level period of the first enable signal end (EM1) is located in an invalid level period of the second enable signal end (EM2).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a pixel driving circuit and a driving method thereof, a display panel and a display device. BACKGROUND

[0002] In the related art, the driving transistor in the pixel driving circuit will cause the characteristic curve to drift under long-time bias, thereby affecting the driving effect.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] According to an aspect of the present disclosure, a pixel driving circuit for driving a light emitting unit is provided, comprising: a driving circuit, a compensation circuit, a control circuit, and a data writing circuit, the driving circuit being connected to a first node, a second node, and a third node, for inputting a driving current to the third node through the second node according to a voltage signal of the first node; the compensation circuit being connected to the first node, the third node, and a gate driving signal terminal, for connecting the first node and the third node in response to a signal of the gate driving signal terminal; the control circuit being connected to the second node, a first power supply terminal, the third node, a first electrode of the light emitting unit, and a first enable signal terminal, for connecting the first power supply terminal and the second node in response to a signal of the first enable signal terminal, and for connecting the third node and the first electrode of the light emitting unit in response to a signal of the first enable signal terminal; the data writing circuit being connected to the second node, a data signal terminal, and a second enable signal terminal, for transmitting a signal of the data signal terminal to the second node in response to a signal of the second enable signal terminal. Wherein, during at least part of the period when the gate driving signal terminal outputs an invalid level, the first enable signal terminal alternately outputs a valid level and an invalid level, the second enable signal terminal alternately outputs a valid level and an invalid level, and the valid level period of the second enable signal terminal is located within the invalid level period of the first enable signal terminal, and the valid level period of the first enable signal terminal is located within the invalid level period of the second enable signal terminal.

[0005] In an exemplary embodiment of the present disclosure, the driving circuit comprises: a driving transistor, a first electrode of the driving transistor being connected to the second node, a second electrode of the driving transistor being connected to the third node, and a gate of the driving transistor being connected to the first node.

[0006] In an exemplary embodiment of the present disclosure, the compensation circuit comprises: a second transistor, a first electrode of the second transistor being connected to the first node, a second electrode of the second transistor being connected to the third node, and a gate of the second transistor being connected to the gate driving signal terminal.

[0007] In an example embodiment of the present disclosure, the data writing circuit includes a fourth transistor, a first electrode of the fourth transistor is connected to the data signal terminal, a second electrode of the fourth transistor is connected to the second node, and a gate of the fourth transistor is connected to the second enable signal terminal.

[0008] In an example embodiment of the present disclosure, the control circuit includes a fifth transistor and a sixth transistor, a first electrode of the fifth transistor is connected to the first power supply terminal, a second electrode of the fifth transistor is connected to the second node, and a gate of the fifth transistor is connected to the first enable signal terminal; a first electrode of the sixth transistor is connected to the third node, a second electrode of the sixth transistor is connected to the first electrode of the light emitting unit, and a gate of the sixth transistor is connected to the first enable signal terminal.

[0009] In an example embodiment of the present disclosure, the second enable signal terminal and the first enable signal terminal are logically opposite.

[0010] In an example embodiment of the present disclosure, the pixel driving circuit further includes a first reset circuit and a second reset circuit, the first reset circuit is connected to the first node, a first initial signal terminal, and a reset signal terminal, and is configured to transmit a signal of the first initial signal terminal to the first node in response to a signal of the reset signal terminal; the second reset circuit is connected to the first electrode of the light emitting unit and a second initial signal terminal, and is configured to transmit a signal of the second initial signal terminal to the first electrode of the light emitting unit in response to a control signal.

[0011] In an example embodiment of the present disclosure, the second reset circuit is further connected to the second enable signal terminal, and the second reset circuit is configured to transmit the signal of the second initial signal terminal to the first electrode of the light emitting unit in response to the signal of the second enable signal terminal.

[0012] In an example embodiment of the present disclosure, the first reset circuit includes a first transistor, a first electrode of the first transistor is connected to the first initial signal terminal, a second electrode of the first transistor is connected to the first node, and a gate of the first transistor is connected to the reset signal terminal; and the second reset circuit includes a seventh transistor, a first electrode of the seventh transistor is connected to the second initial signal terminal, a second electrode of the seventh transistor is connected to the first electrode of the light emitting unit, and a gate of the seventh transistor is connected to the second enable signal terminal.

[0013] In an example embodiment of the present disclosure, the pixel driving circuit further includes a storage circuit, the storage circuit is connected between the first node and the first power supply terminal.

[0014] In an example embodiment of the present disclosure, the storage circuit includes a capacitor, the capacitor is connected between the first node and the first power supply terminal.

[0015] In an example embodiment of the present disclosure, the driving circuit comprises: a driving transistor, a first electrode of the driving transistor being connected to the second node, a second electrode of the driving transistor being connected to the third node, and a gate electrode of the driving transistor being connected to the first node; the compensation circuit comprises: a second transistor, a first electrode of the second transistor being connected to the first node, a second electrode of the second transistor being connected to the third node, and a gate electrode of the second transistor being connected to the gate driving signal terminal; the data writing circuit comprises: a fourth transistor, a first electrode of the fourth transistor being connected to the data signal terminal, a second electrode of the fourth transistor being connected to the second node, and a gate electrode of the fourth transistor being connected to the second enable signal terminal; the control circuit comprises: a fifth transistor and a sixth transistor, a first electrode of the fifth transistor being connected to the first power supply terminal, a second electrode of the fifth transistor being connected to the second node, and a gate electrode of the fifth transistor being connected to the first enable signal terminal; a first electrode of the sixth transistor being connected to the third node, a second electrode of the sixth transistor being connected to the first electrode of the light emitting unit, and a gate electrode of the sixth transistor being connected to the first enable signal terminal; the pixel driving circuit further comprises a first reset circuit, a second reset circuit, and a storage circuit; the first reset circuit comprises: a first transistor, a first electrode of the first transistor being connected to the first initial signal terminal, a second electrode of the first transistor being connected to the first node, and a gate electrode of the first transistor being connected to the reset signal terminal; the second reset circuit comprises: a seventh transistor, a first electrode of the seventh transistor being connected to the second initial signal terminal, a second electrode of the seventh transistor being connected to the first electrode of the light emitting unit, and a gate electrode of the seventh transistor being connected to the second enable signal terminal; the coupling circuit comprises: a capacitor, the capacitor being connected between the first node and the first power supply terminal; wherein the driving transistor, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors.

[0016] According to an aspect of the present disclosure, a driving method of a pixel driving circuit is provided for driving the pixel driving circuit described above, wherein the driving method comprises:

[0017] In the first stage:

[0018] In a first sub-stage, the gate driving signal terminal and the second enable signal terminal output valid levels, and the first enable signal terminal outputs an invalid level;

[0019] In a second sub-stage, the first enable signal terminal outputs a valid level, and the second enable signal terminal and the gate driving signal terminal output invalid levels;

[0020] In the second stage, the gate driving signal terminal outputs an invalid level, the first enable signal terminal alternately outputs a valid level and an invalid level, and the second enable signal terminal alternately outputs a valid level and an invalid level;

[0021] The valid level period of the second enable signal end is located in the invalid level period of the first enable signal end, the valid level period of the first enable signal end is located in the invalid level period of the second enable signal end, and the level of the data signal end written to the second node is not equal to the voltage of the first power supply end at least in part in the second stage.

[0022] In an example embodiment of the present disclosure, the pixel driving circuit is applied to a display panel, and a frame period of the display panel includes a picture update period and a picture retention period. In a frame period, a first stage of all pixel driving circuits in the display panel is located in the picture update period, and a second stage of all pixel driving circuits in the display panel is located in the picture retention period.

[0023] According to an aspect of the present disclosure, a display panel is provided, wherein the display panel includes the pixel driving circuit described above.

[0024] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel comprises a pixel driving circuit for driving a light emitting unit, the pixel driving circuit comprises a driving transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor. The first electrode of the second transistor is connected to the gate electrode of the driving transistor, the second electrode is connected to the second electrode of the driving transistor, and the gate electrode is connected to a gate line; the first electrode of the fourth transistor is connected to a data line, the second electrode is connected to the first electrode of the driving transistor, and the gate electrode is connected to a second enable signal line; the first electrode of the fifth transistor is connected to a power supply line, the second electrode is connected to the first electrode of the driving transistor, and the gate electrode is connected to a first enable signal line; the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light emitting unit, and the gate electrode is connected to the first enable signal line. The display panel further comprises a substrate, an active layer, and a first conductive layer. The active layer is located on one side of the substrate, and comprises a second active part, a third active part, a fourth active part, a fifth active part, and a sixth active part. The second active part is used to form a channel region of the second transistor, the third active part is used to form a channel region of the driving transistor, the fourth active part is used to form a channel region of the fourth transistor, the fifth active part is used to form a channel region of the fifth transistor, and the sixth active part is used to form a channel region of the sixth transistor. The first conductive layer is located on the side of the active layer away from the substrate, and comprises the first enable signal line, the second enable signal line, the gate line, and a first conductive part. The orthogonal projection of the first conductive part on the substrate covers the orthogonal projection of the third active part on the substrate, and the first conductive part is used to form the gate electrode of the driving transistor. The orthogonal projection of the first enable signal line on the substrate extends along a first direction and covers the orthogonal projection of the fifth active part on the substrate and the orthogonal projection of the sixth active part on the substrate, and part of the structure of the first enable signal line is used to form the gate electrode of the fifth transistor and the gate electrode of the sixth transistor. The orthogonal projection of the second enable signal line on the substrate extends along the first direction and covers the orthogonal projection of the fourth active part on the substrate, and part of the structure of the second enable signal line is used to form the gate electrode of the fourth transistor. The orthogonal projection of the gate line on the substrate extends along the first direction and covers the orthogonal projection of the second active part on the substrate, and part of the structure of the gate line is used to form the gate electrode of the second transistor.

[0025] In an example embodiment of the present disclosure, a projection of the first enable signal line on the substrate substrate is located between a projection of the second enable signal line on the substrate substrate and a projection of the first conductive part on the substrate substrate. The active layer further includes an eighth active part and a ninth active part, the eighth active part being connected between the third active part and the fifth active part, and the ninth active part being connected to the fourth active part, a projection of the ninth active part on the substrate substrate being located between the projection of the first enable signal line on the substrate substrate and the projection of the second enable signal line on the substrate substrate. The display panel further includes a third conductive layer located on a side of the first conductive layer away from the substrate substrate, the third conductive layer including a first connection part, the first connection part being connected to the eighth active part and the ninth active part through vias, respectively.

[0026] In an example embodiment of the present disclosure, the pixel driving circuit further comprises a capacitor, a first transistor and a seventh transistor. The capacitor is connected between the power supply line and the gate of the driving transistor. The first transistor has a first electrode connected to a first initial signal line, a second electrode connected to the gate of the driving transistor, and a gate electrode connected to a reset signal line. The seventh transistor has a first electrode connected to a second initial signal line, a second electrode connected to the first electrode of the light-emitting unit, and a gate electrode connected to the second enable signal line. The driving transistor, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are P-type transistors. The active layer further comprises a first active part and a seventh active part. The first active part is used to form a channel region of the first transistor, and the seventh active part is used to form a channel region of the seventh transistor. The first conductive layer further comprises a reset signal line. The orthogonal projection of the reset signal line on the substrate substrate extends along the first direction. The orthogonal projection of the reset signal line on the substrate substrate covers the orthogonal projection of the first active part on the substrate substrate. Part of the structure of the reset signal line is used to form the gate of the first transistor. The orthogonal projection of the second enable signal line on the substrate substrate further covers the seventh active part. Part of the structure of the second enable signal line is used to form the gate of the seventh transistor. The display panel further comprises a second conductive layer. The second conductive layer is located on the side of the first conductive layer away from the substrate substrate. The second conductive layer comprises a second conductive part. The orthogonal projection of the second conductive part on the substrate substrate at least partially overlaps the orthogonal projection of the first conductive part on the substrate substrate. The first conductive part is further used to form the first electrode of the capacitor, and the second conductive part is used to form the second electrode of the capacitor. The orthogonal projection of the gate line on the substrate substrate is located on the side of the orthogonal projection of the first conductive part on the substrate substrate away from the orthogonal projection of the first enable signal line on the substrate substrate. The orthogonal projection of the reset signal line on the substrate substrate is located on the side of the orthogonal projection of the gate line on the substrate substrate away from the orthogonal projection of the first conductive part on the substrate substrate.

[0027] In an example embodiment of the present disclosure, the active layer further comprises a tenth active part and an eleventh active part, the tenth active part is connected to one end of the first active part away from the second active part, and the eleventh active part is connected to one end of the seventh active part away from the sixth active part. The second conductive layer further comprises the first initial signal line and the second initial signal line, a projection of the first initial signal line on the substrate substrate extends along the first direction, and the projection of the first initial signal line on the substrate substrate is located on a side of the projection of the reset signal line on the substrate substrate away from the projection of the first conductive part on the substrate substrate; a projection of the second initial signal line on the substrate substrate extends along the first direction, and the projection of the second initial signal line on the substrate substrate is located on a side of the projection of the second enable signal line on the substrate substrate away from the projection of the first conductive part on the substrate substrate. The display panel further comprises a third conductive layer located on a side of the second conductive layer away from the substrate substrate, and the third conductive layer comprises a second connecting part and a third connecting part, the second connecting part is connected to the tenth active part and the first initial signal line through a via hole respectively, and the third connecting part is connected to the second initial signal line and the eleventh active part through a via hole respectively.

[0028] In an example embodiment of the present disclosure, the first direction is a row direction, and the display panel comprises a plurality of rows of pixel driving circuits, and a projection of a second initial signal line in a current row of pixel driving circuits on the substrate substrate is located between a projection of a reset signal line and a projection of a gate line on the substrate substrate in an adjacent next row of pixel driving circuits.

[0029] In an example embodiment of the present disclosure, the first active part comprises a first sub-active part and a second sub-active part, and the active layer further comprises a third sub-active part connected between the first sub-active part and the second sub-active part; a projection of the first initial signal line on the substrate substrate at least partially overlaps with a projection of the third sub-active part on the substrate substrate.

[0030] In an example embodiment of the present disclosure, the second active part includes a fourth sub-active part and a fifth sub-active part, and the active layer further includes a sixth sub-active part connected between the fourth sub-active part and the fifth sub-active part. The second initial signal line includes a main body line, a first protruding part, a projection of the main body line on the substrate substrate extends along the first direction; the first protruding part is connected to the main body line, and a projection of the first protruding part on the substrate substrate extends along a second direction intersecting the first direction; wherein a projection of the first protruding part on the substrate substrate in the pixel driving circuit of the previous row at least partially overlaps with a projection of the sixth sub-active part on the substrate substrate in the pixel driving circuit of the current row.

[0031] In an example embodiment of the present disclosure, the active layer further includes a twelfth sub-active part connected between the first active part and the second active part. The second initial signal line includes a main body line, a second protruding part, a projection of the main body line on the substrate substrate extends along the first direction; the second protruding part is connected to the main body line, and a projection of the second protruding part on the substrate substrate extends along a second direction intersecting the first direction; wherein a projection of the second protruding part on the substrate substrate in the pixel driving circuit of the previous row at least partially overlaps with a projection of the twelfth sub-active part on the substrate substrate in the pixel driving circuit of the current row.

[0032] In an example embodiment of the present disclosure, the second initial signal line further includes a third protruding part connected to the main body line, a projection of the third protruding part on the substrate substrate extends along the second direction, and a projection of the third protruding part on the substrate substrate is located on a side of the projection of the main body line on the substrate substrate away from the projection of the second protruding part on the substrate substrate; wherein a projection of the third protruding part on the substrate substrate in the pixel driving circuit of the previous row at least partially overlaps with a projection of the twelfth sub-active part on the substrate substrate in the pixel driving circuit of the current row.

[0033] According to an aspect of the present disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0034] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0035] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the disclosure. It is to be understood that the drawings are designed solely for purposes of illustration to be used in conjunction with the description in envisioning the embodiments. Obviously, other embodiments can be used without departing from the spirit and scope of the present disclosure.

[0036] Figure 1 A circuit structure diagram of a pixel driving circuit in the related art;

[0037] Figure 2 A driving method of a pixel driving circuit in the related art; Figure 1 A timing diagram of nodes in the pixel driving circuit in the related art;

[0038] Figure 3 A change diagram of a characteristic curve of a driving transistor under a hysteresis effect;

[0039] Figure 4 A structure diagram of an exemplary embodiment of a pixel driving circuit of the present disclosure;

[0040] Figure 5 A structure diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure;

[0041] Figure 6 A driving method of a pixel driving circuit in the related art; Figure 5 A timing diagram of nodes in the pixel driving circuit shown in the related art;

[0042] Figure 7 A structure diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure;

[0043] Figure 8 A driving method of a pixel driving circuit in the related art; Figure 7 A timing diagram of nodes in the pixel driving circuit shown in the related art;

[0044] Figure 9 A structure layout of an exemplary embodiment of a display panel of the present disclosure;

[0045] Figure 10 A structure layout of an active layer in the related art; Figure 9

[0046] A structure layout of a first conductive layer in the related art; Figure 11 Figure 9 A structure layout of a second conductive layer in the related art;

[0047] Figure 12 Figure 9 A structure layout of a third conductive layer in the related art;

[0048] Figure 13 A structure layout of a third conductive layer in the related art; Figure 9

[0049] ​​​Figure 14 For Figure 9 a structure layout of the fourth conductive layer in the

[0050] Figure 15 For Figure 9 a structure layout of the active layer, the first conductive layer in the

[0051] Figure 16 For Figure 9 a structure layout of the active layer, the first conductive layer, the second conductive layer in the

[0052] Figure 17 For Figure 9 a structure layout of the active layer, the first conductive layer, the second conductive layer, the third conductive layer in the

[0053] Figure 18 For Figure 9 a partial cross-sectional view of the display panel shown in FIG. 8 along the dotted line CC. DETAILED DESCRIPTION

[0054] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and thus description of the same will be omitted.

[0055] The use of the terms "one" and "the" and "said" used in the context of describing the relevant structures throughout this patent document are to be construed to cover both the singular and the plural, unless otherwise indicated by the context. The use of the term "including" and "comprising" and variations thereof are meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The use of the term "about" in relation to a geographic location refers to a location within a 10 km radius of the geographic location.

[0056] As Figure 1As shown in FIG. 1, a circuit structure schematic diagram of a pixel driving circuit in the related art is shown. The pixel driving circuit can include a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. The first electrode of the first transistor T1 is connected to an initial signal terminal Vinit, the second electrode is connected to a node N, and the gate electrode is connected to a reset signal terminal Re. The second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, the first electrode is connected to the node N, and the gate electrode is connected to a gate driving signal terminal Gate. The gate electrode of the driving transistor T3 is connected to the node N. The first electrode of the fourth transistor T4 is connected to a data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate electrode is connected to the gate driving signal terminal Gate. The first electrode of the fifth transistor T5 is connected to a first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate electrode is connected to an enable signal terminal EM. The first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, and the gate electrode is connected to the enable signal terminal EM. The first electrode of the seventh transistor T7 is connected to the initial signal terminal Vinit, the second electrode is connected to the second electrode of the sixth transistor T6, and the gate electrode is connected to the reset signal terminal Re. The capacitor C is connected between the gate electrode of the driving transistor T3 and the first power supply terminal VDD. The pixel driving circuit can be connected to a light emitting unit OLED. The pixel driving circuit can be used to drive the light emitting unit OLED to emit light. The light emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and a second power supply terminal VSS. The driving transistor, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor can be P-type transistors.

[0057] As Figure 2 shown in FIG. 2, a circuit structure schematic diagram of a pixel driving circuit in the related art is shown. Figure 1A timing diagram of each node in a driving method of a middle pixel driving circuit. Wherein, Gate represents the timing of the gate driving signal end Gate, Re represents the timing of the reset signal end Re, EM represents the timing of the enable signal end EM, and Da represents the timing of the data signal end Da. The driving method of the pixel driving circuit can include a reset stage t1, a compensation stage t2, and a light emitting stage t3. In the reset stage t1, the reset signal end Re outputs a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the initial signal end Vinit inputs an initial signal to the node N and the second electrode of the sixth transistor T6. In the compensation stage t2, the gate driving signal end Gate outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal end Da outputs a data signal to write a voltage Vdata+Vth to the node N, wherein Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3. In the light emitting stage t3, the enable signal end EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 outputs a driving current to the light emitting unit OLED under the action of the voltage Vdata+Vth stored in the capacitor C. According to the driving transistor output current formula I=(μWCox / 2L)(Vgs-Vth) 2 , wherein μ is the carrier mobility, Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the driving transistor gate-source voltage difference, and Vth is the driving transistor threshold voltage. The output current I=(μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 of the driving transistor in the pixel driving circuit of the present disclosure. The pixel driving circuit can avoid the influence of the threshold voltage of the driving transistor on its output current.

[0058] However, due to the hysteresis effect of the driving transistor T3, that is, when the driving transistor is kept at a constant bias (Vgs) for a long time, the characteristic curve of the driving transistor will drift. As Figure 3 shown, it is a diagram showing the change of the characteristic curve of the driving transistor under the hysteresis effect. Wherein, the vertical coordinate I is the output current of the driving transistor, and the horizontal coordinate Vgs is the driving transistor gate-source voltage difference. Curve B is the original characteristic curve of the transistor, and curve A is the characteristic curve after drift. According to Figure 3 It can be seen that under the same bias, the characteristic curve drift will cause the output current of the driving transistor to decrease, thereby causing the luminance of the light emitting unit to decrease. Especially when the refresh frequency of the display panel is low, due to the longer frame time, the driving transistor is maintained at the bias for a longer time, thereby causing the luminance of the light emitting unit to decrease seriously, and further causing the display panel to flicker.

[0059] Based on this, the present exemplary embodiment provides a pixel driving circuit, as Figure 4As shown, it is a structural schematic diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit can include: a driving circuit 1, a compensation circuit 2, a control circuit 3, a data writing circuit 4, the driving circuit 1 is connected with a first node N1, a second node N2, a third node N3, for inputting a driving current to the third node N3 through the second node N2 according to a voltage signal of the first node N1; the compensation circuit 2 is connected with the first node N1, the third node N3, a gate driving signal end Gate, for connecting the first node N1 and the third node N3 in response to a signal of the gate driving signal end Gate; the control circuit 3 is connected with the second node N2, a first power supply end VDD, the third node N3, a first electrode of a light emitting unit, a first enable signal end EM1, for connecting the first power supply end VDD and the second node N2 in response to a signal of the first enable signal end EM1, and for connecting the third node N3 and the first electrode of the light emitting unit in response to a signal of the first enable signal end EM1; the data writing circuit 4 is connected with the second node N2, a data signal end Da, a second enable signal end EM2, for transmitting a signal of the data signal end Da to the second node N2 in response to a signal of the second enable signal end EM2. Another electrode of the light emitting unit OLED can be connected with a second power supply end VSS. The first electrode of the light emitting unit can be an anode of the light emitting unit.

[0060] In the example embodiment, the pixel driving circuit can be applied to a display panel, which can include a picture update period and a picture maintaining period in a frame driving period. In the picture update period, the pixel driving circuit in the display panel can be scanned line by line, and the scan period of each pixel driving circuit can include at least a reset stage, a data writing stage and a light emitting stage. In the reset stage, the first node N1 and the first electrode of the light emitting unit can be reset. In the data writing stage, the data writing circuit is turned on to transmit the signal of the data signal terminal Da to the second node, the compensation circuit is turned on to connect the first node N1 and the third node N3, and the driving circuit 1 is turned on to write the data signal and the threshold voltage of the driving circuit to the first node N1. In the light emitting stage, the control circuit is turned on to connect the first power supply terminal VDD and the second node N2, and connect the third node N3 and the first electrode of the light emitting unit. In the picture maintaining period, the gate driving signal terminal Gate outputs an invalid level, the first enable signal terminal EM1 alternately outputs an effective level and an invalid level, the second enable signal terminal EM2 alternately outputs an effective level and an invalid level, and the effective level period of the second enable signal terminal EM2 is located in the invalid level period of the first enable signal terminal EM1, and the effective level period of the first enable signal terminal EM1 is located in the invalid level period of the second enable signal terminal EM2. At the same time, the data signal terminal Da outputs a stable voltage, which is different from the voltage of the first power supply terminal VDD. For example, the stable voltage output by the data signal terminal Da can be greater than or less than the voltage of the first power supply terminal VDD. In the picture maintaining period, the data writing circuit 4 is alternately turned on and turned off, the control circuit 3 is alternately turned on and turned off, and the turn-on period of the data writing circuit 4 is located in the turn-off period of the control circuit 3, and the turn-on period of the control circuit 3 is located in the turn-off period of the data writing circuit 4. On the one hand, the data signal terminal Da can alternately write the stable voltage to the second node N2, and the bias voltage of the driving circuit on the first node N1 and the second node N2 is always changing, so that the characteristic curve drift caused by the long-term unchanged bias voltage of the driving circuit 1 can be reduced. On the other hand, when the data writing circuit 4 is turned on, the control circuit 3 is turned off, so that the stable voltage on the data signal terminal Da will not affect the normal light emitting of the pixel driving circuit.

[0061] It should be noted that in the example embodiment, the effective level refers to the logic level for turning on the target circuit, and the invalid level refers to the logic level for turning off the target circuit. For example, when the target circuit is a P-type transistor, the effective level is low and the invalid level is high; when the target circuit is an N-type transistor, the effective level is high and the invalid level is low.

[0062] It should be understood that in other exemplary embodiments, the data signal terminal Da can also output a non-stable voltage during the picture retention period. As long as the data writing circuit 4 inputs a voltage signal different from the first power terminal to the second node N2 during the picture retention period, the problem of characteristic curve drift can be improved. In other exemplary embodiments, after each pixel driving circuit completes its own scanning, the first enable signal terminal EM1 and the second enable signal terminal EM2 can also alternately output the active level and the inactive level at any time period, i.e., the first enable signal terminal EM1 and the second enable signal terminal EM2 can also alternately output the active level and the inactive level during the picture update period described above. Since the data signal terminals of the pixel driving circuits in the same column are connected to the same data line, at this time, the pixel driving circuit can use the data signal corresponding to the unscanned pixel driving circuit to write a voltage signal different from the voltage of the first power terminal to the second node N2.

[0063] In the present exemplary embodiment, as shown in Figure 4 The driving circuit 1 can include a driving transistor T3, the first electrode of the driving transistor T3 is connected to the second node N2, the second electrode is connected to the third node N3, and the gate electrode is connected to the first node N1. The compensation circuit 2 can include a second transistor T2, the first electrode of the second transistor T2 is connected to the first node N1, the second electrode is connected to the third node N3, and the gate electrode is connected to the gate drive signal terminal Gate. The data writing circuit 4 can include a fourth transistor T4, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the second node N2, and the gate electrode is connected to the second enable signal terminal EM2. The control circuit 3 can include a fifth transistor T5 and a sixth transistor T6, the first electrode of the fifth transistor T5 is connected to the first power terminal VDD, the second electrode is connected to the second node N2, and the gate electrode is connected to the first enable signal terminal EM1; the first electrode of the sixth transistor T6 is connected to the third node N3, the second electrode is connected to the first electrode of the light emitting unit, and the gate electrode is connected to the first enable signal terminal EM1.

[0064] In the present exemplary embodiment, the driving transistor T3 can be a P-type transistor, for example, the driving transistor T3 can be a P-type low-temperature polysilicon transistor. The second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can also be P-type transistors.

[0065] In the example embodiment, the logic levels of the second enable signal terminal EM2 and the first enable signal terminal EM1 can be opposite, and this setting can enable the fourth transistor T4 to be turned on while the fifth transistor T5 and the sixth transistor T6 are turned off. It should be understood that in other example embodiments, the timing on the second enable signal terminal EM2 and the first enable signal terminal EM1 can also have other corresponding relationships, as long as the active level period of the second enable signal terminal EM2 is within the inactive level period of the first enable signal terminal EM1.

[0066] In the example embodiment, as shown in FIG. 6, the pixel driving circuit is another example embodiment of the pixel driving circuit of the present disclosure. Figure 5 As shown in FIG. 7, the pixel driving circuit is another example embodiment of the pixel driving circuit of the present disclosure. Figure 5 As shown in FIG. 8, the pixel driving circuit is another example embodiment of the pixel driving circuit of the present disclosure. Figure 4 As shown in FIG. 9, the pixel driving circuit is another example embodiment of the pixel driving circuit of the present disclosure. Figure 5 As shown in FIG. 10, the pixel driving circuit further includes a first reset circuit 5, a second reset circuit 6, and a storage circuit 7. The first reset circuit 5 is connected to the first node N1, a first initial signal terminal Vinit1, and a reset signal terminal Re, and is configured to transmit a signal of the first initial signal terminal Vinit1 to the first node N1 in response to a signal of the reset signal terminal Re. The second reset circuit 6 is connected to the first electrode of the light emitting unit, a second initial signal terminal Vinit2, and a second enable signal terminal EM2, and is configured to transmit a signal of the second initial signal terminal Vinit2 to the first electrode of the light emitting unit in response to a signal of the second enable signal terminal EM2. The storage circuit 7 is connected between the first node N1 and the first power supply terminal VDD. The first initial signal terminal Vinit1 and the second initial signal terminal Vinit2 can output stable voltages, and the voltage of the second initial signal terminal Vinit2 can be equal to or close to the voltage of the second power supply terminal VSS.

[0067] In the example embodiment, the control terminal of the second reset circuit 6 is connected to the second enable signal terminal EM2. Since the second enable signal terminal EM2 alternately outputs high and low levels during the picture retention period, this setting can enable the light emitting unit OLED to be turned on and off more times within the same time interval. In low gray scale and low frequency display, anode reset can easily cause the display panel to flicker, and thus this setting can effectively improve the problem of panel flicker by increasing the number of anode reset times. It should be understood that in other example embodiments, the control terminal of the second reset circuit 6 can also be connected to other signal terminals, for example, the control terminal of the second reset circuit 6 can also be connected to the reset signal terminal Re, and the second reset circuit 6 can transmit a signal of the second initial signal terminal Vinit2 to the first electrode of the light emitting unit in response to a signal of the reset signal terminal Re. In addition, in other example embodiments, the second initial signal terminal Vinit2 can share the first initial signal terminal Vinit1.

[0068] In the example embodiment, as shown in Figure 5 The first reset circuit 5 can include a first transistor T1, a first electrode of the first transistor T1 being connected to the first initial signal terminal Vinit1, a second electrode being connected to the first node N1, and a gate being connected to the reset signal terminal Re. The second reset circuit 6 can include a seventh transistor T7, a first electrode of the seventh transistor T7 being connected to the second initial signal terminal Vinit2, a second electrode being connected to the first electrode of the light emitting unit, and a gate being connected to the second enable signal terminal EM2. The storage circuit 7 can include a capacitor C, the capacitor C being connected between the first node N1 and the first power supply terminal VDD. The first transistor T1 and the seventh transistor T7 can be P-type transistors, for example, P-type low temperature poly-silicon transistors.

[0069] As shown in Figure 6 , the first reset circuit 5 can include a first transistor T1, a first electrode of the first transistor T1 being connected to the first initial signal terminal Vinit1, a second electrode being connected to the first node N1, and a gate being connected to the reset signal terminal Re. The second reset circuit 6 can include a seventh transistor T7, a first electrode of the seventh transistor T7 being connected to the second initial signal terminal Vinit2, a second electrode being connected to the first electrode of the light emitting unit, and a gate being connected to the second enable signal terminal EM2. The storage circuit 7 can include a capacitor C, the capacitor C being connected between the first node N1 and the first power supply terminal VDD. The first transistor T1 and the seventh transistor T7 can be P-type transistors, for example, P-type low temperature poly-silicon transistors. Figure 5The timing diagram of each node in the pixel driving circuit is shown. The Gate is the timing of the gate driving signal end, EM1 is the timing of the first enable signal end, EM2 is the timing of the second enable signal end, Re is the timing of the reset signal end, and Da is the timing of the data signal end. The pixel driving circuit can be applied to a display panel. The display panel can include a picture update period T1 and a picture retention period T2 in a frame driving period. In the picture update period T1, the display panel can perform line-by-line scanning on the pixel driving circuit therein. The scanning period of each pixel driving circuit can include a first sub-stage t1, a second sub-stage t2, a third sub-stage t3, and a fourth sub-stage t4. In the first sub-stage t1, the reset signal end Re and the second enable signal end EM2 output a valid low (low) level, the gate driving signal end Gate and the first enable signal end EM1 output an invalid high (high) level, the first transistor T1 and the seventh transistor T7 are turned on, the first initial signal end Vinit1 writes an initial signal to the first node, and the second initial signal end Vinit2 writes an initial signal to the first electrode of the light-emitting unit. In the second sub-stage, the gate driving signal end Gate and the second enable signal end EM2 output a valid low (low) level, the reset signal end Re and the first enable signal end EM1 output an invalid high (high) level, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal end Da outputs a data signal to write a voltage Vdata+Vth to the first node N1, where Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3. In the third sub-stage, the second enable signal end EM2 outputs a valid low (low) level, the first enable signal end EM1, the gate driving signal end Gate, and the reset signal end output an invalid high (high) level, and the voltage of the first node N1 remains unchanged. In the fourth sub-stage, the first enable signal end EM1 outputs a valid low (low) level, the second enable signal end EM2, the gate driving signal end Gate, and the reset signal end output an invalid high (high) level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving transistor T3 outputs a driving current to the light-emitting unit OLED under the action of the voltage Vdata+Vth stored in the capacitor C. According to the driving transistor output current formula I=(μWCox / 2L)(Vgs-Vth) 2 where μ is the carrier mobility, Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the driving transistor gate-source voltage difference, and Vth is the driving transistor threshold voltage. In the example embodiment, the output current I of the driving transistor in the pixel driving circuit is (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2In the picture retention period T2, the data signal terminal Da outputs a stable voltage which is not the same as the voltage of the first power supply terminal VDD, for example, the stable voltage outputted by the data signal terminal Da can be greater than the voltage of the first power supply terminal VDD or less than the voltage of the first power supply terminal VDD. In the picture retention period T2, the gate drive signal terminal Gate outputs an invalid level, the first enable signal terminal EM1 alternately outputs a valid level and an invalid level, the second enable signal terminal EM2 alternately outputs a valid level and an invalid level, and the valid level period of the second enable signal terminal is located in the invalid level period of the first enable signal terminal. In one aspect, the data signal terminal Da can intermittently write the stable voltage to the second node N2, and the bias of the drive transistor T3 on the first node N1 and the second node N2 is always changing, so that the setting can reduce the characteristic curve drift caused by the long-time unchanged bias of the drive transistor T3; in another aspect, when the data writing circuit 4 is turned on, the control circuit 3 is turned off, so that the stable voltage on the data signal terminal Da will not affect the normal light emission of the pixel driving circuit.

[0070] In the present exemplary embodiment, the first sub-stage of the present row of pixel driving circuits can be located in the same period as the second sub-stage of the adjacent previous row of pixel driving circuits.

[0071] It should be understood that, in other exemplary embodiments, the driving method of the pixel driving circuit can also not include the third sub-stage t3. In addition, in the present exemplary embodiment, after all the pixel driving circuits in the display panel complete scanning, the display panel enters the picture retention period T2, and in other exemplary embodiments, after each pixel driving circuit completes its own scanning, the first enable signal terminal EM1 and the second enable signal terminal EM2 can also alternately output a valid level and an invalid level at any period, i.e., the first enable signal terminal EM1 and the second enable signal terminal EM2 can also alternately output a valid level and an invalid level in the above-mentioned picture update period. Since the data signal terminals of pixel driving circuits in the same column are connected to the same data line, at this time, the pixel driving circuit can use the data signal corresponding to the unscanned pixel driving circuit to write a voltage signal different from the voltage of the first power supply terminal to the second node N2.

[0072] In the present exemplary embodiment, the first transistor T1 and the second transistor T2 are P-type low-temperature polysilicon transistors, and it should be understood that, in other exemplary embodiments, the first transistor T1 and the second transistor T2 can also be N-type transistors, for example, the first transistor T1 and the second transistor T2 can be metal oxide transistors with small drain current.

[0073] In the present exemplary embodiment, the drive transistor T3 is a P-type transistor, and it should be understood that, in other exemplary embodiments, the drive transistor T3 can also be an N-type transistor. For example, as shown in FIG. 6, the drive transistor T3 can be an N-type metal oxide transistor. Figure 7 、8 As shown, Figure 7 Structure diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. Figure 8 As Figure 7 Timing diagram of each node in the pixel driving circuit as shown. Figure 7 In the pixel driving circuit, all the transistors can be N-type transistors. Figure 8 In the pixel driving circuit, Gate is the timing of the gate driving signal end, EM1 is the timing of the first enable signal end, EM2 is the timing of the second enable signal end, Re1 is the timing of the first reset signal end, Re2 is the timing of the second reset signal end, and Da is the timing of the data signal end.

[0074] The pixel driving circuit can be applied to a display panel, the display panel can include a picture update period T1 and a picture holding period T2 in a frame driving period, in the picture update period T1, the pixel driving circuit in the display panel can be scanned line by line, and the scan period of each pixel driving circuit can include a first sub-stage t1, a second sub-stage t2, a third sub-stage t3, and a fourth sub-stage t4. In the first sub-stage t1, the first enable signal end EM1 and the gate driving signal end Gate output invalid level signals (low level signals), the first reset signal end Re1, the second reset signal end Re2, and the second enable signal end EM2 output valid level signals (high level signals), the first transistor T1 and the seventh transistor T7 are turned on, the high level signal of the first power supply end VDD is transmitted to the first node N1, and the signal of the initial signal end Vinit is transmitted to the fourth node N4. In the second sub-stage t2, the first enable signal end EM1 and the first reset signal end Re1 output low level signals, the gate driving signal end Gate, the second enable signal end EM2, and the second reset signal end Re2 output high level signals, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal end Da writes the compensation voltage Vdata+Vth to the first node N1. In the third sub-stage t3: the gate driving signal end Gate, the first enable signal end EM1, the first reset signal end Re1, and the second reset signal end Re2 output low level signals, the second enable signal end EM2 outputs a high level signal, and the voltage of the first node N1 remains unchanged. In the fourth sub-stage t4, the first reset signal end Re1, the second reset signal end Re2, the gate driving signal end Gate, and the second enable signal end EM2 output low level signals, the first enable signal end EM1 outputs a high level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and the voltage of the fourth node N4 changes from Vinit to Voled, wherein Vinit is the voltage of the initial signal end, under the coupling effect of the capacitor C, the voltage of the first node N1 changes to Vdata+Vth+Voled-Vinit, so that the output current I of the driving transistor T3 in the embodiment is (μWCox / 2L)(Vdata+Vth+Voled-Vinit-Voled-Vth) 2 =(μWCox / 2L)(Vdata-Vinit) 2In the picture retention period T2, the data signal terminal Da outputs a stable voltage which is not equal to the voltage of the first power supply terminal VDD, for example, the stable voltage outputted by the data signal terminal Da can be greater than or less than the voltage of the first power supply terminal VDD. Meanwhile, in the picture retention period T2, the gate drive signal terminal Gate inputs an invalid level, the first enable signal terminal EM1 alternately inputs a valid level and an invalid level, the second enable signal terminal EM2 alternately inputs a valid level and an invalid level, the valid level period of the second enable signal terminal is located in the invalid level period of the first enable signal terminal, and the valid level period of the first enable signal terminal is located in the invalid level period of the second enable signal terminal. In one aspect, in the present exemplary embodiment, the data signal terminal Da can intermittently write the stable voltage to the second node N2, and the bias of the driving transistor T3 on the first node N1 and the second node N2 is always changing, so that the setting can reduce the characteristic curve drift caused by the long-time unchanged bias of the driving transistor T3; on the other hand, when the data writing circuit 4 is turned on, the control circuit 3 is turned off, so that the stable voltage on the data signal terminal Da will not affect the normal light emission of the pixel driving circuit.

[0075] The present exemplary embodiment further provides a driving method of a pixel driving circuit, used for driving the pixel driving circuit described above, wherein the driving method comprises:

[0076] In the first stage:

[0077] In a first sub-stage, the gate drive signal terminal and the second enable signal terminal output a valid level, and the first enable signal terminal outputs an invalid level;

[0078] In a second sub-stage, the first enable signal terminal outputs a valid level, and the second enable signal terminal and the gate drive signal terminal output an invalid level;

[0079] In the second stage, the gate drive signal terminal outputs an invalid level, the first enable signal terminal alternately outputs a valid level and an invalid level, and the second enable signal terminal alternately outputs a valid level and an invalid level;

[0080] Wherein, the valid level period of the second enable signal terminal is located in the invalid level period of the first enable signal terminal, and in the second stage, the level written to the second node by the data signal terminal is at least partially not equal to the voltage of the first power supply terminal.

[0081] In the example embodiment, the pixel driving circuit is applied to a display panel, and a frame period of the display panel includes a picture update period and a picture maintaining period. In the frame period, the first stage of all pixel driving circuits in the display panel is located in the picture update period, and the second stage of all pixel driving circuits in the display panel is located in the picture maintaining period.

[0082] The driving method of the pixel driving circuit has been described in detail above, and will not be repeated here.

[0083] The example embodiment also provides a display panel, which can include the pixel driving circuit described above. As shown in Figure 5 , the pixel driving circuit in the display panel can be as described above. The display panel can also include a substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, which are sequentially stacked, and an insulating layer is arranged between each of the layers. As shown in Figures 9-17 , Figure 9 The structural layout of an example embodiment of the display panel of the present disclosure is shown in Figure 10 , Figure 9 The structural layout of the active layer in Figure 11 , Figure 9 The structural layout of the first conductive layer in Figure 12 , Figure 9 The structural layout of the second conductive layer in Figure 13 , Figure 9 The structural layout of the third conductive layer in Figure 14 , Figure 9 The structural layout of the fourth conductive layer in Figure 15 , Figure 9 The structural layout of the active layer and the first conductive layer in Figure 16 , Figure 9 The structural layout of the active layer, the first conductive layer, and the second conductive layer in Figure 17 , Figure 9 The structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in

[0084] As shown in Figure 9 , 10As shown in Figure 15, the active layer may include a first active portion 51, a second active portion 52, a third active portion 53, a fourth active portion 54, a fifth active portion 55, a sixth active portion 56, a seventh active portion 57, an eighth active portion 58, a ninth active portion 59, a tenth active portion 510, an eleventh active portion 511, a twelfth active portion 512, a third sub-active portion 513, and a sixth sub-active portion 526. The first active portion 51 is used to form the channel region of the first transistor T1, the second active portion 52 is used to form the channel region of the second transistor T2, the third active portion 53 is used to form the channel region of the driving transistor T3, the fourth active portion 54 is used to form the channel region of the fourth transistor T4, the fifth active portion 55 is used to form the channel region of the fifth transistor T5, the sixth active portion 56 is used to form the channel region of the sixth transistor T6, and the seventh active portion 57 is used to form the channel region of the seventh transistor T7. The first transistor T1 and the second transistor T2 are dual-gate structures. Correspondingly, the first active portion 51 may include a first sub-active portion 501 and a second sub-active portion 502, with a third sub-active portion 513 connected between the first sub-active portion 501 and the second sub-active portion 502. The second active portion 52 may include a fourth sub-active portion 524 and a fifth sub-active portion 525, with a sixth sub-active portion 526 connected between the fourth sub-active portion 524 and the fifth sub-active portion 525. An eighth active portion 58 is connected between the fifth active portion 55 and the third active portion 53; a ninth active portion 59 is connected to one side of the fourth active portion 54; a tenth active portion 510 is connected to the end of the first active portion 51 away from the second active portion 52; an eleventh active portion 511 is connected to the end of the seventh active portion 57 away from the sixth active portion 56; and a twelfth active portion 512 is connected between the second active portion 52 and the first active portion 51. The active layer can be formed from polycrystalline silicon.

[0085] like Figure 9 , 11 As shown in Figure 15, the first conductive layer may include a reset signal line Re, a gate line Gate, a first enable signal line EM1, a second enable signal line EM2, and a first conductive portion 11. The reset signal line Re can be used to provide... Figure 5 The reset signal terminal in the circuit, the gate line can be used to provide... Figure 5 The gate drive signal terminal in the middle, the first enable signal line EM1 can be used to provide Figure 5 The first enable signal terminal and the second enable signal line EM2 can be used to provide... Figure 5The second enable signal end in the display panel. The orthogonal projection of the reset signal line Re on the substrate, the orthogonal projection of the gate line Gate on the substrate, the orthogonal projection of the first enable signal line EM1 on the substrate, the orthogonal projection of the second enable signal line EM2 on the substrate can extend along the first direction X. The first direction X can be the row direction of the display panel, and the pixel driving circuit in the display panel can be driven row by row. In the present exemplary embodiment, the orthogonal projection of a certain structure on the substrate extends along a certain direction, which can be understood as that the orthogonal projection of the structure on the substrate extends linearly or bends along the direction. The orthogonal projection of the reset signal line Re on the substrate can cover the orthogonal projection of the first active part 51 on the substrate, and part of the structure of the reset signal line Re can be used to form the gate of the first transistor T1. The orthogonal projection of the first conductive part 11 on the substrate covers the third active part 53, and the first conductive part 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor. The orthogonal projection of the first enable signal line EM1 on the substrate covers the orthogonal projection of the fifth active part 55 on the substrate and the orthogonal projection of the sixth active part 56 on the substrate, and part of the structure of the first enable signal line EM1 can be used to form the gate of the fifth transistor T5 and the gate of the sixth transistor T6, respectively. The orthogonal projection of the second enable signal line EM2 on the substrate covers the orthogonal projection of the fourth active part 54 on the substrate and the orthogonal projection of the seventh active part 57 on the substrate, and part of the structure of the second enable signal line EM2 can be used to form the gate of the fourth transistor and the gate of the seventh transistor T7, respectively. The orthogonal projection of the gate line Gate on the substrate covers the orthogonal projection of the second active part 52 on the substrate, and part of the structure of the gate line Gate can be used to form the gate of the second transistor T2. As shown in FIGS. Figure 9 、 11 , 15, the orthogonal projection of the reset signal line Re on the substrate, the orthogonal projection of the gate line Gate on the substrate, the orthogonal projection of the first conductive part 11 on the substrate, the orthogonal projection of the first enable signal line EM1 on the substrate, and the orthogonal projection of the second enable signal line EM2 on the substrate can be distributed along the second direction Y in sequence. The second direction Y can intersect the first direction X, for example, the second direction Y can be the column direction of the display panel. The orthogonal projection of the ninth active part 59 on the substrate can be located between the orthogonal projection of the first enable signal line EM1 on the substrate and the orthogonal projection of the second enable signal line EM2 on the substrate. In the present exemplary embodiment, the display panel can perform conductorization processing on the active layer by taking the first conductive layer as a mask, that is, the region of the active layer covered by the first conductive layer forms the channel region of the transistor, and the region of the active layer not covered by the first conductive layer forms the conductor structure.

[0086] As shown in FIGS. Figure 9 ,12 As shown in Figure 16, the second conductive layer may include a first initial signal line Vinit1, a second initial signal line Vinit2, and a second conductive portion 22. The first initial signal line Vinit1 can be used to provide... Figure 5 The first initial signal terminal and the second initial signal line Vinit2 can be used to provide... Figure 5 The second initial signal terminal in the [theory / mechanism]. The orthographic projections of the first initial signal line Vinit1 and the second initial signal line Vinit2 on the substrate can both extend along the first direction X. The orthographic projection of the first initial signal line Vinit1 on the substrate can be located on the side of the reset signal line Re on the substrate away from the orthographic projection of the first conductive part 11 on the substrate. The orthographic projection of the second initial signal line Vinit2 on the substrate can be located on the side of the second enable signal line EM2 on the substrate away from the orthographic projection of the first conductive part 11 on the substrate.

[0087] like Figure 9 , 12 As shown in Figure 16, the display panel in this exemplary embodiment may include multiple rows of pixel driving circuits. The orthographic projection of the second initial signal line Vinit2 in the pixel driving circuit of this row onto the substrate may be located between the orthographic projection of the reset signal line Re in the pixel driving circuit of the adjacent next row onto the substrate and the orthographic projection of the gate line Gate onto the substrate. Figure 12 As shown, the second initial signal line Vinit2 located at the top is the second initial signal line Vinit2 in the pixel driving circuit of the previous row. Figure 11 As shown, the reset signal line Re located below is the reset signal line Re in the next row of pixel driving circuits. This arrangement can improve the integration of the pixel driving circuit. The orthographic projection of the second conductive part 22 on the substrate can at least partially overlap with the orthographic projection of the first conductive part 11 on the substrate, and the second conductive part 22 can be used to form the second electrode of the capacitor C. The second conductive parts 22 in the pixel driving circuits located in the same row can be interconnected.

[0088] like Figure 9 , 12As shown in FIG. 16, the second initial signal line Vinit2 can include a main line Vinit20, a first protruding part Vinit21, a second protruding part Vinit22, and a third protruding part Vinit23. The orthogonal projection of the main line Vinit20 on the substrate substrate extends along the first direction X. The first protruding part Vinit21 is connected to the main line Vinit20, and the orthogonal projection of the first protruding part Vinit20 on the substrate substrate extends along the second direction Y. The second protruding part Vinit22 is connected to the main line Vinit20, and the orthogonal projection of the second protruding part Vinit22 on the substrate substrate extends along the second direction Y. The third protruding part Vinit23 is connected to the main line Vinit20, the orthogonal projection of the third protruding part Vinit23 on the substrate substrate extends along the second direction Y, and the orthogonal projection of the third protruding part Vinit23 on the substrate substrate is located on the side of the orthogonal projection of the main line Vinit20 on the substrate substrate away from the orthogonal projection of the second protruding part Vinit22 on the substrate substrate. The orthogonal projection of the first protruding part Vinit21 of the second initial signal line Vinit2 in the pixel driving circuit of the above row on the substrate substrate at least partially overlaps with the orthogonal projection of the sixth sub-active part 526 in the pixel driving circuit of the current row on the substrate substrate, and the second initial signal line Vinit2 can stabilize the voltage of the sixth sub-active part 526, thereby reducing the leakage current of the sixth sub-active part 526 to the source-drain electrode of the second transistor T2. The orthogonal projection of the second protruding part Vinit22 and the third protruding part Vinit23 of the second initial signal line Vinit2 in the pixel driving circuit of the above row on the substrate substrate at least partially overlaps with the orthogonal projection of the twelfth active part 512 in the pixel driving circuit of the current row on the substrate substrate, and the second initial signal line Vinit2 can stabilize the voltage of the twelfth active part 512, thereby reducing the fluctuation of the gate voltage of the transistor driven by the pixel driving circuit in the light-emitting stage. The orthogonal projection of the first initial signal line Vinit1 on the substrate substrate can at least partially overlap with the orthogonal projection of the third sub-active part 513 on the substrate substrate, and the first initial signal line Vinit1 can stabilize the voltage of the third sub-active part 513, thereby reducing the leakage current of the third sub-active part 513 to the source-drain electrode of the first transistor T1.

[0089] As Figure 9 , 13As shown in Figure 17, the third conductive layer may include a first connecting portion 31, a second connecting portion 32, a third connecting portion 33, a fourth connecting portion 34, a fifth connecting portion 35, a sixth connecting portion 36, and a seventh connecting portion 37. The first connecting portion 31 can connect to the eighth active portion 58 and the ninth active portion 59 via vias H, thereby connecting the second electrode of the fourth transistor T4 and the first electrode of the driving transistor T3. It should be noted that the vias H in this exemplary embodiment are represented by black squares, and only the positions of some vias are marked in this exemplary embodiment. The second connecting portion 32 can connect to the first initial signal line Vinit1 and the tenth active portion 510 via vias, thereby connecting the first electrode of the first transistor T1 and the first initial signal terminal. The third connecting portion 33 can connect to the eleventh active portion 511 and the second initial signal line Vinit2 via vias, thereby connecting the first electrode of the seventh transistor and the second initial signal terminal. The fourth connection portion 34 can be connected to the first conductive portion 11 and the twelfth active portion 512 respectively through vias, so as to connect the gate of the driving transistor T3, the first electrode of the second transistor T2, and the second electrode of the first transistor T1. For example... Figure 12 As shown, the second conductive portion 22 has an opening 221. The orthographic projection of the via connecting the first conductive portion 11 and the fourth connecting portion 34 on the substrate is located within the orthographic projection of the opening 221 on the substrate, to prevent the via connecting the first conductive portion 11 and the fourth connecting portion 34 from being electrically connected to the second conductive portion 22. The fifth connecting portion 35 can be connected to the active layer between the sixth active portion 56 and the seventh active portion 57 through a via, to connect to the second electrode of the sixth transistor T6. The sixth connecting portion 36 can be connected to the active layer of the fourth active portion 54 on the side away from the ninth active portion 59 through a via, to connect to the first electrode of the fourth transistor T4. The seventh connecting portion 37 can be connected to the active layers of the second conductive portion 22 and the fifth active portion 55 on the side away from the third active portion 53 through vias, respectively, to connect the first electrode of the fifth transistor T5 and the second electrode of the capacitor.

[0090] like Figure 9 , 14 As shown, the fourth conductive layer may include a data line Da, a power line VDD, and an eighth connection portion 48. The data line Da can be used to provide... Figure 5 The data signal terminal in the middle, the power line VDD can be used to provide Figure 5The first power supply terminal, the orthographic projection of data line Da on the substrate, and the orthographic projection of power line VDD on the substrate can extend along the second direction Y. Data line Da can be connected to the sixth connection portion 36 through via H to connect the first electrode of the fourth transistor T4 and the data signal terminal. Power line VDD can be connected to the seventh connection portion 37 through via to connect the first power supply terminal and the first electrode of the fifth transistor and the second electrode of capacitor C. The eighth connection portion 48 can be connected to the fifth connection portion 35 through via via to connect the second electrode of the sixth transistor. The eighth connection portion 48 can be used to connect the first electrode of the light-emitting unit.

[0091] like Figure 18 As shown, Figure 9 The partial cross-sectional view along the dashed line CC in the shown display panel further includes a first insulating layer 62, a second insulating layer 63, a dielectric layer 64, a passivation layer 65, and a planarization layer 66. The substrate 61, active layer, first insulating layer 62, first conductive layer, second insulating layer 63, second conductive layer, dielectric layer 64, third conductive layer, passivation layer 65, planarization layer 66, and fourth conductive layer are sequentially stacked. The first insulating layer 62 and second insulating layer 63 can be silicon oxide layers; the dielectric layer 64 and passivation layer 65 can be silicon nitride layers; the planarization layer 66 can be made of organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The substrate 61 may include a polyimide layer, and the materials of the first conductive layer and the second conductive layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy, or a stack thereof. The materials of the third and fourth conductive layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or titanium / aluminum / titanium stacks.

[0092] This exemplary embodiment also provides a display device, wherein the display device includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0093] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0094] It should be understood that the present disclosure is not limited to the precise construction that has been described above and shown in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the present disclosure. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein, The display panel comprises a pixel driving circuit for driving a light emitting unit, the pixel driving circuit comprises: a driving transistor; a second transistor, a first electrode of which is connected to a gate electrode of the driving transistor, a second electrode of which is connected to a second electrode of the driving transistor, and a gate electrode of which is connected to a gate line; a fourth transistor, a first electrode of which is connected to a data line, a second electrode of which is connected to a first electrode of the driving transistor, and a gate electrode of which is connected to a second enable signal line; a fifth transistor, a first electrode of which is connected to a power supply line, a second electrode of which is connected to the first electrode of the driving transistor, and a gate electrode of which is connected to a first enable signal line; a sixth transistor, a first electrode of which is connected to the second electrode of the driving transistor, a second electrode of which is connected to a first electrode of the light emitting unit, and a gate electrode of which is connected to the first enable signal line; The display panel further comprises: a substrate; an active layer located on one side of the substrate, the active layer comprising a second active part, a third active part, a fourth active part, a fifth active part, and a sixth active part, the second active part being used to form a channel region of the second transistor, the third active part being used to form a channel region of the driving transistor, the fourth active part being used to form a channel region of the fourth transistor, the fifth active part being used to form a channel region of the fifth transistor, and the sixth active part being used to form a channel region of the sixth transistor; a first conductive layer located on a side of the active layer away from the substrate, the first conductive layer comprising the first enable signal line, the second enable signal line, the gate line, and a first conductive part; wherein a projection of the first conductive part on the substrate covers a projection of the third active part on the substrate, and the first conductive part is used to form a gate electrode of the driving transistor; a projection of the first enable signal line on the substrate extends along a first direction and covers a projection of the fifth active part on the substrate and a projection of the sixth active part on the substrate, and part of the structure of the first enable signal line is used to form a gate electrode of the fifth transistor and a gate electrode of the sixth transistor; a projection of the second enable signal line on the substrate extends along the first direction and covers a projection of the fourth active part on the substrate, and part of the structure of the second enable signal line is used to form a gate electrode of the fourth transistor; a projection of the gate line on the substrate extends along the first direction and covers a projection of the second active part on the substrate, and part of the structure of the gate line is used to form a gate electrode of the second transistor; The pixel driving circuit further comprises: a first transistor, a first electrode of which is connected to a first initial signal line, a second electrode of which is connected to a gate electrode of the driving transistor, and a gate electrode of which is connected to a reset signal line; a seventh transistor, a first electrode of which is connected to a second initial signal line, a second electrode of which is connected to a first electrode of the light emitting unit, and a gate electrode of which is connected to the second enable signal line; The active layer further comprises a first active part and a seventh active part, the first active part being used to form a channel region of the first transistor, and the seventh active part being used to form a channel region of the seventh transistor. The normal projection of the second initial signal line and the reset signal line on the substrate substrate extends along the first direction; The first direction is a row direction, and the display panel includes a plurality of rows of pixel drive circuits; the normal projection of a second initial signal line in a current row of pixel drive circuits on the substrate substrate is located between the normal projection of a reset signal line and the normal projection of a gate line in an adjacent next row of pixel drive circuits on the substrate substrate; The second active part includes a fourth sub-active part and a fifth sub-active part, and the active layer further includes a sixth sub-active part connected between the fourth sub-active part and the fifth sub-active part; The second initial signal line includes: A main line, the normal projection of which on the substrate substrate extends along the first direction; A first protruding part connected to the main line, and the normal projection of the first protruding part on the substrate substrate extends along a second direction intersecting the first direction; The normal projection of the first protruding part on the substrate substrate in a previous row of pixel drive circuits at least partially overlaps the normal projection of the sixth sub-active part on the substrate substrate in a current row of pixel drive circuits; The active layer further includes a twelfth active part connected between the first active part and the second active part; The second initial signal line includes: A second protruding part connected to the main line, and the normal projection of the second protruding part on the substrate substrate extends along a second direction; The normal projection of the second protruding part on the substrate substrate in a previous row of pixel drive circuits at least partially overlaps the normal projection of the twelfth active part on the substrate substrate in a current row of pixel drive circuits.

2. The display panel of claim 1, wherein, The normal projection of the first enable signal line on the substrate substrate is located between the normal projection of the second enable signal line on the substrate substrate and the normal projection of the first conductive part on the substrate substrate; The active layer further includes: An eighth active part connected between the third active part and the fifth active part; A ninth active part connected to the fourth active part, and the normal projection of the ninth active part on the substrate substrate is located between the normal projection of the first enable signal line on the substrate substrate and the normal projection of the second enable signal line on the substrate substrate; The display panel further includes: A third conductive layer located on a side of the first conductive layer away from the substrate substrate, and the third conductive layer includes a first connecting part, and the first connecting part is connected to the eighth active part and the ninth active part through a via hole respectively.

3. The display panel of claim 1, wherein, The pixel drive circuit further includes: A capacitor connected between the power supply line and the gate of the drive transistor; The drive transistor, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors; The first conductive layer further includes a reset signal line, and the normal projection of the reset signal line on the substrate substrate covers the normal projection of the first active part on the substrate substrate, and part of the structure of the reset signal line is used to form a gate of the first transistor; A projection of the second enable signal line on the substrate substrate also covers the seventh active part, and a partial structure of the second enable signal line is used to form a gate of the seventh transistor; The display panel further includes a second conductive layer located on a side of the first conductive layer away from the substrate substrate, and the second conductive layer includes: A second conductive part, a projection of the second conductive part on the substrate substrate at least partially overlaps with a projection of the first conductive part on the substrate substrate, wherein the first conductive part is also used to form a first electrode of the capacitor, and the second conductive part is used to form a second electrode of the capacitor; A projection of the gate line on the substrate substrate is located on a side of a projection of the first conductive part on the substrate substrate away from a projection of the first enable signal line on the substrate substrate; A projection of the reset signal line on the substrate substrate is located on a side of a projection of the gate line on the substrate substrate away from a projection of the first conductive part on the substrate substrate.

4. The display panel of claim 3, wherein, The active layer further includes a tenth active part and an eleventh active part, the tenth active part is connected to an end of the first active part away from the second active part, and the eleventh active part is connected to an end of the seventh active part away from the sixth active part; The second conductive layer further includes: The first initial signal line, a projection of the first initial signal line on the substrate substrate extends along the first direction, and the projection of the first initial signal line on the substrate substrate is located on a side of a projection of the reset signal line on the substrate substrate away from a projection of the first conductive part on the substrate substrate; The second initial signal line, a projection of the second initial signal line on the substrate substrate is located on a side of a projection of the second enable signal line on the substrate substrate away from a projection of the first conductive part on the substrate substrate; The display panel further includes a third conductive layer located on a side of the second conductive layer away from the substrate substrate, and the third conductive layer includes: A second connection part, the second connection part is connected to the tenth active part and the first initial signal line through a via hole respectively; A third connection part, the third connection part is connected to the second initial signal line and the eleventh active part through a via hole respectively.

5. The display panel of claim 3, wherein, The first active part includes a first sub-active part and a second sub-active part, and the active layer further includes a third sub-active part connected between the first sub-active part and the second sub-active part; A projection of the first initial signal line on the substrate substrate at least partially overlaps with a projection of the third sub-active part on the substrate substrate.

6. The display panel of claim 1, wherein, The second initial signal line further includes: A third protruding part connected to the main body line, a projection of the third protruding part on the substrate substrate extends along the second direction, and the projection of the third protruding part on the substrate substrate is located on a side of a projection of the main body line on the substrate substrate away from a projection of the second protruding part on the substrate substrate; The third protruding part in the pixel driving circuit of the above row has a normal projection on the substrate which at least partially overlaps with the twelfth active part in the pixel driving circuit of the present row.

7. The display panel of claim 1, wherein, The signal on the first enable signal line and the signal on the second enable signal line are opposite in logic level.

8. A display device, wherein, The display device comprises the display panel of any one of claims 1-7.

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