Semiconductor Structure and Method of Fabricating the Same

Abstract

The present invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a resistive random access memory located on the substrate, which includes an upper electrode, a lower electrode, and a resistive switching layer located between the upper electrode and the lower electrode, and a capping layer covering the outside of the resistive random access memory. The capping layer has an upper half and a lower half, and the stresses included in the upper half and the lower half are different.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and more particularly to a resistive random access memory (RRAM) having a capping layer with different stresses. Background Art

[0002] Resistive random access memory (RRAM) has the advantages of simple structure, low operating voltage, high operation speed, good durability, and compatibility with CMOS manufacturing processes. RRAM is the most promising alternative to traditional flash memory for the purpose of reducing the element size. RRAM is widely used in various components such as optical discs and non-volatile memory arrays.

[0003] The RRAM cell stores data in a material layer that can be induced to undergo a phase change. In all or part of the layer, the material can undergo a phase change and switch between a high-resistance state and a low-resistance state. After different resistance states are detected, they can be represented as "0" or "1". In a typical RRAM cell, the data storage layer includes an amorphous metal oxide. After applying a sufficient voltage, the voltage can form a metal bridge across the data storage layer, thus forming a low-resistance state. Then, by applying a pulse with a high current density or in other ways, all or part of the metal structure can be decomposed or melted to break the metal bridge and restore the high-resistance state. Then, when the data storage layer is rapidly cooled, it will change back to the low-resistance state from the high-resistance state again. Summary of the Invention

[0004] The present invention provides a semiconductor structure, comprising a substrate, a resistive random access memory located on the substrate, including an upper electrode, a lower electrode, and a resistive switching layer located between the upper electrode and the lower electrode, and a capping layer covering the outside of the resistive random access memory, wherein the capping layer has an upper half and a lower half, and the stresses contained in the upper half and the lower half are different.

[0005] The present invention further provides a method for forming a semiconductor structure, comprising providing a substrate, forming a resistive random access memory on the substrate, the resistive random access memory including an upper electrode, a lower electrode, and a resistive switching layer located between the upper electrode and the lower electrode, and forming a capping layer covering the outside of the resistive random access memory, wherein the capping layer has an upper half and a lower half, and the stresses contained in the upper half and the lower half are different.

[0006] The present invention is characterized in that, before the initialization (Forming) step, ion doping is first performed on the capping layer covering the resistive random access memory to form a stress gradient (i.e., the stress gradually changes with different positions) inside the capping layer to conform to the lattice arrangement required by the Forming step, reduce the energy required for the subsequent Forming step, and can accelerate the carrier migration rate of the resistive random access memory and improve the quality of the resistive random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 5 It is a schematic diagram of manufacturing a semiconductor structure according to the first preferred embodiment of the present invention.

[0008] LIST OF MAIN ELEMENT SYMBOLS

[0009] 100: Resistive random access memory

[0010] 102: Dielectric layer

[0011] 104: Contact structure

[0012] 110: Lower electrode

[0013] 112: Resistive switching layer

[0014] 114: Upper electrode

[0015] 119: Recessed notch

[0016] 120: Capping layer

[0017] 121: Tapered capping layer

[0018] 122: Upper half

[0019] 124: Lower half

[0020] 130: Dielectric layer

[0021] 132: Contact structure

[0022] A1: First angle

[0023] A2: Second angle

[0024] P1: Partial etching step

[0025] P2: First ion doping step

[0026] P3: Second ion doping step DETAILED DESCRIPTION OF THE INVENTION

[0027] To enable those of ordinary skill in the art to which the present invention pertains to further understand the present invention, the following specifically lists the preferred embodiments of the present invention and, in conjunction with the accompanying drawings, details the composition and the desired effects of the present invention.

[0028] For ease of explanation, the drawings of the present invention are only schematic for easier understanding of the present invention, and their detailed proportions can be adjusted according to the design requirements. Regarding the up-and-down relationship of the relative components in the drawings described in the text, those skilled in the art should understand that it refers to the relative positions of the objects. Therefore, they can all be flipped to present the same components, and this should all fall within the scope disclosed in this specification. This is hereby stated in advance.

[0029] Please refer to Figures 1 to 5 , Figures 1 to 5 FIG. showing a schematic diagram of fabricating a semiconductor structure according to a first preferred embodiment of the present invention. As Figure 1 shown, first, a resistive random access memory (RRAM) 100 is provided and electrically connected to a contact structure 104. Among them, the contact structure 104 may be located in a single-layer or multi-layer dielectric layer, and it may be electrically connected to another contact structure or wire below. Taking this embodiment as an example, the contact structure 104 is located in the dielectric layer 102, and there is another wire (not shown in the figure) below the contact structure 104, and the wire is electrically connected to the contact structure. The dielectric layer 102 described here is, for example, one of the inter-metal dielectric (IMD) layers in the semiconductor structure, and the wire and the contact structure 104 are, for example, wires or conductive vias located in the IMD. The material of the dielectric layer 102 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., and the wire and the contact structure 104 include, for example, conductive materials such as metals such as tungsten, cobalt, copper, aluminum, or other conductive materials. The present invention is not limited thereto.

[0030] The resistive random access memory 100 is located on the dielectric layer 102 and is electrically connected to the contact structure 104. Generally, the resistive random access memory 100 may at least include a lower electrode 110, a resistive switching layer 112, and an upper electrode 114. Among them, the materials of the lower electrode 110 and the upper electrode 114 are, for example, conductive materials such as titanium, tantalum, titanium nitride, tantalum nitride, etc., and the resistive switching layer 112 includes, for example, a dielectric material with a dielectric constant greater than 4, such as selected from hafnium oxide (hafnium oxide, HfO2), hafnium silicon oxide (hafnium silicon oxide, HfSiO4), hafnium silicon oxynitride (hafnium siliconoxynitride, HfSiON), aluminum oxide (aluminum oxide, Al2O3), lanthanum oxide (lanthanum oxide, La2O3), tantalum oxide (tantalum oxide, Ta2O5), yttrium oxide (yttrium oxide, Y2O3), zirconium oxide (zirconiumoxide, ZrO2), strontium titanate oxide (strontium titanate oxide, SrTiO3), zirconium silicon oxide (zirconiumsilicon oxide, ZrSiO4), hafnium zirconium oxide (hafnium zirconium oxide, HfZrO4), strontium bismuth tantalate (strontium bismuth tantalate, SrBi2Ta2O9, SBT), lead zirconate titanate (lead zirconate titanate, PbZr x Ti 1-x O3, PZT), barium strontium titanate (barium strontium titanate, Ba x Sr 1-x TiO3, BST), or a group consisting of a combination thereof.

[0031] In addition, in addition to the above materials, the resistive random access memory 100 may also include more material layers, which also fall within the scope of the present invention. Taking one embodiment of the present invention as an example, the resistive random access memory 100 sequentially includes a lower electrode (material: TaN), a resistive switching layer (material: Ta2O5), a metal layer (material: iridium (Ir)), and an upper electrode (material: TaN) from bottom to top. This structure also falls within the scope of the present invention. However, it should be noted that this structure is only one example of the present invention, and the resistive random access memory composed of other materials also falls within the scope of the present invention.

[0032] Next, a partial etching step is performed on the resistive random access memory 100 to remove a part of the resistive random access memory 100 and form a resistive random access memory 100 having a profile with a narrower upper part and a wider lower part. More specifically, the partial etching step P1 is, for example, ion beam etching. The angle of the ion beam etching is adjusted so that a larger volume of the upper electrode 114 and the resistive switching layer 112 is removed, while a smaller volume of the lower electrode 110 is removed. Therefore, after the ion beam etching is completed, the width of the upper electrode 114 of the resistive random access memory 100 ( Figure 1 the width W1 marked therein) will be smaller than the width of the lower electrode 110 ( Figure 1 the width W2 marked therein). In addition, in some embodiments, the angle of the partial etching step P1 can be adjusted so that a recessed notch 119 is formed between the lower electrode 110 and the resistive switching layer 112.

[0033] Next, as Figure 2 shown, after the resistive random access memory 100 is formed, a capping layer 120 is formed on the surface of the resistive random access memory 100. The material of the capping layer 120 is, for example, silicon nitride. Additionally, when the capping layer 120 is formed on the surface of the recessed notch 119, the capping layer 120 stays on the recessed notch 119 and forms an inclined capping layer 121 beside the resistive switching layer 112 of the resistive random access memory 100.

[0034] After a general resistive random access memory is produced, the newly produced variable resistive memory will be initialized first. This process is called Forming. During the Forming process, a bias voltage is applied to the resistive random access memory. When the electric field exceeds the critical value, dielectric breakdown occurs in the dielectric layer, causing the dielectric layer to change from a high resistance state to a low resistance state. And for the phenomenon of changing the resistance value after Forming, if the process from a high resistance state to a low resistance state is called SET, conversely, the process from a low resistance state to a high resistance state is called RESET. After the above Forming step is completed, the applicant found that the stress of the capping layer covering the resistive random access memory will also change accordingly. Among them, the capping layer on the upper half of the resistive random access memory (such as above the horizontal center line of the resistive switching layer) is prone to exhibit compressive force, while the capping layer on the lower half of the resistive random access memory (such as below the horizontal center line of the resistive switching layer) is prone to exhibit tensile force. The reason for this phenomenon may be that during the Forming process, the migration of oxygen atoms causes the lattice arrangement of the capping layer to change.

[0035] The applicant has found that if the stress of the capping layer covering the resistive random access memory is actively adjusted before the Forming step, it may be possible to reduce the energy required for the Forming step. In addition, the characteristics of the resistive random access memory (such as increasing the migration rate of oxygen atoms, etc.) can also be finely adjusted by adjusting the stress of the capping layer.

[0036] To achieve the above object, after forming the capping layer 120 covering the resistive random access memory 100, as Figures 3 to 4 shown, the capping layer 120 is subjected to more than two ion doping steps, wherein the two ion doping steps dope the capping layer 120 at different angles, different types of ions are doped into different regions of the capping layer, and a stress gradient (stress gradient), that is, a structure in which the stress gradually changes with position, is formed within the capping layer 120.

[0037] More specifically, taking this embodiment as an example, Figure 3 a first ion doping step P2 is first performed on the capping layer 120. The ions doped in the first ion doping step P2 are, for example, boron ions, and the ion doping is performed on the capping layer 120 in a direction at a first angle A1 with respect to the horizontal plane. The angle between the first angle A1 and the horizontal plane (such as the X direction) is preferably greater than 60 degrees. Since the size of the above boron ions is smaller than the lattice of other atoms (nitrogen atoms, silicon atoms) inside the capping layer 120, the capping layer 120 exhibits tensile stress. Additionally, it is worth noting that the above beveled capping layer 121 can help collect more doping ions during the first ion doping step P2, so the stress change in the region next to the resistive switching layer 112 of the resistive random access memory 100 will be more obvious.

[0038] Then, as Figure 4As shown, a second ion doping step P3 is then performed on the capping layer 120. The ions doped in this second ion doping step P3 are, for example, phosphorus, argon, germanium ions, etc., and ion doping is performed on the capping layer 120 in a direction at a second angle A2 with respect to the horizontal direction (X-axis). In the present invention, the first angle A1 is different from the second angle A2, and preferably the first angle A1 is greater than the second angle A2. In this embodiment, the angle between the second angle A2 and the horizontal plane (e.g., the X direction) is preferably less than 45 degrees. Since the above-mentioned boron ions are relatively large in size, they will squeeze the lattices of other atoms (nitrogen atoms, silicon atoms) inside the capping layer 120, causing the capping layer 120 to exhibit stress. The second ion doping step P3 mainly performs ion doping on the upper half 122 of the capping layer 120 (e.g., the part above the horizontal midline of the resistive switching layer 112). Therefore, after the second ion doping step P3 is performed, the upper half of the capping layer 120 will be converted into stress, while the lower half 124 of the capping layer 120 (e.g., the part below the horizontal midline of the resistive switching layer 112) may still maintain tensile stress. In this embodiment, the capping layer 120 has different degrees of stress combinations in the upper half 122 and the lower half 124. For example, the upper half 122 contains compressive stress, and the lower half 124 contains tensile stress; or the upper half 122 contains a relatively large compressive stress, and the lower half 124 contains a relatively small compressive stress, etc. In addition, there is a junction 126 between the upper half 122 and the lower half 124, and the junction 126 overlaps with the resistive switching layer 122 in the horizontal direction (X direction).

[0039] Next, please refer to the figure, as Figure 5 shown, a dielectric layer 130 is formed to cover the resistive random access memory 100 and outside the capping layer 120. The dielectric layer 130 is, for example, a dielectric material with an ultra-low dielectric constant (ultra low-k, ULK), and its dielectric constant is preferably lower than 2.9, but not limited thereto. Commonly used ULK materials may include Black Diamond (a low dielectric constant material of carbon-doped silicon oxide introduced by Applied Materials), MSQ (methylsilsesquioxane), etc., porous SiLK (a low dielectric constant material developed by Dow Chemical), etc., but not limited thereto. Then an opening (not shown) is formed in the dielectric layer 130, and after filling a conductive material (not shown) in the opening and performing planarization and other steps, a contact structure 132 is formed in the opening, where the contact structure 132 is electrically connected to the upper electrode 114 of the resistive random access memory 100. The contact structure 132 may include a conductive material, such as tungsten, cobalt, copper, aluminum, etc.

[0040] Therefore, referring to the above Figures 1 to 5 , the present invention provides a semiconductor structure and a manufacturing method thereof.

[0041] According to an embodiment of the present invention, a semiconductor structure is provided, including a substrate (dielectric layer 102), a resistive random access memory 100 located on the substrate, including a top electrode 114, a bottom electrode 110, and a resistive switching layer 112 located between the top electrode 114 and the bottom electrode 112, and a capping layer 120 covering the outside of the resistive random access memory 100, wherein the capping layer 120 has an upper half 122 and a lower half 124, and the stresses included in the upper half 122 and the lower half 124 are different.

[0042] According to an embodiment of the present invention, a method for forming a semiconductor structure is provided, including providing a substrate (dielectric layer 102), forming a resistive random access memory 100 on the substrate, the resistive random access memory including a top electrode 114, a bottom electrode 110, and a resistive switching layer 112 located between the top electrode 114 and the bottom electrode 110, and forming a capping layer 120 covering the outside of the resistive random access memory 100, wherein the capping layer 120 has an upper half 122 and a lower half 124, and the stresses included in the upper half 122 and the lower half 124 are different.

[0043] In some embodiments of the present invention, the upper half 122 includes compressive stress, and the lower half 124 includes tensile stress.

[0044] In some embodiments of the present invention, the upper half 122 includes a larger compressive stress, and the lower half 124 includes a smaller compressive stress.

[0045] In some embodiments of the present invention, a horizontal width W1 of the top electrode is smaller than a horizontal width W2 of the bottom electrode.

[0046] In some embodiments of the present invention, a junction 126 is included between the upper half 122 and the lower half 124, and the junction 126 overlaps with the resistive switching layer 112 of the resistive random access memory 100 in a horizontal direction (X-axis).

[0047] In some embodiments of the present invention, the material of the capping layer 120 includes silicon nitride.

[0048] In some embodiments of the present invention, the lower half 124 includes a first ion, and the first ion includes boron ions.

[0049] In some embodiments of the present invention, the upper half 122 includes a second ion, and the second ion includes phosphorus ions, germanium ions, or argon ions.

[0050] In some embodiments of the present invention, after the capping layer 120 is formed, a first ion doping step P2 and a second ion doping step P3 are further included to dope different ions into the capping layer 120 respectively.

[0051] In some embodiments of the present invention, when the first ion doping step P2 and the second ion doping step P3 are carried out, the doping angles for the capping layer 120 are different (the first angle A1 and the second angle A2 respectively).

[0052] In some embodiments of the present invention, before the capping layer 120 is formed, a partial etching step P1 is further included to form a recessed notch 119 between the resistive switching layer 122 and the lower electrode 110.

[0053] In summary, in some embodiments of the present invention, before the Forming step is carried out, ion doping is first performed on the capping layer covering the resistive random access memory to form a stress gradient inside the capping layer (that is, the stress gradually changes with different positions) to conform to the lattice arrangement required by the Forming step, reduce the energy required for the subsequent Forming step, and can accelerate the carrier migration rate of the resistive random access memory and improve the quality of the resistive random access memory.

[0054] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope covered by the present invention.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A resistive random access memory located on the substrate, comprising a top electrode, a bottom electrode, and a resistive switching layer between the top electrode and the bottom electrode, wherein the resistive switching layer comprises a metal oxide; And A capping layer covering the outside of the resistive random access memory, wherein the capping layer has an upper part and a lower part, and the stresses contained in the upper part and the lower part are different in the uninitialized state of the semiconductor structure.

2. The semiconductor structure according to claim 1, wherein the upper part contains compressive stress and the lower part contains tensile stress.

3. The semiconductor structure according to claim 1, wherein the upper part contains a larger compressive stress and the lower part contains a smaller compressive stress.

4. The semiconductor structure according to claim 1, wherein the horizontal width of the top electrode is smaller than the horizontal width of the bottom electrode.

5. The semiconductor structure according to claim 1, wherein there is a junction between the upper part and the lower part, and the junction overlaps with the resistive switching layer of the resistive random access memory in the horizontal direction.

6. The semiconductor structure according to claim 1, wherein the material of the capping layer comprises silicon nitride.

7. The semiconductor structure according to claim 6, wherein the lower part contains a first ion, and the first ion comprises boron ions.

8. The semiconductor structure according to claim 6, wherein the upper part contains a second ion, and the second ion comprises phosphorus ions, germanium ions or argon ions.

9. A method for forming a semiconductor structure, comprising: Providing a substrate; Forming a resistive random access memory on the substrate, the resistive random access memory comprising a top electrode, a bottom electrode, and a resistive switching layer between the top electrode and the bottom electrode, wherein the resistive switching layer comprises a metal oxide; and Forming a capping layer covering the outside of the resistive random access memory, wherein the capping layer has an upper part and a lower part, and the stresses contained in the upper part and the lower part are different in the uninitialized state of the semiconductor structure.

10. The forming method according to claim 9, wherein the upper part contains compressive stress and the lower part contains tensile stress.

11. The forming method according to claim 9, wherein the upper part contains a larger compressive stress and the lower part contains a smaller compressive stress.

12. The forming method according to claim 9, wherein the horizontal width of the top electrode is smaller than the horizontal width of the bottom electrode.

13. The forming method according to claim 9, wherein there is a junction between the upper part and the lower part, and the junction overlaps with the resistive switching layer of the resistive random access memory in the horizontal direction.

14. The forming method according to claim 9, wherein the material of the capping layer comprises silicon nitride.

15. The forming method according to claim 14, wherein the lower part contains a first ion, and the first ion comprises boron ions.

16. The forming method according to claim 14, wherein the upper half portion contains a second ion, and the second ion contains a phosphorus ion, a germanium ion, or an argon ion.

17. The forming method according to claim 9, wherein after the capping layer is formed, a first ion doping step and a second ion doping step are further included to dope different ions into the capping layer respectively.

18. The forming method according to claim 17, wherein when the first ion doping step and the second ion doping step are performed, the doping angles for the capping layer are different.

19. The forming method according to claim 9, wherein before the capping layer is formed, a partial etching step is further included to form a recessed notch between the resistive switching layer and the lower electrode.

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