Digital Isolators

Abstract

This application discloses a digital isolator, including a pair of transceiver circuits and a control circuit. Each transceiver circuit includes a transmitting circuit, a receiving circuit, and a DC isolation circuit, which are connected to each other. Each receiving circuit includes a pair of feedback voltage divider circuits and a differential comparator circuit. When the control circuit controls one transceiver circuit to operate in transmit mode and the other transceiver circuit to operate in receive mode, the transmitting circuit of the transceiver circuit operating in transmit mode receives a square wave signal to generate a corresponding pair of differential square wave signals. The connected DC isolation circuit receives the pair of differential square wave signals and generates a pair of differential coupling signals. The transceiver circuit operating in receive mode outputs the square wave signal using the pair of differential coupling signals through its design of a pair of feedback voltage divider circuits and differential comparator circuits.

Description

Technical Field

[0001] This application relates to an isolator, and more particularly to a digital isolator. Background Technology

[0002] When signals or energy are transferred between two circuits with different voltage domains, the difference in voltage domains may cause interference or damage to surrounding circuits during transmission. Therefore, isolators are typically used to protect the circuits and improve their reliability when transmitting signals between circuits in different voltage domains.

[0003] Currently, digital isolators typically employ on-off keying (OOK) modulation. When the input signal is low voltage, an oscillating signal is output; when the input signal is high voltage, there is no signal output. Although the oscillating signal is relatively high-frequency and can pass through the isolation circuit more easily, it suffers from the problem that the supported input square wave signal is relatively low-frequency, and the signal attenuation during transmission is significant, making it susceptible to noise. Summary of the Invention

[0004] In view of this, this application provides a digital isolator to solve the problems of the prior art, which supports relatively low frequency square wave input signals and is susceptible to noise due to significant signal attenuation during transmission.

[0005] This application provides a digital isolator, comprising a pair of transceiver circuits and a control circuit. Each transceiver circuit operates in either a receive mode or a transmit mode, and includes a DC isolation circuit, a transmit circuit, and a receive circuit connected to the DC isolation circuit. Each receive circuit includes a first feedback voltage divider circuit, a second feedback voltage divider circuit, and a differential comparator circuit. The first and second feedback voltage divider circuits are respectively connected to the differential comparator circuit, wherein the DC isolation circuits are interconnected. The control circuit is connected to the pair of transceiver circuits and controls one of the pair of transceiver circuits to operate in transmit mode and controls the other of the pair of transceiver circuits to operate in receive mode. This allows the transmit circuit of the transceiver circuit operating in transmit mode to receive a square wave signal from the input / output terminal of the digital isolator and generate corresponding positive differential square wave signals and negative differential square wave signals. The interconnected DC isolation circuits, after receiving the positive and negative differential square wave signals, generate positive differential coupling signals and negative differential coupling signals. The receive circuit of the transceiver circuit operating in receive mode... In the circuit, the first feedback voltage divider circuit is used to output a positive differential voltage divider signal to the differential comparator circuit based on the positive differential coupling signal and the positive differential comparison signal. The second feedback voltage divider circuit is used to output a negative differential voltage divider signal to the differential comparator circuit based on the negative differential coupling signal and the negative differential comparison signal. The differential comparator circuit is used to compare the positive differential voltage divider signal and the negative differential voltage divider signal and to feed back the positive differential comparison signal to the first feedback voltage divider circuit and the negative differential comparison signal to the second feedback voltage divider circuit. It also outputs a positive differential comparison signal that is the same as a square wave signal from another input / output terminal of the digital isolator.

[0006] The digital isolator provided in this embodiment can be designed by interconnecting two identical transceiver circuits and controlling one of the transceiver circuits to operate in transmit mode while the other operates in receive mode. This allows users to adjust the direction of the input and output signals according to their needs. The transmitting circuit, receiving circuit, and DC isolation circuit of each transceiver circuit can be integrated together, and the two transceiver circuits can be connected by wires to form a digital isolator. Therefore, in the manufacturing process of the digital isolator, there is no need to make an additional DC isolation circuit or use special processes, making the manufacturing process of the digital isolator easier. The isolation voltage difference that the digital isolator can withstand can be increased by interconnecting the two transceiver circuits through their included DC isolation circuits. The differential signal transmission technology of the transceiver circuit can solve the problems of relatively low frequency of the supported input square wave signal and the large attenuation and susceptibility to noise during signal transmission in the prior art.

[0007] The above description of the contents of this application and the following description of the embodiments are used to demonstrate and explain the spirit and principles of this application, and to provide a further explanation of the claims of this application. Attached Figure Description

[0008] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0009] Figure 1 This is a schematic diagram of the digital isolator disclosed in the first embodiment of this application;

[0010] Figure 2 for Figure 1 A schematic diagram of signal waveforms for each key node in an embodiment of a digital isolator transmitting signals;

[0011] Figure 3 This is a schematic diagram of the transmitting circuit disclosed in an embodiment of this application;

[0012] Figure 4 This is a schematic diagram of a receiving circuit disclosed in an embodiment of this application;

[0013] Figure 5A This is a schematic diagram of a first embodiment of the first feedback voltage divider circuit disclosed in this application;

[0014] Figure 5B This is a schematic diagram of a second embodiment of the first feedback voltage divider circuit disclosed in this application;

[0015] Figure 5C This is a schematic diagram of a third embodiment of the first feedback voltage divider circuit disclosed in this application;

[0016] Figure 5D This is a schematic diagram of a fourth embodiment of the first feedback voltage divider circuit disclosed in this application;

[0017] Figure 6 This is a schematic diagram of a differential comparator circuit disclosed in an embodiment of this application;

[0018] Figure 7 This is a schematic diagram of the digital isolator disclosed in the second embodiment of this application;

[0019] Figure 8 This is a schematic diagram of the digital isolator disclosed in the third embodiment of this application. Detailed Implementation

[0020] The following detailed description of the features and advantages of this application in the embodiments is sufficient to enable anyone skilled in the art to understand the technical content of this application and implement it accordingly. Furthermore, based on the disclosure, claims, and drawings in this specification, anyone skilled in the art can easily understand the related objectives and advantages of this application. The following embodiments further illustrate the viewpoints of this application in detail, but are not intended to limit the scope of this application in any way.

[0021] Certain terms are used in the specification and claims to refer to specific elements. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same element. This specification and claims do not distinguish elements by differences in name, but by differences in function. The term "comprising" throughout the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to." Furthermore, the term "connection" here includes any direct and indirect means of connection. Therefore, if the text describes a first device connected to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or means of connection. The following descriptions in the specification are preferred embodiments for carrying out this application; however, these descriptions are for the purpose of illustrating the general principles of this application and are not intended to limit the scope of this application. The scope of protection of this application shall be determined by the appended claims.

[0022] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes said element.

[0023] Furthermore, the use of terms such as "first," "second," and "third" in this application is to modify elements in the claims and is not intended to indicate a priority order, a prior relationship, or that one element precedes another, or the chronological order of the execution of method steps. They are only used to distinguish elements with the same name.

[0024] Please see Figure 1 This is a schematic diagram of the digital isolator disclosed in the first embodiment of this application. In this embodiment, the digital isolator 100 may include a pair of transceiver circuits (i.e., transceiver circuit 110a and transceiver circuit 110b) and a control circuit 120, wherein the control circuit 120 is connected to transceiver circuit 110a and transceiver circuit 110b.

[0025] In this embodiment, both transceiver circuits 110a and 110b can operate in either a receive mode or a transmit mode (i.e., each transceiver circuit can operate in either a receive mode or a transmit mode). Transceiver circuit 110a may include a DC isolation circuit 112a and a transmit circuit 114a and a receive circuit 116a connected to the DC isolation circuit 112a. Transceiver circuit 110b may include a DC isolation circuit 112b and a transmit circuit 114b and a receive circuit 116b connected to the DC isolation circuit 112b (i.e., each transceiver circuit may include a DC isolation circuit and a transmit circuit and a receive circuit connected to the DC isolation circuit). The DC isolation circuit 112a is connected to the DC isolation circuit 112b (i.e., the DC isolation circuits are interconnected). More specifically, the transmitting circuit 114a is connected to the receiving circuit 116b through DC isolation circuits 112a and 112b, and the receiving circuit 116a is connected to the transmitting circuit 114b through DC isolation circuits 112a and 112b (that is, DC isolation circuits 112a and 112b are located between the transmitting circuit 114a and its corresponding receiving circuit 116b, and DC isolation circuits 112a and 112b are located between the transmitting circuit 114b and its corresponding receiving circuit 116a).

[0026] Since the transmitting circuit 114a and its corresponding receiving circuit 116b, and the transmitting circuit 114b and its corresponding receiving circuit 116a, transmit signals are transmitted via differential signals (i.e., differential square wave signals, differential coupling signals, differential comparison signals, and differential voltage divider signals). Therefore, the DC isolation circuits 112a and 112b may each include a pair of coupling elements. In this embodiment, the DC isolation circuit 112a may include capacitors 70a and 70b, and the DC isolation circuit 112b may include capacitors 70c and 70d (i.e., the coupling elements are capacitors, meaning that the DC isolation circuits 112a and 112b adopt a capacitive coupling isolation design). Among them, capacitors 70a and 70c are connected, and capacitors 70b and 70d are connected. The transmitting circuit 114a and the receiving circuit 116a are respectively connected to capacitors 70a and 70b, and the transmitting circuit 114b and the receiving circuit 116b are respectively connected to capacitors 70c and 70d. However, this embodiment is not intended to limit this application. For example, the coupling element mentioned above can also be an inductor. In other words, DC isolation circuit 112a and DC isolation circuit 112b can each include a pair of inductors, using a magnetically coupled isolation design.

[0027] In this embodiment, the receiving circuit 116a may include a first feedback voltage divider circuit 1162a, a second feedback voltage divider circuit 1162b, and a differential comparator circuit 1164a. The receiving circuit 116b may include a first feedback voltage divider circuit 1162c, a second feedback voltage divider circuit 1162d, and a differential comparator circuit 1164b. More specifically, one side of the first feedback voltage divider circuit 1162a is connected to a capacitor 70a, and the other side is connected to the differential comparator circuit 1164a; one side of the second feedback voltage divider circuit 1162b is connected to a capacitor 70b, and the other side is connected to the differential comparator circuit 1164a; one side of the first feedback voltage divider circuit 1162c is connected to a capacitor 70c, and the other side is connected to the differential comparator circuit 1164b; one side of the second feedback voltage divider circuit 1162d is connected to a capacitor 70d, and the other side is connected to the differential comparator circuit 1164b. It should be noted that since the first feedback voltage divider circuits 1162a and 1162c and the second feedback voltage divider circuits 1162b and 1162d have a signal feedback mechanism with the differential comparator circuits 1164a and 1164b connected to them, there are two connection lines between the first feedback voltage divider circuits 1162a and 1162c and the second feedback voltage divider circuits 1162b and 1162d and the differential comparator circuits 1164a and 1164b connected to them. The detailed signal feedback transmission situation will be described in detail later.

[0028] In this embodiment, transceiver circuits 110a and 110b are connected via a control circuit 120, allowing the control circuit 120 to control one of transceiver circuits 110a and 110b to operate in transmit mode, and to control the other of transceiver circuits 110a and 110b to operate in receive mode. The following description of this embodiment uses the control circuit 120 to control transceiver circuit 110a to operate in transmit mode and to control transceiver circuit 110b to operate in receive mode.

[0029] Please see Figure 1 and Figure 2 , Figure 2 for Figure 1 This is a schematic diagram of signal waveforms at key nodes in an embodiment of a digital isolator transmitting signals. The horizontal axis represents time, the direction perpendicular to the horizontal axis represents signal magnitude, and the horizontal dashed line represents a baseline where the signal magnitude is zero volts (V). When transceiver circuit 110a operates in transmit mode and transceiver circuit 110b operates in receive mode, the transmit circuit 114a of transceiver circuit 110a operating in transmit mode can receive square wave signals from the input / output terminal 50 of digital isolator 100 and generate corresponding positive differential square wave signals and negative differential square wave signals (e.g., ...). Figure 1 Node P and node Q are at Figure 2The signal waveform diagram is shown below. The interconnected DC isolation circuits 112a and 112b can be used to receive positive differential square wave signals and negative differential square wave signals, and then generate positive differential coupling signals and negative differential coupling signals. (In this embodiment, since DC isolation circuits 112a and 112b adopt a capacitive coupling isolation design, the positive differential coupling signal can be a positive differential surge signal, and the negative differential coupling signal can be a negative differential surge signal.) Figure 1 Node E and node F are at Figure 2 (The signal waveform diagram is shown); In one embodiment, when the DC isolation circuit 112a and the DC isolation circuit 112b are designed with magnetic coupling isolation, the positive differential coupling signal can be a positive differential triangular signal, and the negative differential coupling signal can be a negative differential triangular signal); The first feedback voltage divider circuit 1162c of the transceiver circuit 110b operating in the receiving mode can be used to output a positive differential voltage divider signal based on the positive differential coupling signal and the positive differential comparison signal, and the second feedback voltage divider circuit 1162d can be used to output a negative differential voltage divider signal based on the negative differential coupling signal and the negative differential comparison signal (e.g. Figure 1 Node G and node H are at Figure 2 (As shown in the signal waveform diagram) to the differential comparator circuit 1164b, the differential comparator circuit 1164b can be used to compare the positive differential voltage divider signal and the negative differential voltage divider signal and feed back the positive differential comparison signal to the first feedback voltage divider circuit 1162c (as shown in the diagram). Figure 1 Node I at Figure 2 As shown in the waveform diagram), the feedback transmission negative differential comparison signal is given to the second feedback voltage divider circuit 1162d (as shown in the waveform diagram). Figure 1 Node J at Figure 2 (As shown in the waveform diagram), and a positive differential comparison signal identical to the square wave signal is output from another input / output terminal 60 of the digital isolator 100. It should be noted that... Figure 2 The system is used to present the waveform correspondence between nodes (i.e., nodes P, Q, E, F, G, H, I, and J), so the time delay issue is not considered.

[0030] Please see Figure 3This is a schematic diagram of a transmitting circuit disclosed in an embodiment of this application. The transmitting circuit 114a may include: a differential conversion circuit 80a, a pair of differential amplifiers (i.e., differential amplifier 90a and differential amplifier 90b), and an inverter 10a. The differential amplifiers 90a and 90b are connected to the differential conversion circuit, and the inverter 10a is connected to the input / output terminal 50 of the digital isolator 100 and the differential conversion circuit 80a. When the transceiver circuit 110a operates in transmit mode, the inverter 10a can be used as a buffer when the transmitting circuit 114a receives a square wave signal from the input / output terminal 50 of the digital isolator 100. The differential conversion circuit 80a can be used to perform differential conversion processing on the square wave signal received from the input / output terminal 50 of the digital isolator 100 to output corresponding positive differential square wave signals and negative differential square wave signals. The differential amplifier 90a can be used to amplify the positive differential square wave signal, and the differential amplifier 90b can be used to amplify the negative differential square wave signal. It should be noted that since the design of the transmitting circuit 114b can be the same as that of the transmitting circuit 114a, it will not be described again here.

[0031] Please see Figure 1 and Figure 4 , Figure 4 This is a schematic diagram of a receiving circuit disclosed in an embodiment of this application. The receiving circuit 116b may further include two inverters 10b and 10c connected in series, which are connected to another input / output terminal 60 of the digital isolator 100 and the differential comparator circuit 1164b. When the transceiver circuit 110b operates in receive mode, the two inverters 10b and 10c connected in series act as buffers for the square wave signal output by the differential comparator circuit 116b to the other input / output terminal 60 of the digital isolator 100. It should be noted that since the design of the receiving circuit 116a can be the same as that of the receiving circuit 116b, it will not be described again here.

[0032] Please see Figure 1 and Figure 5A , Figure 5A A schematic diagram of a first embodiment of the first feedback voltage divider circuit disclosed in this application. Figure 5AIn the first feedback voltage divider circuit 1162c, two P-channel MOSFETs (PMOS) (PMOS M3 and PMOS M4), two N-channel MOSFETs (NMOS) (NMOS M2 and NMOS M5), a capacitor C1, and three resistors (R1, R3, and R4) are included. ENRX and ENRXb are a pair of inverted power control signals, which act as power switches for the first feedback voltage divider circuit 1162c. The first feedback voltage divider circuit 1162c changes the connection relationship between resistors R1, R3, and R4 by adjusting the magnitude of the received positive differential voltage divider signal and the magnitude of the positive differential comparison signal fed back by the differential comparison circuit 1164b, thereby changing the magnitude of the output positive differential voltage divider signal.

[0033] Please see Figure 1 and Figure 5B , Figure 5B This is a schematic diagram of a second embodiment of the first feedback voltage divider circuit disclosed in this application. Figure 5B In the first feedback voltage divider circuit 1162c, there may be a PMOS M6, two NMOS transistors (i.e., NMOS M2 and NMOS M7), a capacitor C1, and five resistors (i.e., resistors R3, R5, R6, R7, and R8). ENRX and ENRXb are a pair of inverted power control signals, which function as power switches for the first feedback voltage divider circuit 1162c. The first feedback voltage divider circuit 1162c changes the connection relationship between resistors R3, R5, R6, R7, and R8 by adjusting the magnitude of the received positive differential voltage divider signal and the magnitude of the positive differential comparison signal fed back by the differential comparison circuit 1164b, thereby changing the magnitude of the output positive differential voltage divider signal.

[0034] In one embodiment, the first feedback voltage divider circuit 1162c may further include an electrostatic discharge (ESD) protection circuit 20, connected to a capacitor 70a (i.e., connected to a DC isolation circuit 112b), for providing electrostatic discharge protection to the first feedback voltage divider circuit 1162c in the transceiver circuit 110b operating in receive mode (e.g., ...). Figure 5C and Figure 5D As shown, Figure 5C This is a schematic diagram of a third embodiment of the first feedback voltage divider circuit disclosed in this application. Figure 5D (This is a schematic diagram of the fourth embodiment of the first feedback voltage divider circuit disclosed in this application). Figure 5C and Figure 5DIn the circuit, the ESD protection circuit 20 includes NMOS M1, inverter K1, three diodes (i.e., diode D1, diode D2 and diode D3) and resistor R2.

[0035] It should be noted that since the design of the first feedback voltage divider circuit 1162a, the second feedback voltage divider circuit 1162b, and the second feedback voltage divider circuit 1162d can be the same as that of the first feedback voltage divider circuit 1162c, they will not be described again here.

[0036] Please see Figure 1 and Figure 6 , Figure 6 This is a schematic diagram of a differential comparator circuit disclosed in an embodiment of this application. The differential comparator circuit 1164b may include: a comparator circuit 30, a differential amplifier circuit 32, and a bias circuit 34. In the transceiver circuit 110b operating in receive mode, the comparator circuit 30 can be used to convert the positive differential voltage divider signal (i.e., ...) from the first feedback voltage divider circuit 1162c connected thereto into a positive differential voltage divider signal. Figure 1 The signal from node G) and the negative differential voltage divider signal from the second feedback voltage divider circuit 1162d connected to it (i.e. Figure 1 After comparing the signals of node H, the output is a positive differential voltage divider signal and a negative differential comparison signal; the differential amplifier circuit 32 is connected to the comparator circuit 30 and can be used to amplify the positive differential comparison signal and the negative differential comparison signal (i.e., Figure 1 The signals of node I and node J are output to the first feedback voltage divider circuit 1162c and the second feedback voltage divider circuit 1162d connected thereto; the bias circuit 34 can be used to provide bias signals to the comparator circuit 30 and the differential amplifier circuit 32. Enb, ENPOCbb, and ENPOCb are power control signals for the differential comparator circuit 1164b, which act as power switches for the differential comparator circuit 1164b. ENPOCb and ENPOCbb are inverted. The comparator circuit 30 includes PMOS M4', PMOS M5', PMOS M6', PMOS M7', NMOS M20', and NMOS M21'. The differential amplifier circuit 32 includes PMOS M2', PMOS M3', PMOS M8', PMOS M9', NMOS M19', NMOS M18', NMOS M13', and NMOS M12'. The bias circuit 34 includes PMOS M1', PMOS M10', PMOS M15', NMOS M17', NMOS M16', NMOS M14', NMOS M11', and resistor R9. It should be noted that since the design of differential comparator circuit 1164a is the same as that of differential comparator circuit 1164b, it will not be described again here.

[0037] Please see Figure 7 , Figure 7This is a schematic diagram of the digital isolator disclosed in the second embodiment of this application. The difference between the digital isolator 200 disclosed in the second embodiment and the digital isolator 100 disclosed in the first embodiment is that, in the digital isolator 200, the transmitting circuit 114a may further include a transmit on / off key connected to the input / output terminal 50 of the digital isolator 200. The keying (OOK) unit 40, when enabled in the transceiver circuit 110a operating in transmit mode, receives and modulates the square wave signal from the input / output terminal 50 of the digital isolator 200 to generate corresponding positive differential square wave signals and negative differential square wave signals (the frequencies of the positive and negative differential square wave signals in the second embodiment are higher than those in the first embodiment); the receiving circuit 116b may further include a receiving OOK unit 42 connected to the differential comparator circuit 1164b and another input / output terminal 60 of the digital isolator 200, when enabled in the transceiver circuit 110b operating in receive mode, demodulates the positive differential comparison signal output by the differential comparator circuit 1164b (the frequency of the positive differential comparison signal in the second embodiment is higher than that in the first embodiment) to output the square wave signal. The control circuit 120 can also be used to enable or disable the receiving OOK unit 42 and the transmitting OOK unit 40. It should be noted that since the design of the transmitting circuit 114b can be the same as that of the transmitting circuit 114a, and the design of the receiving circuit 116a can be the same as that of the receiving circuit 116b, they will not be described in detail here.

[0038] The digital isolators 100 and 200 in the above embodiments include only one pair of transceiver circuits. However, the embodiments are not intended to limit this application. For example, the digital isolators of this application may also include multiple pairs of transceiver circuits. Since one pair of transceiver circuits can provide digital isolation function for a single channel, when the digital isolator also includes multiple pairs of transceiver circuits, it can provide digital isolation function for multiple channels. Moreover, each pair of transceiver circuits included in the digital isolator of this application can be controlled by the control circuit to operate in transmit mode or receive mode, so it is not necessary to make different digital isolators for different channel direction configurations of input and output signals required by the user.

[0039] In addition, please see Figure 8 , Figure 8This is a schematic diagram of the digital isolator disclosed in the third embodiment of this application. The difference between the digital isolator 300 in this embodiment and the digital isolator 100 in the first embodiment is that the control circuit 120 in this embodiment may further include a first control unit 122a and a second control unit 122b. When the first control unit 122a controls the transceiver circuit 110a to operate in the receiving mode, the second control unit 122b controls the transceiver circuit 110b to operate in the transmitting mode; when the first control unit 122a controls the transceiver circuit 110a to operate in the transmitting mode, the second control unit 122b controls the transceiver circuit 110b to operate in the receiving mode.

[0040] In summary, the digital isolator disclosed in this application provides a digital isolator that allows users to adjust the direction of its input and output signals according to their needs. This is achieved by interconnecting two identical transceiver circuits and controlling one of these transceiver circuits to operate in transmit mode while the other operates in receive mode via a control circuit. Furthermore, the transmitting circuit, receiving circuit, and DC isolation circuit of each transceiver circuit can be integrated together, and the two transceiver circuits can be connected by wires to form a digital isolator. Therefore, during the fabrication of the digital isolator, there is no need to fabricate an additional DC isolation circuit or use special processes, making the fabrication process easier. The design of interconnecting two transceiver circuits via their included DC isolation circuits increases the isolation voltage difference that the digital isolator can withstand. Finally, the differential signal transmission technology of the transceiver circuits supports higher frequency input square wave signals, solving the problems of relatively low-frequency input square wave signals and significant signal attenuation during transmission, which makes the signal susceptible to noise in conventional technologies.

[0041] Although this application has been disclosed above with reference to the foregoing embodiments, it is not intended to limit this application. Any modifications and refinements made without departing from the spirit and scope of this application are within the scope of patent protection of this application. For the scope of protection defined in this application, please refer to the appended claims.

Claims

1. A digital isolator, comprising: a pair of transceiver circuits, each of the pair of transceiver circuits operating in one of a receive mode and a transmit mode, and including a DC isolation circuit and a transmit circuit and a receive circuit connected to the DC isolation circuit, each of the receive circuits including a first feedback voltage dividing circuit, a second feedback voltage dividing circuit, and a differential comparison circuit, the first feedback voltage dividing circuit and the second feedback voltage dividing circuit being connected to the differential comparison circuit, wherein the DC isolation circuits are connected to each other; and a control circuit connected to the pair of transceiver circuits for controlling one of the pair of transceiver circuits to operate in the transmit mode and for controlling the other of the pair of transceiver circuits to operate in the receive mode, such that the transmit circuit of the one of the pair of transceiver circuits operating in the transmit mode is for generating a corresponding positive differential square wave signal and a negative differential square wave signal after receiving a square wave signal from an input / output terminal of the digital isolator, the DC isolation circuits connected to each other are for generating a positive differential coupled signal and a negative differential coupled signal after receiving the positive differential square wave signal and the negative differential square wave signal, and the receive circuit of the other of the pair of transceiver circuits operating in the receive mode is for outputting a positive differential divided signal to the differential comparison circuit based on the positive differential coupled signal and a positive differential comparison signal by the first feedback voltage dividing circuit, outputting a negative differential divided signal to the differential comparison circuit based on the negative differential coupled signal and a negative differential comparison signal by the second feedback voltage dividing circuit, and comparing the positive differential divided signal and the negative differential divided signal by the differential comparison circuit and feeding back the positive differential comparison signal to the first feedback voltage dividing circuit and the negative differential comparison signal to the second feedback voltage dividing circuit, and outputting the positive differential comparison signal from another input / output terminal of the digital isolator which is the same as the square wave signal.

2. The digital isolator of claim 1, wherein, In each of the pair of transceiver circuits, the DC isolation circuit includes a pair of capacitors or a pair of inductors connected to the transmit circuit and the receive circuit, respectively.

3. The digital isolator of claim 1, wherein, The transmit circuit of each of the pair of transceiver circuits includes a differential conversion circuit and a pair of differential amplifiers connected to the differential conversion circuit, and in the one of the pair of transceiver circuits operating in the transmit mode, the differential conversion circuit is for performing differential conversion processing on the square wave signal from the input / output terminal of the digital isolator to output the corresponding positive differential square wave signal and the negative differential square wave signal, and the pair of differential amplifiers is for performing signal amplification on the positive differential square wave signal and the negative differential square wave signal.

4. The digital isolator of claim 3, wherein, The pair of transceiver circuits each further includes an inverter connected to the input / output terminal of the digital isolator and the differential conversion circuit, for use as a buffer when the one of the pair of transceiver circuits operating in the transmit mode receives the square wave signal from the input / output terminal of the digital isolator.

5. The digital isolator of claim 1, wherein, Each of the transmitting circuits comprises a transmitting on-off keying unit connected to the input / output terminals of the digital isolator, for receiving and demodulating the square wave signal from the input / output terminals of the digital isolator to generate the corresponding positive differential square wave signal and negative differential square wave signal when enabled in one of the pair of transceiver circuits operating in the transmitting mode; each of the receiving circuits further comprises a receiving on-off keying unit connected to the differential comparison circuit thereof, for demodulating the positive differential comparison signal output by the differential comparison circuit connected thereto to output the square wave signal when enabled in the other of the pair of transceiver circuits operating in the receiving mode.

6. The digital isolator of claim 5, wherein, The control circuit is further configured to enable or disable the receiving on-off keying unit and the transmitting on-off keying unit.

7. The digital isolator of claim 1, wherein, Each of the receiving circuits further comprises two inverters connected in series and connected to the differential comparison circuit, for buffering the square wave signal output by the differential comparison circuit to the other input / output terminal of the digital isolator when enabled in the other of the pair of transceiver circuits operating in the receiving mode.

8. The digital isolator of claim 1, wherein, Each of the differential comparison circuits comprises a comparison circuit, a differential amplification circuit connected to the comparison circuit, and a bias circuit, wherein the comparison circuit is configured to compare the positive differential comparison signal from the first feedback voltage dividing circuit connected thereto with the negative differential comparison signal from the second feedback voltage dividing circuit connected thereto to output the positive differential comparison signal and the negative differential comparison signal when enabled in the other of the pair of transceiver circuits operating in the receiving mode; the differential amplification circuit is configured to amplify the positive differential comparison signal and the negative differential comparison signal to output to the first feedback voltage dividing circuit and the second feedback voltage dividing circuit connected thereto; and the bias circuit is configured to provide a bias signal to the comparison circuit and the differential amplification circuit.

9. The digital isolator of claim 1, wherein, The digital isolator comprises a plurality of pairs of the transceiver circuits.

10. The digital isolator of claim 1, wherein, The control circuit comprises a first control unit and a second control unit, wherein the second control unit controls the other of the pair of transceiver circuits to operate in the transmitting mode when the first control unit controls one of the pair of transceiver circuits to operate in the receiving mode; and the second control unit controls the other of the pair of transceiver circuits to operate in the receiving mode when the first control unit controls one of the pair of transceiver circuits to operate in the transmitting mode.

11. The digital isolator of claim 1, wherein, In each of the receiving circuits, the first feedback voltage dividing circuit and the second feedback voltage dividing circuit each comprises an electrostatic discharge protection circuit connected to the DC isolation circuit, for providing electrostatic discharge protection to the first feedback voltage dividing circuit and the second feedback voltage dividing circuit, respectively, when enabled in the other of the pair of transceiver circuits operating in the receiving mode.

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