A clock data recovery device and its phase detector

Abstract

The present invention provides a clock data recovery device and a phase detector thereof. The phase detector includes a first sampling element, a second sampling element, a first comparison element, a first pulse width adjustment module, and a first output element. The first sampling element and the second sampling element sample a data signal corresponding to a first clock signal and a second clock signal respectively and output a first sampling value and a second sampling value. The first comparison element receives the first sampling value and the second sampling value and outputs a first comparison signal. The first pulse width adjustment module outputs a first adjustment signal within a time interval between the positive edge point of a third clock signal and the positive edge point of a first adjustment clock signal. The first output element performs a logical operation on the first comparison signal and the first adjustment signal and outputs a first output signal.

Description

Technical Field

[0001] The present invention relates to a device for improving the stability of a clock data recovery circuit, and more particularly to a device for improving the stability of a clock data recovery circuit that provides an appropriate pulse width. Background Art

[0002] Clock data recovery (CDR) circuits are often used in high-speed transmission applications, typically to recover the phase and / or frequency information of an input data signal, for example, by acquiring the rising / falling edges of the data signal. Existing CDR circuits, such as Figure 1 shown, for example, include a phase detector (PD), a charge pump (CP), a loop filter (LF), and a voltage-controlled oscillator (VCO).

[0003] In response to the increase in operating speed, most of the currently widely used clock data recovery circuit architectures adopt a 1 / N rate architecture, where N is any positive integer. The 1 / N rate clock data recovery circuit architecture can not only overcome the process limitations of the voltage-controlled oscillator but also reduce the overall power consumption of the clock data recovery circuit. In the 1 / N rate architecture, the phase detector, such as a Bang-Bang type phase detector, generates a pulse width of N unit intervals (UI). When the value of N is larger, the charging and discharging time of the charge pump also becomes longer, which makes the integral response of the loop filter more affected, and thus the jitter increases and / or the jitter becomes larger. The increase in jitter generation or the increase in jitter will both lead to poor stability of the clock data recovery circuit and affect the product quality.

[0004] Therefore, how to improve the stability of the clock data recovery circuit when applied to high-speed operation or high N values will be a major goal of the technical research and development in this field. Summary of the Invention

[0005] The object of the present invention is to provide a phase detector and a clock data recovery device applying the phase detector for improving the stability of the clock data recovery circuit.

[0006] The present invention provides a phase detector, which includes a first sampling element, a second sampling element, a first comparison element, a first pulse width adjustment module, and a first output element. The first sampling element samples a data signal corresponding to a first clock signal and outputs a first sampling value. The second sampling element samples the data signal corresponding to a second clock signal and outputs a second sampling value. The first comparison element is coupled to the first sampling element and the second sampling element and receives the first sampling value and the second sampling value. When the first sampling value and the second sampling value are different, the first comparison element outputs a first comparison signal. The first pulse width adjustment module receives a third clock signal and a first adjustment clock signal. There is a time interval between the positive edge point of the third clock signal and the positive edge point of the first adjustment clock signal. The first pulse width adjustment module outputs a first adjustment signal within the interval of the time interval. The first output element is coupled to the first comparison element and the first pulse width adjustment module and receives the first comparison signal and the first adjustment signal. The first output element performs a logical operation on the first comparison signal and the first adjustment signal and then outputs a first output signal.

[0007] In one embodiment, it further includes: a third sampling element that samples the data signal corresponding to the third clock signal and outputs a third sampling value; a second comparison element that is coupled to the second sampling element and the third sampling element and receives the second sampling value and the third sampling value. When the second sampling value and the third sampling value are different, the second comparison element outputs a second comparison signal; a second pulse width adjustment module that receives a fourth clock signal and a second adjustment clock signal. There is the time interval between the positive edge point of the fourth clock signal and the positive edge point of the second adjustment clock signal. The second pulse width adjustment module outputs a second adjustment signal within the interval of the time interval; and a second output element that is coupled to the second comparison element and the second pulse width adjustment module and receives the second comparison signal and the second adjustment signal. The second output element performs the logical operation on the second comparison signal and the second adjustment signal and then outputs a second output signal.

[0008] In one embodiment, the clock widths of the first clock signal, the second clock signal, and the third clock signal are the same as each other, and the positive edge points of the first clock signal, the second clock signal, and the third clock signal lag behind each other in sequence.

[0009] In one embodiment, the interval by which the positive edge points of the first clock signal, the second clock signal, and the third clock signal lag behind each other in sequence is 0.5UI.

[0010] In one embodiment, the time interval is one of 0.5UI, 1UI, and 1.5UI.

[0011] In one embodiment, the clock widths of the third clock signal and the fourth clock signal are the same as each other, and the interval by which the positive edge point of the fourth clock signal lags behind the third clock signal is 0.5 UI.

[0012] In one embodiment, the first pulse width adjustment module includes a NOT gate and an AND gate. The first adjusted clock signal is input to the AND gate after passing through the NOT gate, and the third clock signal is input to the AND gate.

[0013] In one embodiment, the logical operation is an AND logical operation.

[0014] The present invention further provides a clock data recovery device, including a phase detector of any one of the above; a charge pump, coupled to the phase detector and receiving at least the first output signal; a loop filter, coupled to the charge pump; and a voltage controlled oscillator, coupled to the charge pump.

[0015] As described above, the first pulse width adjustment module receives the clock signal and the first adjusted clock signal and outputs an adjustment signal, thereby providing an appropriate pulse width. When the charge pump charges or discharges according to the appropriate pulse width, the generation or influence of jitter in the clock data recovery circuit will be reduced. Thereby, the purpose of improving the loop stability of the clock data recovery circuit is achieved. Description of the Drawings

[0016] Figure 1 It is a schematic diagram of a conventional clock data recovery circuit architecture.

[0017] Figure 2 It is a schematic diagram of the phase detector in the first embodiment of the present invention.

[0018] Figure 3 It is a signal timing diagram of the phase detector in the first embodiment of the present invention.

[0019] Figure 4 It is a schematic diagram of the phase detector in the second embodiment of the present invention.

[0020] Figure 5 It is a signal timing diagram of the phase detector in the second embodiment of the present invention.

[0021] Figure 6 It is a schematic diagram of the phase detector in the third embodiment of the present invention.

[0022] Figure 7 It is a schematic diagram of the phase detector in the fourth embodiment of the present invention.

[0023] Figure 8 It is a signal timing diagram of the phase detector in the fourth embodiment of the present invention.

[0024] Main Element Symbol Description:

[0025] 100, 200, 300 Phase Detector

[0026] 111 - 1118 Sampling Element

[0027] 121 - 1218 Comparison Element

[0028] 131 - 1318 Pulse Width Adjustment Module

[0029] 141 - 1418 Output Element

[0030] DS Data Signal

[0031] CLK1 - CLK18 Clock Signal

[0032] D1 - D18 Sampling Value

[0033] CS1 - CS18 Control Signal

[0034] AS1 - AS18 Adjustment Signal

[0035] OS1 - OS18 Output Signal

[0036] XOR1, NOT1, AND1, AND2 Logic Gates Detailed Implementation Manner

[0037] The spirit of the present invention will be clearly described below with reference to the accompanying drawings and detailed description. After any person skilled in the art understands the embodiments of the present invention, the techniques disclosed by the present invention can be changed and modified, which do not depart from the spirit and scope of the present invention.

[0038] Regarding the "first", "second", etc. used herein, they do not particularly refer to the meaning of order or sequence, nor are they used to limit the present invention. They are only used to distinguish elements or operations described with the same technical terms. Regarding the "comprising", "including", "having", "containing", etc. used herein, they are all open-ended terms, that is, they mean including but not limited to.

[0039] Regarding the terms used herein, unless otherwise specified, they generally have the ordinary meanings of each term used in this field, in the content disclosed herein, and in the special content. Some terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art regarding the description of the present disclosure.

[0040] In the drawings, for clarity, the thickness of layers, plates, regions, spaces, etc. is enlarged. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, plate, region, or space is referred to as being "on" or "connected to" another element, it can be interpreted as being directly on or connected to the other element, or it can be interpreted as having or existing an intermediate element between the element and the other element. As used herein, "connected" or "coupled" can refer to physical and / or electrical connections. Furthermore, to simplify the drawings and highlight the content presented by the drawings, existing structures or elements in the drawings may be drawn in a simple schematic manner or presented in an omitted manner.

[0041] As Figure 2 shown, the present invention provides a phase detector 100, comprising a first sampling element 111, a second sampling element 112, a first comparison element 121, a first pulse width adjustment module 131, and a first output element 141. The first sampling element 111 samples the data signal DS corresponding to the first clock signal CLK1 and outputs a first sampled value D1. The second sampling element 112 samples the data signal DS corresponding to the second clock signal CLK2 and outputs a second sampled value D2. Specifically, the first sampling element 111 and / or the second sampling element 112 can be, but are not limited to, flip-flops or other elements that sample according to a clock signal. In addition, the definitions of the sampling elements 111 and 112 corresponding to the clock signals CLK1 and CLK2 are, for example but not limited to, edge-triggered according to the rising edge points and / or falling edge points of the clock signals CLK1 and CLK2. The data signal DS and the sampled values D1 and D2 are, for example but not limited to, serial digital signals and the bit values in the serial digital signals.

[0042] The first comparison element 121 is coupled to the first sampling element 111 and the second sampling element 112 and receives a first sampled value D1 and a second sampled value D2. Specifically, the first comparison element 121 is, for example but not limited to, a comparator or a logic gate, and preferably an Exclusive OR (XOR) logic gate. When the first sampled value D1 and the second sampled value D2 are different, the first comparison element 121 outputs a first comparison signal CS1. For example, if the value of the first sampled value D1 is the binary value "1" and the value of the second sampled value D2 is the binary value "0", then the first sampled value D1 and the second sampled value D2 are different. The definition of the first comparison signal CS1 is, for example, the comparison result of the first sampled value D1 and the second sampled value D2. For example, when the first sampled value D1 and the second sampled value D2 are different, the first comparison signal CS1 is the binary value "1". Conversely, when the first sampled value D1 and the second sampled value D2 are the same, the first comparison signal CS1 is the binary value "0". It should be noted that the above examples are only for illustrating the embodiments and not for limiting the present invention.

[0043] Such as Figure 2 And Figure 3As shown, the first pulse width adjustment module 131 receives the third clock signal CLK3 and the first adjustment clock signal ACK1. For example, the first pulse width adjustment module 131 can be implemented by, but not limited to, a logic circuit or a switching circuit. There is a time interval TS between the positive edge point P3 of the third clock signal CLK3 and the positive edge point PA1 of the first adjustment clock signal ACK1. Specifically, the clock widths (Pulse widths, PW) of the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 are the same as each other. In addition, the positive edge point P1 of the first clock signal CLK1, the positive edge point P2 of the second clock signal CLK2, and the positive edge point P3 of the third clock signal CLK3 lag behind each other in sequence, and the lag amplitude is the lag width DW. Preferably, the lag width DW is 0.5UI. For example, the positive edge point P2 of the second clock signal CLK2 lags behind the positive edge point P1 of the first clock signal CLK1 by an amplitude of 0.5UI, and the positive edge point P3 of the third clock signal CLK3 also lags behind the positive edge point P2 of the second clock signal CLK2 by an amplitude of 0.5UI. It should be noted that the lag width DW by which the clock signals CLK1 - CLK3 of the present invention lag behind each other is not limited to 0.5UI. On the other hand, the present invention is not limited to the number of clock signals. In other words, the present invention can have clock signals CLK1 - CLKX, where the number of clock signals is X, and X is any positive integer greater than 3. In an embodiment, when the phase detector 100 is applied to a clock data recovery circuit with a 1 / N rate architecture, X will be equal to twice N. The first adjustment clock signal ACK1 can be one of the clock signals CLK1 - CLKX that lags behind the third clock signal CLK3. The width of the time interval TS is preferably 0.5UI, 1UI, or 1.5UI. For example, when the amplitude by which each of the clock signals CLK1 - CLKX lags behind in sequence is 0.5UI and the time interval TS between the positive edge point P3 of the third clock signal CLK3 and the positive edge point PA1 of the first adjustment clock signal ACK1 is 0.5UI, the first adjustment clock signal ACK1 can be the fourth clock signal CLK4. Next, the first pulse width adjustment module 131 outputs the first adjustment signal AS1 within the time interval TS. For example, as Figure 3 shown, the first adjustment signal AS1 outputs the binary value "1" within the time interval TS and outputs the binary value "0" in the remaining intervals. In this way, the first adjustment signal AS1 with a width equal to the time interval TS can be generated.

[0044] The first output element 141 is coupled to the first comparison element 121 and the first pulse width adjustment module 131 and receives the first comparison signal CS1 and the first adjustment signal AS1. Specifically, the first output element 141 is, for example, a logic circuit element. The first output element 141 performs a logical operation on the first comparison signal CS1 and the first adjustment signal AS1 and then outputs a first output signal OS1. In one embodiment, the logical operation is an AND logical operation. In this embodiment, for example, when both the first comparison signal CS1 and the first adjustment signal AS1 are binary value "1", the first output signal OS1 is binary value "1". In addition, in one embodiment, the first output signal OS1 output by the first output element 141 can be provided to a charge pump connected at the back end. In this embodiment, the first output signal OS1 is, for example, an up signal or a down signal provided to the charge pump. The first output element 141 can adjust the first comparison signal CS1 according to the width of the first adjustment signal AS1. Through the above-mentioned phase detector 100, the clock data recovery circuit can provide an appropriate charging and / or discharging time for the charge pump, reducing the integration response of the loop filter. By this setting, the entire clock data recovery circuit reduces jitter generation.

[0045] In one embodiment, as Figure 4 and Figure 5The phase detector 200 further includes a third sampling element 113, a second comparison element 122, a second pulse width adjustment module 132, and a second output element 142. The third sampling element 113 samples the data signal DS corresponding to the third clock signal CLK3 and outputs a third sampling value D3. The second comparison element 122 is coupled to the second sampling element 112 and the third sampling element 113 and receives the second sampling value D2 and the third sampling value D3. When the second sampling value D2 and the third sampling value D3 are different, the second comparison element 122 outputs a second comparison signal CS2. The second pulse width adjustment module 132 receives the fourth clock signal CLK4 and the second adjustment clock signal ACK2, where there is a time interval TS between the positive edge point P4 of the fourth clock signal CLK4 and the positive edge point PA2 of the second adjustment clock signal ACK2. The second pulse width adjustment module 132 outputs a second adjustment signal AS2 within the time interval TS. The second output element 142 is coupled to the second comparison element 122 and the second pulse width adjustment module 132 and receives the second comparison signal CS2 and the second adjustment signal AS2. The second output element 142 performs a logical operation on the second comparison signal CS2 and the second adjustment signal AS2 and outputs a second output signal OS2. Specifically, the clock widths of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 are the same, and the positive edge point P1 of the first clock signal CLK1, the positive edge point P2 of the second clock signal CLK2, the positive edge point P3 of the third clock signal CLK3, and the positive edge point P4 of the fourth clock signal CLK4 lag behind each other in sequence. The interval by which the positive edge point of the fourth clock signal CLK4 lags behind the third clock signal CLK3 is preferably 0.5U I. In this embodiment, the first output signal OS1 and the second output signal OS2 can be used as the leading signal and the lagging signal of the charge pump, respectively.

[0046] In one embodiment, the clock data recovery circuit including the phase detector 200 can be a half-rate architecture. In this embodiment, the number of clock signals is 4 groups, CLK1-CLK4. After the fourth clock signal CLK4, the first clock signal CLK1_T2 of the next cycle can be connected, where the amplitude by which the first clock signal CLK1_T2 lags behind the fourth clock signal CLK4 is the lag width DW. For example, the first adjustment clock signal ACK1 input to the first pulse width adjustment module 131 can be the fourth clock signal CLK4 or the first clock signal CLK1_T2 of the next cycle or the second clock signal CLK2_T2. It should be noted that this embodiment illustrates the cycle of the clock signal and the relationship between the clock signal and the adjustment clock signal, and the present invention is not limited to this embodiment.

[0047] In one embodiment, the comparison elements 121, 122, the pulse width adjustment modules 131, 132, and the output elements 141, 142 may be constituted by logic gate circuits. As Figure 6 , the first comparison element 121 may be an exclusive OR gate XOR1. The first pulse width adjustment module 131 includes a NOT gate NOT1 and a first AND gate AND1. The first adjustment clock signal ACK1 is input to the AND gate AND1 after passing through the NOT gate NOT1, and the third clock signal CLK3 is input to the AND gate AND1. The first output element 141 may be a second AND gate AND2. Through the composition of logic gates, the architectures of the above phase detectors 100, 200 can be achieved in a simple manner. It should be noted that this embodiment is only for illustrating that the present invention can be implemented by logic gates and is not intended to limit the present invention. Any person with ordinary knowledge in the art who uses different logic gate elements according to the implementation mode of the present invention shall fall within the scope of the present invention. In addition, Figure 6 in the sampling elements 111, 112, 113, D-type flip-flops are only used for example and are not intended to limit the present invention.

[0048] In one embodiment, the present invention can be applied to a clock data recovery circuit with a 1 / N rate architecture where N is greater than 2 by increasing the number of phase detectors and clock signals. Figure 7 And Figure 8 describe a phase detector 300 applied to a 1 / 9 rate architecture and its related timing diagram. When applied to a 1 / 9 rate architecture, there are a total of 18 groups of clock signals CLK1 - CLK18, 18 groups of sampling elements 111 - 1118, 18 groups of comparison elements 121 - 1218, 18 groups of pulse width adjustment modules 131 - 1318, and 18 groups of output elements 141 - 1418. The clock signals CLK1 - CLK18 lag behind each other in sequence, and the lag amplitude is 0.5UI. The pulse width of each clock signal CLK1 - CLK18 is 4.5UI. After the data signal DS is sampled by the sampling elements 111 - 1118 corresponding to the clock signals CLK1 - CLK18 respectively, the sampled values D1 - D18 are provided to the comparison elements 121 - 1218 for comparison. It should be noted that each comparison element 121 - 1218 only inputs two adjacent sampled values. For example, the sampled values input to the comparison element 121 are D1 and D2. When the sampled value reaches the last bit (in this embodiment, it is the sampled value D18), the next sampled value is the first bit of the sampled value (in this embodiment, it is the sampled value D1). For example, the sampled values input to the comparison element 1218 are D18 and D1. In addition, Figure 7 for the sake of clear representation of the drawing, the circuit connections in the drawing are simplified. For example Figure 7The sampling element 113 shown is only for illustrating the connection manner of the sampling element 113, and it is not necessary to have two sampling elements 113. The remaining processes of the phase detector 300 are the same as those of the foregoing embodiments, and will not be described herein. However, the present invention is not limited to the architecture for 1 / 9 rate, and the present invention can be applied to various architectures by increasing or decreasing the number of elements.

[0049] In an embodiment, the present invention provides a clock data recovery device, including any one of the foregoing phase detectors, a charge pump, a loop filter, and a voltage controlled oscillator. The charge pump is coupled to the phase detector and receives at least a first output signal. The loop filter is coupled to the charge pump. The voltage controlled oscillator is coupled to the charge pump.

[0050] The present invention has been described by the above related embodiments. However, the above embodiments are only examples for implementing the present invention. It should be noted that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the claims are included in the scope of the present invention.

Claims

1. A phase detector, characterized in that, Comprising: A first sampling element that samples a data signal corresponding to a first clock signal and outputs a first sampling value; A second sampling element that samples the data signal corresponding to a second clock signal and outputs a second sampling value; A first comparison element coupled to the first sampling element and the second sampling element and receiving the first sampling value and the second sampling value. When the first sampling value and the second sampling value are different, the first comparison element outputs a first comparison signal; A first pulse width adjustment module that receives a third clock signal and a first adjustment clock signal, wherein there is a time interval between the positive edge points of the third clock signal and the first adjustment clock signal. The first pulse width adjustment module outputs a first adjustment signal within the interval of the time interval; And A first output element coupled to the first comparison element and the first pulse width adjustment module and receiving the first comparison signal and the first adjustment signal. The first output element performs a logic operation on the first comparison signal and the first adjustment signal and outputs a first output signal; The clock widths of the first clock signal, the second clock signal, and the third clock signal are the same as each other, and the positive edge points of the first clock signal, the second clock signal, and the third clock signal lag behind each other in sequence.

2. The phase detector according to claim 1, wherein Further comprising: A third sampling element that samples the data signal corresponding to the third clock signal and outputs a third sampling value; A second comparison element coupled to the second sampling element and the third sampling element and receiving the second sampling value and the third sampling value. When the second sampling value and the third sampling value are different, the second comparison element outputs a second comparison signal; A second pulse width adjustment module that receives a fourth clock signal and a second adjustment clock signal, wherein there is the time interval between the positive edge points of the fourth clock signal and the second adjustment clock signal. The second pulse width adjustment module outputs a second adjustment signal within the interval of the time interval; And A second output element coupled to the second comparison element and the second pulse width adjustment module and receiving the second comparison signal and the second adjustment signal. The second output element performs the logic operation on the second comparison signal and the second adjustment signal and outputs a second output signal.

3. The phase detector according to claim 1, wherein, The intervals at which the positive edge points of the first clock signal, the second clock signal, and the third clock signal lag behind each other in sequence are 0.5UI.

4. The phase detector according to claim 1, wherein, The time interval is one of 0.5UI, 1UI, and 1.5UI.

5. The phase detector according to claim 2, characterized in that, The clock widths of the third clock signal and the fourth clock signal are the same as each other, and the interval at which the positive edge point of the fourth clock signal lags behind the third clock signal is 0.5UI.

6. The phase detector according to claim 1, wherein The first pulse width adjustment module includes a NOT gate and an AND gate. The first adjustment clock signal is input to the AND gate after passing through the NOT gate, and the third clock signal is input to the AND gate.

7. The phase detector according to claim 1, wherein The logic operation is an AND logic operation.

8. A clock data recovery device, characterized in that, Comprising: A phase detector according to any one of claims 1-7; A charge pump coupled to the phase detector and receiving at least the first output signal; A loop filter coupled to the charge pump; And A voltage controlled oscillator coupled to the charge pump.

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