Hybrid multi-stage operation encryption and decryption system, transmitting end device and receiving end device

Abstract

The present application relates to the field of encryption technology, and provides a hybrid multi-stage operation encryption and decryption system, including a sending end device and a receiving end device, wherein the sending end device includes a data generation module and a data encryption module, wherein the data encryption module obtains at least one data packet from the data generation module, encrypts the data packet via a three-stage parallel encryptor, and then outputs an encrypted sequence. The receiving end device includes a data target module and a data decryption module. The data decryption module obtains the encrypted sequence from the sending end device, decrypts the encrypted sequence via a three-stage parallel decryptor, and then outputs the restored data packet to the data target module.

Description

Technical Field

[0001] The present application relates to the field of encryption technology, and provides an encryption and decryption system, a transmitting end device, and a receiving end device, and more particularly, refers to a hybrid multi-stage operation encryption and decryption system, a transmitting end device, and a receiving end device capable of switching internal / external encryption keys and encryption levels. Background Art

[0002] Advanced Encryption Standard (AES), also known as Rijndael encryption in cryptography, is a block encryption standard adopted by the U.S. federal government. This standard is used to replace the original DES, has been analyzed by many parties and is widely used around the world.

[0003] The Advanced Encryption Standard has been cracked many times. The 128-bit key version of AES has 10 encryption cycles, the 192-bit key version has 12 encryption cycles, and the 256-bit key version has 14 encryption cycles. As of 2006, the most famous attacks were against the 128-bit key version of AES with 7 encryption cycles, the 192-bit key version with 8 encryption cycles, and the 256-bit key version with 9 encryption cycles. As hardware becomes more efficient, it is estimated that the day when AES can be completely cracked by brute force attacks is not far away.

[0004] In addition, with the continuous upgrading of hardware, artificial intelligence has now reached the stage of commercialization. Through the processing performance of hardware and the powerful computing power of artificial intelligence, the encryption standards widely used today are likely to be cracked by artificial intelligence through a large number of calculations. For the above reasons, it is necessary to improve the existing encryption technology. Summary of the invention

[0005] In order to solve the above problems, the present application provides a hybrid multi-stage operation encryption and decryption system, including a sending end device and a receiving end device. The sending end device includes a data generation module and a data encryption module. The data encryption module includes an encryption key setter, an encryption level setter and a three-stage parallel encryptor. The encryption key setter includes an internal key encryption mode and an external key encryption mode. The encryption key setter is used to select the internal key encryption mode or the external key encryption mode. The encryption level setter is used to select the encryption level. The data encryption module obtains at least one data packet from the data generation module. The encryption key setter selects the internal key encryption mode or the external key encryption mode, and updates the key of the three-stage parallel encryptor accordingly. The three-stage parallel encryptor encrypts the data packet according to the selected encryption level and outputs an encryption sequence. The receiving device includes a data target module and a data decryption module. The data decryption module includes a decryption key setter, a decryption level setter and a three-order parallel decryptor. The decryption key setter includes an internal key decryption mode and an external key decryption mode. The decryption key setter is used to select the internal key decryption mode or the external key decryption mode. The decryption level setter selects the decryption level corresponding to the encryption level selected by the sending device. The data decryption module obtains the encryption sequence from the sending device. The decryption key setter selects the internal key decryption mode or the external key decryption mode corresponding to the internal key encryption mode or the external key encryption mode selected by the sending device and updates the key of the three-order parallel decryptor accordingly. The three-order parallel decryptor decrypts the encryption sequence according to the selected decryption level and outputs the restored data packet to the data target module.

[0006] The present application further provides a transmitting end device, which includes a data generation module and a data encryption module. The data encryption module includes an encryption key setter, an encryption level setter, and a three-stage parallel encryptor. The encryption key setter includes an internal key encryption mode and an external key encryption mode. The encryption key setter is used to select the internal key encryption mode or the external key encryption mode. The encryption level setter is used to select the encryption level. The data encryption module obtains at least one data packet from the data generation module. The encryption key setter selects the internal key encryption mode or the external key encryption mode and updates the key of the three-stage parallel encryptor accordingly. The three-stage parallel encryptor encrypts the data packet according to the selected encryption level and outputs an encryption sequence.

[0007] The present application further provides a receiving device, which includes a data target module and a data decryption module. The data decryption module includes a decryption key setter, a decryption level setter and a three-stage parallel decryptor. The decryption key setter includes an internal key decryption mode and an external key decryption mode. The decryption key setter is used to select the internal key decryption mode or the external key decryption mode. The decryption level setter selects a decryption level corresponding to the encryption level selected by the sending device. The data decryption module obtains an encryption sequence from the sending device. The decryption key setter selects the internal key decryption mode or the external key decryption mode corresponding to the internal key encryption mode or the external key encryption mode selected by the sending device, and updates the key of the three-stage parallel decryptor accordingly. The three-stage parallel decryptor decrypts the encryption sequence according to the selected decryption level and outputs the restored data packet to the data target module.

[0008] Compared with the prior art, the present application can adjust the key to an internal key or an external key according to the required encryption mode and adjust the encryption level according to the needs, and can implement different encryption methods through a set of hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0010] Figure 1 A schematic diagram of the modules of the hybrid multi-stage operation encryption and decryption system provided in an embodiment of the present application.

[0011] Figure 2 A module schematic diagram of a data encryption module provided in an embodiment of the present application.

[0012] Figure 3 A schematic diagram of a module of a first parallel stream encryption unit provided in an embodiment of the present application.

[0013] Figure 4 A schematic diagram of a module of a second parallel stream encryption unit provided in an embodiment of the present application.

[0014] Figure 5 A schematic diagram of a module of a third parallel stream encryption unit provided in an embodiment of the present application.

[0015] Figure 6 A schematic diagram of the logical operations of a three-order parallel encryptor provided in an embodiment of the present application.

[0016] Figure 7 A module schematic diagram of a data decryption module provided in an embodiment of the present application.

[0017] Figure 8 A schematic diagram of a module of a first parallel stream decryption unit provided in an embodiment of the present application.

[0018] Fig. 9 A schematic diagram of a module of a second parallel stream decryption unit provided in an embodiment of the present application.

[0019] Fig.10 A schematic diagram of a module of a third parallel stream decryption unit provided in an embodiment of the present application.

[0020] Fig.11 A schematic diagram of the logical operations of a three-order parallel decryptor provided in an embodiment of the present application.

[0021] Fig.12 A schematic diagram of the flow of a hybrid multi-stage operation encryption and decryption system provided in an embodiment of the present application.

[0022] Fig.13 A schematic diagram of the process flow of a three-stage parallel encryptor provided in an embodiment of the present application.

[0023] Fig.14 A schematic diagram of the process flow of a three-stage parallel decryptor provided in an embodiment of the present application.

[0024] 100: hybrid multi-stage operation encryption and decryption system; 10: transmitter device; 12: data generation module; 14: data encryption module; 142: encryption key setter; 144: encryption level setter; 146: three-stage parallel encryptor; 1462: first parallel stream encryption unit; 14621: sixteen-bit encryption operand generator; 14621L: encryption linear feedback shift register; 14621G: generate encryption logic gate; 14622: first thirty-two-bit encryption operand generator; 14622L: encryption linear feedback shift register; 14622G: generate encryption logic gate; 14623: first external encryption key input device; 14624: first internal encryption key storage; G11: first encryption Logic operator; G112: first encryption logic operation module; G114: first data encryption logic gate; 1464: second parallel stream encryption unit; 14641: second thirty-two-bit encryption operand generator; 14641L: encryption linear feedback shift register; 14641G: generate encryption logic gate; 14642: first sixty-four-bit encryption operand generator; 14642L: encryption linear feedback shift register; 14642G: generate encryption logic gate; 14643: second external encryption key input device; 14644: second internal encryption key storage; G12: second encryption logic operator; G122: second encryption logic operation module; G124: second data encryption logic gate; 1466: The third parallel stream encryption unit; 14661: the second sixty-four-bit encryption operand generator; 14661L: the encryption linear feedback shift register; 14661G: the encryption logic gate generation; 14662: the one hundred and twenty-eight-bit encryption operand generator; 14662L: the encryption linear feedback shift register; 14662G: the encryption logic gate generation; 14663: the third external encryption key input device; 14664: the third internal encryption key storage; G13: the third encryption logic operator; G132: the third encryption logic operation module; G134: the third data encryption logic gate; 242: the decryption key setter; 244: the decryption level setter; 246: the third-order parallel decryptor; 2462: the first parallel stream Decryption unit; 24621: 16-bit decryption operand generator; 24621L: decryption linear feedback shift register; 24621G: generate decryption logic gate; 24622: first 32-bit decryption operand generator; 24622L: decryption linear feedback shift register; 24622G: generate decryption logic gate; 24623: first external decryption key input device; 24624: first internal decryption key storage; G21: first decryption logic operator; G212: first decryption logic operation module; G224: first data decryption logic gate; 2464: second parallel stream decryption unit; 24641: second 32-bit decryption operand generator; 24641L: decryption linear feedback shift register;24641G: generate decryption logic gate; 24642: first sixty-four-bit decryption operand generator; 24642L: decryption linear feedback shift register; 24642G: generate decryption logic gate; 24643: second external decryption key input device; 24644: second internal decryption key storage; G22: second decryption logic operator; G222: second decryption logic operation module; G224: second data decryption logic gate; 2466: third parallel stream decryption unit; 24661: second sixty-four-bit decryption operand generator; 24661L: decryption linear feedback shift register; 24661G: generate decryption logic gate; 24662: one hundred and twenty-eight-bit decryption operand generator; 24662L: decryption linear feedback shift register Feedback shift register; 24662G: generate decryption logic gate; 24663: third external decryption key input device; 24664: third internal decryption key storage; G23: third decryption logic operator; G232: third decryption logic operation module; G234: third data decryption logic gate; ES: encryption sequence; ES1: first encryption sequence; ES2: second encryption sequence; ES3: third encryption sequence; A1: encryption operand; B1: encryption operand; C1: encryption operand; D1: encryption operand; E1: encryption operand; F1: encryption operand; A2: decryption operand; B2: decryption operand; C2: decryption operand; D2: decryption operand; E2: decryption operand; F2: decryption operand. ; DETAILED DESCRIPTION

[0025] The detailed description and technical content of this application are described below with reference to the accompanying drawings. Figure 1 , is a module diagram of the hybrid multi-stage operation encryption and decryption system of this application, as shown in the figure:

[0026] This embodiment mainly discloses a hybrid multi-stage operation encryption and decryption system 100, which is used for encrypting and decrypting the data transmitted by the devices when multiple devices transmit data to each other. The device that generates or receives data can be a computer, a server, a mobile device, an Internet of Things device (for example, a monitor, a television, a cloud hard drive, a lamp, etc.), a large number of manufacturing equipment or machines, etc., which are not limited in this application. In this application, the device is defined as a sending device 10 as a data transmission source and a receiving device 20 corresponding to the sending device 10 for receiving the data of the sending device 10 based on the signal transmission and reception relationship. It should be noted that this application is not limited to the sending device 10 only performing the data encryption function and the receiving device 20 only performing the data decryption function. Specifically, the sending device 10 and the receiving device 20 described herein generally have encryption and decryption functions at the same time to ensure that the data is encrypted or decrypted with each other's keys during the two-way transmission process, which must be explained in advance.

[0027] The transmitting device 10 and the receiving device 20 can transmit data through a wired or wireless network. In one preferred embodiment, the transmitting device 10 and the receiving device 20 can transmit data through the Internet, a local area network, or between any wired or wireless communication ports, which is not limited in this application. In order to complete the functions of data encryption, decryption and transmission, the transmitting device 10 and the receiving device 20 should at least include a processor, a storage unit, and a communication unit to cooperate with each other to complete the corresponding functions, such as a physical line network card, a wireless network card, a Bluetooth module, a Zigbee module, etc. The transmission method and transmission interface of the signal are not within the scope of the application.

[0028] In one embodiment, the modules, devices, units or their combinations and the corresponding functions performed in the hybrid multi-stage operation encryption and decryption system 100 of the present application can be executed by a single chip or a combination of multiple chips, and the number of chip configurations is not within the scope of the present application. In addition, the chip can be, but is not limited to, a processor, a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), and other similar devices or combinations of these devices that can process, convert or perform special purposes on information or signals, which are not limited in the present application.

[0029] In one embodiment, the transmitting device 10 mainly includes a data generation module 12 and a data encryption module 14. The data generation module 12 can be, for example, a cache memory, a dynamic random access memory (DRAM), or a persistent memory for storing and managing data to be transmitted and encrypted. The data encryption module 14 obtains at least one data packet from the data generation module 12. The data encryption module 14 can be a processor or a microprocessor for performing encryption calculation processing, which is not limited in this application. Finally, the data encryption module 14 outputs the encrypted data packet to the receiving device 20. The encrypted data packet output by the data encryption module 14 is defined as an encryption sequence.

[0030] In one embodiment, please refer to Figure 2 , the data encryption module 14 includes an encryption key setter 142, an encryption level setter 144 and a three-stage parallel encryptor 146. The output end of the encryption key setter 142 is connected to the input end of the three-stage parallel encryptor 146, and the output end of the encryption level setter 144 is connected to the other input end of the three-stage parallel encryptor 146. The encryption key setter 142 includes an internal key encryption mode and an external key encryption mode. The encryption key setter 142 is used to select the internal key encryption mode or the external key encryption mode, and update the key of the three-stage parallel encryptor 146 accordingly. The encryption level setter 144 is used to select the encryption level of the three-stage parallel encryptor 146. The three-stage parallel encryptor 146 encrypts the data packet according to the selected encryption level and outputs an encryption sequence.

[0031] In one embodiment, the three-stage parallel encryptor 146 includes a first parallel stream encryption unit 1462, a second parallel stream encryption unit 1464, and a third parallel stream encryption unit 1466 connected in sequence. Figure 3 The first parallel stream encryption unit 1462 includes a 16-bit encryption operand generator 14621, a first 32-bit encryption operand generator 14622, a first external encryption key input 14623, a first internal encryption key storage 14624, and a first encryption logic operator G11. The input end of the first external encryption key input 14623 is connected to the output end of the encryption key setter 142, and the output end of the first external encryption key input 14623 is connected to the input end of the 16-bit encryption operand generator 14621 and the input end of the first 32-bit encryption operand generator 14622. The input end of the first internal encryption key storage 14624 is connected to the other output end of the encryption key setter 142, and the output end of the first internal encryption key storage 14624 is connected to the other input end of the 16-bit encryption operand generator 14621 and the other input end of the first 32-bit encryption operand generator 14622. In the external encryption key mode, the encryption key setter 142 starts the first external encryption key inputter 14623 and outputs the external encryption key. In the internal encryption key mode, the encryption key setter 142 starts the first internal encryption key storage 14624 and outputs the internal encryption key. The sixteen-bit encryption operand generator 14621 and the first thirty-two-bit encryption operand generator 14622 respectively generate the first encryption operand according to the external encryption key or the internal encryption key. The input end of the first encryption logic operator G11 is connected to the output end of the sixteen-bit encryption operand generator 14621, and the other input end of the first encryption logic operator G11 is connected to the output end of the first thirty-two-bit encryption operand generator 14622. The first encryption operand and the data packet are calculated and encrypted by the first encryption logic operator G11 to obtain the first encryption sequence ES1.

[0032] In one embodiment, see Figure 4The second parallel stream encryption unit 1464 includes a second 32-bit encryption operand generator 14641, a first 64-bit encryption operand generator 14642, a second external encryption key input 14643, a second internal encryption key storage 14644, and a second encryption logic operator G12. The input end of the second external encryption key input 14643 is connected to the output end of the encryption key setter 142, and the output end of the second external encryption key input 14643 is connected to the input end of the second 32-bit encryption operand generator 14641 and the input end of the first 64-bit encryption operand generator 14642. The input end of the second internal encryption key storage 14644 is connected to the other output end of the encryption key setter 142, and the output end of the second internal encryption key storage 14644 is connected to the other input end of the second 32-bit encryption operand generator 14641 and the other input end of the first 64-bit encryption operand generator 14642. In the external encryption key mode, the encryption key setter 142 starts the second external encryption key inputter 14643 and outputs the external encryption key. In the internal encryption key mode, the encryption key setter 142 starts the second internal encryption key storage 14644 and outputs the internal encryption key. The second thirty-two-bit encryption operand generator 14641 and the first sixty-four-bit encryption operand generator 14642 respectively generate the second encryption operand according to the external encryption key or the internal encryption key. The input end of the second encryption logic operator G12 is respectively connected to the output end of the second thirty-two-bit encryption operand generator 14641 and the output end of the first sixty-four-bit encryption operand generator 14642. The second encryption operand and the first encryption sequence ES1 are calculated and encrypted by the second encryption logic operator G12 to obtain the second encryption sequence ES2.

[0033] In one embodiment, see Figure 5The third parallel stream encryption unit 1466 includes a second sixty-four-bit encryption operand generator 14661, a one hundred and twenty-eight-bit encryption operand generator 14662, a third external encryption key input device 14663, a third internal encryption key storage device 14664 and a third encryption logic operator G13. (The upper ends of the sixteen-bit encryption operand generator 14621, the first thirty-two-bit encryption operand generator 14622, the second thirty-two-bit encryption operand generator 14641, the first sixty-four-bit encryption operand generator 14642, the second sixty-four-bit encryption operand generator 14661, and the one hundred and twenty-eight-bit encryption operand generator 14662 are collectively referred to as encryption operand generators) The input end of the third external encryption key input 14663 is connected to the output end of the encryption key setter 142, and the output end of the third external encryption key input 14663 is connected to the input end of the second sixty-four-bit encryption operand generator 14661 and the input end of the one hundred and twenty-eight-bit encryption operand generator 14662. The input end of the third internal encryption key storage 14664 is connected to the other output end of the encryption key setter 142, and the output end of the third internal encryption key storage 14664 is connected to the other input end of the second 64-bit encryption operand generator 14661 and the other input end of the 128-bit encryption operand generator 14662. In the external encryption key mode, the encryption key setter 142 activates the third external encryption key input 14663 and outputs the external encryption key. In the internal encryption key mode, the encryption key setter 142 activates the third internal encryption key storage 14664 and outputs the internal encryption key. The second 64-bit encryption operand generator 14661 and the 128-bit encryption operand generator 14662 generate the third encryption operand according to the external encryption key or the internal encryption key. The output end of the second sixty-four-bit encryption operand generator 14661 and the output end of the one hundred and twenty-eight-bit encryption operand generator 14662 are connected to the third encryption logic operator G13, and the third encryption operand and the second encryption sequence ES2 are calculated and encrypted by the third encryption logic operator G13 to obtain a third encryption sequence ES3.

[0034] In one embodiment, the first external encryption key input 14623, the second external encryption key input 14643, and the third external encryption key input 14663 respectively include an encryption key generator and an encryption controller (not shown). The encryption key generator may be (but not limited to) a key generator (Key Generator), a random number generator (Random Number Generator, RNG) or a pseudo-random number generator (Pseudorandom Number Generator, PRNG) and other devices that can generate various sequences, which are not limited in this application. The encryption key generator generates an external encryption key according to the external key encryption mode. The encryption controller may be (but not limited to) a controller (Controller) or other device that can control the output of a signal, which is not limited in this application. The encryption controller outputs the external encryption key to the encryption operand generator according to the external key encryption mode.

[0035] In another embodiment, the first external encryption key input device 14623, the second external encryption key input device 14643, and the third external encryption key input device 14663 are encryption input controllers (not shown), and the encryption input controller includes an encryption input device and an encryption controller. The encryption input device can be (but not limited to) an input device (InputDevice), a keyboard (Keyboard), a computer (Computer) or other devices that can be used to provide data and control signals, which are not limited in this application. The encryption input device is used to input an external encryption key. The encryption controller can be (but not limited to) a controller (Controller) or other devices that can control signal output. The encryption controller outputs the external encryption key to the encryption operand generator based on the input external encryption key and the external key encryption mode.

[0036] In one embodiment, the first internal encryption key storage 14624, the second internal encryption key storage 14644, and the third internal encryption key storage 14664 may be (but not limited to) a persistent memory device that can be used to store and manage data, which is not limited in this application. The first internal encryption key storage 14624, the second internal encryption key storage 14644, and the third internal encryption key storage 14664 output the internal encryption key of the encryption operand generator according to the internal encryption key mode.

[0037] In one embodiment, see Figure 6The 16-bit encryption operand generator 14621, the first 32-bit encryption operand generator 14622, the second 32-bit encryption operand generator 14641, the first 64-bit encryption operand generator 14642, the second 64-bit encryption operand generator 14661, and the 128-bit encryption operand generator 14662 respectively include an encryption linear feedback shift register (LFSR) and one or more encryption logic gates (Logic Gate), the encryption linear feedback shift register has the internal encryption key or the external encryption key, the encryption linear feedback shift register performs a logic operation on a plurality of encryption bit taps of the internal encryption key or the external encryption key through the generated encryption logic gate to obtain the encryption operand, the encryption operand is fed back to the first bit of the encryption linear feedback shift register as an update of the encryption key, the update means that the encryption operand will be input to the first bit of the encryption key of the encryption linear feedback shift register, so that the original first bit of the encryption key is moved to the second bit, the original second bit of the encryption key is moved to the third bit, and so on, the original last bit of the encryption key will be covered by the previous bit, thereby achieving the update of the encryption key.The 16-bit encryption operand generator 14621 includes an encryption linear feedback shift register 14621L (storing 16-bit encryption keys a[1] to a

[16] , a[n] is the nth bit of the 16-bit encryption key) and generates an encryption logic gate 14621G. The first 32-bit encryption operand generator 14622 includes an encryption linear feedback shift register 14622L (storing the first 32-bit encryption keys b[1] to b

[32] , b[n] is the nth bit of the first 32-bit encryption key) and generates an encryption logic gate 14622G. The second 32-bit encryption operand generator 14641 includes an encryption linear feedback shift register 14641L (storing the second 32-bit encryption keys c[1] to c

[32] , c[n] is the nth bit of the second thirty-two-bit encryption key) and generates an encryption logic gate 14641G, a first sixty-four-bit encryption operand generator 14642 includes an encryption linear feedback shift register 14642L (stores the first sixty-four-bit encryption keys d[1] to d

[64] , d[n] is the nth bit of the first sixty-four-bit encryption key) and generates an encryption logic gate 14642G, a second sixty-four-bit encryption operand generator 14661 includes an encryption linear feedback shift register 14661L (stores the second sixty-four-bit encryption keys e[1] to e

[64] , e[n] is the second six The one hundred and twenty-eight-bit encryption operand generator 14662 includes an encryption linear feedback shift register 14662L (storing the one hundred and twenty-eight-bit encryption keys f[1] to f

[128] , f[n] is the nth bit of the one hundred and twenty-eight-bit encryption key) and generates an encryption logic gate 14661G, wherein the sixteen-bit encryption key, the first thirty-second-bit encryption key, the second thirty-second-bit encryption key, the first sixty-four-bit encryption key, the second sixty-four-bit encryption key and the one hundred and twenty-eight-bit encryption key can be internal encryption keys or external encryption keys.The encryption linear feedback shift register 14621L performs a logic operation on the plurality of encryption bit taps of the 16-bit encryption key through the generated encryption logic gate 14621G to obtain the encryption operation number A1; the encryption linear feedback shift register 14622L performs a logic operation on the plurality of encryption bit taps of the first 32-bit encryption key through the generated encryption logic gate 14622G to obtain the encryption operation number B1; the encryption linear feedback shift register 14641L performs a logic operation on the plurality of encryption bit taps of the second 32-bit encryption key through the generated encryption logic gate 14641G to obtain the encryption operation number C1; The encryption linear feedback shift register 14642L performs a logic operation on the plurality of encryption bit taps of the first sixty-four-bit encryption key through the generated encryption logic gate 14642G to obtain the encryption operand D1; the encryption linear feedback shift register 14661L performs a logic operation on the plurality of encryption bit taps of the second sixty-four-bit encryption key through the generated encryption logic gate 14661G to obtain the encryption operand E1; the encryption linear feedback shift register 14662L performs a logic operation on the plurality of encryption bit taps of the one hundred and twenty-eight-bit encryption key through the generated encryption logic gate 14662G to obtain the encryption operand F1. In one embodiment, the generated encryption logic gates 14621G, 14622G, 14641G, 14642G, 14661G, 14662G and the logic operation all use exclusive or gates (XOR) as operations. In other embodiments, the generated encryption logic gates 14621G, 14622G, 14641G, 14642G, 14661G, 14662G and logic operations can be implemented using AND gates, OR gates, other logic gates or a combination of multiple logic gates, which is not limited in the present application.

[0038] In one embodiment, the number of bits of the encryption bit tap is two. In other embodiments, the number of the encryption bit tap may be an even number.

[0039] In one embodiment, the first encryption logic operator G11 includes a first encryption logic operation module G112 and a first data encryption logic gate G114. The input end of the first encryption logic operation module G112 is respectively connected to the output end of the 16-bit encryption operand generator 14621 and the output end of the first 32-bit encryption operand generator 14622. The first encryption logic operation module G112 receives the encryption operands A1 and B1 and calculates to obtain a first parallel encryption operand. The input end of the first data encryption logic gate G114 receives the first parallel encryption operand and the data packet respectively. The first data encryption logic gate G114 is used to encrypt the data packet via the first parallel encryption operand and output a first encryption sequence ES1; the second encryption logic operator G12 includes a second encryption logic operation module G122 and a second data encryption logic gate G124. The input end of the second encryption logic operation module G122 is respectively connected to the output end of the second thirty-two-bit encryption operand generator 14641 and the output end of the first sixty-four-bit encryption operand generator 14642. The second encryption logic operation module G122 receives the encryption operands C1 and D1 and calculates to obtain the second parallel encryption operand. The input end of the second data encryption logic gate G124 receives the second parallel encryption operand and the first encryption sequence ES1 respectively. The second data encryption logic gate G124 is used to encrypt the first encryption sequence ES1 through the second parallel encryption operand and output the second encryption sequence ES2; the third logic operator G13 includes a third encryption logic operation module G132 and a third data encryption logic gate G134. The input end of the third encryption logic operation module G132 is respectively connected to the output end of the second sixty-four-bit encryption operand generator 14661 and the output end of the one hundred and twenty-eight-bit encryption operand generator 14662. The third encryption logic operation module G132 receives the encryption operands E1 and F1 and calculates to obtain a third parallel encryption operand. The input end of the third data encryption logic gate G134 receives the third parallel encryption operand and the second encryption sequence ES2 respectively. The third data encryption logic gate G134 is used to encrypt the second encryption sequence ES2 via the third parallel encryption operand and output the third encryption sequence ES3. The first encryption logic operation module G112, the first data encryption logic gate G114, the second encryption logic operation module G122, the second data encryption logic gate G124, the third encryption logic operation module G132, and the third data encryption logic gate G134 are one or more logic gates. The logic gates all use exclusive or gates (Exclusive Or, XOR) as operations.

[0040] In other embodiments, the logic gate may be implemented using an AND gate, an OR gate, other logic gates, or a combination of multiple logic gates, which is not limited in the present application.

[0041] In one embodiment, please refer to Figure 1 , the receiving device 20 includes a data target module 22 and a data decryption module 24. The data target module 22 can also be a cache memory, a dynamic random access memory (DRAM), or a persistent memory to store and manage the received data. The data decryption module 24 can be a processor or a microprocessor for performing decryption calculation processing, which is not limited in this application. Finally, the data decryption module 24 is used to decrypt the received encryption sequence ES through the internal key decryption mode and the external decryption key encryption mode corresponding to the internal key encryption mode and the external key encryption mode, and then output the restored original data packet to the data target module 22 for storage.

[0042] In one embodiment, see Figure 7 The data decryption module 24 includes a decryption key setter 242, a decryption level setter 244, and a three-order parallel decryptor 246. The output end of the decryption key setter 242 is connected to the input end of the three-order parallel decryptor 246, and the decryption level setter 244 is connected to the other input end of the three-order parallel decryptor 246. The decryption key setter 242 includes an internal key decryption mode and an external key decryption mode. The decryption key setter 242 is used to select the internal key decryption mode or the external key decryption mode and update the key of the three-order parallel decryptor 246 accordingly. The internal key decryption mode or the external key decryption mode will correspond to the internal key encryption mode or the external key encryption mode. Specifically, the internal decryption key selected by the internal key decryption mode will be the same as the internal encryption key selected by the internal key encryption mode; the external decryption key selected by the external key decryption mode will be the same as the external encryption key selected by the external key encryption mode. The decryption level setter 244 is used to select the decryption level of the three-stage parallel decryptor 246. The three-stage parallel decryptor 246 decrypts the encrypted sequence ES according to the selected decryption level and outputs a restored data packet.

[0043] In one embodiment, the three-stage parallel decryptor 246 includes a first parallel stream decryption unit 2462, a second parallel stream decryption unit 2464, and a third parallel stream decryption unit 2466 connected in sequence. Figure 8The first parallel stream decryption unit 2462 includes a 16-bit decryption operand generator 24621, a first 32-bit decryption operand generator 24622, a first external decryption key input 24623, a first internal decryption key storage 24624, and a first decryption logic operator G21. The input end of the first external decryption key input 24623 is connected to the output end of the decryption key setter 242, and the output end of the first external decryption key input 24623 is connected to the input end of the 16-bit decryption operand generator 24621 and the input end of the first 32-bit decryption operand generator 24622. The input end of the first internal decryption key storage 24624 is connected to the other output end of the decryption key setter 242, and the output end of the first internal decryption key storage 24624 is connected to the other input end of the 16-bit decryption operand generator 24621 and the other input end of the first 32-bit decryption operand generator 24622. In the external decryption key mode, the decryption key setter 242 activates the first external decryption key inputter 24623 and outputs the external decryption key. In the internal decryption key mode, the decryption key setter 242 activates the first internal decryption key storage 24624 and outputs the internal decryption key. The sixteen-bit decryption operand generator 24621 and the first thirty-two-bit decryption operand generator 24622 respectively generate the first decryption operand according to the external decryption key or the internal decryption key. The input end of the first decryption logic operator G21 is respectively connected to the output end of the sixteen-bit decryption operand generator 24621 and the output end of the first thirty-two-bit decryption operand generator 24622. The first decryption operand and the encryption sequence ES (or the first encryption sequence ES1) are calculated and decrypted by the first decryption logic operator G21 to obtain a restored data packet.

[0044] In one embodiment, see Fig. 9The second parallel stream decryption unit 2464 includes a second 32-bit decryption operand generator 24641, a first 64-bit decryption operand generator 24642, a second external decryption key input 24643, a second internal decryption key storage 24644, and a second decryption logic operator G22. The input end of the second external decryption key input 24643 is connected to the output end of the decryption key setter 242, and the output end of the second external decryption key input 24643 is connected to the input end of the second 32-bit decryption operand generator 24641 and the input end of the first 64-bit decryption operand generator 24642. The input end of the second internal decryption key storage 24644 is connected to the other output end of the decryption key setter 242, and the output end of the second internal decryption key storage 24644 is connected to the other input end of the second 32-bit decryption operand generator 24641 and the other input end of the first 64-bit decryption operand generator 24642. In the external decryption key mode, the decryption key setter 242 starts the second external decryption key inputter 24643 and outputs the external decryption key. In the internal decryption key mode, the decryption key setter 242 starts the second internal decryption key storage 24644 and outputs the internal decryption key. The second 32-bit decryption operand generator 24641 and the first 64-bit decryption operand generator 24642 ​​respectively generate the second decryption operand according to the external decryption key or the internal decryption key. The input end of the second decryption logic operation G22 is respectively connected to the output end of the second 32-bit decryption operand generator 24641 and the output end of the first 64-bit decryption operand generator 24642. The second decryption operand and the second encryption sequence ES2 are calculated and decrypted by the second decryption logic operator G22 to obtain the first encryption sequence ES1.

[0045] In one embodiment, see Fig.10The third parallel stream decryption unit 2466 includes a second sixty-four-bit decryption operand generator 24661, a one hundred and twenty-eight-bit decryption operand generator 24662, a third external decryption key input device 24663, a third internal decryption key storage device 24664 and a third decryption logic operator G23. (Herein, the upper bits of the sixteen-bit decryption operand generator 24621, the first thirty-two-bit decryption operand generator 24622, the second thirty-two-bit decryption operand generator 24641, the first sixty-four-bit decryption operand generator 24642, the second sixty-four-bit decryption operand generator 24661, and the one hundred and twenty-eight-bit decryption operand generator 24662 are collectively referred to as the decryption operand generator) The input end of the third external decryption key input 24663 is connected to the output end of the decryption key setter 242, and the output end of the third external decryption key input 24663 is connected to the input end of the second sixty-four-bit decryption operand generator 24661 and the input end of the one hundred and twenty-eight-bit decryption operand generator 24662. The input end of the third internal decryption key storage 24664 is connected to the other output end of the decryption key setter 242, and the output end of the third internal decryption key storage 24664 is connected to the other input end of the second 64-bit decryption operand generator 24661 and the other input end of the 128-bit decryption operand generator 24662. In the external decryption key mode, the decryption key setter 242 activates the third external decryption key inputter 24663 and outputs the external decryption key. In the internal decryption key mode, the decryption key setter 242 activates the third internal decryption key storage 24664 and outputs the internal decryption key. The second 64-bit decryption operand generator 24661 and the 128-bit decryption operand generator 24662 generate the third decryption operand according to the external decryption key or the internal decryption key. The input end of the third decryption logic operator G23 is respectively connected to the output end of the second sixty-four-bit decryption operand generator 24661 and the output end of the one hundred and twenty-eight-bit decryption operand generator 24662. The third decryption operand and the third encryption sequence ES3 are calculated and decrypted by the third decryption logic operator G23 to obtain the second encryption sequence ES2.

[0046] In one embodiment, the first external decryption key input device 24623, the second external decryption key input device 24643, and the third external decryption key input device 24663 respectively include a decryption key generator and a decryption controller (not shown). The decryption key generator may be (but not limited to) a key generator (Key Generator), a random number generator (Random Number Generator, RNG) or a pseudo-random number generator (Pseudorandom Number Generator, PRNG) and other devices that can generate various sequences, which are not limited in this application. The decryption key generator generates an external decryption key according to the external key decryption mode. The decryption controller may be (but not limited to) a controller (Controller) or other device that can control the output of a signal, which is not limited in this application. The decryption controller outputs the external decryption key to the decryption operand generator according to the external key decryption mode.

[0047] In another embodiment, the first external decryption key input device 24623, the second external decryption key input device 24643, and the third external decryption key input device 24663 are decryption input controllers (not shown), and the decryption input controller includes a decryption input device and a decryption controller. The decryption input device can be (but is not limited to) an input device (InputDevice), a keyboard (Keyboard), a computer (Computer) or other devices that can be used to provide data and control signals, which are not limited in this application. The decryption input device is used to input an external decryption key. The decryption controller can be (but is not limited to) a controller (Controller) or other devices that can control signal output. The decryption controller outputs the external decryption key to the decryption operand generator based on the input external decryption key and the external key decryption mode.

[0048] In one embodiment, the first internal decryption key storage 24624, the second internal decryption key storage 24644, and the third internal decryption key storage 24664 can be (but not limited to) a persistent memory or other device that can be used to store and manage data, which is not limited in this application. The first internal decryption key storage 24624, the second internal decryption key storage 24644, and the third internal decryption key storage 24664 output the internal decryption key of the decryption operand generator according to the internal decryption key mode.

[0049] In one embodiment, see Fig.11The 16-bit decryption operand generator 24621, the 132-bit decryption operand generator 24622, the 232-bit decryption operand generator 24641, the 164-bit decryption operand generator 24642, the 264-bit decryption operand generator 24661, and the 128-bit decryption operand generator 24662 respectively include a decryption linear feedback shift register (LFSR) and one or more decryption logic gates (Logic Gates) Gate), the decryption linear feedback shift register has the internal decryption key or the external decryption key, the decryption linear feedback shift register performs a logic operation on a plurality of decryption bit taps of the internal decryption key or the external decryption key through the generation decryption logic gate to obtain the decryption operand, the decryption operand is fed back to the first bit of the decryption linear feedback shift register as the update of the decryption key, the update means that the decryption operand is input to the first bit of the decryption key of the decryption linear feedback shift register, so that the original first bit of the decryption key is moved to the second bit, the original second bit of the decryption key is moved to the third bit, and so on, the original last bit of the decryption key is covered by the previous bit, thereby achieving the update of the decryption key.The 16-bit decryption operand generator 24621 includes a decryption linear feedback shift register 24621L (which stores the same 16-bit decryption key as the 16-bit encryption key a[1] to a

[16] , and is labeled the same as the 16-bit encryption key) and a decryption logic gate 24621G. The first 32-bit decryption operand generator 24622 includes a decryption linear feedback shift register 24622L (which stores the same 132-bit decryption key as the first 32-bit encryption key b[1] to b

[32] , and is labeled the same ... The first 32-bit encryption key) and the decryption logic gate 24622G are generated, the second 32-bit decryption operand generator 24641 includes a decryption linear feedback shift register 24641L (which stores the second 32-bit decryption key that is the same as the second 32-bit encryption key c[1] to c

[32] , and the label is the same as the second 32-bit encryption key) and the decryption logic gate 24641G are generated, the first 64-bit decryption operand generator 24642 ​​includes a decryption linear feedback shift register 24642L (which stores the second 32-bit decryption key that is the same as the first 64-bit encryption key The first sixty-four-bit decryption key which is the same as the first sixty-four-bit encryption key d[1] to d

[64] and is labeled the same as the first sixty-four-bit encryption key) and generates a decryption logic gate 24642G, a second sixty-four-bit decryption operand generator 24661 including a decryption linear feedback shift register 24661L (which stores the second sixty-four-bit decryption key which is the same as the second sixty-four-bit encryption key e[1] to e

[64] and is labeled the same as the second sixty-four-bit encryption key) and generates a decryption logic gate 24661G, a one hundred and twenty-eight decryption operand generator 24661L The operation generator 24662 includes a decryption linear feedback shift register 24662L (which stores a one hundred and twenty-eight-bit decryption key which is the same as the one hundred and twenty-eight-bit encryption key f[1] to f

[128] , and is labeled the same as the one hundred and twenty-eight-bit encryption key) and a decryption logic gate 24662G, wherein the sixteen-bit decryption key, the first thirty-second-bit decryption key, the second thirty-second-bit decryption key, the first sixty-four-bit decryption key, the second sixty-four-bit decryption key and the one hundred and twenty-eight-bit decryption key can be internal decryption keys or external decryption keys.The decryption linear feedback shift register 24621L performs a logic operation on the plurality of decryption bit taps of the 16-bit decryption key through the generation decryption logic gate 24621G to obtain a decryption operand A2; the decryption linear feedback shift register 24622L performs a logic operation on the plurality of decryption bit taps of the first 32-bit decryption key through the generation decryption logic gate 24622G to obtain a decryption operand B2; the decryption linear feedback shift register 24641L performs a logic operation on the plurality of decryption bit taps of the second 32-bit decryption key through the generation decryption logic gate 24641G to obtain a decryption operand C2; The decryption linear feedback shift register 24642L performs a logical operation on the plurality of decryption bit taps of the first sixty-four-bit decryption key through the generation decryption logic gate 24642G to obtain a decryption operand D2; the decryption linear feedback shift register 24661L performs a logical operation on the plurality of decryption bit taps of the second sixty-four-bit decryption key through the generation decryption logic gate 24661G to obtain a decryption operand E2; the decryption linear feedback shift register 24662L performs a logical operation on the plurality of decryption bit taps of the one hundred and twenty-eight-bit decryption key through the generation decryption logic gate 24662G to obtain a decryption operand F2. In principle, the generated decryption logic gates 24621G, 24622G, 24641G, 24642G, 24661G, and 24662G in the three-stage parallel decryptor 246 must perform reverse logic operations with the three-stage parallel encryptor 146 (for example, if the three-stage parallel encryptor 146 is AND, then the three-stage parallel decryptor 246 is NAND).

[0050] In one embodiment, the number of bits of the decryption bit tap is two. In other embodiments, the number of the decryption bit tap may be an even number.

[0051] In one embodiment, the first decryption logic operator G21 includes a first decryption logic operation module G212 and a first data decryption logic gate G214. The input end of the first decryption logic operation module G212 is respectively connected to the output end of the 16-bit decryption operand generator 24621 and the output end of the first 32-bit decryption operand generator 24622. The first decryption logic operation module G212 receives the decryption operands A2 and B2 and calculates to obtain a first parallel decryption operand. The input end of the first data decryption logic gate G214 receives the first parallel decryption operand and the encryption sequence ES or the first encryption sequence ES1 respectively. The first data decryption logic gate G214 is used to decrypt the encryption sequence ES or the first encryption sequence ES1 through the first parallel decryption operand and output the restored data packet; the second decryption logic operator G22 includes a second decryption logic operation module G222 and a second data decryption logic gate G224. The input end of the second decryption logic operation module G22 is respectively connected to the output end of the second 32-bit decryption operand generator 24641 and the output end of the first 64-bit decryption operand generator 24642. The second decryption logic operation module G222 receives the decryption operands C2 and D2 and calculates to obtain a second parallel decryption operand. The input end of the second data decryption logic gate G224 receives the second parallel decryption operand and the second encryption sequence ES2 respectively. The second data decryption logic gate G224 is used to decrypt the second encryption sequence ES2 through the second parallel decryption operand and output the first encryption sequence ES1. The third logic operator G23 includes a third decryption logic operation module G232 and a third data decryption logic gate G234. The input end of the third decryption logic operation module G232 is respectively connected to the output end of the second 64-bit decryption operand generator 24661 and the output end of the 128-bit decryption operand generator 24662. The third decryption logic operation module G232 receives the decryption operands E2 and F2 and calculates to obtain a third parallel decryption operand. The input end of the third data decryption logic gate G234 receives the third parallel decryption operand and the third encryption sequence ES3 respectively, and the third data decryption logic gate G234 is used to decrypt the third encryption sequence ES3 through the third parallel decryption operand and output the second encryption sequence ES2. In principle, the first decryption logic operation module G212, the first data decryption logic gate G214, the second decryption logic operation module G222, the second data decryption logic gate G224, the third decryption logic operation module G232, and the third data decryption logic gate G234 must perform reverse logic operations with the three-level parallel encryptor 146 (for example, if the three-level parallel encryptor 146 is AND, then the three-level parallel decryptor 246 is NAND).

[0052] The above is a description of a specific embodiment of the hardware architecture of the present application. The working procedure of the present application will be further described below. Please refer to Fig.12 , is a flow chart of the hybrid multi-stage operation encryption and decryption system of this application:

[0053] Before data transmission, the encryption key setter 142 and the decryption key setter 242 will set the same external key encryption / decryption mode and internal key encryption / decryption mode according to user settings / automatic configuration. For example: when the encryption key setter 142 selects the 16-bit encryption operand generator 14621 in the three-order parallel encryptor 146 as the external key encryption mode, the first 32-bit encryption operand generator 14622 as the external key encryption mode, the second 32-bit encryption operand generator 14641 as the external key encryption mode, the first 64-bit encryption operand generator 14642 as the external key encryption mode, the second 64-bit encryption operand generator 14661 as the internal key encryption mode, and the one hundred and twenty-eight-bit encryption operand generator 14662 as the internal key encryption mode (setting four external key encryption modes and two internal key encryption modes) ), the decryption key setter 242 selects the sixteen-bit decryption operand generator 24621 in the three-order parallel decryptor 246 as the external key decryption mode, the first thirty-two-bit decryption operand generator 24622 as the external key decryption mode, the second thirty-two-bit decryption operand generator 24641 as the external key decryption mode, the first sixty-four-bit decryption operand generator 24642 ​​as the external key decryption mode, the second sixty-four-bit decryption operand generator 24661 as the internal key decryption mode, and the one hundred and twenty-eight-bit decryption operand generator 24662 as the internal key decryption mode (setting four external key decryption modes and two internal key decryption modes).

[0054] Specifically, the encryption operand generator may be various permutations and combinations of an external key encryption mode and an internal key encryption mode; the decryption operand generator may be various permutations and combinations of an external key decryption mode and an internal key decryption mode matched with the encryption operand generator. Specifically, any one or more of the encryption operand generators may be set to an external encryption key mode or an internal encryption key mode according to the aforementioned permutations and combinations; any one or more of the decryption operand generators may be set to an external decryption key mode or an internal decryption key mode according to the matching of the decryption operand generators. The aforementioned various permutations, combinations and changes are not within the scope of the present application (for example: when two external key encryption modes and four internal key encryption modes are set, two external key decryption modes and four internal key decryption modes will be set accordingly; when one external key encryption mode and five internal key encryption modes are set accordingly, one external key decryption mode and five internal key decryption modes will be set accordingly; when five external key encryption modes and one internal key encryption mode are set accordingly, five external key decryption modes and one internal key decryption mode will be set accordingly; when six external key encryption modes are set accordingly, six external key decryption modes will be set accordingly; and when six internal key encryption modes are set accordingly, six internal key decryption modes will be set accordingly.

[0055] Similarly, before data transmission, the encryption level setter 144 and the decryption level setter 244 will set the same encryption / decryption level according to the user setting / automatic configuration (for example, when the encryption level setter 144 selects the encryption level of the three-stage parallel encryptor 146 as the third stage, the decryption level setter 244 will select the decryption level of the three-stage parallel decryptor 246 as the third stage), which is explained here in advance.

[0056] First, in the transmitting device 10 , the data packet is output from the data generating module 12 to the data encrypting module 14 (step S201 ).

[0057] The data packet is received by the three-stage parallel encryptor 146 of the data encryption module 14 and is encrypted according to the external key encryption mode or internal key encryption mode and the encryption level set by the encryption key setter 142 and the encryption level setter 144 (step S202 ).

[0058] The encrypted data packet is outputted by the three-stage parallel encryptor 146 as an encrypted sequence ES to the receiving device 20 (step S203).

[0059] The encrypted sequence ES is decrypted by the three-stage parallel decryptor 246 in the data decryption module 24 according to the external key decryption mode or internal key decryption mode and the decryption level set by the decryption key setter 242 and the decryption level setter 244 (step S204 ).

[0060] The decrypted encrypted sequence ES is outputted by the three-stage parallel decryptor 246 as a restored data packet to the data target module 22 for storage (step S205 ).

[0061] The following specifically lists an embodiment, in which the three-stage parallel encryptor 146 includes a first parallel stream encryption unit 1462, a second parallel stream encryption unit 1464, and a third parallel stream encryption unit 1466 connected in sequence, and the three-stage parallel decryptor 246 includes a first parallel stream decryption unit 2462, a second parallel stream decryption unit 2464, and a third parallel stream decryption unit 2466 connected in sequence, please refer to Fig.13 , Fig.14 , which is a schematic diagram of the encryption process of the three-stage parallel encryptor 146 and the decryption process of the three-stage parallel decryptor 246 of the present application.

[0062] The aforementioned step S202 can be replaced by one or more steps among steps S2021-S2023 according to the encryption level, and the multiple steps must exist in sequence (for example: in the case of the second-level encryption level, step S202 needs to be replaced by the corresponding step S2022, and step S2021 must also be included at this time, so step S202 can be replaced by steps S2021-S2022 in the case of the second-level encryption level); step S204 can be replaced by one or more steps among steps S2041-S2043 according to the decryption level, and the multiple steps must exist in reverse sequence (for example: in the case of the second-level decryption level, step S204 needs to be replaced by the corresponding step S2042, and step S2043 must also be included at this time, so step S204 can be replaced by steps S2042-S2043). The contents of the steps previously described will not be repeated here, but will be described first.

[0063] In this embodiment, the logical operations described in the three-stage parallel encryptor 146 are all XOR; the logical operations described in the three-stage parallel decryptor 246 are all XOR (corresponding to the logical operations of the five-stage encryptor).

[0064] In other embodiments, the aforementioned logical operation can be other logical operations such as AND, NAND, which are not limited in this application; in this embodiment, the plurality of encryption bit taps selected by the encryption linear feedback shift register and the plurality of decryption bit taps and the number selected by the decryption feedback shift register are only one embodiment, and the encryption / decryption bit taps can be selected and changed in quantity according to actual needs (for example: select the first and seventh bits as encryption / decryption bit taps; select the fourth, fifth, sixth, and eighth bits as encryption / decryption bit taps; select the second and thirty-seventh bits in the case of more bits, etc.), and the selection of the encryption / decryption bit taps is not within the scope of the application. The aforementioned decryption bit taps will be selected corresponding to the encryption bit taps to match the decryption. In this embodiment, the number of encryption bit taps of the sixteen-bit encryption operand generator 14621, the first thirty-two-bit encryption operand generator 14622, the second thirty-two-bit encryption operand generator 14641, the first sixty-four-bit encryption operand generator 14642, the second sixty-four-bit encryption operand generator 14661, and the one hundred and twenty-eight-bit encryption operand generator 14662 is two; the number of decryption bit taps of the sixteen-bit decryption operand generator 24621, the first thirty-two-bit decryption operand generator 24622, the second thirty-two-bit decryption operand generator 24641, the first sixty-four-bit decryption operand generator 24642, the second sixty-four-bit decryption operand generator 24661, and the one hundred and twenty-eight-bit decryption operand generator 24662 is two, which is stated here in advance.

[0065] In one embodiment, the number of bits of the aforementioned encryption bit tap and decryption bit tap is an even number.

[0066] The following describes steps S2021-S2023. Please refer to them together. Figure 6 , Fig.13 The data packet is received by the first parallel stream encryption unit 1462 and encrypted and then output (step S2021).

[0067] In one embodiment, the sixteen-bit encryption operand generator 14621 in the first parallel stream encryption unit 1462 extracts the second bit a[2] and the fifteenth bit a

[15] for logical operation to obtain the encryption operand A1, and the first thirty-two-bit encryption operand generator 14622 extracts the second bit b[2] and the thirty-first bit b

[31] for logical operation to obtain the encryption operand B1. The encryption operand A1 and the encryption operand B1 are operated via the first encryption logic operation module G112 to obtain the first parallel encryption operand, which is encrypted and output via the first data decryption logic gate G114. When the encryption level setter 144 is set to encryption of level two or above, the first encryption sequence ES1 output by the first parallel stream encryption unit 1462 is output to the second stream encryption unit 1464. When the encryption level setter 144 is set to encryption of level one, the first encryption sequence ES1 output by the first parallel stream encryption unit 1462 is output to the receiving device 20.

[0068] The first encrypted sequence ES1 is received by the second parallel stream encryption unit 1464 and is encrypted and then output (step S2022 ).

[0069] In one embodiment, the second thirty-two-bit encryption operand generator 14641 in the second parallel stream encryption unit 1464 extracts the second bit c[2] and the thirty-two-bit c

[32] for logical operation to obtain the encryption operand C1, and the first sixty-four-bit encryption operand generator 14642 extracts the first bit d[1] and the sixty-fourth bit d

[64] for logical operation to obtain the encryption operand D1. The encryption operand C1 and the encryption operand D1 are operated via the second decryption logic operation module G122 to obtain the second parallel encryption operand, and the second parallel encryption operand is encrypted and output via the second data decryption logic gate G124. When the encryption level setter 144 is set to encryption of level three or above, the second encryption sequence ES2 output by the second parallel stream encryption unit 1464 will be output to the third parallel stream encryption unit 1466. When the encryption level setter 144 is set to level two, the second encryption sequence ES2 output by the second parallel stream encryption unit 1464 will be output to the receiving device 20.

[0070] The second encrypted sequence ES2 is received by the third parallel stream encryption unit 1466 and is encrypted and then output (step S2023).

[0071] In one embodiment, the second sixty-four-bit encryption operand generator 14661 in the third parallel stream encryption unit 1466 extracts the second bit e[2] and the sixty-third bit e

[63] for logical operation to obtain the encryption operand E1, and the one hundred and twenty-eight-bit encryption operand generator 14662 extracts the first bit f[1] and the first twenty-seventh bit f

[127] for logical operation to obtain the encryption operand F1. The encryption operand E1 and the encryption operand F1 are operated via the third decryption logic operation module G232 to obtain the third parallel encryption operand, and the third parallel encryption operand is encrypted and output via the third data decryption logic gate G234. When the encryption level setter 144 is set to the third level, the third encryption sequence ES3 output by the third parallel stream encryption unit 1466 will be output to the receiving device 20.

[0072] The following describes steps S2041-S2043. Please refer to Fig.11 , Fig.14 The third encrypted sequence ES3 is received and decrypted by the third parallel stream decryption unit 2466 and then output (step S2041 ).

[0073] In one embodiment, the second sixty-four-bit decryption operand generator 24661 in the third parallel stream decryption unit 2466 extracts the second bit e[2] and the sixty-third bit e

[63] for logical operation to obtain the decryption operand E2, and the one hundred and twenty-eight-bit decryption operand generator 24662 extracts the first bit f[1] and the first twenty-seventh bit f

[127] for logical operation to obtain the decryption operand F2. The decryption operand E2 and the decryption operand F2 are operated via the third decryption logic operation module G232 to obtain the third parallel decryption operand. The third parallel decryption operand and the third encryption sequence ES3 are decrypted and output via the third data decryption logic gate G234. When the decryption level setter 244 is set to the third level, the second encryption sequence ES2 output by the third parallel stream decryption unit 2466 will be output to the second parallel stream decryption unit 2464.

[0074] The second encrypted sequence ES2 is received and decrypted by the second parallel stream decryption unit 2464 and then output (step S2042 ).

[0075] The first thirty-two-bit decryption operand generator 24641 in the second parallel stream decryption unit 2464 extracts the second bit c[2] and the thirty-two-bit c

[32] for logical operation to obtain the decryption operand C1, and the first sixty-four-bit decryption operand generator 24642 ​​extracts the first bit d[1] and the sixty-fourth bit d

[64] for logical operation to obtain the decryption operand D1. The decryption operand C1 and the decryption operand D1 are operated via the second decryption logic operation module G222 to obtain the second parallel decryption operand, and the second parallel decryption operand is decrypted and output via the second data decryption logic gate G224. When the decryption level setter 244 is set to decryption of the second order or above, the first encryption sequence ES1 output by the second parallel stream decryption unit 2464 will be output to the first parallel stream decryption unit 2462.

[0076] The first encrypted sequence ES1 is received and decrypted by the first parallel stream decryption unit 2462 and then output (step S2043 ).

[0077] In one embodiment, the 16-bit decryption operand generator 24621 in the first parallel stream decryption unit 2462 extracts the second bit a[2] and the fifteenth bit a

[15] to perform a logical operation to obtain the decryption operand A2, and the first thirty-two-bit decryption operand generator 24622 extracts the second bit b[2] and the thirty-first bit b

[31] to perform a logical operation to obtain the decryption operand B2. The decryption operand A2 and the decryption operand B2 are operated by the first decryption logic operation module G212 to obtain the first parallel decryption operand, and the first parallel decryption operand is decrypted and output by the first data decryption logic gate G214. At this time, the output of the first parallel stream decryption unit 2462 is a restored data packet.

[0078] Compared with the prior art, the present application can adjust the key to an internal key or an external key according to the required encryption mode and adjust the encryption level according to the needs, and can implement different encryption methods through a set of hardware.

[0079] The present application has been described in detail above. However, what is described above is only a preferred embodiment of the present application and should not be used to limit the scope of implementation of the present application. That is, all equivalent changes and modifications made according to the scope of the patent application of the present application should still fall within the scope of the patent application of the present application.

Claims

1. A hybrid multi-stage operation encryption and decryption system, characterized in that: include: A transmitting end device comprises a data generating module and a data encryption module, wherein the data encryption module comprises an encryption key setter, an encryption level setter and a three-stage parallel encryptor, wherein the encryption key setter comprises an internal key encryption mode and an external key encryption mode, wherein the encryption key setter is used to select the internal key encryption mode or the external key encryption mode, and the encryption level setter is used to select the encryption level, wherein the data encryption module obtains at least one data packet from the data generating module, wherein the encryption key setter selects the internal key encryption mode or the external key encryption mode and updates the key of the three-stage parallel encryptor accordingly, and wherein the three-stage parallel encryptor encrypts the data packet according to the selected encryption level and outputs an encryption sequence; as well as A receiving end device, comprising a data target module and a data decryption module, wherein the data decryption module comprises a decryption key setter, a decryption level setter and a three-stage parallel decryptor, wherein the decryption key setter comprises an internal key decryption mode and an external key decryption mode, wherein the decryption key setter is used to select the internal key decryption mode or the external key decryption mode, wherein the decryption level setter selects the encryption level corresponding to the encryption level selected by the sending end device, wherein the data decryption module obtains the encryption sequence from the sending end device, wherein the decryption key setter selects the internal key decryption mode or the external key decryption mode corresponding to the internal key encryption mode or the external key encryption mode selected by the sending end device, and updates the key of the three-stage parallel decryptor accordingly, wherein the three-stage parallel decryptor decrypts the encryption sequence according to the selected decryption level and outputs the restored data packet to the data target module; The three-stage parallel encryptor includes a first parallel stream encryption unit, a second parallel stream encryption unit and a third parallel stream encryption unit connected in sequence; The first parallel stream encryption unit includes a sixteen-bit encryption operand generator, a first thirty-two-bit encryption operand generator, a first external encryption key input device, a first internal encryption key storage device and a first encryption logic operator. The sixteen-bit encryption operand generator and the first thirty-two-bit encryption operation generator generate a first encryption operand based on the first external encryption key of the first external encryption key input device or the first internal encryption key of the first internal encryption key storage device. The first encryption operand and the data packet are operated and encrypted via the first encryption logic operator to obtain a first encryption sequence.

2. The hybrid multi-stage operation encryption and decryption system as claimed in claim 1, characterized in that: The three-stage parallel decryptor includes a first parallel stream decryption unit, a second parallel stream decryption unit and a third parallel stream decryption unit connected in sequence.

3. The hybrid multi-stage operation encryption and decryption system as claimed in claim 2, characterized in that: The first parallel stream decryption unit includes a sixteen-bit decryption operand generator, a first thirty-two-bit decryption operand generator, a first external decryption key input device, a first internal decryption key storage device and a first decryption logic operator. The sixteen-bit decryption operand generator and the first thirty-two-bit decryption operation generator generate a first decryption operand based on a first external decryption key of the first external decryption key input device or a first internal decryption key of the first internal decryption key storage device. The first decryption operand and the first encryption sequence are operated and decrypted via the first decryption logic operator to obtain the restored data packet.

4. The hybrid multi-stage operation encryption and decryption system as claimed in claim 3, characterized in that: The second parallel stream encryption unit includes a second 32-bit encryption operand generator, a first 64-bit encryption operand generator, a second external encryption key input device, a second internal encryption key storage device and a second encryption logic operator. The second 32-bit encryption operand generator and the first 64-bit encryption operation generator generate a second encryption operand according to the second external encryption key of the second external encryption key input device or the second internal encryption key of the second internal encryption key storage device. The second encryption operand and the first encryption sequence are operated and encrypted via the second encryption logic operator to obtain a second encryption sequence. The second parallel stream decryption unit includes a second 32-bit decryption operand generator, a first 64-bit decryption operand generator, a second external decryption key input device, a second internal decryption key storage device and a second decryption logic operator. The second 32-bit decryption operand generator and the first 64-bit decryption operation generator generate a second decryption operand according to the second external decryption key of the second external decryption key input device or the second internal decryption key of the second internal decryption key storage device. The second decryption operand and the second encryption sequence are operated and decrypted via the second decryption logic operator to obtain the first encryption sequence.

5. The hybrid multi-stage operation encryption and decryption system as claimed in claim 4, characterized in that: The third parallel stream encryption unit includes a second sixty-four-bit encryption operand generator, a one hundred and twenty-eight-bit encryption operand generator, a third external encryption key input device, a third internal encryption key storage device, and a third encryption logic operator. The second sixty-four-bit encryption operand generator and the one hundred and twenty-eight-bit encryption operation generator generate a third encryption operand according to a third external encryption key of the third external encryption key input device or a third internal encryption key of the third internal encryption key storage device. The third encryption operand and the second encryption sequence are operated and encrypted by the third encryption logic operator to obtain a third encryption sequence. The third parallel stream decryption unit includes a second sixty-four-bit decryption operand generator, a one hundred and twenty-eight-bit decryption operand generator, a third external decryption key input device, a third internal decryption key storage device and a third decryption logic operator. The second sixty-four-bit decryption operand generator and the one hundred and twenty-eight-bit decryption operation generator generate a third decryption operand based on the third external decryption key of the third external decryption key input device or the third internal decryption key of the third internal decryption key storage device. The third decryption operand and the third encryption sequence are operated and decrypted via the third decryption logic operator to obtain the second encryption sequence.

6. The hybrid multi-stage operation encryption and decryption system as claimed in claim 5, characterized in that: The sixteen-bit encryption operand generator, the first thirty-two-bit encryption operand generator, the second thirty-two-bit encryption operand generator, the first sixty-four-bit encryption operation generator, the second sixty-four-bit encryption operand generator and the one hundred and twenty-eight-bit encryption operation generator respectively have an encryption linear feedback shift register and one or more generation encryption logic gates, and the generation encryption logic gate performs a tap operation on the encryption linear feedback shift register to obtain the first encryption operand, the second encryption operand or the third encryption operand; the sixteen-bit decryption operand generator, the first thirty-two-bit decryption operand generator, the second thirty-two-bit decryption operand generator, the first sixty-four-bit decryption operation generator, the second sixty-four-bit decryption operand generator and the one hundred and twenty-eight-bit decryption operation generator respectively have a decryption linear feedback shift register and one or more generation decryption logic gates, and the generation decryption logic gate performs a tap operation on the decryption linear feedback shift register to obtain the first decryption operand, the second decryption operand or the third decryption operand.

7. A transmitting device, characterized in that: include: Data generation module; as well as A data encryption module, the data encryption module includes an encryption key setter, an encryption level setter, and a three-stage parallel encryptor, the encryption key setter includes an internal key encryption mode and an external key encryption mode, the encryption key setter is used to select the internal key encryption mode or the external key encryption mode, the encryption level setter is used to select the encryption level, the data encryption module obtains at least one data packet from the data generation module, the encryption key setter selects the internal key encryption mode or the external key encryption mode and updates the key of the three-stage parallel encryptor accordingly, the three-stage parallel encryptor encrypts the data packet according to the selected encryption level and outputs an encryption sequence; The three-stage parallel encryptor includes a first parallel stream encryption unit, a second parallel stream encryption unit and a third parallel stream encryption unit connected in sequence; The first parallel stream encryption unit includes a sixteen-bit encryption operand generator, a first thirty-two-bit encryption operand generator, a first external encryption key input device, a first internal encryption key storage device and a first encryption logic operator. The sixteen-bit encryption operand generator and the first thirty-two-bit encryption operation generator generate a first encryption operand based on the first external encryption key of the first external encryption key input device or the first internal encryption key of the first internal encryption key storage device. The first encryption operand and the data packet are operated and encrypted via the first encryption logic operator to obtain a first encryption sequence.

8. The transmitting end device according to claim 7, characterized in that: The second parallel stream encryption unit includes a second thirty-two-bit encryption operand generator, a first sixty-four-bit encryption operand generator, a second external encryption key input device, a second internal encryption key storage device and a second encryption logic operator. The second thirty-two-bit encryption operand generator and the first sixty-four-bit encryption operation generator generate a second encryption operand based on the second external encryption key of the second external encryption key input device or the second internal encryption key of the second internal encryption key storage device. The second encryption operand and the first encryption sequence are operated and encrypted via the second encryption logic operator to obtain a second encryption sequence.

9. The transmitting end device according to claim 8, characterized in that: The third parallel stream encryption unit includes a second sixty-four-bit encryption operand generator, a one hundred and twenty-eight-bit encryption operand generator, a third external encryption key input device, a third internal encryption key storage device and a third encryption logic operator. The second sixty-four-bit encryption operand generator and the one hundred and twenty-eight-bit encryption operation generator generate a third encryption operand based on the third external encryption key of the third external encryption key input device or the third internal encryption key of the third internal encryption key storage device. The third encryption operand and the second encryption sequence are calculated and encrypted via the third encryption logic operator to obtain a third encryption sequence.

10. The transmitting end device according to claim 9, characterized in that: The sixteen-bit encryption operand generator, the first thirty-two-bit encryption operand generator, the second thirty-two-bit encryption operand generator, the first sixty-four-bit encryption operation generator, the second sixty-four-bit encryption operand generator and the one hundred and twenty-eight-bit encryption operation generator respectively have an encryption linear feedback shift register and one or more generation encryption logic gates, and the generation encryption logic gate performs a tap operation on the encryption linear feedback shift register to obtain the first encryption operand, the second encryption operand or the third encryption operand.

11. A receiving device, characterized in that: include: Data target module; as well as A data decryption module, the data decryption module includes a decryption key setter, a decryption level setter and a three-stage parallel decryptor, the decryption key setter includes an internal key decryption mode and an external key decryption mode, the decryption key setter is used to select the internal key decryption mode or the external key decryption mode, the decryption level setter selects the encryption level corresponding to the encryption level selected by the sending end device, the data decryption module obtains an encryption sequence from the sending end device, the decryption key setter selects the internal key decryption mode or the external key decryption mode corresponding to the internal key encryption mode or the external key encryption mode selected by the sending end device, and updates the key of the three-stage parallel decryptor accordingly, the three-stage parallel decryptor decrypts the encryption sequence according to the selected decryption level and outputs the restored data packet to the data target module; The three-stage parallel decryptor comprises a first parallel stream decryption unit, a second parallel stream decryption unit and a third parallel stream decryption unit connected in sequence; The first parallel stream decryption unit includes a sixteen-bit decryption operand generator, a first thirty-two-bit decryption operand generator, a first external decryption key input device, a first internal decryption key storage device and a first decryption logic operator. The sixteen-bit decryption operand generator and the first thirty-two-bit decryption operation generator generate a first decryption operand based on a first external decryption key of the first external decryption key input device or a first internal decryption key of the first internal decryption key storage device. The first decryption operand and the first encryption sequence are operated and decrypted by the first decryption logic operator to obtain the restored data packet.

12. The receiving device according to claim 11, characterized in that: The second parallel stream decryption unit includes a second thirty-two-bit decryption operand generator, a first sixty-four-bit decryption operand generator, a second external decryption key input device, a second internal decryption key storage device and a second decryption logic operator. The second thirty-two-bit decryption operand generator and the first sixty-four-bit decryption operation generator generate a second decryption operand based on the second external decryption key of the second external decryption key input device or the second internal decryption key of the second internal decryption key storage device. The second decryption operand and the second encryption sequence are operated and decrypted via the second decryption logic operator to obtain the first encryption sequence.

13. The receiving end device according to claim 12, characterized in that: The third parallel stream decryption unit includes a second sixty-four-bit decryption operand generator, a one hundred and twenty-eight-bit decryption operand generator, a third external decryption key input device, a third internal decryption key storage device and a third decryption logic operator. The second sixty-four-bit decryption operand generator and the one hundred and twenty-eight-bit decryption operation generator generate a third decryption operand based on the third external decryption key of the third external decryption key input device or the third internal decryption key of the third internal decryption key storage device. The third decryption operand and a third encryption sequence are operated and decrypted via the third decryption logic operator to obtain the second encryption sequence.

14. The receiving end device according to claim 13, characterized in that: The sixteen-bit decryption operand generator, the first thirty-two-bit decryption operand generator, the second thirty-two-bit decryption operand generator, the first sixty-four-bit decryption operation generator, the second sixty-four-bit decryption operand generator and the one hundred and twenty-eight-bit decryption operation generator respectively have a decryption linear feedback shift register and one or more generation decryption logic gates, and the generation decryption logic gate performs a tap operation on the decryption linear feedback shift register to obtain the first decryption operand, the second decryption operand or the third decryption operand.

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