Evaluation method and evaluation system for interconnection topology on UBB

Abstract

The present invention provides an evaluation method and evaluation system for interconnection topology on a UBB. The UBB includes N OAM installation areas for installing OAM modules, each of the OAM installation areas corresponds to a group of connectors, each group of the connectors includes N-1 SerDes, N≥2, and the evaluation method includes: installing at least two test boards on at least two OAM installation areas to be evaluated, so that the differential port pairs in each SerDes are electrically connected to the differential interface pairs on the test board; wherein the test board matches the OAM installation areas one by one, and each of the test boards includes N-1 differential interface pairs; the differential interface pairs on one of the two test boards are connected to the differential interface pairs on the other to a vector network analyzer, and the link status between the two OAM installation areas to be evaluated is evaluated according to the S parameters tested by the vector network analyzer. The present invention can quickly and efficiently evaluate the interconnection topology on the UBB.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of interconnection topology evaluation, and in particular to an evaluation method and evaluation system for interconnection topology on a UBB. Background Art

[0002] OAM (OCP Accelerator Module) is a hardware acceleration module based on the OCP standard. Compared with the traditional PCIe form factor, the high-speed communication link interconnection between modules has stronger scalability and more complex interconnection topology. An OAM server usually inserts 8 OAM accelerator cards. The interconnection between OAM accelerator cards mainly includes intra-board interconnection through UBB (Universal Baseboard) and inter-board interconnection through QSFP-DD interface Scale-Out. How to quickly and efficiently evaluate the interconnection topology on UBB has become an important issue.

[0003] There are two existing methods for evaluating the interconnection topology between OAM accelerator cards. One is to use the tester provided by the connector manufacturer to test the performance of the connector, but it is impossible to evaluate the interconnection topology of the entire UBB. The other is to use active testing after the OAM accelerator card is installed. However, the OAM needs to be installed before testing, which has low test efficiency. Summary of the invention

[0004] The present invention provides an evaluation method and an evaluation system for interconnection topology on a UBB, so as to quickly and efficiently evaluate the interconnection topology on the UBB.

[0005] In a first aspect, an embodiment of the present invention provides an evaluation method for interconnection topology on a UBB, wherein the UBB includes N OAM installation areas for installing OAM modules, each of the OAM installation areas corresponds to a group of connectors, each group of the connectors includes N-1 SerDes, N≥2, and the evaluation method includes:

[0006] Install at least two test boards respectively in at least two OAM installation areas to be evaluated, so that the differential port pairs in each SerDes are electrically connected to the differential interface pairs on the test board; wherein the test boards are matched one-to-one with the OAM installation areas, and each of the test boards includes N-1 differential interface pairs;

[0007] The differential interface pair on one of the two test boards and the differential interface pair on the other test board are connected to a vector network analyzer correspondingly, and the link status between the two OAM installation areas to be evaluated is evaluated according to the S parameters tested by the vector network analyzer.

[0008] Optionally, evaluating the link status between the two OAM installation areas to be evaluated according to the S parameters tested by the vector network analyzer includes:

[0009] If the S11 low-frequency end of the S parameter tested by the vector network analyzer is zero and the S12 curve disappears, it is determined that there is no link between the two differential interface pairs currently connected to the vector network analyzer;

[0010] If the S11 low-frequency end of the S parameter tested by the vector network analyzer is not zero and the S12 curve exists, it is determined that there is a link between the two differential interface pairs currently connected to the vector network analyzer.

[0011] Optionally, after determining that there is a link between two differential interface pairs currently connected to the vector network analyzer, the method further includes:

[0012] Evaluate whether the insertion loss of the link meets the preset requirements.

[0013] Optionally, before evaluating whether the insertion loss of the link meets a preset requirement, the method further includes:

[0014] The insertion loss obtained by the vector network analyzer test is de-embedded with the loss of the test board to obtain the insertion loss of the link.

[0015] Optionally, the step of installing at least two test boards respectively in at least two OAM installation areas to be evaluated comprises:

[0016] Install N test boards in N OAM installation areas respectively.

[0017] Optionally, the SerDes includes a plurality of pairs of differential port pairs with data bits from low to high;

[0018] Installing at least two test boards respectively in at least two OAM installation areas to be evaluated so that the differential port pairs in each SerDes are electrically connected to the differential interface pairs on the test board accordingly comprises:

[0019] At least two test boards are respectively installed in at least two OAM installation areas to be evaluated, so that a pair of differential port pairs in the lower position of each SerDes is electrically connected to a pair of differential interface pairs on the test board.

[0020] Optionally, the evaluation method further includes:

[0021] The link status between any two OAM installation areas is evaluated to determine the interconnection topology on the UBB.

[0022] In a second aspect, an embodiment of the present invention further provides an evaluation system for interconnection topology on a UBB, the evaluation system being used to execute the evaluation method described in the first aspect, the evaluation system comprising:

[0023] At least two test boards, the at least two test boards are matched one by one with at least two OAM installation areas to be evaluated on the UBB, each of the test boards includes N-1 differential interface pairs, and a pair of differential port pairs in each SerDes can be electrically connected to a pair of differential interface pairs;

[0024] A vector network analyzer is used to obtain S parameters after the differential interface pairs on one of the two test boards are connected to the vector network analyzer correspondingly with the differential interface pairs on the other of the two test boards;

[0025] An evaluation device is used to evaluate the link status between the two OAM installation areas to be evaluated according to the S parameters tested by the vector network analyzer.

[0026] Optionally, the evaluation system includes N test boards, and the N test boards are matched one-to-one with the N OAM installation areas on the UBB.

[0027] Optionally, the SerDes includes a plurality of pairs of differential port pairs with data bits from low to high;

[0028] The differential interface pair on the test board is used to be electrically connected to the low-order differential port pair in the SerDes.

[0029] The technical solution of the embodiment of the present invention adopts a method for evaluating the interconnection topology on a UBB, including: installing at least two test boards respectively on at least two OAM installation areas to be evaluated, so that the differential port pairs in each SerDes are electrically connected to the differential interface pairs on the test board; wherein the test board matches the OAM installation area one by one, and each test board includes N-1 differential interface pairs; the differential interface pairs on one of the two test boards are connected to the differential interface pairs on the other test board to a vector network analyzer, and the link status between the two OAM installation areas to be evaluated is evaluated according to the S parameters tested by the vector network analyzer. This solution can evaluate the link status on the UBB without installing the OAM module on the UBB, and can simply and conveniently evaluate the link status between any two OAM installation areas on the UBB. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A flowchart of a method for evaluating interconnection topology on a UBB provided by an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of the structure of a UBB after installing an OAM module provided by an embodiment of the present invention;

[0032] Figure 3 A schematic diagram of the structure of a connector provided by an embodiment of the present invention;

[0033] Figure 4 A schematic diagram of the structure after a test board is installed on a UBB provided by an embodiment of the present invention;

[0034] Figure 5 A schematic diagram of the structure of an evaluation system for interconnection topology on a UBB provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0036] Figure 1 A flowchart of a method for evaluating interconnection topology on a UBB provided by an embodiment of the present invention, referring to Figure 1 ,The evaluation methods of interconnection topology on UBB include:

[0037] Step S101, respectively installing at least two test boards in at least two OAM installation areas to be evaluated, so that the differential port pairs in each SerDes are electrically connected to the differential interface pairs on the test board; wherein the test boards are matched one by one with the OAM installation areas, and each test board includes N differential interface pairs;

[0038] Specifically, Figure 2 A schematic diagram of the structure of a UBB after installing an OAM module according to an embodiment of the present invention is provided. Figure 3 A schematic diagram of a connector structure provided by an embodiment of the present invention, combined with Figures 1 to 3, the UBB includes N OAM installation areas 111 for installing OAM modules 1111, each OAM installation area 111 corresponds to a group of connectors 1112, the connectors may be, for example, Mezzanine connectors, each group of connectors 1112 includes N-1 SerDes, N ≥ 2; in this embodiment, the UBB may include, for example, 8 OAM installation areas 111, which may be respectively installed with 8 OAM modules from OAM module 0 to OAM module 7, it should be noted that when the OAM module is installed in the OAM installation area, the connector 1112 is covered by the OAM module 1111; each OAM installation area on the UBB is used to install an OAM module, and there is no overlapping part between different OAM installation areas, for example, each OAM installation area and the corresponding OAM module may occupy the same area of ​​the UBB; each OAM installation area 111 also includes a group of connectors 1112, each group of connectors 1112 may include, for example, two connectors, such as Figure 3 As shown, each group of connectors 1112 includes N-1 SerDes, which may be, for example, x16 SerDes, and each group of connectors may also include a x16 Host Power; after the UBB is manufactured, there is an interconnection topology between the connectors 1112 of each OAM installation area 111, for example Figure 2 As shown in , there are link paths between OAM0 and OAM7, OAM3, OAM6, and OAM2, and each link path is connected to the SerDes corresponding to the connector in each OAM installation area, and different link paths are connected to different SerDes. For example, there is a link path between the SerDes1 corresponding to OAM0 and the SerDes1 corresponding to OAM7, and there is a link path between the SerDes2 corresponding to OAM0 and the SerDes1 corresponding to OAM3; of course, the user may not be sure between which OAM installation areas on the UBB have links, that is, the interconnection topology on the UBB is not sure. In order to determine the interconnection topology on the UBB, for example, in order to determine whether there is a link path between the OAM installation area corresponding to OAM0 and the OAM installation area corresponding to OAM7, after the UBB is manufactured, it is not necessary to install the OAM module 1111 in the corresponding OAM installation area 111; as shown in Figure 4 As shown, Figure 4A schematic diagram of a structure after a test board is installed on a UBB provided in an embodiment of the present invention. After the UBB 11 is manufactured, the test board 201 is first installed in the OAM installation area to be evaluated, that is, two test boards 201 are respectively installed in the OAM installation area corresponding to OAM0 and the OAM installation area corresponding to OAM7, wherein the test board 201 matches the OAM installation area one by one, which means that the area of ​​the UBB occupied by the test board 201 is less than or equal to the area of ​​the corresponding OAM installation area. Preferably, the area of ​​the UBB occupied by the test board 201 and the corresponding OAM module can be set to be exactly the same, for example, the test board 201 can be a test board that only lacks a chip relative to the corresponding OAM module, thereby maximizing the accuracy of the test; for ease of description, the test board 201 installed in the OAM installation area corresponding to OAM0 is set as the first test board 2011, and the test board 201 installed in the OAM installation area corresponding to OAM7 is set as the second test board 2012. The test board 201 includes N-1 differential interface pairs, and the number of differential interface pairs can be set equal to the number of SerDes in the connector group. After the test board 201 is installed in the corresponding OAM installation area 111, the N-1 differential interface pairs on the test board 201 are respectively connected to the differential port pairs of the N-1 SerDes in the connector group. Therefore, the OAM installation area corresponding to OAM0 and the OAM installation area corresponding to OAM7 can determine whether there is a link through the two test boards 201.

[0039] Step S102 : Connect the differential interface pair on one of the two test boards and the differential interface pair on the other test board to a vector network analyzer accordingly, and evaluate the link status between the two OAM installation areas to be evaluated according to the S parameters tested by the vector network analyzer.

[0040] Specifically, Figure 5 A schematic diagram of a UBB interconnection topology evaluation system provided by an embodiment of the present invention, referring to Figure 5Since each test board has N-1 pairs of differential interface pairs 202, if it is necessary to determine whether there is a link between two OAM installation areas, a differential interface pair on one of the test boards and N-1 differential interface pairs on the other test board can be connected to the vector network analyzer 202 in sequence. For example, the differential interface pair 202 corresponding to SerDes1 in the first test board 2011 is connected to the vector network analyzer, and then the differential interface pairs corresponding to SerDes1 to SerDes7 in the second test board 2012 are respectively connected to the vector network analyzer 203. According to the S parameters tested by the vector network analyzer 203, it is evaluated whether there is a link between the two pairs of SerDes connected to the vector network analyzer at this time, that is, whether there is a link between the OAM installation areas to be evaluated; If there is no link between the SerDes1 corresponding to the first test board 2011 and the N-1 SerDes corresponding to the second test board 2012, the differential interface pair 202 corresponding to SerDes2 of the first test board 2011 can be connected to the vector network analyzer 203, and the differential interface pairs corresponding to SerDes1 to SerDes7 in the second test board 2012 can be connected to the vector network analyzer 203 respectively, and the S parameters tested by the vector network analyzer 203 are used to evaluate whether there is a link between the two pairs of SerDes connected to the vector network analyzer at this time; thereby, it is easy and convenient to determine whether there is a link between any two OAM installation areas on the UBB, and it can be further determined between which SerDes in the connector group the link exists.

[0041] The technical solution of this embodiment adopts a method for evaluating the interconnection topology on the UBB, including: installing at least two test boards respectively on at least two OAM installation areas to be evaluated, so that the differential port pairs in each SerDes are electrically connected to the differential interface pairs on the test board; wherein the test board matches the OAM installation area one by one, and each test board includes N-1 differential interface pairs; the differential interface pairs on one of the two test boards are connected to the vector network analyzer correspondingly with the differential interface pairs on the other test board, and the link status between the two OAM installation areas to be evaluated is evaluated according to the S parameters tested by the vector network analyzer. This solution does not require the OAM module to be installed on the UBB to evaluate the link status on the UBB, and can simply and conveniently evaluate the link status between any two OAM installation areas on the UBB; thereby being able to quickly check and evaluate the interconnection topology of the high-speed link. In addition, the OAM and UBB PCB designs, as well as the Mezzanine connector design, can be decoupled, so as to quickly evaluate the possible problems of each, and thus can be improved in a timely manner.

[0042] It should be noted that the differential interface pair 202 on the test board 201 can be an SMA interface, and the size of the SMA interface can be configured to be exactly the same as the size of the SMA interface in the corresponding OAM module, ensuring that the S parameters tested by the vector network analyzer are closer to the actual S parameters after the OAM module is installed on the UBB.

[0043] Optionally, evaluating the link status between two OAM installation areas to be evaluated according to S parameters tested by a vector network analyzer includes:

[0044] If the S11 low-frequency end of the S parameters tested by the vector network analyzer is zero and the S12 curve disappears, it is determined that there is no link between the two differential interface pairs currently connected to the vector network analyzer; if the S11 low-frequency end of the S parameters tested by the vector network analyzer is not zero and the S12 curve exists, it is determined that there is a link between the two differential interface pairs currently connected to the vector network analyzer.

[0045] Specifically, in this embodiment, it is possible to determine whether there is a link between two differential interface pairs connected to the vector network analyzer based on the S11 curve and the S12 curve. If the low-frequency end of the S11 curve is zero and the S12 curve disappears, it means that the SerDes corresponding to the second test board cannot receive the signal sent by the SerDes corresponding to the first test board, that is, there is no link between the two SerDes; and if the S11 low-frequency end in the S parameter tested by the vector network analyzer is not zero, and the S12 curve exists, it means that the SerDes corresponding to the second test board can receive the signal sent by the SerDes corresponding to the first test board, that is, there is a link between the two SerDes.

[0046] Optionally, after determining that there is a link between the two differential interface pairs currently accessing the vector network analysis, the method further includes: evaluating whether an insertion loss of the link meets a preset requirement.

[0047] Specifically, the preset requirement is, for example, that the error of the insertion loss is within 10% compared to the set value. It can be determined whether the insertion loss meets the preset requirement based on the S parameter tested by the vector network analyzer. If not, it indicates that the link may be abnormal and cannot be used normally; and if the insertion loss meets the preset requirement, it indicates that the link is not abnormal and can be used normally. It should be noted that the preset requirement can be set according to the specific scenario in which the UBB needs to be applied, and the embodiment of the present invention does not specifically limit this. Exemplarily, the method of this embodiment can be used by UBB manufacturers. For UBB manufacturers, it can be determined whether the UBB meets the requirements of Spec based on the measured insertion loss of each link; it can also be used by OAM manufacturers. For OAM manufacturers, for different models of UBB, the passive performance such as impedance, return loss and insertion loss of each SerDes full link can be measured to quickly evaluate whether it meets the capabilities of their own chips.

[0048] Optionally, before evaluating whether the insertion loss of the link meets the preset requirement, the method further includes:

[0049] The insertion loss obtained by the vector network analyzer test is de-embedded from the loss of the test board to obtain the insertion loss of the link.

[0050] Specifically, the loss of the test board can be tested in advance. The insertion loss obtained by the vector network analyzer test includes not only the insertion loss of the UBB link, but also the insertion loss of the two test boards. If de-embedding is not performed, the insertion loss error obtained will be large, thereby affecting the judgment of whether the insertion loss meets the preset requirements. In this embodiment, the insertion loss obtained by the vector network analyzer test is de-embedded and then it is judged whether it meets the preset requirements, which can greatly improve the accuracy of the judgment and prevent misjudgment.

[0051] Optionally, installing at least two test boards respectively in at least two OAM installation areas to be evaluated includes: installing N test boards respectively in the N OAM installation areas.

[0052] Specifically, since it is necessary to evaluate the complete interconnection topology on the UBB, that is, to determine the link status between all OAM installation areas on the UBB, if only two test boards are set, after the evaluation of the two OAM installation areas to be evaluated is completed, the test boards need to be disassembled and then installed in other OAM installation areas to be evaluated. Repeated disassembly of the test boards is not only cumbersome, but may also cause damage to the test boards. In this embodiment, N test boards can be configured. When evaluating the complete interconnection topology on the UBB, each test board only needs to be disassembled once, which greatly reduces the risk of damage to the test boards.

[0053] Optionally, the SerDes includes a plurality of pairs of differential port pairs with data bits from low to high; and at least two test boards are respectively installed in at least two OAM installation areas to be evaluated so that the differential port pairs in each SerDes are electrically connected to the differential interface pairs on the test board correspondingly, including:

[0054] At least two test boards are respectively installed in at least two OAM installation areas to be evaluated, so that a pair of differential port pairs in the lower position of each SerDes is electrically connected to a pair of differential interface pairs on the test board.

[0055] Specifically, the x16 model SerDes includes 16 pairs of differential port pairs. If all the differential port pairs in each SerDes have corresponding differential interface pairs in the test board, since the differential interface pairs are SMA interfaces with large size, it is difficult to layout the differential interface pairs on the test board. In this embodiment, the test board can be set to include only the differential interface pairs corresponding to the lowest-order differential port pairs in each SerDes, reducing the number of differential interface pairs on the test board, which is more conducive to the design of the test board. It should be noted that in some other implementations, the differential interface pairs on the test board can also be differential port pairs corresponding to other positions in the SerDes.

[0056] Optionally, the method for evaluating the interconnection topology on the UBB further includes: evaluating the link status between any two OAM installation areas to determine the interconnection topology on the UBB.

[0057] Specifically, when the link status between any two OAM installation areas is determined, the complete interconnection topology diagram on the UBB can be obtained, such as Figure 3 or Figure 5As shown, in this embodiment, the interconnection topology relationship on the UBB is that there are links between the OAM corresponding to OAM0 installed in the OAM installation area corresponding to OAM3, the OAM installation area corresponding to OAM7, the OAM installation area corresponding to OAM2, and the OAM installation area corresponding to OAM6; there are links between the OAM installation area corresponding to OAM3 and the OAM installation area corresponding to OAM0, the OAM installation area corresponding to OAM4, and the OAM installation area corresponding to OAM2; there are links between the OAM installation area corresponding to OAM4 and the OAM installation area corresponding to OAM3, the OAM installation area corresponding to OAM5, and the OAM installation area corresponding to OAM7; the OAM installation area corresponding to OAM7 is respectively connected to the OAM installation area corresponding to OAM0, the OAM installation area corresponding to OAM4, the OAM installation area corresponding to OAM1, and the OAM installation area corresponding to OAM5. There are links between the AM installation areas; there are links between the OAM installation area corresponding to OAM1 and the OAM installation area corresponding to OAM7, the OAM installation area corresponding to OAM2, and the OAM installation area corresponding to OAM6; there are links between the OAM installation area corresponding to OAM2 and the OAM installation area corresponding to OAM3, the OAM installation area corresponding to OAM0, the OAM installation area corresponding to OAM1, and the OAM installation area corresponding to OAM5; there are links between the OAM installation area corresponding to OAM5 and the OAM installation area corresponding to OAM7, the OAM installation area corresponding to OAM4, the OAM installation area corresponding to OAM2, and the OAM installation area corresponding to OAM6; there are links between the OAM installation area corresponding to OAM6 and the OAM installation area corresponding to OAM0, the OAM installation area corresponding to OAM5, and the OAM installation area corresponding to OAM1. It should be noted that the interconnection topology on the UBB can also be other topological forms, which are not specifically limited in the embodiments of the present invention.

[0058] The embodiment of the present invention further provides an evaluation system for interconnection topology on a UBB, wherein the evaluation system is used to execute the evaluation method provided by any embodiment of the present invention, such as Figure 4 and Figure 5 As shown, the evaluation system comprises:

[0059] At least two test boards 201, at least two test boards 201 are matched one by one with at least two OAM installation areas to be evaluated on the UBB, each test board includes N-1 differential interface pairs, and a pair of differential port pairs in each SerDes can be electrically connected to a pair of differential interface pairs; a vector network analyzer 203 is used to obtain S parameters after the differential interface pairs on one of the two test boards are connected to the differential interface pairs on the other test board; an evaluation device (not shown) is used to evaluate the link status between the two OAM installation areas to be evaluated according to the S parameters tested by the vector network analyzer.

[0060] Specifically, the test board 201 matches the OAM installation area one by one, which means that the area of ​​the UBB occupied by the test board 201 is less than or equal to the area of ​​the corresponding OAM installation area. Preferably, the test board 201 can be set to have exactly the same area as the UBB occupied by the corresponding OAM module. For example, the test board 201 can be a test board that only lacks a chip relative to the corresponding OAM module, thereby maximizing the accuracy of the test; the test board 201 includes N-1 differential interface pairs, and the number of differential interface pairs can be set equal to the number of SerDes in the connector group. After the test board 201 is installed in the corresponding OAM installation area 111, the N-1 differential interface pairs on the test board 201 are respectively connected to the differential port pairs of the N-1 SerDes in the connector group. Therefore, the OAM installation area corresponding to OAM0 and the OAM installation area corresponding to OAM7 can determine whether there is a link through the two test boards 201. The evaluation device may be, for example, a processor, which may automatically determine whether a link exists between two OAM installation areas to be evaluated based on the S parameters tested by the vector network analyzer. The evaluation method is described above and will not be repeated here.

[0061] The interconnection topology evaluation system on the UBB adopted in this embodiment can evaluate the link status on the UBB without installing an OAM module on the UBB, and can simply and conveniently evaluate the link status between any two OAM installation areas on the UBB.

[0062] Optionally, the evaluation system includes N test boards, and the N test boards are matched one-to-one with the N OAM installation areas on the UBB.

[0063] Specifically, since it is necessary to evaluate the complete interconnection topology on the UBB, that is, to determine the link status between all OAM installation areas on the UBB, if only two test boards are set, after the evaluation of the two OAM installation areas to be evaluated is completed, the test boards need to be disassembled and then installed in other OAM installation areas to be evaluated. Repeated disassembly of the test boards is not only cumbersome, but may also cause damage to the test boards. In this embodiment, N test boards can be configured. When evaluating the complete interconnection topology on the UBB, each test board only needs to be disassembled once, which greatly reduces the risk of damage to the test boards.

[0064] Optionally, the SerDes includes a plurality of differential port pairs with data bits from low to high; the differential interface pairs on the test board are used to be electrically connected to the differential port pairs at low positions in the SerDes.

[0065] Specifically, the x16 model SerDes includes 16 pairs of differential port pairs. If all the differential port pairs in each SerDes have corresponding differential interface pairs in the test board, since the differential interface pairs are SMA interfaces with large size, it is difficult to layout the differential interface pairs on the test board. In this embodiment, the test board can be set to include only the differential interface pairs corresponding to the lowest-order differential port pairs in each SerDes, reducing the number of differential interface pairs on the test board, which is more conducive to the design of the test board. It should be noted that in some other implementations, the differential interface pairs on the test board can also be differential port pairs corresponding to other positions in the SerDes.

[0066] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for evaluating interconnection topology on a UBB, wherein the UBB includes N OAM installation areas for installing OAM modules, each of the OAM installation areas corresponds to a group of connectors, and each group of the connectors includes N-1 SerDes, N≥2, characterized in that: The evaluation methods include: Install at least two test boards respectively in at least two OAM installation areas to be evaluated, so that the differential port pairs in each SerDes are electrically connected to the differential interface pairs on the test board; wherein the test boards are matched one-to-one with the OAM installation areas, and each of the test boards includes N-1 differential interface pairs; Connecting the differential interface pair on one of the two test boards and the differential interface pair on the other test board to a vector network analyzer, and evaluating the link status between the two OAM installation areas to be evaluated according to the S parameters tested by the vector network analyzer; The evaluating the link status between the two OAM installation areas to be evaluated according to the S parameters tested by the vector network analyzer comprises: If the S11 low-frequency end of the S parameter tested by the vector network analyzer is zero and the S12 curve disappears, it is determined that there is no link between the two differential interface pairs currently connected to the vector network analyzer; If the S11 low-frequency end of the S parameter tested by the vector network analyzer is not zero and the S12 curve exists, it is determined that there is a link between the two differential interface pairs currently connected to the vector network analyzer.

2. The method for evaluating interconnection topology on UBB according to claim 1, characterized in that: After determining that there is a link between the two differential interface pairs currently connected to the vector network analyzer, the method further includes: Evaluate whether the insertion loss of the link meets the preset requirements.

3. The method for evaluating interconnection topology on UBB according to claim 2, characterized in that: Before evaluating whether the insertion loss of the link meets the preset requirements, it also includes: The insertion loss obtained by the vector network analyzer test is de-embedded with the loss of the test board to obtain the insertion loss of the link.

4. The method for evaluating interconnection topology on UBB according to claim 1, characterized in that: The step of installing at least two test boards respectively in at least two OAM installation areas to be evaluated comprises: Install N test boards in N OAM installation areas respectively.

5. The method for evaluating interconnection topology on UBB according to claim 1, characterized in that: The SerDes includes multiple pairs of differential port pairs with data bits from low to high; Installing at least two test boards respectively in at least two OAM installation areas to be evaluated so that the differential port pairs in each SerDes are electrically connected to the differential interface pairs on the test board accordingly comprises: At least two test boards are respectively installed in at least two OAM installation areas to be evaluated, so that a pair of differential port pairs in the lower position of each SerDes is electrically connected to a pair of differential interface pairs on the test board.

6. The method for evaluating interconnection topology on UBB according to claim 1, characterized in that: The evaluation method also includes: The link status between any two OAM installation areas is evaluated to determine the interconnection topology on the UBB.

7. A system for evaluating interconnection topology on a UBB, characterized in that: The evaluation system is used to execute the evaluation method according to any one of claims 1 to 6, and the evaluation system comprises: At least two test boards, the at least two test boards are matched one by one with at least two OAM installation areas to be evaluated on the UBB, each of the test boards includes N-1 differential interface pairs, and a pair of differential port pairs in each SerDes can be electrically connected to a pair of differential interface pairs; A vector network analyzer is used to obtain S parameters after the differential interface pairs on one of the two test boards are connected to the vector network analyzer correspondingly with the differential interface pairs on the other of the two test boards; An evaluation device for evaluating the link status between the two OAM installation areas to be evaluated according to the S parameters tested by the vector network analyzer; The evaluating the link status between the two OAM installation areas to be evaluated according to the S parameters tested by the vector network analyzer comprises: If the S11 low-frequency end of the S parameter tested by the vector network analyzer is zero and the S12 curve disappears, it is determined that there is no link between the two differential interface pairs currently connected to the vector network analyzer; If the S11 low-frequency end of the S parameter tested by the vector network analyzer is not zero and the S12 curve exists, it is determined that there is a link between the two differential interface pairs currently connected to the vector network analyzer.

8. The evaluation system for interconnection topology on UBB according to claim 7, characterized in that: The evaluation system includes N test boards, and the N test boards are matched one by one with the N OAM installation areas on the UBB.

9. The evaluation system for interconnection topology on UBB according to claim 7, characterized in that: The SerDes includes multiple pairs of differential port pairs with data bits from low to high; The differential interface pair on the test board is used to be electrically connected to the low-order differential port pair in the SerDes.

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