Image sensing device

By designing a pixel group containing semi-blocking pixels and normal pixels in an image sensing device, and using an image processor to process signals in different time periods, it is solved that it is difficult to simultaneously support phase detection autofocus and high dynamic range functions in the prior art. The problem of achieving higher functional integrity and image quality.

CN114449189BActive Publication Date: 2025-02-21SK HYNIX INC
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Patent Information

Application Number
CN202110660808.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2020-11-04
Filing Date
2021-06-15
Publication Date
2025-02-21
Estimated Expiration
2041-06-15

Smart Images

  • Figure CN114449189B_ABST
    Figure CN114449189B_ABST
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Abstract

An image sensing device is disclosed, which includes: a first pixel group, the first pixel group including at least one first semi-shielded pixel and at least one first normal pixel; and an image processor, the image processor being adapted to use a first pixel signal generated from the first semi-shielded pixel during a first time period as phase information, and to use a first pixel signal generated from the first semi-shielded pixel during a second time period as dynamic range information.
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Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a semiconductor design technology, and more particularly, to an image sensing device. Background Art

[0002] Image sensing devices use the properties of semiconductors that react to light to capture images. Generally, image sensing devices can be roughly divided into charge coupled device (CCD) image sensing devices and complementary metal oxide semiconductor (CMOS) image sensing devices. Recently, CMOS image sensing devices are widely used because they allow both analog control circuits and digital control circuits to be directly implemented on a single integrated circuit (IC). Summary of the invention

[0003] Various embodiments of the present disclosure are directed to an image sensing device supporting a phase detection auto focus function and a high dynamic range function.

[0004] According to an embodiment, the image sensing device may include: a first pixel group, the first pixel group including at least one first semi-shielded pixel and at least one first normal pixel; and an image processor, the image processor being adapted to use a first pixel signal generated from the first semi-shielded pixel during a first time period as phase information, and to use a first pixel signal generated from the first semi-shielded pixel during a second time period as dynamic range information.

[0005] The image processor can calculate the depth to the object based on the phase information of the first pixel signal generated during the first period, generate a high-brightness image based on the dynamic range information of the first pixel signal generated during the second period, and generate a low-brightness image based on the pixel signal generated from the first normal pixel during the second period.

[0006] The image sensing device may further include a second pixel group including at least one second semi-shielded pixel and at least one second normal pixel, wherein the image processor may use a second pixel signal generated from the second semi-shielded pixel during the second period as dynamic range information.

[0007] The first semi-shielded pixel may have a green color filter, and the second semi-shielded pixel may have a red color filter or a blue color filter.

[0008] According to an embodiment, the image sensing device may include: a first pixel group, the first pixel group including a first semi-shielded pixel and three first normal pixels; and an image processor, the image processor being adapted to use a first pixel signal generated from the first semi-shielded pixel during a first time period as phase information, and to use a first pixel signal generated from the first semi-shielded pixel during a second time period as dynamic range information.

[0009] The image processor can calculate the depth to the object based on the phase information of the first pixel signal generated during the first period, generate a high-brightness image based on the dynamic range information of the first pixel signal generated during the second period, and generate a low-brightness image based on the pixel signal generated from the first normal pixel during the second period.

[0010] The image sensing device may further include a second pixel group including one second semi-shielded pixel and three second normal pixels, wherein the image processor may use a second pixel signal generated from the second semi-shielded pixel during the second period as dynamic range information.

[0011] The first semi-shielded pixel may have a green color filter, and the second semi-shielded pixel may have a red color filter or a blue color filter.

[0012] The first period may include a time section in which the image sensing device performs a phase detection auto focus function, and the second period may include a time section in which the image sensing device captures an image.

[0013] According to an embodiment, the image sensing device may include: a first pixel group, the first pixel group including two first semi-shielded pixels and two first normal pixels; and an image processor, the image processor being adapted to use phase information of a first pixel signal generated from the first semi-shielded pixels during a first time period, and dynamic range information of the first pixel signal generated from the first semi-shielded pixels during a second time period.

[0014] The image processor can calculate the depth to the object based on the phase information of the first pixel signal generated during the first period, generate a high-brightness image based on the dynamic range information of the first pixel signal generated during the second period, and generate a low-brightness image based on the pixel signal generated from the first normal pixel during the second period.

[0015] The image sensing device may further include a second pixel group including two second semi-shielded pixels and two second normal pixels, wherein the image processor may use a second pixel signal generated from the second semi-shielded pixels during the second period as the dynamic range information.

[0016] Each of the first semi-light-shielded pixels may have a green color filter, and each of the second semi-light-shielded pixels may have a red color filter or a blue color filter.

[0017] The first period may include a time section in which the image sensing device performs a phase detection auto focus function, and the second period may include a time section in which the image sensing device captures an image.

[0018] According to an embodiment, there is provided an operating method for an image sensing device including one or more semi-shielded pixels and one or more normal pixels, the operating method may include the following steps: generating a semi-shielded pixel signal with an integration time through each semi-shielded pixel, and generating a normal pixel signal with an integration time through each normal pixel; generating a high-brightness image based on the semi-shielded pixel signal, and generating a low-brightness image based on the normal pixel signal; and generating a high dynamic range image based on the high-brightness image and the low-brightness image. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a block diagram illustrating an image sensing device according to a first embodiment of the present disclosure.

[0020] Figure 2 is an example Figure 1 A diagram of an example of a pixel array is shown.

[0021] Figure 3 is an example Figure 2 A circuit diagram of an example of a unit pixel circuit is shown.

[0022] Figure 4 is an example Figure 2 A circuit diagram of another example of a unit pixel circuit is shown.

[0023] Figure 5 is a block diagram illustrating an image sensing device according to a second embodiment of the present disclosure.

[0024] Figure 6 is an example Figure 5 A diagram of an example of a pixel array is shown.

[0025] Figure 7 is an example Figure 6 A circuit diagram of an example of a unit pixel circuit is shown.

[0026] Figure 8 is an example Figure 6 A circuit diagram of another example of a unit pixel circuit is shown. DETAILED DESCRIPTION

[0027] Various embodiments are described below with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily practice the present invention.

[0028] It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected or coupled to the other element, or electrically connected or coupled to the other element in a state where one or more elements are interposed. In addition, it will be understood that the terms "comprises," "comprising," "having," and "containing" when used herein specify the presence of the elements described and do not exclude the presence or addition of one or more other elements. In the following description, components described in the singular do not exclude the presence of multiple instances of such components. Throughout the specification, references to "an embodiment," "a first embodiment," or "a second embodiment" do not necessarily refer only to one embodiment, and the term "embodiment" when used herein does not necessarily refer to all embodiments.

[0029] Figure 1 is a block diagram illustrating an image sensing device 100 according to a first embodiment of the present disclosure.

[0030] Reference Figure 1 , the image sensing device 100 may include a row controller 110 , a pixel array 120 , a signal converter 130 , and an image processor 140 .

[0031] The row controller 110 may generate a plurality of row control signals CTRL for controlling respective rows of the pixel array 120. For example, the row controller 110 may generate a first row control signal for controlling pixels arranged in a first row of the pixel array 120 during a first unit row time, and generate an nth row control signal for controlling pixels arranged in an nth row of the pixel array 120 during an nth unit row time (where “n” is a natural number greater than 2).

[0032] The pixel array 120 may include pixels arranged at the intersection of a plurality of rows and a plurality of columns. Figure 2 The pixels may output a plurality of pixel signals VPX for each row to the signal converter 130 under the control of the row controller 110. For example, the pixels arranged in the first row may generate the pixel signal VPX during the first unit row time based on the first row control signal, and the pixels arranged in the nth row may generate the pixel signal VPX during the nth unit row time based on the nth row control signal.

[0033] The signal converter 130 may generate an image signal DPX corresponding to the pixel signal VPX. For example, the signal converter 130 may include an analog-to-digital converter (ADC).

[0034] Based on the image signal DPX, the image processor 140 may process phase information related to a phase detection auto focus function during a first period, and process an image related to a high dynamic range function during a second period.

[0035] Figure 2 is an example Figure 1 A diagram of an example of a pixel array 120 is shown.

[0036] Reference Figure 2 , the pixel array 120 may include a plurality of pixels arranged in a quad pattern. The quad pattern refers to a pattern in which pixels each having a color filter of the same color are arranged in units of 2×2. Hereinafter, a group of pixels arranged in units of 2×2 is referred to as a unit pixel circuit.

[0037] The unit pixel circuit may include first to fourth pixels, one of which may be a semi-shielding pixel having a semi-shielding layer; the other three pixels may be normal pixels. The semi-shielding layer may have any one of a left shielding pattern S1, a right shielding pattern S2, an upper shielding pattern S3, and a lower shielding pattern S4. The left shielding pattern S1, the right shielding pattern S2, the upper shielding pattern S3, and the lower shielding pattern S4 do not necessarily have to be formed as shown in FIG. Figure 2 As shown, and can be variously changed according to the design.

[0038] Figure 3 is an example Figure 2 A circuit diagram of an example of any one unit pixel circuit shown.

[0039] Reference Figure 3 The unit pixel circuit may include first to fourth photodiodes PD1, PD2, PD3 and PD4, first to fourth transfer elements MT1, MT2, MT3 and MT4, a first floating diffusion node FD1, a first reset element MR1, a first driving element MD1 and a first selection element MS1.

[0040] The unit pixel circuit may have a structure in which the first to fourth photodiodes PD1 , PD2 , PD3 , and PD4 share a first floating diffusion node FD1 , a first reset element MR1 , a first driving element MD1 , and a first selection element MS1 .

[0041] The first photodiode PD1 may be coupled between a low voltage terminal (e.g., a ground voltage terminal) and the first transmission element MT1. The second photodiode PD2 may be coupled between the low voltage terminal and the second transmission element MT2. The third photodiode PD3 may be coupled between the low voltage terminal and the third transmission element MT3. The fourth photodiode PD4 may be coupled between the low voltage terminal and the fourth transmission element MT4. The first photodiode PD1 may be associated with a semi-shielded pixel, and the second to fourth photodiodes PD2, PD3, and PD4 may be associated with a normal pixel.

[0042] The first transmission element MT1 may be connected between the first photodiode PD1 and the first floating diffusion node FD1. The first transmission element MT1 may selectively connect the first photodiode PD1 to the first floating diffusion node FD1 based on the first transmission control signal TX1. The second transmission element MT2 may be connected between the second photodiode PD2 and the first floating diffusion node FD1. The second transmission element MT2 may selectively connect the second photodiode PD2 to the first floating diffusion node FD1 based on the second transmission control signal TX2. The third transmission element MT3 may be connected between the third photodiode PD3 and the first floating diffusion node FD1. The third transmission element MT3 may selectively connect the third photodiode PD3 to the first floating diffusion node FD1 based on the third transmission control signal TX3. The fourth transmission element MT4 may be connected between the fourth photodiode PD4 and the first floating diffusion node FD1. The fourth transmission element MT4 may selectively connect the fourth photodiode PD4 to the first floating diffusion node FD1 based on the fourth transmission control signal TX4. For example, during the first period, only the first transmission control signal TX1 among the first to fourth transmission control signals TX1, TX2, TX3 and TX4 may be activated, and during the second period, the first transmission control signal TX1 may be activated, and the second to fourth transmission control signals TX2, TX3 and TX4 may be activated at the same time.

[0043] Although not illustrated in the drawings, a first parasitic capacitor may be coupled to the first floating diffusion node FD1. The first parasitic capacitor may store charges generated from the first to fourth photodiodes PD1, PD2, PD3, and PD4.

[0044] The first reset element MR1 may be coupled between a high voltage terminal (eg, a power voltage terminal AVDD) and the first floating diffusion node FD1. The first reset element MR1 may selectively couple the high voltage terminal to the first floating diffusion node FD1 based on a first reset control signal RX1.

[0045] The first driving element MD1 may be coupled between the high voltage terminal and the first selection element MS1. The first driving element MD1 may drive the pixel signal VPX based on a voltage loaded on the first floating diffusion node FD1.

[0046] The first selection element MS1 may be coupled between the first driving element MD1 and the first column line COL1 The first selection element MS1 may output the pixel signal VPX to the first column line COL1 based on the first selection control signal SX1.

[0047] The first to fourth transmission control signals TX1 to TX4 , the first reset control signal RX1 , and the first selection control signal SX1 may be included in the above-mentioned row control signal CTRL.

[0048] Figure 4 is an example Figure 2 A circuit diagram of another example of any one of the unit pixel circuits shown.

[0049] Reference Figure 4 The unit pixel circuit may include first to fourth photodiodes PD1, PD2, PD3 and PD4, first to fourth transmission elements MT1, MT2, MT3 and MT4, a first floating diffusion node FD1, a first storage element MG1, a first reset element MR1, a first driving element MD1 and a first selection element MS1.

[0050] In this article, since the first to fourth photodiodes PD1, PD2, PD3 and PD4, the first to fourth transmission elements MT1, MT2, MT3 and MT4, the first floating diffusion node FD1, the first reset element MR1, the first drive element MD1 and the first selection element MS1 are connected to Figure 3 The same as shown, so the detailed description thereof is omitted, and only the first storage element MG1 is described below.

[0051] The first storage element MG1 may be selectively coupled to the first floating diffusion node FD1 based on the first gain conversion signal VG1. For example, when performing a high dynamic range function, the first storage element MG1 may be selectively coupled to the first floating diffusion node FD1. More specifically, the first storage element MG1 may not be coupled to the first floating diffusion node FD1 during a first portion of a second period in which a high brightness image is generated, and may be coupled to the first floating diffusion node FD1 during a second portion of a second period in which a low brightness image is generated. For example, the first storage element MG1 may receive the first gain conversion signal VG1 through its gate terminal, and have a source terminal and a drain terminal coupled between the first floating diffusion node FD1 and the floating node.

[0052] Hereinafter, the operation of the image sensing device 100 according to the first embodiment is described, wherein the image sensing device 100 has the above-described configuration.

[0053] First, the operation of the image sensing device 100 according to the phase detection auto focus function is described.

[0054] During the first period, when the pixel array 120 generates a pixel signal VPX corresponding to the depth of the object under the control of the row controller 110, the signal converter 130 may generate an image signal DPX corresponding to the pixel signal VPX. The image processor 140 may calculate the depth of the object based on some of the image signal DPX. The image signal for calculating the depth may correspond to the pixel signal generated from the semi-shielded pixel among the pixels in the pixel array 120. Specifically, considering the operation amount (i.e., throughput) of the image processor 140, the pixel signal generated from some of the semi-shielded pixels may be used as a depth calculation image signal. For example, the semi-shielded pixels used in the depth calculation may each have a green filter. Because the semi-shielded pixels each having a green filter have better sensitivity and resolution than the semi-shielded pixels each having a red filter or a blue filter, it may be advantageous to use the semi-shielded pixels each having a green filter.

[0055] Next, the operation of the image sensing device 100 according to the high dynamic range function is described.

[0056] During the second period, when the pixel array 120 generates a pixel signal VPX corresponding to the captured image under the control of the row controller 110, the signal converter 130 may generate an image signal DPX corresponding to the pixel signal VPX. The image processor 140 may generate a high brightness image based on the first image signal among the image signal DPX, and generate a low brightness image based on the second image signal. For example, the first image signal may correspond to the pixel signal generated from the first semi-shielded pixel among the pixels in the unit pixel circuit, respectively, and the second image signal may correspond to the pixel signal generated and synthesized from the first normal pixel to the third normal pixel among the pixels in the unit pixel circuit, respectively. Specifically, since the semi-shielded pixel and the normal pixel are controlled to have the same integration time, and the semi-shielded pixel has a light transmittance halved compared to the normal pixel, motion artifacts can be suppressed. The image processor 140 may generate a high dynamic range image based on the high brightness image and the low brightness image. In addition, when the first storage element MG1 is included in the unit pixel circuit, the maximum output range of the second image signal corresponding to the low brightness image can be increased.

[0057] Figure 5 is a block diagram illustrating an image sensing device 200 according to a second embodiment of the present disclosure.

[0058] Reference Figure 5 , the image sensing device 200 may include a row controller 210 , a pixel array 220 , a signal converter 230 , and an image processor 240 .

[0059] The row controller 210 may generate a plurality of row control signals CTRL for controlling respective rows of the pixel array 220. For example, the row controller 210 may generate a first row control signal for controlling pixels arranged in a first row of the pixel array 220 during a first unit row time, and generate an nth row control signal for controlling pixels arranged in an nth row of the pixel array 220 during an nth unit row time (where “n” is a natural number greater than 2).

[0060] The pixel array 220 may include pixels arranged at the intersection of a plurality of rows and a plurality of columns. For example, the pixels may be arranged as follows: Figure 6 The pixels may output a plurality of pixel signals VPX for each row to the signal converter 230 under the control of the row controller 210. For example, the pixels arranged in the first row may generate the pixel signal VPX during the first unit row time based on the first row control signal, and the pixels arranged in the nth row may generate the pixel signal VPX during the nth unit row time based on the nth row control signal.

[0061] The signal converter 230 may generate an image signal DPX corresponding to the pixel signal VPX. For example, the signal converter 230 may include an analog-to-digital converter (ADC).

[0062] Based on the image signal DPX, the image processor 240 may process phase information related to a phase detection auto focus function during a first period, and process an image related to a high dynamic range function during a second period.

[0063] Figure 6 is an example Figure 5 A diagram of an example of a pixel array 220 is shown.

[0064] Reference Figure 6 , the pixel array 220 may include a plurality of pixels arranged in a quad pattern. The quad pattern refers to a pattern in which pixels each having a color filter of the same color are arranged in units of 2×2. Hereinafter, a group of pixels arranged in units of 2×2 is referred to as a unit pixel circuit.

[0065] The unit pixel circuit may include first to fourth pixels, two of which may be semi-shielding pixels each having a semi-shielding layer, and the other two pixels may be normal pixels. The semi-shielding layer may have any one of a left shielding pattern S1, a right shielding pattern S2, an upper shielding pattern S3, and a lower shielding pattern S4. The left shielding pattern S1, the right shielding pattern S2, the upper shielding pattern S3, and the lower shielding pattern S4 do not necessarily have to be formed as follows. Figure 6 As shown, and can be variously changed according to the design.

[0066] Figure 7 is an example Figure 6 A circuit diagram of an example of any one unit pixel circuit shown.

[0067] Reference Figure 7 The unit pixel circuit may include first to fourth photodiodes PD1, PD2, PD3 and PD4, first to fourth transfer elements MT1, MT2, MT3 and MT4, a first floating diffusion node FD1, a first reset element MR1, a first driving element MD1 and a first selection element MS1.

[0068] The unit pixel circuit may have a structure in which the first to fourth photodiodes PD1 , PD2 , PD3 , and PD4 share a first floating diffusion node FD1 , a first reset element MR1 , a first driving element MD1 , and a first selection element MS1 .

[0069] The first photodiode PD1 may be coupled between a low voltage terminal (e.g., a ground voltage terminal) and the first transmission element MT1. The second photodiode PD2 may be coupled between the low voltage terminal and the second transmission element MT2. The third photodiode PD3 may be coupled between the low voltage terminal and the third transmission element MT3. The fourth photodiode PD4 may be coupled between the low voltage terminal and the fourth transmission element MT4. The first photodiode PD1 and the second photodiode PD2 may be associated with a semi-shielded pixel, and the third photodiode PD3 and the fourth photodiode PD4 may be associated with a normal pixel.

[0070] The first transmission element MT1 may be connected between the first photodiode PD1 and the first floating diffusion node FD1. The first transmission element MT1 may selectively connect the first photodiode PD1 to the first floating diffusion node FD1 based on the first transmission control signal TX1. The second transmission element MT2 may be connected between the second photodiode PD2 and the first floating diffusion node FD1. The second transmission element MT2 may selectively connect the second photodiode PD2 to the first floating diffusion node FD1 based on the second transmission control signal TX2. The third transmission element MT3 may be connected between the third photodiode PD3 and the first floating diffusion node FD1. The third transmission element MT3 may selectively connect the third photodiode PD3 to the first floating diffusion node FD1 based on the third transmission control signal TX3. The fourth transmission element MT4 may be connected between the fourth photodiode PD4 and the first floating diffusion node FD1. The fourth transmission element MT4 may selectively connect the fourth photodiode PD4 to the first floating diffusion node FD1 based on the fourth transmission control signal TX4. For example, during the first period, only the first transmission control signal TX1 and the second transmission control signal TX2 among the first to fourth transmission control signals TX1, TX2, TX3 and TX4 may be activated sequentially, and during the second period, the first transmission control signal TX1 and the second transmission control signal TX2 may be activated simultaneously, and the third transmission control signal TX3 and the fourth transmission control signal TX4 may be activated simultaneously.

[0071] Although not illustrated in the drawings, a first parasitic capacitor may be coupled to the first floating diffusion node FD1. The first parasitic capacitor may store charges generated from the first to fourth photodiodes PD1, PD2, PD3, and PD4.

[0072] The first reset element MR1 may be coupled between a high voltage terminal (eg, a power voltage terminal AVDD) and the first floating diffusion node FD1. The first reset element MR1 may selectively couple the high voltage terminal to the first floating diffusion node FD1 based on a first reset control signal RX1.

[0073] The first driving element MD1 may be coupled between the high voltage terminal and the first selection element MS1. The first driving element MD1 may drive the pixel signal VPX based on a voltage loaded on the first floating diffusion node FD1.

[0074] The first selection element MS1 may be coupled between the first driving element MD1 and the first column line COL1 The first selection element MS1 may output the pixel signal VPX to the first column line COL1 based on the first selection control signal SX1.

[0075] The first to fourth transmission control signals TX1 to TX4 , the first reset control signal RX1 , and the first selection control signal SX1 may be included in the above-mentioned row control signal CTRL.

[0076] Figure 8 is an example Figure 6 A circuit diagram of another example of any one of the unit pixel circuits shown.

[0077] Reference Figure 8 The unit pixel circuit may include first to fourth photodiodes PD1, PD2, PD3 and PD4, first to fourth transmission elements MT1, MT2, MT3 and MT4, a first floating diffusion node FD1, a first storage element MG1, a first reset element MR1, a first driving element MD1 and a first selection element MS1.

[0078] In this article, since the first to fourth photodiodes PD1, PD2, PD3 and PD4, the first to fourth transmission elements MT1, MT2, MT3 and MT4, the first floating diffusion node FD1, the first reset element MR1, the first drive element MD1 and the first selection element MS1 are connected to Figure 7 The same as shown, so the detailed description thereof is omitted, and only the first storage element MG1 is described below.

[0079] The first storage element MG1 may be selectively coupled to the first floating diffusion node FD1 based on the first gain conversion signal VG1. For example, when the high dynamic range function is performed, the first storage element MG1 may be selectively coupled to the first floating diffusion node FD1. According to an example, the first storage element MG1 may be coupled to the first floating diffusion node FD1 during a period of generating a high brightness image in the second period, and may not be coupled to the first floating diffusion node FD1 during a period of generating a low brightness image in the second period. A high brightness image may be generated based on a first image signal generated from a semi-shielded pixel, and a low brightness image may be generated based on a second image signal generated from a normal pixel. According to another example, the first storage element MG1 may be coupled to the first floating diffusion node FD1 during a period of generating a high brightness image in the second period, and may be coupled to the first floating diffusion node FD1 during a period of generating a low brightness image in the second period. For example, the first storage element MG1 may receive the first gain conversion signal VG1 through its gate terminal, and has a source terminal and a drain terminal coupled between the first floating diffusion node FD1 and the floating node.

[0080] Hereinafter, the operation of the image sensing device 200 according to the second embodiment is described, wherein the image sensing device has a Figure 7 and Figure 8Describes the configuration.

[0081] First, the operation of the image sensing device 200 according to the phase detection auto focus function is described.

[0082] During the first period, when the pixel array 220 generates a pixel signal VPX corresponding to the depth of the object under the control of the row controller 210, the signal converter 230 can generate an image signal DPX corresponding to the pixel signal VPX. The image processor 240 can calculate the depth of the object based on some of the image signals DPX. The image signal for calculating the depth can correspond to the pixel signal generated from the semi-shielded pixel among the pixels in the pixel array 120. Specifically, considering the operation amount (i.e., throughput) of the image processor 240, the pixel signal generated from some of the semi-shielded pixels can be used as a depth calculation image signal. For example, the semi-shielded pixels used in the depth calculation can each have a green filter. Because the semi-shielded pixels each having a green filter have better sensitivity and resolution than the semi-shielded pixels each having a red filter or a blue filter, it can be advantageous to use the semi-shielded pixels each having a green filter.

[0083] Next, the operation of the image sensing device 200 according to the high dynamic range function is described.

[0084] During the second period, when the pixel array 220 generates a pixel signal VPX corresponding to the captured image under the control of the row controller 210, the signal converter 230 may generate an image signal DPX corresponding to the pixel signal VPX. The image processor 240 may generate a high brightness image based on the first image signal among the image signal DPX, and generate a low brightness image based on the second image signal. For example, the first image signal may correspond to pixel signals generated and synthesized from the first semi-shielded pixel and the second semi-shielded pixel among the pixels included in the unit pixel circuit, respectively, and the second image signal may correspond to pixel signals generated and synthesized from the first normal pixel and the second normal pixel among the pixels included in the unit pixel circuit, respectively. Specifically, since the semi-shielded pixel and the normal pixel are controlled to have the same integration time, and the semi-shielded pixel has a light transmittance halved compared to the normal pixel, motion artifacts can be suppressed. The image processor 240 may generate a high dynamic range image based on the high brightness image and the low brightness image. In addition, when the first storage element MG1 is included in the unit pixel circuit, the maximum output range of the second image signal corresponding to the low brightness image can be increased.

[0085] According to an embodiment of the present disclosure, pixels related to a phase detection auto focus function may be arranged over the entire area of ​​an image, and the pixels may also be used for a high dynamic range function.

[0086] According to an embodiment of the present disclosure, pixels related to the phase detection autofocus function can be arranged over the entire area of ​​the image and can also be used for the high dynamic range function, thereby obtaining an image within a high dynamic range while improving the accuracy of the phase detection autofocus function.

[0087] Although the present disclosure has been illustrated and described with reference to specific embodiments, various changes and modifications can be made as those skilled in the art can recognize from the present disclosure. Therefore, the disclosed embodiments and any specific details are not restrictive. The present disclosure covers all variations that fall within the scope of the claims.

[0088] CROSS-REFERENCE TO RELATED APPLICATIONS

[0089] This application claims priority to Korean Patent Application No. 10-2020-0146139, filed on November 4, 2020, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An image sensing device, comprising: A first pixel group, the first pixel group comprising at least one first semi-shielded pixel and at least one first normal pixel; as well as an image processor that calculates a depth from an object by using phase information of a first pixel signal generated from the first semi-shielded pixel during a first period, generates a high-brightness image by using dynamic range information of the first pixel signal generated from the first semi-shielded pixel during a second period, and generates a low-brightness image based on a pixel signal generated from the first normal pixel during the second period, The first semi-shielded pixel and the first normal pixel are controlled to have the same integration time.

2. The image sensing device according to claim 1, further comprising a second pixel group, wherein the second pixel group comprises at least one second semi-shielded pixel and at least one second normal pixel, in, The image processor uses the dynamic range information of a second pixel signal generated from the second semi-shielded pixel during the second period.

3. The image sensing device according to claim 2, wherein: The first semi-shielded pixel has a green color filter, and the second semi-shielded pixel has a red color filter or a blue color filter.

4. The image sensing device according to claim 2, wherein: The first semi-shielding pixel includes a first semi-shielding layer, the second semi-shielding pixel includes a second semi-shielding layer, and each of the first semi-shielding layer and the second semi-shielding layer has any one of a left shielding pattern, a right shielding pattern, an upper shielding pattern and a lower shielding pattern.

5. The image sensing device according to claim 1, wherein: The first period includes a time segment when the image sensing device performs a phase detection auto focus function, and the second period includes a time segment when the image sensing device captures an image.

6. An image sensing device, comprising: A first pixel group, the first pixel group comprising a first semi-light-shielded pixel and three first normal pixels; as well as an image processor that calculates a depth from an object by using phase information of a first pixel signal generated from the first semi-shielded pixel during a first period, generates a high-brightness image by using dynamic range information of the first pixel signal generated from the first semi-shielded pixel during a second period, and generates a low-brightness image based on a pixel signal generated from the first normal pixel during the second period, The first semi-shielded pixel and the first normal pixel are controlled to have the same integration time.

7. The image sensing device according to claim 6, further comprising a second pixel group, wherein the second pixel group comprises a second semi-shielded pixel and three second normal pixels. in, The image processor uses the dynamic range information of a second pixel signal generated from the second semi-shielded pixel during the second period.

8. The image sensing device according to claim 7, wherein: The first semi-shielded pixel has a green color filter, and the second semi-shielded pixel has a red color filter or a blue color filter.

9. The image sensing device according to claim 7, wherein: The first semi-shielding pixel includes a first semi-shielding layer, the second semi-shielding pixel includes a second semi-shielding layer, and each of the first semi-shielding layer and the second semi-shielding layer has any one of a left shielding pattern, a right shielding pattern, an upper shielding pattern and a lower shielding pattern.

10. The image sensing device according to claim 6, wherein: The first pixel group comprises: The one first half light-shielded pixel; a first transmission element, the first transmission element being connected between the one first semi-shielded pixel and the first floating diffusion node; The three first normal pixels; and The first to third transmission elements are connected between the three first normal pixels and the first floating diffusion node.

11. The image sensing device according to claim 6, wherein: The first pixel group comprises: The one first half light-shielded pixel; a first transmission element, the first transmission element being connected between the one first semi-shielded pixel and the first floating diffusion node; The three first normal pixels; first to third transmission elements, the first to third transmission elements being coupled between the three first normal pixels and the first floating diffusion node; and A first storage element is coupled to the first floating diffusion node and is controlled by a first gain conversion signal.

12. An image sensing device, comprising: A first pixel group, the first pixel group comprising two first semi-light-shielded pixels and two first normal pixels; as well as an image processor that calculates a depth from an object by using phase information of a first pixel signal generated from the first semi-shielded pixel during a first period, generates a high-brightness image by using dynamic range information of the first pixel signal generated from the first semi-shielded pixel during a second period, and generates a low-brightness image based on a pixel signal generated from the first normal pixel during the second period, The first semi-shielded pixel and the first normal pixel are controlled to have the same integration time.

13. The image sensing device according to claim 12, further comprising a second pixel group, wherein the second pixel group comprises two second semi-shielded pixels and two second normal pixels, in, The image processor uses the dynamic range information of a second pixel signal generated from the second semi-shielded pixel during the second period.

14. The image sensing device according to claim 13, wherein: Each of the first semi-shielded pixels has a green color filter, and each of the second semi-shielded pixels has a red color filter or a blue color filter.

15. The image sensing device according to claim 13, wherein: Each of the first semi-shielding pixels includes a first semi-shielding layer, each of the second semi-shielding pixels includes a second semi-shielding layer, and each of the first semi-shielding layer and the second semi-shielding layer has any one of a left shielding pattern, a right shielding pattern, an upper shielding pattern and a lower shielding pattern.

16. The image sensing device according to claim 12, wherein: The first pixel group comprises: The two first semi-light-shielded pixels; a first transmission element and a second transmission element, wherein the first transmission element and the second transmission element are connected between the two first semi-shielded pixels and the first floating diffusion node; The two first normal pixels; and A third transmission element and a fourth transmission element are coupled between the two first normal pixels and the first floating diffusion node.

17. The image sensing device according to claim 12, wherein: The first pixel group further includes: The two first semi-light-shielded pixels; a first transmission element and a second transmission element, wherein the first transmission element and the second transmission element are connected between the two first semi-shielded pixels and the first floating diffusion node; The two first normal pixels; a third transmission element and a fourth transmission element, the third transmission element and the fourth transmission element being coupled between the two first normal pixels and the first floating diffusion node; and A first storage element is coupled to the first floating diffusion node and is controlled by a first gain conversion signal.

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