Display substrate, manufacturing method thereof, and display device

Abstract

The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes: a first sub-pixel and a second sub-pixel, the first sub-pixel including a first data line pattern, and the second sub-pixel including a second data line pattern; the second electrode of a sixth transistor in the first sub-pixel is electrically connected to an anode pattern via a third conductive connection portion and a fourth conductive connection portion in sequence; in the first sub-pixel, an orthographic projection of the anode pattern on a substrate at least partially overlaps with an orthographic projection of the second data line pattern on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with an orthographic projection of a data line pattern adjacent to the second data line pattern along a first direction on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] Active-matrix Organic Light-Emitting Diode (AMOLED) displays are currently attracting widespread attention due to their numerous advantages, including self-luminescence, ultra-thinness, fast response time, high contrast, and wide viewing angle. These AMOLED displays include multiple pixel driver circuits and multiple light-emitting elements. The pixel driver circuits drive the corresponding light-emitting elements to emit light, thereby achieving the display function of the AMOLED display.

[0003] When the pixel driving circuit drives the light-emitting element to emit light, it includes a low-frequency driving mode and a high-frequency driving mode. When the low-frequency driving mode is used to drive the light-emitting element, the data writing time of each row of pixels controlled by the pixel driving circuit is longer. When the high-frequency driving mode is used to drive the light-emitting element, the data writing time of each row of pixels will be compressed, so that the data writing time of each row of pixels controlled by the pixel driving circuit is shorter. Summary of the Invention

[0004] The present disclosure aims to provide a display substrate, a method for manufacturing the same, and a display device.

[0005] A first aspect of the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels arrayed on the substrate, the plurality of sub-pixels comprising:

[0006] a first subpixel and a second subpixel arranged along a second direction, the first subpixel including a first data line pattern, the second subpixel including a second data line pattern, the first data line pattern being configured to provide a first data signal to the first subpixel, and the second data line pattern being configured to provide a second data signal to the second subpixel;

[0007] At least a portion of the first data line pattern and at least a portion of the second data line pattern both extend along a second direction, the first data line pattern is located on a first side of the first sub-pixels in the same column extending along the second direction, and the second data line pattern is located on a second side of the second sub-pixels in the same column extending along the second direction; the first side and the second side are opposite to each other along the first direction, and the first direction intersects the second direction;

[0008] The first subpixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; a second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion;

[0009] In the first subpixel, an orthographic projection of the anode pattern on the substrate at least partially overlaps with an orthographic projection of the second data line pattern on the substrate, and an orthographic projection of a data line pattern adjacent to the second data line pattern along the first direction on the substrate at least partially overlaps.

[0010] Optionally, in the first sub-pixel, the anode pattern and the first data line pattern do not overlap.

[0011] Optionally, the second sub-pixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion;

[0012] In the second sub-pixel, the fourth conductive connection portion includes a solid portion and a hollow portion;

[0013] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the first data line pattern on the substrate, and the orthographic projection of the data line pattern adjacent to the first data line pattern along the first direction on the substrate at least partially overlaps;

[0014] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the second data line pattern on the substrate, and respectively overlaps with the orthographic projection of the solid portion on the substrate and the orthographic projection of the hollow portion on the substrate.

[0015] Optionally, the plurality of sub-pixels further include:

[0016] a third sub-pixel and a fourth sub-pixel arranged along the second direction, wherein along the first direction, the third sub-pixel and the first sub-pixel are located in the same row, and the fourth sub-pixel and the second sub-pixel are located in the same row;

[0017] The third sub-pixel includes a third data line pattern, and the fourth sub-pixel includes a fourth data line pattern. At least a portion of the third data line pattern and at least a portion of the fourth data line pattern extend along a second direction. The third data line pattern is located on a second side of the third sub-pixels in the same column extending along the second direction. The fourth data line pattern is located on a first side of the fourth sub-pixels in the same column extending along the second direction.

[0018] The third sub-pixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; a second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion;

[0019] In the third sub-pixel, the fourth conductive connection portion includes a solid portion and a hollow portion;

[0020] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the solid portion on the substrate and the orthographic projection of the hollow portion on the substrate;

[0021] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the third data line pattern on the substrate, and at least partially overlaps with the orthographic projection of a data line pattern adjacent to the third data line pattern along the first direction on the substrate.

[0022] Optionally, the fourth subpixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion;

[0023] In the fourth sub-pixel, the fourth conductive connection portion includes a solid portion and a hollow portion;

[0024] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the solid portion on the substrate;

[0025] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the third data line pattern on the substrate, and at least partially overlaps with the orthographic projection of a data line pattern adjacent to the third data line pattern along the first direction on the substrate.

[0026] Optionally, in the fourth sub-pixel, an orthographic projection of the anode pattern on the substrate does not overlap with an orthographic projection of the fourth data line pattern on the substrate.

[0027] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each include:

[0028] a power signal line pattern, at least a portion of which extends along the second direction;

[0029] a power compensation pattern, at least a portion of which extends along the first direction, and the power signal line pattern and the power compensation pattern are both located on a side of the first data line pattern, the second data line pattern, the third data line pattern, and the fourth data line pattern close to the substrate;

[0030] The power compensation pattern is electrically connected to the power signal line pattern in the sub-pixel to which it belongs and the power signal line pattern in the adjacent sub-pixel along the first direction.

[0031] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include: a reset signal line pattern, a gate line pattern and a light-emitting control signal line pattern distributed along the second direction; at least a portion of the reset signal line pattern extends along the first direction, at least a portion of the gate line pattern extends along the first direction, and at least a portion of the light-emitting control signal line pattern extends along the first direction; in the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, the orthographic projection of the power supply compensation pattern on the substrate is located between the orthographic projection of the gate line pattern on the substrate and the orthographic projection of the light-emitting control signal line pattern on the substrate.

[0032] Optionally, in the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, the power signal line pattern in each sub-pixel includes: a power main portion and a power protrusion portion electrically connected to each other, at least a portion of the power protrusion portion extends along the second direction, and a gap is formed between the power protrusion portion and the power main portion;

[0033] A first end of the power compensation pattern is electrically connected to the power protrusion portion of the sub-pixel to which it belongs; a second end of the power compensation pattern is electrically connected to the power main portion of the adjacent sub-pixel along the first direction.

[0034] Optionally, in the first sub-pixel, the orthographic projection of the power protrusion on the substrate overlaps with the orthographic projection of the first data line pattern on the substrate, and the orthographic projection of the power main body on the substrate at least partially overlaps with the orthographic projection of the data line pattern adjacent along the first direction on the substrate.

[0035] Optionally, in the second sub-pixel, an orthographic projection of the power source protrusion on the substrate does not overlap with an orthographic projection of the second data line pattern on the substrate.

[0036] Optionally, in the third sub-pixel, an orthographic projection of the power source protrusion on the substrate does not overlap with an orthographic projection of the third data line pattern on the substrate.

[0037] Optionally, in the fourth sub-pixel, the orthographic projection of the power protrusion on the substrate overlaps with the orthographic projection of the fourth data line pattern on the substrate, and the orthographic projection of the power main body on the substrate overlaps with the orthographic projection of the data line pattern adjacent along the first direction on the substrate.

[0038] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include: an initialization signal line pattern, a second transistor and a second conductive connection portion;

[0039] At least a portion of the initialization signal line pattern extends along the second direction, and the initialization signal line pattern is used to transmit an initialization signal;

[0040] The first electrode of the second transistor is electrically connected to the initialization signal line pattern through the second conductive connection portion, and the second electrode of the second transistor is electrically connected to the gate of the driving transistor;

[0041] In the first sub-pixel, an orthographic projection of the second conductive connection portion on the substrate overlaps with an orthographic projection of the first data line pattern on the substrate;

[0042] In the second sub-pixel, an orthographic projection of the second conductive connection portion on the substrate does not overlap with an orthographic projection of the second data line pattern on the substrate;

[0043] In the third sub-pixel, an orthographic projection of the second conductive connection portion on the substrate does not overlap with an orthographic projection of the third data line pattern on the substrate;

[0044] In the fourth sub-pixel, an orthographic projection of the second conductive connection portion on the substrate overlaps with an orthographic projection of the fourth data line pattern on the substrate.

[0045] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include: an initialization signal line pattern, a shielding pattern, a driving transistor and a second transistor;

[0046] In the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, a first electrode of the second transistor is electrically connected to the initialization signal line pattern, and a second electrode of the second transistor is electrically connected to the gate of the driving transistor;

[0047] The shielding pattern is electrically connected to a power signal line pattern in the display substrate, and an orthographic projection of the shielding pattern on the substrate at least partially overlaps with an orthographic projection of the first electrode of the second transistor on the substrate.

[0048] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include: a first conductive connection portion, a fifth conductive connection portion and a data writing transistor,

[0049] In the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, the second electrode of the second transistor is electrically connected to the gate of the driving transistor through the fifth conductive connection portion;

[0050] The first conductive connection portion is electrically connected to the first electrode of the data writing transistor; the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor;

[0051] An orthographic projection of the shielding pattern on the substrate at least partially overlaps with an orthographic projection of the first conductive connection portion on the substrate.

[0052] Optionally, an orthographic projection of at least part of the shielding pattern on the substrate is located between an orthographic projection of the first conductive connection portion on the substrate and an orthographic projection of the fifth conductive connection portion on the substrate.

[0053] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each include: a light-emitting element, an initialization signal line pattern, a reset signal line pattern, a gate line pattern, a light-emitting control signal line pattern, and a power signal line pattern; at least a portion of the initialization signal line pattern, at least a portion of the reset signal line pattern, at least a portion of the gate line pattern, and at least a portion of the light-emitting control signal line pattern all extend along the first direction, and at least a portion of the power signal line pattern extends along the second direction;

[0054] The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel further include: a first transistor, a second transistor, a driving transistor, a data writing transistor, a fifth transistor, a sixth transistor, a seventh transistor and a storage capacitor;

[0055] In each sub-pixel, the gate of the driving transistor is electrically connected to the second electrode of the first transistor, the first electrode of the driving transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the driving transistor is electrically connected to the first electrode of the first transistor;

[0056] The gate of the first transistor is electrically connected to the gate line pattern;

[0057] The gate of the second transistor is electrically connected to the reset signal line pattern, the first electrode of the second transistor is electrically connected to the initialization signal line pattern, and the second electrode of the second transistor is electrically connected to the gate of the driving transistor;

[0058] The gate of the data writing transistor is electrically connected to the gate line pattern, the first electrode of the data writing transistor is electrically connected to the data line pattern in the sub-pixel, and the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor;

[0059] The gate of the fifth transistor is electrically connected to the light emitting control signal line pattern, and the first electrode of the fifth transistor is electrically connected to the power signal line pattern;

[0060] The gate of the sixth transistor is electrically connected to the light emitting control signal line pattern, the first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is electrically connected to the light emitting element;

[0061] The gate of the seventh transistor is electrically connected to the reset signal line pattern in the next sub-pixel adjacent to the second direction, the first electrode of the seventh transistor is electrically connected to the initialization signal line pattern in the next sub-pixel adjacent to the second direction, and the second electrode of the seventh transistor is electrically connected to the light-emitting element;

[0062] The first plate of the storage capacitor is multiplexed as the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the power signal line pattern.

[0063] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate.

[0064] Based on the technical solution of the display substrate described above, a third aspect of the present disclosure provides a method for manufacturing a display substrate, comprising: manufacturing a plurality of sub-pixels distributed in an array on a substrate, the plurality of sub-pixels comprising:

[0065] a first subpixel and a second subpixel arranged along a second direction, the first subpixel including a first data line pattern, the second subpixel including a second data line pattern, the first data line pattern being configured to provide a first data signal to the first subpixel, and the second data line pattern being configured to provide a second data signal to the second subpixel;

[0066] At least a portion of the first data line pattern and at least a portion of the second data line pattern both extend along a second direction, the first data line pattern is located on a first side of the first sub-pixels in the same column extending along the second direction, and the second data line pattern is located on a second side of the second sub-pixels in the same column extending along the second direction; the first side and the second side are opposite to each other along the first direction, and the first direction intersects the second direction;

[0067] The first subpixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; a second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion;

[0068] In the first subpixel, an orthographic projection of the anode pattern on the substrate at least partially overlaps with an orthographic projection of the second data line pattern on the substrate, and an orthographic projection of a data line pattern adjacent to the second data line pattern along the first direction on the substrate at least partially overlaps. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0070] Figure 1a A schematic diagram of sub-pixel layout in related art;

[0071] Figure 1b 1 is a schematic diagram of the layout of the active layer;

[0072] Figure 1c 1 is a schematic diagram of the layout of the first gate metal layer;

[0073] Figure 1d 1 is a schematic diagram of the layout of the second gate metal layer;

[0074] Figure 1e 1 is a schematic diagram of the layout of the source and drain metal layers;

[0075] Figure 1f is a cross-sectional schematic diagram of an anode pattern in the related art;

[0076] Figure 2 A circuit diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0077] Figure 3 This is a working timing diagram of the sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0078] Figure 4 A schematic diagram of a first layout of sub-pixels provided in an embodiment of the present disclosure;

[0079] Figure 5 A schematic diagram of a second layout of sub-pixels provided in an embodiment of the present disclosure;

[0080] Figure 6 for Figure 5 Schematic diagram of the layout of the active layer and the first gate metal layer;

[0081] Figure 7 for Figure 5 Schematic diagram of the layout of the second gate metal layer;

[0082] Figure 8 for Figure 5 Schematic diagram of the layout of the first source and drain metal layer;

[0083] Figure 9 for Figure 5 Schematic diagram of the structure of the power compensation diagram;

[0084] Figure 10 for Figure 5 Schematic diagram of the layout of the first source and drain metal layer and the second source and drain metal layer;

[0085] Figure 11 for Figure 5 Schematic diagram of the layout of the second source and drain metal layer;

[0086] Figure 12 Schematic diagram of the layout of eight sub-pixels;

[0087] Figure 13a for Figure 12 Schematic diagram of the cross section along the A1A2 direction;

[0088] Figure 13b for Figure 12 Schematic diagram of the cross section along the B1B2 direction;

[0089] Figure 13c for Figure 12 Schematic diagram of the cross section along the C1C2 direction;

[0090] Figure 13d for Figure 12 Schematic diagram of the cross section along the D1D2 direction;

[0091] Figure 14 for Figure 12 Schematic diagram of the layout of the two source and drain metal layers and the anode layer;

[0092] Figure 15 A schematic diagram of the layout of the second source / drain metal layer and the anode layer provided in an embodiment of the present disclosure;

[0093] Figure 16 for Figure 12 Schematic diagram of the layout of the active layer in ;

[0094] Figure 17 for Figure 12 Schematic diagram of the layout of the first gate metal layer;

[0095] Figure 18 for Figure 12 Schematic diagram of the layout of the second gate metal layer;

[0096] Figure 19 for Figure 12 Layout diagram of the first source and drain metal layer. DETAILED DESCRIPTION

[0097] In order to further illustrate the display substrate and its manufacturing method, and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0098] The structure of an AMOLED display panel includes: a substrate, multiple sub-pixel driving circuits arranged on the substrate, and multiple light-emitting elements arranged on the side of the sub-pixel driving circuit facing away from the substrate. The light-emitting elements correspond one-to-one to the sub-pixel driving circuits. The sub-pixel driving circuits are used to drive the corresponding light-emitting elements to emit light, thereby realizing the display function of the display panel.

[0099] In the related art, the sub-pixel driving circuit generally includes a plurality of thin film transistors, such as Figure 1a As shown, Figure 1a FIG. 1 shows a specific layout of the seven thin film transistors Q1 to Q7 when the sub-pixel driving circuit includes seven thin film transistors. When arranged in this manner, the sub-pixel driving circuit includes the following: Figure 1b The active layer shown, such as Figure 1c The first metal layer shown, such as Figure 1d The second metal layer shown, and Figure 1e The third metal layer shown; the active layer includes an active pattern (such as Figure 1b The portion within the dotted frame in FIG), and the active pattern electrically connected to the active pattern, having conductive properties (such as Figure 1b The first metal layer includes the gates of each thin film transistor, the scanning signal line GATE electrically connected to the gate, one electrode plate CE1 of the storage capacitor in the sub-pixel driving circuit, the reset signal line RST, and the light-emitting control signal line EM; the second metal layer includes the initialization signal line VINT, and another electrode plate CE2 of the storage capacitor in the sub-pixel driving circuit; the third metal layer includes the data line DATA, the power signal line VDD, and some conductive connection parts (such as marks 341~343).

[0100] It is worth noting that, as shown in FIG1 , when laying out the sub-pixel driving circuit, some vias (such as those marked: 381 to 388 ) may be provided in order to achieve electrical connection between functional patterns provided on different layers.

[0101] With the development of AMOLED technology, the requirements for display quality are becoming increasingly higher. AMOLED display products have many performance specifications, and color shift is one of the most important parameters.

[0102] like Figure 1f As shown, due to the differences in the film structure below the flat layer PLN, height differences will appear at different locations above the flat layer PLN, and the source-drain metal pattern 344 is relatively thick. This problem is particularly prominent at the location where the source-drain metal pattern 344 is present. If there is no source-drain metal pattern 344 below the anode pattern 70', the anode pattern 70' will be relatively flat. If there is a source-drain metal pattern 344 on one side below the anode pattern 70, but not on the other side, this will result in a height difference between the two sides of the anode pattern, causing the anode pattern 70 to "tilt," resulting in inconsistent light intensity from a single sub-pixel to the left and right. Moreover, because the anode patterns of different color sub-pixels "tilt" in different directions, the light intensity emitted by multiple sub-pixels to the left and right sides does not match. In this case, the display panel will experience a large visual color deviation, which will appear to be red on one side and blue on the other side.

[0103] It can be seen that the design of the source-drain metal pattern 344 below the anode pattern has a great influence on the color shift of the display panel. The anode pattern 70 is lower when there is no source-drain metal pattern 344, while it is higher when there is a source-drain metal pattern 344. The flatness of the anode pattern directly affects the pixel luminescence and determines the color shift characteristics of the panel.

[0104] In the related art, the layout position of the anode pattern causes it to be "tilted", which leads to color cast in the display product.

[0105] like Figures 12 to 15 As shown, an embodiment of the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels arrayed on the substrate, wherein the plurality of sub-pixels include:

[0106] A first subpixel M1 and a second subpixel M2 are arranged along the second direction, wherein the first subpixel M1 includes a first data line pattern 981, and the second subpixel M2 includes a second data line pattern 982. The first data line pattern 981 is configured to provide a first data signal to the first subpixel M1, and the second data line pattern 982 is configured to provide a second data signal to the second subpixel M2.

[0107] At least a portion of the first data line pattern 981 and at least a portion of the second data line pattern 982 both extend along the second direction. The first data line pattern 981 is located on a first side of the first sub-pixel M1 in the same column extending along the second direction, and the second data line pattern 982 is located on a second side of the second sub-pixel M2 in the same column extending along the second direction. The first side and the second side are opposite to each other along the first direction, and the first direction intersects the second direction.

[0108] The first subpixel M1 includes a sixth transistor T6, and a third conductive connection portion 963, a fourth conductive connection portion 964, and an anode pattern stacked in a direction away from the substrate; a second electrode of the sixth transistor T6 is electrically connected to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964;

[0109] In the first sub-pixel M1, the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the second data line pattern 982 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the data line pattern adjacent to the second data line pattern 982 along the first direction on the substrate.

[0110] Specifically, the display substrate includes a plurality of sub-pixels arrayed on a substrate, wherein the plurality of sub-pixels can be divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels. The plurality of rows of sub-pixels are arranged along the second direction, and each row of sub-pixels includes a plurality of sub-pixels sequentially arranged along the first direction. The plurality of columns of sub-pixels are arranged along the first direction, and each column of sub-pixels includes a plurality of sub-pixels sequentially arranged along the second direction.

[0111] Exemplarily, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0112] At least a portion of the first data line pattern 981 and at least a portion of the second data line pattern 982 extend along the second direction. The first data line patterns 981 included in each first sub-pixel M1 in the same column of sub-pixels are electrically connected in sequence to form an integrated structure. The second data line patterns 982 included in each second sub-pixel M2 in the same column of sub-pixels are electrically connected in sequence to form an integrated structure.

[0113] For example, Figure 15 As shown, the first data line pattern 981 is: along the second direction, the data line portion between the data writing position of the current first sub-pixel M1 (such as the position of the data line protrusion 9802) and the data writing position of the adjacent first sub-pixel M1 in the next row.

[0114] Exemplarily, in the same column of sub-pixels, the first sub-pixels M1 and the second sub-pixels M2 are alternately arranged.

[0115] Exemplarily, in the same column of sub-pixels, the first sub-pixel M1 is the odd-numbered sub-pixel, which receives the first data signal provided by the first data line graphic 981 included therein, and the second sub-pixel M2 is the even-numbered sub-pixel, which receives the second data signal provided by the second data line graphic 982 included therein.

[0116] Exemplarily, the first side is set to Figure 5 The right side of the Figure 5 In the same column of sub-pixels, the first data line pattern 981 is located on a first side of the same column of sub-pixels, and the second data line pattern 982 is located on a second side of the same column of sub-pixels.

[0117] The first sub-pixel M1 and the second sub-pixel M2 each include a sub-pixel driving circuit. The sub-pixel driving circuit includes a storage capacitor and a plurality of thin film transistors, such as Figure 2 and Figure 5 As shown, the sub-pixel driving circuit exemplarily includes 7T1C, ie, 7 transistors and a storage capacitor. The sub-pixel driving circuit is used to generate a driving signal for driving the light-emitting element to emit light.

[0118] Exemplarily, the sub-pixel driving circuit includes a driving transistor and a data writing transistor. In the first sub-pixel M1, the first electrode of the data writing transistor is electrically connected to the first data line pattern 981, and in the second sub-pixel M2, the first electrode of the data writing transistor is electrically connected to the second data line pattern 982. In each sub-pixel, the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor. The data writing transistor can transmit a data signal received at its first electrode to the first electrode of the driving transistor.

[0119] In the same column of sub-pixels, the first electrodes of the data write transistors in adjacent sub-pixels are electrically connected to different data line patterns. More specifically, in the same column of sub-pixels, the first electrode of the data write transistor included in one of the adjacent sub-pixels is electrically connected to the first data line pattern 981, while the first electrode of the data write transistor included in the other of the adjacent sub-pixels is electrically connected to the second data line pattern 982.

[0120] Each sub-pixel includes a light-emitting element located on the side of the sub-pixel driving circuit facing away from the substrate. The light-emitting element includes an anode pattern, a light-emitting functional layer, and a cathode, which are stacked in sequence in a direction away from the substrate. The anode pattern is electrically connected to the sub-pixel driving circuit in the sub-pixel to which it belongs, and receives a driving signal provided by the sub-pixel driving circuit. The light-emitting functional layer includes an organic light-emitting material layer. In addition, the light-emitting functional layer may also include: an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL) and other common layers of the entire layer structure. The cathode is electrically connected to the negative power signal line in the display substrate and receives a negative power signal provided by the negative power signal line. The light-emitting functional layer emits light under the combined action of the anode pattern and the cathode, thereby realizing the display function of the display substrate.

[0121] like Figure 12 、 Figure 13a and Figure 15 As shown, each sub-pixel in the display substrate includes a sixth transistor T6, the gate of the sixth transistor T6 is electrically connected to the light-emitting control signal line pattern 93, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the driving transistor, the orthographic projection of the second electrode of the sixth transistor T6 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have a third overlapping area, the second electrode of the sixth transistor T6 and the third conductive connection portion 963 are electrically connected through a first via 61 provided in the third overlapping area; the third conductive connection portion 963 is electrically connected to the first via 61 provided in the third overlapping area. The orthographic projection on the substrate and the orthographic projection of the fourth conductive connecting portion 964 on the substrate have a fourth overlapping area, and the third conductive connecting portion 963 and the fourth conductive connecting portion 964 are electrically connected through the second via 62 set in the fourth overlapping area; the orthographic projection of the fourth conductive connecting portion 964 on the substrate and the orthographic projection of the anode pattern (such as the first anode pattern 71 to the eighth anode pattern 78) on the substrate have a fifth overlapping area, and the fourth conductive connecting portion 964 and the anode pattern are electrically connected through the third via 63 set in the fifth overlapping area.

[0122] During the light emitting period, the sixth transistor T6 transmits the driving signal outputted from the second electrode of the driving transistor to the anode of the light emitting element through the third conductive connection portion 963 and the fourth conductive connection portion 964 in sequence.

[0123] By providing the second electrode of the sixth transistor T6 to be electrically connected to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964 in sequence, the electrical connection performance between the second electrode of the sixth transistor T6 and the anode pattern is better guaranteed.

[0124] For example, Figure 11 、 Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown, in the first sub-pixel M1, the fourth conductive connection portion 964 includes a solid portion; the orthographic projection of the solid portion on the substrate at least partially overlaps with the orthographic projection of the anode pattern on the substrate; the orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the first data line pattern 981 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the second data line pattern 982 on the substrate.

[0125] Exemplarily, in the first subpixel M1, the light-emitting element includes a first light-emitting element, which includes a first anode pattern 71, a first light-emitting functional layer, and a cathode stacked in sequence in a direction away from the substrate. Exemplarily, the first light-emitting element includes a red light-emitting element.

[0126] Exemplarily, in the first sub-pixel M1, the orthographic projection of the entity portion on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping area; the orthographic projection of the entity portion on the substrate and the orthographic projection of the first anode pattern 71 on the substrate have the fifth overlapping area.

[0127] Exemplarily, the orthographic projection of the first anode pattern 71 on the substrate does not overlap with the orthographic projection of the first data line pattern 981 on the substrate, the orthographic projection of the first anode pattern 71 on the substrate does not overlap with the orthographic projection of the third data line pattern 983 adjacent to the first direction on the substrate, and the orthographic projection of the first anode pattern 71 on the substrate at least partially overlaps with the orthographic projection of the second data line pattern 982 adjacent to the second direction on the substrate.

[0128] Illustratively, the orthographic projection of the first side portion of the first anode pattern 71 on the substrate overlaps with the orthographic projection of the second data line pattern 982 adjacent to the second direction on the substrate; the orthographic projection of the second side portion of the first anode pattern 71 on the substrate overlaps with the orthographic projection of the eighth data line pattern 988 adjacent to the second data line pattern 982 along the first direction on the substrate; the first side portion and the second side portion are arranged opposite to each other along the first direction.

[0129] According to the specific structure of the above-mentioned display substrate, in the display substrate provided by the embodiment of the present disclosure, in the first sub-pixel M1, by setting the orthographic projection of the anode pattern on the substrate to at least partially overlap with the orthographic projection of the second data line pattern on the substrate, the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the data line pattern adjacent to the second data line pattern along the first direction on the substrate; so that the second data line pattern 982 and its adjacent data line pattern can compensate for the step difference generated by each other under the anode pattern (such as the first anode pattern 71), so that the anode pattern can be formed on a relatively flat surface, so that the anode pattern has a high flatness, ensuring that the sub-pixel has consistent luminous intensity in all directions, and effectively improving the color deviation problem generated by the display product when the display substrate is used in the display product.

[0130] like Figure 11 、 Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown, in some embodiments, in the first sub-pixel M1 , the anode pattern does not overlap with the first data line pattern 981 .

[0131] Specifically, in the first sub-pixel M1 , the first anode pattern 71 does not overlap with the first data line pattern 981 .

[0132] like Figure 11 、 Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown, in some embodiments, the second sub-pixel M2 includes a sixth transistor T6, and a third conductive connection portion 963, a fourth conductive connection portion 964, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor T6 is electrically connected to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964;

[0133] In the second sub-pixel M2, the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642;

[0134] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the first data line pattern 981 on the substrate, and the orthographic projection of the data line pattern adjacent to the first data line pattern 981 along the first direction on the substrate at least partially overlaps;

[0135] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the second data line pattern 982 on the substrate, and at least partially overlaps with the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the hollow portion 9642 on the substrate.

[0136] Specifically, in the second sub-pixel M2, the light-emitting element includes a second light-emitting element, which includes a second anode pattern 72, a second light-emitting functional layer, and a cathode stacked in sequence in a direction away from the substrate. Exemplarily, the second light-emitting element includes a blue light-emitting element.

[0137] Exemplarily, in the second sub-pixel M2, the orthographic projection of the entity portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping area; the orthographic projection of the entity portion 9641 on the substrate and the orthographic projection of the second anode pattern 72 on the substrate have the fifth overlapping area.

[0138] Exemplarily, the orthographic projection of the second side of the second anode pattern 72 on the substrate at least partially overlaps with the orthographic projection of the second data line pattern 982 in the sub-pixel to which it belongs on the substrate. The orthographic projection of the second side of the second anode pattern 72 on the substrate overlaps with both the orthographic projection of the solid portion and the orthographic projection of the hollow portion on the substrate. The orthographic projection of the first side of the second anode pattern 72 on the substrate overlaps with the orthographic projection of the first data line pattern 981 adjacent to the first direction on the substrate, and overlaps with the orthographic projection of the third data line pattern 983 adjacent to the first data line pattern 981 along the second direction on the substrate. The first side and the second side are arranged opposite each other along the first direction.

[0139] Exemplarily, the hollow portion 9642 is formed in a U-shape, and the orthographic projection of the second side of the second anode pattern 72 on the substrate overlaps with the orthographic projections of two sides of the hollow portion 9642 opposite to each other along the first direction on the substrate. Exemplarily, the orthographic projection of the second side of the second anode pattern 72 on the substrate overlaps with the orthographic projections of two sides of the hollow portion 9642 opposite to each other along the second direction on the substrate.

[0140] In the display substrate provided in the above embodiment, the fourth conductive connection portion 964 and the second data line pattern 982 can compensate for the step difference between the first data line pattern 981 and the data line pattern adjacent to the first data line pattern 981 (such as the third data line pattern 983) below the second anode pattern 72, so that the second anode pattern 72 can be formed on a relatively flat surface, thereby making the second anode pattern 72 have a higher flatness, effectively reducing the color shift phenomenon generated by the display substrate during display.

[0141] like Figure 11 、 Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown, in some embodiments, the third sub-pixel M3 and the fourth sub-pixel M4 are arranged along the second direction. Along the first direction, the third sub-pixel M3 and the first sub-pixel M1 are located in the same row, and the fourth sub-pixel M4 and the second sub-pixel M2 are located in the same row;

[0142] The third sub-pixel M3 includes a third data line pattern 983, and the fourth sub-pixel M4 includes a fourth data line pattern 984. At least a portion of the third data line pattern 983 and at least a portion of the fourth data line pattern 984 extend along the second direction. The third data line pattern 983 is located on the second side of the third sub-pixels M3 in the same column extending along the second direction, and the fourth data line pattern 984 is located on the first side of the fourth sub-pixels M4 in the same column extending along the second direction.

[0143] The third subpixel M3 includes a sixth transistor T6, and a third conductive connection portion 963, a fourth conductive connection portion 964, and an anode pattern stacked in a direction away from the substrate; a second electrode of the sixth transistor T6 is electrically connected to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964;

[0144] In the third sub-pixel M3, the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642;

[0145] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the hollow portion 9642 on the substrate;

[0146] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the third data line pattern 983 on the substrate, and at least partially overlaps with the orthographic projection of the data line pattern adjacent to the third data line pattern 983 along the first direction on the substrate.

[0147] Specifically, at least a portion of the third data line pattern 983 and at least a portion of the fourth data line pattern 984 both extend along the second direction. The third data line pattern 983 included in each third sub-pixel M3 located in the same column of sub-pixels are electrically connected in sequence to form an integrated structure. The fourth data line pattern 984 included in each fourth sub-pixel M4 located in the same column of sub-pixels are electrically connected in sequence to form an integrated structure. The third data line pattern 983 is configured to provide a third data signal to the third sub-pixel M3, and the fourth data line pattern 984 is configured to provide a fourth data signal to the fourth sub-pixel M4.

[0148] Exemplarily, along the first direction, the third sub-pixel M3 and the first sub-pixel M1 are located in the same row, and the fourth sub-pixel M4 and the second sub-pixel M2 are located in the same row.

[0149] Exemplarily, in the same column of sub-pixels, the third sub-pixels M3 and the fourth sub-pixels M4 are alternately arranged.

[0150] Similarly, the third sub-pixel M3 and the fourth sub-pixel M4 also include a sub-pixel driving circuit. In the third sub-pixel M3, the first electrode of the data write transistor is electrically connected to the third data line pattern 983, and in the fourth sub-pixel M4, the first electrode of the data write transistor is electrically connected to the fourth data line pattern 984. In each sub-pixel, the second electrode of the data write transistor is electrically connected to the first electrode of the driving transistor. The data write transistor can transmit a data signal received at its first electrode to the first electrode of the driving transistor.

[0151] Exemplarily, the first side is set to Figure 5 The right side of the Figure 5 The third data line pattern 983 is located on the second side of the third sub-pixel in the same column extending along the second direction, and the fourth data line pattern 984 is located on the first side of the fourth sub-pixel in the same column extending along the second direction.

[0152] Exemplarily, among the sub-pixels located in the same row along the first direction, the first data line pattern 981 and the third data line pattern 983 are both located between the first sub-pixel M1 to which the first data line pattern 981 belongs and the third sub-pixel M3 to which the third data line pattern 983 belongs. Among the sub-pixels located in the same row along the first direction, the second data line pattern 982 and the fourth data line pattern 984 are both located between the second sub-pixel M2 to which the second data line pattern 982 belongs and the fourth sub-pixel M4 to which the fourth data line pattern 984 belongs.

[0153] The third sub-pixel M3 and the fourth sub-pixel M4 both include: the power signal line pattern and the power compensation pattern. The structure of the power signal line pattern is the same as that of the power signal line pattern in the first sub-pixel M1 and the second sub-pixel M2. The structure of the power compensation pattern is the same as that of the power compensation pattern in the first sub-pixel M1 and the second sub-pixel M2.

[0154] It is worth noting that the sub-pixel driving circuits included in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 have the same structure, and the difference between the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 lies in the setting method of the data line and the structure of the light-emitting element.

[0155] In the third subpixel M3, the light-emitting element includes a third light-emitting element, which includes a third anode pattern 73, a third light-emitting functional layer, and a cathode sequentially stacked in a direction away from the substrate. Exemplarily, the third light-emitting element includes a green light-emitting element.

[0156] Exemplarily, in part of the third sub-pixel M3, the orthographic projection of the entity portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping area; the orthographic projection of the entity portion 9641 on the substrate and the orthographic projection of the third anode pattern 73 on the substrate have the fifth overlapping area.

[0157] Exemplarily, the orthographic projection of the second side of the third anode pattern 73 on the substrate at least partially overlaps with the orthographic projection of the third data line pattern 983 in the sub-pixel to which it belongs on the substrate, and the orthographic projection of the second side of the third anode pattern 73 on the substrate at least partially overlaps with the orthographic projection of the first data line 981 adjacent to the first direction on the substrate; the orthographic projection of the first side of the third anode pattern 73 on the substrate overlaps with the orthographic projection of the solid part on the substrate and the orthographic projection of the hollow part on the substrate; the first side and the second side are arranged opposite to each other along the first direction.

[0158] Exemplarily, the hollow portion 9642 is formed in a U-shape, and the orthographic projection of the first side of the third anode pattern 73 on the substrate overlaps with the orthographic projections of two opposite sides of the hollow portion 9642 along the first direction on the substrate.

[0159] The above-mentioned arrangement enables the fourth conductive connection portion 964 to compensate for the step difference generated by the first data line pattern 981 and the third data line pattern 983 below the third anode pattern 73, so that the third anode pattern 73 can be formed on a relatively flat surface, thereby making the fifth anode pattern 75 have a higher flatness, effectively reducing the color shift phenomenon generated by the display substrate during display.

[0160] like Figure 11 、 Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown, in some embodiments, the fourth sub-pixel M4 includes a sixth transistor T6, and a third conductive connection portion 963, a fourth conductive connection portion 964, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor T6 is electrically connected to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964;

[0161] In the fourth sub-pixel M4, the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642;

[0162] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the solid portion 9641 on the substrate;

[0163] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the third data line pattern 983 on the substrate, and at least partially overlaps with the orthographic projection of the data line pattern adjacent to the third data line pattern 983 along the first direction on the substrate.

[0164] Specifically, in the fourth subpixel M4, the light-emitting element includes a fourth light-emitting element, which includes a fourth anode pattern 74, a fourth light-emitting functional layer, and a cathode sequentially stacked in a direction away from the substrate. Exemplarily, the fourth light-emitting element includes a green light-emitting element.

[0165] Exemplarily, in the fourth sub-pixel M4, the orthographic projection of the entity portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping area; the orthographic projection of the entity portion 9641 on the substrate and the orthographic projection of the fourth anode pattern 74 on the substrate have the fifth overlapping area.

[0166] Illustratively, the orthographic projection of the second side portion of the fourth anode pattern 74 on the substrate at least partially overlaps with the orthographic projection of the third data line pattern 983 adjacent to it along the second direction on the substrate; the orthographic projection of the second side portion of the fourth anode pattern 74 on the substrate at least partially overlaps with the orthographic projection of the first data line pattern 981 adjacent to the third data line pattern 983 along the first direction on the substrate; the orthographic projection of the first side portion of the fourth anode pattern 74 on the substrate overlaps with the orthographic projection of the solid part on the substrate, and does not overlap with the orthographic projection of the hollow part on the substrate; the first side portion and the second side portion are arranged opposite to each other along the first direction.

[0167] The above-mentioned arrangement enables the fourth conductive connection portion 964 to compensate for the step difference generated by the first data line pattern 981 and the third data line pattern 983 below the fourth anode pattern 74, so that the fourth anode pattern 74 can be formed on a relatively flat surface, thereby making the fourth anode pattern 74 have a higher flatness, effectively reducing the color shift phenomenon generated by the display substrate during display.

[0168] like Figure 11 、 Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown, in some embodiments, in the fourth sub-pixel M4, the orthographic projection of the anode pattern on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate.

[0169] The orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the fourth data line pattern 984 on the substrate, and the orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the second data line pattern 982 adjacent along the first direction on the substrate.

[0170] Need to explain, such as Figure 12 As shown, the multiple sub-pixels also include: a fifth sub-pixel M5, a sixth sub-pixel M6, a seventh sub-pixel M7 and an eighth sub-pixel M8; the fifth sub-pixel M5 and the sixth sub-pixel M6 are alternately arranged along the second direction, and the seventh sub-pixel M7 and the eighth sub-pixel M8 are alternately arranged along the second direction; along the first direction, the first sub-pixel M1, the third sub-pixel M3, the fifth sub-pixel M5 and the seventh sub-pixel M7 are located in the same row; along the first direction, the second sub-pixel M2, the fourth sub-pixel M4, the sixth sub-pixel M6 and the eighth sub-pixel M8 are located in the same row.

[0171] The fifth subpixel M5 includes a fifth data line pattern 985 , the sixth subpixel M6 includes a sixth data line pattern 986 , the seventh subpixel M7 includes a seventh data line pattern 987 , and the eighth subpixel M8 includes an eighth data line pattern 988 .

[0172] like Figure 12 The eight sub-pixels from the first sub-pixel M1 to the eighth sub-pixel M8 form a repeating unit, and the display substrate includes a plurality of the repeating units.

[0173] like Figure 11 、 Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown, in some embodiments, in the fifth sub-pixel M5, the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the hollow portion 9642 on the substrate both at least partially overlap with the orthographic projection of the anode pattern on the substrate; the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the fifth data line pattern 985 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the seventh data line pattern 987 adjacent along the first direction on the substrate.

[0174] Specifically, in the fifth subpixel M5, the light-emitting element includes a fifth light-emitting element, which includes a fifth anode pattern 75, a fifth light-emitting functional layer, and a cathode sequentially stacked in a direction away from the substrate. Exemplarily, the fifth light-emitting element includes a blue light-emitting element.

[0175] Exemplarily, in the fifth sub-pixel M5, the orthographic projection of the entity portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping area; the orthographic projection of the entity portion 9641 on the substrate and the orthographic projection of the fifth anode pattern 75 on the substrate have the fifth overlapping area.

[0176] Illustratively, the orthographic projection of the first side portion of the fifth anode pattern 75 on the substrate overlaps with the orthographic projection of the fifth data line pattern 985 in the sub-pixel to which it belongs on the substrate, and overlaps with the orthographic projection of the seventh data line pattern 987 adjacent to the fifth data line pattern 985 along the first direction on the substrate; the orthographic projection of the second side portion of the fifth anode pattern 75 on the substrate overlaps with the orthographic projection of the hollow portion 9642 on the substrate; the first side portion and the second side portion are arranged opposite to each other along the first direction.

[0177] Exemplarily, the hollow portion 9642 is formed in a U-shape, and the orthographic projection of the second side of the fifth anode pattern 75 on the substrate overlaps with the orthographic projections of two sides of the hollow portion 9642 opposite to each other along the first direction on the substrate. Exemplarily, the orthographic projection of the second side of the fifth anode pattern 75 on the substrate overlaps with the orthographic projections of two sides of the hollow portion 9642 opposite to each other along the second direction on the substrate.

[0178] Exemplarily, there is a first distance L3 between the two opposite sides of the hollow portion 9642 along the first direction, and in two adjacent sub-pixels along the first direction, there is a second distance L4 between the adjacent fifth data line graphic 985 and the seventh data line graphic 987 along the first direction, and the first distance L3 is equal to the second distance L4.

[0179] The above-mentioned arrangement enables the fourth conductive connection portion 964 to compensate for the step difference between the fifth data line pattern 985 and the seventh data line pattern 987 below the fifth anode pattern 75, so that the fifth anode pattern 75 can be formed on a relatively flat surface, thereby making the fifth anode pattern 75 have a higher flatness, effectively reducing the color shift phenomenon generated by the display substrate during display.

[0180] like Figure 11 、 Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown, in some embodiments, in the sixth sub-pixel M6, the fourth conductive connection portion 964 includes a solid portion;

[0181] The orthographic projection of the solid portion on the substrate at least partially overlaps with the orthographic projection of the anode pattern on the substrate;

[0182] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the sixth data line pattern 986 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the fourth data line pattern 984 adjacent along the first direction on the substrate.

[0183] Specifically, in the sixth subpixel M6, the light-emitting element includes a sixth light-emitting element, which includes a sixth anode pattern 76, a sixth light-emitting functional layer, and a cathode stacked in sequence in a direction away from the substrate. Exemplarily, the sixth light-emitting element includes a red light-emitting element.

[0184] Exemplarily, in the sixth sub-pixel M6, the orthographic projection of the entity portion on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping area; the orthographic projection of the entity portion on the substrate and the orthographic projection of the sixth anode pattern 76 on the substrate have the fifth overlapping area.

[0185] Illustratively, an orthographic projection of a first side portion of the sixth anode pattern 76 on the substrate at least partially overlaps an orthographic projection of the sixth data line pattern 986 on the substrate, and an orthographic projection of a second side portion of the sixth anode pattern 76 on the substrate at least partially overlaps an orthographic projection of a fourth data line pattern 984 adjacent along the first direction on the substrate. The first side portion and the second side portion are disposed opposite each other along the first direction.

[0186] The above-mentioned arrangement enables the sixth data line pattern 986 and the fourth data line pattern 984 to compensate for the step difference between each other below the sixth anode pattern 76, so that the sixth anode pattern 76 can be formed on a relatively flat surface, thereby making the sixth anode pattern 76 have a higher flatness, effectively reducing the color shift phenomenon generated by the display substrate during display.

[0187] like Figure 11 、 Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown, in some embodiments, in the seventh sub-pixel M7, the fourth conductive connection portion includes a solid portion and a hollow portion;

[0188] The orthographic projection of the solid portion on the substrate at least partially overlaps with the orthographic projection of the anode pattern on the substrate, and the orthographic projection of the hollow portion on the substrate does not overlap with the orthographic projection of the anode pattern on the substrate;

[0189] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the seventh data line pattern 987 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the fifth data line pattern 985 adjacent along the first direction on the substrate.

[0190] Specifically, in the seventh subpixel M7, the light-emitting element includes a seventh light-emitting element, which includes a seventh anode pattern 77, a seventh light-emitting functional layer, and a cathode sequentially stacked in a direction away from the substrate. Exemplarily, the seventh light-emitting element includes a green light-emitting element.

[0191] Exemplarily, in the seventh sub-pixel M7, the orthographic projection of the entity portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping area; the orthographic projection of the entity portion 9641 on the substrate and the orthographic projection of the seventh anode pattern 77 on the substrate have the fifth overlapping area.

[0192] Illustratively, the orthographic projection of the second side of the seventh anode pattern 77 on the substrate at least partially overlaps with the orthographic projection of the seventh data line pattern 987 in the sub-pixel to which it belongs on the substrate; the orthographic projection of the second side of the seventh anode pattern 77 on the substrate at least partially overlaps with the orthographic projection of the fifth data line pattern 985 adjacent along the first direction on the substrate; the orthographic projection of the first side of the seventh anode pattern 77 on the substrate overlaps with the orthographic projection of the solid part on the substrate; the first side and the second side are arranged opposite to each other along the first direction.

[0193] The above-mentioned arrangement enables the fourth conductive connection portion 964 to compensate for the step difference of the seventh data line pattern 987 and the fifth data line pattern 985 below the seventh anode pattern 77, so that the seventh anode pattern 77 can be formed on a relatively flat surface, thereby making the seventh anode pattern 77 have a higher flatness, effectively reducing the color shift phenomenon generated by the display substrate during display.

[0194] like Figure 11 、 Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown, in some embodiments, in the eighth sub-pixel M8, the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642;

[0195] The orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the hollow portion 9642 on the substrate at least partially overlap with the orthographic projection of the anode pattern on the substrate;

[0196] The orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the eighth data line pattern 988 on the substrate, and does not overlap with the orthographic projection of the sixth data line pattern 986 adjacent to the first direction on the substrate.

[0197] Specifically, in the eighth subpixel M8, the light-emitting element includes an eighth light-emitting element, which includes an eighth anode pattern 78, an eighth light-emitting functional layer, and a cathode sequentially stacked in a direction away from the substrate. Exemplarily, the eighth light-emitting element includes a green light-emitting element.

[0198] Exemplarily, in part of the eighth sub-pixel M8, the orthographic projection of the entity portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping area; the orthographic projection of the entity portion 9641 on the substrate and the orthographic projection of the eighth anode pattern 78 on the substrate have the fifth overlapping area.

[0199] Illustratively, the orthographic projection of the second side of the eighth anode pattern 78 on the substrate at least partially overlaps with the orthographic projection of the seventh data line pattern 987 adjacent to it along the second direction on the substrate; the orthographic projection of the second side of the eighth anode pattern 78 on the substrate at least partially overlaps with the orthographic projection of the fifth data line pattern 985 adjacent to the seventh data line pattern 987 along the first direction on the substrate; the orthographic projection of the first side of the eighth anode pattern 78 on the substrate overlaps with the orthographic projection of the solid part on the substrate, and also overlaps with the orthographic projection of the hollow part on the substrate; the first side and the second side are arranged opposite to each other along the first direction.

[0200] The above-mentioned arrangement enables the fourth conductive connection portion 964 to compensate for the step difference generated by the seventh data line pattern 987 and the fifth data line pattern 985 below the eighth anode pattern 78, so that the eighth anode pattern 78 can be formed on a relatively flat surface, thereby making the eighth anode pattern 78 have a higher flatness, effectively reducing the color shift phenomenon generated by the display substrate during display.

[0201] It is worth noting that Figure 16 for Figure 12 Schematic diagram of the layout of the active layer in ; Figure 17 for Figure 12 Schematic diagram of the layout of the first gate metal layer; Figure 18 for Figure 12 Schematic diagram of the layout of the second gate metal layer; Figure 19 for Figure 12 The active layer, the first gate metal layer, the second gate metal layer and the first source / drain metal layer are stacked in sequence in a direction away from the substrate.

[0202] See also Figures 2 to 4 The present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels arrayed on the substrate, wherein the plurality of sub-pixels can be divided into a plurality of rows of sub-pixels arranged in sequence along the second direction, and a plurality of columns of sub-pixels arranged in sequence along the first direction, each sub-pixel comprising: a light-emitting element, an initialization signal line pattern 94, a reset signal line pattern 95, a gate line pattern 92 and a light-emitting control signal line pattern 93.

[0203] The plurality of sub-pixels include:

[0204] The first sub-pixel and the second sub-pixel are alternately arranged along the second direction, the first sub-pixel includes a first data line pattern 981, the second sub-pixel includes a second data line pattern 982, at least a portion of the first data line pattern 981 and at least a portion of the second data line pattern 982 both extend along the second direction, the first data line pattern 981 is located on a first side of the first sub-pixel in the same column extending along the second direction, the second data line pattern 982 is located on a second side of the second sub-pixel in the same column extending along the second direction, the first side and the second side are opposite to each other along the first direction, and the first direction intersects with the second direction. Exemplarily, the first side is Figure 4 The right side of the Figure 4 on the left side of the .

[0205] Both the first sub-pixel and the second sub-pixel include a sub-pixel driving circuit, which includes a driving transistor (i.e., the third transistor T3) and a data writing transistor (i.e., the fourth transistor T4). In the first sub-pixel, the first electrode of the data writing transistor is electrically connected to the first data line pattern 981, and the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor; in the second sub-pixel, the first electrode of the data writing transistor is electrically connected to the second data line pattern 982, and the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor.

[0206] According to the specific structure of the display substrate described above, in the display substrate provided by the present disclosure, in the same column of sub-pixels extending along the second direction, the first electrode of the data write transistor included in one of the adjacent sub-pixels is electrically connected to the first data line pattern 981, and the first electrode of the data write transistor included in the other of the adjacent sub-pixels is electrically connected to the second data line pattern 982. In the display substrate provided by the present disclosure, by configuring the data write transistors in adjacent sub-pixels in the same column to be electrically connected to different data line patterns, adjacent sub-pixels in the same column of sub-pixels are provided with data signals by different data line patterns, ensuring that each sub-pixel has sufficient data signal write time, thereby resolving the problem of insufficient data signal write time for each row of sub-pixels during high-frequency display.

[0207] However, in the above display substrate, since the power signal line patterns included in each sub-pixel in each row of sub-pixels are independent of each other, the display uniformity of the display substrate is poor, which is not conducive to improving the display image quality of the display substrate.

[0208] See also Figure 5、 Figure 12 、 Figure 13c and Figure 13d The present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels arrayed on the substrate, wherein the plurality of sub-pixels include:

[0209] First sub-pixels M1 and second sub-pixels M2 are alternately arranged along a second direction, the first sub-pixel M1 includes a first data line pattern 981, and the second sub-pixel M2 includes a second data line pattern 982. At least a portion of the first data line pattern 981 and at least a portion of the second data line pattern 982 both extend along the second direction. The first data line pattern 981 is located on a first side of the first sub-pixels in the same column extending along the second direction, and the second data line pattern 982 is located on a second side of the second sub-pixels in the same column extending along the second direction. The first side and the second side are opposite to each other along the first direction, and the first direction intersects the second direction.

[0210] like Figure 5 ,like Figure 8 、 Figure 10 、 Figure 12 and Figure 19 As shown, the first sub-pixel M1 and the second sub-pixel M2 each include:

[0211] a power signal line pattern 91, at least a portion of the power signal line pattern 91 extending along the second direction;

[0212] a power compensation pattern 97, at least a portion of which extends along the first direction; the power signal line pattern and the power compensation pattern are both located on a side of the first data line pattern and the second data line pattern close to the substrate; and the power compensation pattern 97 is electrically connected to the power signal line pattern 91 and the power signal line pattern 91 in an adjacent sub-pixel along the first direction.

[0213] Specifically, each sub-pixel includes the power signal line pattern 91, at least part of which extends along the second direction. In the same column of sub-pixels, the power signal line patterns 91 included in each sub-pixel are electrically connected in sequence to form an integrated structure.

[0214] The subpixel also includes a power compensation pattern 97. The power signal line pattern 91 and the power compensation pattern 97 are both located on the side of the first data line pattern 981 and the second data line pattern 982 that is closer to the substrate. Exemplarily, an interlayer insulating layer ILD is provided on the side of the first data line pattern 981 and the second data line pattern 982 that is closer to the substrate. The power compensation pattern 97 and the power signal line pattern 91 are both located on the surface of the interlayer insulating layer ILD that faces away from the substrate. This arrangement allows the power signal line pattern 91 and the power compensation pattern 97 to be located on the same layer. When the power signal line pattern 91 and the power compensation pattern 97 are made of the same material, they can be formed in the same patterning process, thereby simplifying the display substrate manufacturing process and reducing manufacturing costs.

[0215] It should be noted that the power signal line pattern 91 and the power compensation pattern 97 can form a first source-drain metal layer in the display substrate. Of course, the first source-drain metal layer can also include other structures.

[0216] like Figure 5 As shown, illustratively, the power compensation pattern 97 is electrically connected to the power signal line pattern 91 in the sub-pixel to which it belongs, and the power signal line pattern 91 ′ in the adjacent sub-pixel along the first direction.

[0217] Exemplarily, the power compensation pattern 97 and the two power signal line patterns 91 electrically connected thereto are formed into an integral structure. It is worth noting that the integral structure includes: the power compensation pattern 97 and the power signal line patterns 91 being formed of the same material and in contact with each other through a single patterning process.

[0218] In the display substrate provided by the embodiments of the present disclosure, the power compensation pattern 97 is electrically connected to the power signal line pattern 91 in the sub-pixel to which it belongs, as well as to the power signal line pattern 91' in the adjacent sub-pixel located in the same row as the sub-pixel along the first direction. This allows the power signal line patterns 91 included in each sub-pixel in the same row to be electrically connected, thereby reducing the overall resistance of the power signal line patterns 91, thereby further improving the display uniformity of the display substrate. Furthermore, by sequentially electrically connecting the power signal line patterns 91 in each sub-pixel in the same column, all the power signal line patterns 91 included in the display substrate form a mesh structure, further improving the display uniformity of the display substrate.

[0219] In the display substrate provided by the embodiments of the present disclosure, the power compensation pattern 97 and the power signal line pattern 91 are both located on the surface of the interlayer insulating layer ILD of the display substrate facing away from the base, and the power signal line pattern 91 and the power compensation pattern 97 are formed as the first source-drain metal layer of the display substrate. This allows the power signal line pattern 91 and the power compensation pattern 97 to be formed in the same patterning process, thereby further simplifying the display substrate manufacturing process and saving manufacturing costs. Furthermore, because the power compensation pattern 97 and the power signal line pattern 91 are made of the same source-drain metal material, the resistance of the power compensation pattern 97 and the power signal line pattern 91 is relatively low, thereby further improving the display uniformity of the display substrate.

[0220] In the display substrate provided by the embodiment of the present disclosure, all the power signal line patterns 91 are formed into a mesh structure, which effectively improves the stability of the power signal transmitted by the power signal line pattern. The power signal is used to provide the source of the driving transistor in the sub-pixel driving circuit, and the luminous current I generated by the sub-pixel driving circuit is oled =k[(Vgs-Vth)] 2 , Vgs=Vg-Vs, Vg is the gate voltage of the driving transistor, Vs is the source voltage of the driving transistor, and Vth is the threshold voltage of the driving transistor. Therefore, the power signal as Vs will affect the light-emitting current I oled Therefore, the above setting method improves the stability of the power signal line layer while better ensuring the light-emitting current I oled stability, effectively avoiding the occurrence of dynamic crosstalk.

[0221] like Figure 5 ,like Figure 8 、 Figure 10 、 Figure 12 and Figure 19 As shown, further, the third sub-pixel M3 and the fourth sub-pixel M4 both include: the power signal line pattern and the power compensation pattern; the power compensation pattern included in the third sub-pixel M3 is electrically connected to the power signal line pattern included in the third sub-pixel M3 and the power signal line pattern in the first sub-pixel M1 adjacent along the first direction; the power compensation pattern included in the fourth sub-pixel M4 is electrically connected to the power signal line pattern included in the fourth sub-pixel M4 and the power signal line pattern in the second sub-pixel M2 adjacent along the first direction.

[0222] Specifically, the third sub-pixel M3 and the fourth sub-pixel M4 both include: the power signal line pattern and the power compensation pattern, the structure of the power signal line pattern is the same as the structure of the power signal line pattern in the first sub-pixel M1 and the second sub-pixel M2, and the structure of the power compensation pattern is the same as the structure of the power compensation pattern in the first sub-pixel M1 and the second sub-pixel M2.

[0223] like Figure 5 and Figure 8 As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include: a reset signal line pattern 95, a gate line pattern 92, and a light-emitting control signal line pattern 93 distributed along the second direction; at least a portion of the reset signal line pattern 95 extends along the first direction, at least a portion of the gate line pattern 92 extends along the first direction, and at least a portion of the light-emitting control signal line pattern 93 extends along the first direction;

[0224] In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4, the orthographic projection of the power compensation pattern 97 on the substrate is located between the orthographic projection of the gate line pattern 92 on the substrate and the orthographic projection of the light-emitting control signal line pattern 93 on the substrate.

[0225] Specifically, the sub-pixel further includes: a reset signal line pattern 95, a gate line pattern 92, and a light-emission control signal line pattern 93 sequentially distributed along the second direction. The reset signal line is used to transmit a reset signal, the gate line pattern 92 is used to transmit a scan signal, and the light-emission control signal line pattern 93 is used to transmit a light-emission control signal.

[0226] At least a portion of the reset signal line pattern 95 extends along the first direction, and the reset signal line patterns 95 included in each sub-pixel located in the same row along the first direction are electrically connected in sequence to form an integrated structure. At least a portion of the gate line pattern 92 extends along the first direction, and the gate line patterns 92 included in each sub-pixel located in the same row along the first direction are electrically connected in sequence to form an integrated structure. At least a portion of the light-emitting control signal line pattern 93 extends along the first direction, and the light-emitting control signal line patterns 93 included in each sub-pixel located in the same row along the first direction are electrically connected in sequence to form an integrated structure.

[0227] The specific layout positions of the power compensation pattern 97 are varied. For example, in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4, the orthographic projection of the power compensation pattern 97 on the substrate does not overlap with the orthographic projection of the reset signal line pattern 95 on the substrate, the orthographic projection of the power compensation pattern 97 on the substrate does not overlap with the orthographic projection of the gate line pattern 92 on the substrate, and the orthographic projection of the power compensation pattern 97 on the substrate does not overlap with the orthographic projection of the light-emitting control signal line pattern 93 on the substrate.

[0228] Illustratively, the orthographic projection of the power compensation pattern 97 on the substrate is located between the orthographic projection of the gate line pattern 92 on the substrate and the orthographic projection of the light emitting control signal line pattern 93 on the substrate.

[0229] Exemplarily, along the second direction, the minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the gate line pattern 92 on the substrate is greater than the minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the light-emitting control signal line pattern 93 on the substrate.

[0230] The power compensation pattern 97 is arranged in the above manner so that there is a long distance between the power compensation pattern 97 and the reset signal line pattern 95, the gate line pattern 92 and the light-emitting control signal line pattern 93, thereby avoiding increasing the load of the reset signal line pattern 95, the gate line pattern 92 and the light-emitting control signal line pattern 93.

[0231] In some embodiments, the minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the gate line pattern 92 on the substrate is greater than a threshold; the minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the light-emitting control signal line pattern 93 on the substrate is greater than the threshold.

[0232] Exemplarily, the threshold is 5 μm. The minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the gate line pattern 92 on the substrate is greater than 5 μm; the minimum distance between the orthographic projection of the second power compensation pattern 97 on the substrate and the orthographic projection of the light-emitting control signal line pattern 93 on the substrate is greater than 5 μm.

[0233] The above-mentioned setting method makes the power compensation pattern 97 have a long distance from the reset signal line pattern 95, the gate line pattern 92 and the light-emitting control signal line pattern 93, thereby avoiding increasing the load of the reset signal line pattern 95, the gate line pattern 92 and the light-emitting control signal line pattern 93.

[0234] like Figure 5 、 Figure 8 、 Figure 10 、 Figure 12 and Figure 19 As shown, in some embodiments, in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the power signal line pattern 91 in each sub-pixel includes: a power main portion (including a first portion 911 and a second portion 912) and a power protruding portion 913 that are electrically connected to each other;

[0235] The first end of the power compensation pattern 97 is electrically connected to the power protrusion 913; the second end of the power compensation pattern 97 is electrically connected to the power main body portion (ie, Figure 8 The power signal line pattern 91' in the power main body is electrically connected.

[0236] Illustratively, at least a portion of the power protrusion 913 extends along the second direction, and the second end of the power compensation pattern 97 is electrically connected to a middle portion of the power protrusion 913 .

[0237] The above configuration can shorten the length of the power compensation pattern 97 , thereby effectively reducing the layout difficulty of the power compensation pattern 97 .

[0238] like Figure 5 、 Figure 8 、 Figure 10 、 Figure 12 and Figure 19 As shown, in some embodiments, at least a portion of the power source protrusion 913 extends along the second direction, and a gap 50 is defined between the power source protrusion 913 and the power source main body.

[0239] In more detail, the power protrusion 913 includes a third part 9130, a fourth part 9131 and a fifth part 9132; the third part 9130 is electrically connected to the power compensation pattern 97, and the third part 9130 extends along the second direction; the fourth part 9131 is electrically connected to one end of the third part 9130 and the power main part respectively; the fifth part 9132 is electrically connected to the other end of the third part 9130 and the power main part respectively; there is a gap 50 between the third part 9130 and the power main part.

[0240] Specifically, the specific structure of the power source protruding portion 913 is varied. Exemplarily, the power source protruding portion 913 includes the third portion 9130 , the fourth portion 9131 and the fifth portion 9132 of an integrated structure.

[0241] The fourth part 9131 is electrically connected to one end of the third part 9130 and the main power part respectively; the fifth part 9132 is electrically connected to the other end of the third part 9130 and the main power part respectively, thereby better ensuring the connection performance between the power protruding part 913 and the main power part, and more effectively improving the display uniformity of the display substrate.

[0242] In addition, the display substrate may further include a fingerprint recognition module. Exemplarily, the fingerprint recognition module is located on the side of the substrate facing away from the sub-pixel drive circuit. Exemplarily, the orthographic projection of the fingerprint recognition area of ​​the fingerprint recognition module on the substrate overlaps with the orthographic projection of the gap 50 on the substrate. During fingerprint recognition, a finger touches the side of the light-emitting element facing away from the substrate. Light reflected by the finger can pass through the gap 50 and be received by the fingerprint recognition module, thereby realizing the fingerprint recognition function.

[0243] The above-mentioned arrangement of a gap 50 between the third portion 9130 and the main power supply portion better improves the light transmittance of the display substrate. Therefore, when the display substrate provided by the above embodiment is compatible with optical fingerprint recognition technology, it can provide good conditions for the sensor to collect light signals, thereby effectively improving the speed and accuracy of fingerprint recognition.

[0244] In addition, in the display substrate provided by the above embodiment, a gap 50 is formed only on the power signal line pattern 91, and no operations such as narrowing the width of the metal routing lines other than the power signal line pattern 91, compressing the size of the light-emitting elements, compressing the size of the transistors or capacitors, etc. are performed. Therefore, the display substrate provided by the above embodiment is not likely to have a negative impact on the performance of the display substrate while improving the resolution.

[0245] like Figure 5 and Figure 9 As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 all include: a storage capacitor Cst and a driving transistor, and in each sub-pixel, the first plate Cst1 of the storage capacitor Cst is electrically connected to the gate of the driving transistor, and the second plate Cst2 of the storage capacitor Cst is electrically connected to the power protrusion 913.

[0246] Illustratively, the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate overlaps with the orthographic projection of the power supply protrusion 913 on the substrate, and the second plate Cst2 of the storage capacitor Cst is electrically connected to the power supply protrusion at the overlap.

[0247] Exemplarily, the third portion 9130 includes a first sub-portion 9130a and a second sub-portion 9130b, wherein the first sub-portion 9130a is close to the fourth portion 9131, and the second sub-portion 9130b is close to the fifth portion 9132. In a plane parallel to the substrate and in a direction perpendicular to the second direction, a width L1 of the first sub-portion 9130a is greater than a width L2 of the second sub-portion 9130b.

[0248] The orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate overlaps with the orthographic projection of the first sub-part 9130a on the substrate, and the second plate Cst2 of the storage capacitor Cst is electrically connected to the first sub-part 9130a through a via provided at the overlapping position.

[0249] The above arrangement enables the second plate Cst2 of the storage capacitor Cst to form a larger overlapping area with the first sub-portion 9130a, thereby being more conducive to reducing the layout difficulty of the via. Figure 13a The mark 40 in the figure represents a substrate and some film layers (such as a buffer layer, an isolation layer, etc.) arranged on the substrate.

[0250] like Figure 5 and Figure 9 As shown, in some embodiments, in a direction perpendicular to the first direction, the first end D of the power compensation pattern 97 is set to have a first width, and along the direction close to the power signal line pattern in the sub-pixel to which the first sub-pattern belongs (i.e. Figure 9 The first width gradually increases.

[0251] The above arrangement not only improves the connection performance between the power compensation pattern 97 and the power signal line pattern 91 , but also avoids the formation of a right-angle structure at the connection between the power compensation pattern 97 and the power signal line pattern 91 , which would lead to static electricity risks.

[0252] like Figure 5 、 Figure 8 、 Figure 10 and Figure 12As shown, in some embodiments, in the first sub-pixel M1, the orthographic projection of the power protrusion 913 on the substrate overlaps with the orthographic projection of the first data line pattern 981 on the substrate, and the orthographic projection of the power main body portion (including the first portion 911 and the second portion 912) on the substrate at least partially overlaps with the orthographic projection of the data line pattern adjacent along the first direction (such as the third data line pattern 983) on the substrate.

[0253] Specifically, in the display substrate, each subpixel includes a power signal line pattern 91, at least a portion of which extends along the second direction. Within a column of subpixels, the power signal line patterns 91 included in each subpixel are electrically connected in sequence, forming an integrated structure. The specific structure of the power signal line pattern 91 varies. Exemplarily, the power signal line pattern 91 includes an electrically connected first portion 911 and a second portion 912, with the first portion 911 and the second portion 912 alternating. Exemplarily, the second portion 912 protrudes beyond the first portion 911 along the first direction.

[0254] Exemplarily, in the first sub-pixel M1, the orthographic projection of the first portion 911 on the substrate overlaps with the orthographic projection of the data line main portion 9801 of the third data line graphic 983 adjacent along the first direction on the substrate, and the orthographic projection of the second portion 912 on the substrate does not overlap with the orthographic projection of the data line main portion 9801 of the third data line graphic 983 on the substrate.

[0255] Exemplarily, at least a portion of the first portion 911 extends along the second direction, and at least a portion of the second portion 912 extends along the second direction. In a direction perpendicular to the second direction, the width of the first portion 911 is equal to the width of the second portion 912, or the width of the first portion 911 is greater than the width of the second portion 912, or the width of the first portion 911 is less than the width of the second portion 912.

[0256] In the display substrate provided by the above embodiment, the overlapping area between the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, as well as the orthographic projection of the data line pattern adjacent to the first data line pattern 981 along the first direction on the substrate and the overlapping area between the orthographic projection of the functional pattern with a fixed potential on the substrate are close to each other, thereby effectively reducing the load difference between the first data line pattern 981 and the data line pattern adjacent along the first direction.

[0257] It should be noted that the functional graphics with fixed units include: a power signal line graphic 91, an initialization signal line graphic 94, and a conductive functional graphic electrically connected to the power signal line graphic 91 or the initialization signal line graphic 94 (such as: a second conductive connection part 962), etc.

[0258] like Figure 12 As shown, in some embodiments, in the second sub-pixel M2, the orthographic projection of the power protrusion 913 on the substrate does not overlap with the orthographic projection of the second data line pattern 982 on the substrate.

[0259] Exemplarily, in the second sub-pixel M2 , an orthographic projection of the power source protrusion 913 on the substrate overlaps with an orthographic projection of an extended portion of the first data line 981 adjacent to the second direction on the substrate.

[0260] like Figure 12 As shown, in some embodiments, in the third sub-pixel M3, the orthographic projection of the power protrusion 913 on the substrate does not overlap with the orthographic projection of the third data line pattern 983 on the substrate.

[0261] Exemplarily, in the third sub-pixel M3, the orthographic projection of the power protrusion 913 on the substrate overlaps with the orthographic projection of the extended portion of the fourth data line 984 adjacent to the fourth data line 984 along the second direction on the substrate.

[0262] like Figure 12 As shown, in some embodiments, in the fourth sub-pixel M4, the orthographic projection of the power protrusion 913 on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate, and the orthographic projection of the power main body on the substrate overlaps with the orthographic projection of the data line pattern adjacent along the first direction (such as the second data line pattern 982) on the substrate.

[0263] Exemplarily, in the fourth sub-pixel M4, the power source main portion includes a first portion 911 and a second portion 912, the orthographic projection of the first portion 911 on the substrate overlaps with the orthographic projection of the data line main portion 9801 of the sixth data line graphic 986 adjacent along the first direction on the substrate, and the orthographic projection of the second portion 912 on the substrate does not overlap with the orthographic projection of the data line main portion 9801 of the sixth data line graphic 986 on the substrate.

[0264] In the display substrate provided by the above embodiment, the overlapping area between the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate is close to the overlapping area between the orthographic projection of the sixth data line pattern 986 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, thereby effectively reducing the load difference between the fourth data line pattern 984 and the sixth data line pattern 986. It is worth noting that Figure 12 It is also shown in FIG. 1 that the fifth sub-pixel M5 further includes a fifth data line pattern 985 , the seventh sub-pixel M7 further includes a seventh data line pattern 987 , and the eighth sub-pixel further includes an eighth data line pattern 988 .

[0265] In the display substrate provided by the above embodiment, the overlapping area between the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, as well as the orthographic projection of the data line pattern adjacent to the fourth data line pattern 984 along the first direction on the substrate and the overlapping area between the orthographic projection of the functional pattern with a fixed potential on the substrate are close to each other, thereby effectively reducing the load difference between the fourth data line pattern 984 and the data line pattern adjacent along the first direction.

[0266] like Figure 10 and Figure 11 As shown, in some embodiments, the first data line pattern 981, the second data line pattern 982, the third data line pattern 983, and the fourth data line pattern 984 each include a data line main portion 9801 and a data line protrusion 9802, wherein the data line main portion 9801 extends along the second direction, and the data line protrusion 9802 protrudes from the data line main portion 9801 along the first direction;

[0267] The first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 all include a first conductive connection portion 961 and a data write transistor. In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4, the data line protrusion 9802 is electrically connected to the first electrode of the data write transistor through the first conductive connection portion 961.

[0268] Illustratively, at least a portion of the first conductive connection portion 961 extends along the second direction. The orthographic projection of the first end of the first conductive connection portion 961 on the substrate has a first overlapping region with the orthographic projection of the data line protrusion 9802 on the substrate. The first end of the first conductive connection portion 961 and the data line protrusion 9802 are electrically connected via a via provided in the first overlapping region. The orthographic projection of the second end of the first conductive connection portion 961 on the substrate has a second overlapping region with the orthographic projection of the first electrode of the data write transistor on the substrate. The second end of the first conductive connection portion 961 and the first electrode of the data write transistor are electrically connected via a via provided in the second overlapping region. The first electrode of the data write transistor receives a data signal provided by the corresponding data line pattern through the first conductive connection portion 961.

[0269] Illustratively, the orthographic projection of the second portion 912 of the power signal line pattern 91 on the substrate and the first overlapping area are arranged along the first direction.

[0270] Along the first direction, the distance between the first conductive connection portion 961 and the power signal line pattern 91 is relatively far. By arranging the orthographic projection of the second portion 912 of the power signal line pattern 91 on the substrate and the first overlapping area along the first direction, the second portion 912 has sufficient layout space, thereby better reducing the layout difficulty of the display substrate while ensuring that the second portion 912 has a larger area.

[0271] like Figure 5 、 Figure 10 and Figure 12 As shown, in some embodiments, the first sub-pixel M1 and the second sub-pixel M2 both include: an initialization signal line pattern 94, a second transistor T2 and a second conductive connection portion 962;

[0272] At least a portion of the initialization signal line pattern 94 extends along the second direction, and the initialization signal line pattern 94 is used to transmit an initialization signal;

[0273] The first electrode of the second transistor T2 is electrically connected to the initialization signal line pattern 94 through the second conductive connection portion 962, and the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor; in the first sub-pixel M1, the orthographic projection of the second conductive connection portion 962 on the substrate overlaps with the orthographic projection of the first data line pattern 981 on the substrate; in the second sub-pixel M2, the orthographic projection of the second conductive connection portion 962 on the substrate does not overlap with the orthographic projection of the second data line pattern 982 on the substrate.

[0274] like Figure 12 As shown, further, the third sub-pixel M3 and the fourth sub-pixel M4 each include: an initialization signal line pattern 94, a second transistor T2 and a second conductive connection portion 962;

[0275] At least a portion of the initialization signal line pattern 94 extends along the second direction, and the initialization signal line pattern 94 is used to transmit an initialization signal;

[0276] The first electrode of the second transistor T2 is electrically connected to the initialization signal line pattern 94 through the second conductive connection portion 962, and the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor;

[0277] In the third sub-pixel M3, an orthographic projection of the second conductive connection portion 962 on the substrate does not overlap with an orthographic projection of the third data line pattern 983 on the substrate;

[0278] In the fourth sub-pixel M4, an orthographic projection of the second conductive connection portion 962 on the substrate overlaps with an orthographic projection of the fourth data line pattern 984 on the substrate.

[0279] Specifically, the first subpixel M1, the second subpixel M2, the third subpixel M3, and the fourth subpixel M4 each include the initialization signal line pattern 94, the second transistor T2, and the second conductive connection portion 962. Exemplarily, the orthographic projection of the first electrode of the second transistor T2 on the substrate overlaps with the orthographic projection of the first end of the second conductive connection portion 962 on the substrate, and the first electrode of the second transistor T2 and the first end of the second conductive connection portion 962 are electrically connected via a via located at the overlap. The orthographic projection of the second end of the second conductive connection portion 962 on the substrate overlaps with the orthographic projection of the initialization signal line pattern 94 on the substrate, and the second end of the second conductive connection portion 962 and the initialization signal line pattern 94 are electrically connected via a via located at the overlap.

[0280] The second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor. During a reset period, the second transistor T2 can transmit the received initialization signal to the gate of the driving transistor to reset the gate of the driving transistor.

[0281] Because the second conductive connection portion 962 is electrically connected to the initialization signal line pattern 94, the initialization signal line pattern 94 has a stable potential. In the above arrangement, in the first subpixel M1, the orthographic projection of the second conductive connection portion 962 on the substrate overlaps with the orthographic projection of the first data line pattern 981 on the substrate. This makes the overlapping area between the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate closer to the overlapping area between the orthographic projection of the third data line pattern on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, thereby further reducing the load difference between the first data line pattern 981 and the third data line pattern.

[0282] In the fourth sub-pixel M4 as described above, the orthographic projection of the second conductive connection portion 962 on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate, so that the overlapping area between the orthographic projection of the second data line pattern 982 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate and the overlapping area between the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate are closer, thereby further reducing the load difference between the second data line pattern 982 and the fourth data line pattern 984.

[0283] In some embodiments, the overlapping area formed by the orthographic projection of the third data line pattern on the substrate and the orthographic projection of the first portion 911 on the substrate has a first area; the overlapping area formed by the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the power supply protrusion 913 on the substrate has a second area; the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the second conductive connection portion 962 in the display substrate on the substrate have a third area; the sum of the second area and the third area is substantially the same as the first area. The above setting of the sum of the second area and the third area being substantially the same as the first area ensures that the load of the first data line pattern 981 and the load of the third data line pattern are substantially the same, thereby further improving the display uniformity of the display substrate.

[0284] In some embodiments, the overlapping area formed by the orthographic projection of the second data line pattern on the substrate and the orthographic projection of the first portion 911 on the substrate has a first area; the overlapping area formed by the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the power supply protrusion 913 on the substrate has a second area; the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the second conductive connection portion 962 in the display substrate on the substrate have a third area; the sum of the second area and the third area is substantially the same as the first area. The above setting of the sum of the second area and the third area being substantially the same as the first area ensures that the load of the second data line pattern 982 and the load of the fourth data line pattern 984 are substantially the same, thereby further improving the display uniformity of the display substrate.

[0285] like Figure 5 、 Figure 8 、 Figure 9 、 Figure 12 and Figure 19 As shown, in some embodiments, the power source protrusion 913 includes a third portion 9130, a fourth portion 9131, and a fifth portion 9132. The third portion 9130 extends along the second direction. In the first sub-pixel M1, the orthographic projection of the third portion 9130 on the substrate overlaps with the orthographic projection of the first data line pattern 981 on the substrate. In the fourth sub-pixel M4, the orthographic projection of the third portion 9130 on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate.

[0286] In the first sub-pixel M1, by setting the length of the third portion 9130 along the second direction, the area of ​​overlap between the first data line pattern 981 and the third portion 9130 can be controlled, thereby adjusting the load of the first data line pattern 981. In the third sub-pixel M3, by setting the length of the third portion 9130 along the second direction, the area of ​​overlap between the fourth data line pattern 984 and the third portion 9130 can be controlled, thereby adjusting the load of the fourth data line pattern 984.

[0287] like Figure 5 、 Figure 12 and Figure 13aAs shown, in some embodiments, the display substrate further includes an interlayer insulating layer ILD and a first flat layer PLN1 stacked in sequence in a direction away from the base; the first data line graphic 981, the second data line graphic 982, the third data line graphic 983 and the fourth data line graphic 984 are all located on the surface of the first flat layer PLN1 facing away from the base; the power signal line graphic 91 and the power compensation graphic 97 are both located on the surface of the interlayer insulating layer ILD facing away from the base.

[0288] Specifically, the above-mentioned first data line graphic 981, the second data line graphic 982, the third data line graphic 983 and the fourth data line graphic 984 are all located on the surface of the first flat layer PLN1 facing away from the substrate, so that the first data line graphic 981, the second data line graphic 982, the third data line graphic 983 and the fourth data line graphic 984 are all arranged in the same layer. When the first data line graphic 981, the second data line graphic 982, the third data line graphic 983 and the fourth data line graphic 984 are made of the same material, the first data line graphic 981, the second data line graphic 982, the third data line graphic 983 and the fourth data line graphic 984 can be formed in the same patterning process, thereby better simplifying the production process of the display substrate and saving production costs.

[0289] It should be noted that the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 can form a second source-drain metal layer in the display substrate. It is worth noting that the second source-drain metal layer can also include other structures.

[0290] like Figure 5 、 Figure 7 and Figure 18 As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 each include: an anode pattern, an initialization signal line pattern 94, a shielding pattern 80, a driving transistor, and a second transistor T2;

[0291] In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the first electrode of the second transistor T2 is electrically connected to the initialization signal line pattern 94, and the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor;

[0292] The shielding pattern 80 is electrically connected to the power signal line pattern 91 , and an orthographic projection of the shielding pattern 80 on the substrate at least partially overlaps with an orthographic projection of the first electrode of the second transistor T2 on the substrate.

[0293] Specifically, each of the sub-pixels further includes: an anode pattern, an initialization signal line pattern 94, a shielding pattern 80, a driving transistor, a second transistor T2, and a seventh transistor T7; the gate of the second transistor T2 is electrically connected to the reset signal line pattern 95, the first electrode of the second transistor T2 is electrically connected to the initialization signal line pattern 94, the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor, and the second transistor T2 is used to reset the gate of the driving transistor.

[0294] A gate electrode of the seventh transistor T7 is electrically connected to a reset signal line pattern 95' included in a next sub-pixel adjacent to the sub-pixel to which it belongs along the second direction. A first electrode of the seventh transistor T7 is electrically connected to an initialization signal line pattern 94' in a next sub-pixel adjacent to the sub-pixel along the second direction. A second electrode of the seventh transistor T7 is electrically connected to an anode pattern in the sub-pixel. The seventh transistor T7 is used to reset the anode pattern.

[0295] Each sub-pixel further includes a shielding pattern 80, wherein an orthographic projection of the shielding pattern 80 on the substrate overlaps an orthographic projection of the power signal line pattern 91 on the substrate, and the shielding pattern 80 and the power signal line pattern 91 are electrically connected via a via provided at the overlapping location. Exemplarily, the orthographic projection of the shielding pattern 80 on the substrate overlaps an orthographic projection of a second portion 912 of the power signal line pattern 91 on the substrate, and the shielding pattern 80 and the second portion 912 of the power signal line pattern 91 are directly electrically connected via the via provided at the overlapping location.

[0296] The shielding pattern 80 is electrically connected to the power signal line pattern 91 so that the shielding pattern 80 has a stable potential, which not only helps the sub-pixel driving circuit to be in a stable working state, but also better ensures the shielding effect of the shielding pattern 80.

[0297] By setting the orthographic projection of the shielding pattern 80 on the substrate to overlap with the orthographic projection of the first electrode of the second transistor T2 on the substrate, and / or the orthographic projection of the shielding pattern 80 on the substrate to overlap with the orthographic projection of the first electrode of the seventh transistor T7 in the adjacent sub-pixel along the second direction on the substrate, the shielding pattern 80 shields the influence of the data signal jump on the first electrode of the second transistor T2 and / or the first electrode of the seventh transistor T7, thereby avoiding the influence on the initialization signal transmitted on the initialization signal line pattern 94.

[0298] like Figure 5 、 Figure 7 and Figure 18 As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 each include: a first conductive connection portion, a fifth conductive connection portion 965 and a data writing transistor;

[0299] In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4, the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor through the fifth conductive connection portion 965;

[0300] The first conductive connection portion 961 is electrically connected to the first electrode of the data writing transistor; the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor;

[0301] The orthographic projection of the shielding pattern 80 on the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion 961 on the substrate.

[0302] Specifically, in each sub-pixel, at least a portion of the fifth conductive connection portion 965 extends along the second direction. An orthographic projection of one end of the fifth conductive connection portion 965 on the substrate and an orthographic projection of the second electrode of the second transistor T2 on the substrate have a sixth overlapping region. One end of the fifth conductive connection portion 965 is electrically connected to the second electrode of the second transistor T2 via a via provided in the sixth overlapping region. An orthographic projection of the other end of the fifth conductive connection portion 965 on the substrate overlaps with an orthographic projection of the gate electrode of the driving transistor on the substrate. The other end of the fifth conductive connection portion 965 is electrically connected to the gate electrode of the driving transistor via a via provided at the overlapping region.

[0303] Each sub-pixel further includes a first conductive connection portion 961. Exemplarily, at least a portion of the first conductive connection portion 961 extends along the second direction. The orthographic projection of a first end of the first conductive connection portion 961 on the substrate overlaps with the orthographic projection of the corresponding data line protrusion 9802 on the substrate. The first end of the first conductive connection portion 961 is electrically connected to the data line protrusion 9802 via a via provided in the first overlapping region. The orthographic projection of a second end of the first conductive connection portion 961 on the substrate overlaps with the orthographic projection of the first electrode of the data write transistor on the substrate. The second end of the first conductive connection portion 961 is electrically connected to the first electrode of the data write transistor via a via provided in the second overlapping region. The first electrode of the data write transistor receives a data signal provided by the corresponding data line pattern through the first conductive connection portion 961.

[0304] Exemplarily, the shielding pattern 80 includes a first shielding portion 801 and a second shielding portion 802 that are electrically connected, the orthographic projection of the first shielding portion 801 on the substrate overlaps with the orthographic projection of the power signal line pattern 91 on the substrate, and the first shielding portion 801 and the power signal line pattern 91 are directly electrically connected through a via provided at the overlapping portion.

[0305] Exemplarily, the first shielding portion 801 and the second shielding portion 802 form an integrated structure.

[0306] Exemplarily, the first shielding portion 801 is a square structure extending along the first direction, and the orthographic projection of the first shielding portion 801 on the substrate overlaps with the orthographic projection of the first electrode of the second transistor T2 on the substrate, and / or the orthographic projection of the first shielding portion 801 on the substrate overlaps with the orthographic projection of the first electrode of the seventh transistor T7 in the adjacent sub-pixel along the second direction on the substrate.

[0307] Exemplarily, the orthographic projection of the first shielding portion 801 on the substrate does not overlap with the orthographic projection of the reset signal line pattern 95 on the substrate.

[0308] Illustratively, an orthographic projection of the first shielding portion 801 in the shielding pattern 80 on the substrate at least partially overlaps with an orthographic projection of the first conductive connecting portion 961 on the substrate.

[0309] like Figure 5 As shown, in some embodiments, the orthographic projection of at least part of the shielding pattern 80 on the substrate is located between the orthographic projection of the first conductive connection portion 961 on the substrate and the orthographic projection of the fifth conductive connection portion 965 on the substrate.

[0310] For example, Figure 13b As shown, the orthographic projection of the second shielding portion 802 in the shielding pattern 80 on the substrate is located between the second overlapping area and the sixth overlapping area.

[0311] Exemplarily, the second shielding portion 802 is a square structure extending along the second direction.

[0312] This arrangement enables the second shielding portion 802 to better shield the second electrode of the second transistor T2 from changes in the data signal, thereby preventing changes in the data signal from affecting the gate signal of the driving transistor. Since the gate signal of the driving transistor directly affects the brightness of the sub-pixel, this arrangement further stabilizes the gate potential of the driving transistor, thereby enabling the display substrate to achieve better display effects when used for display.

[0313] like Figure 5 、 Figure 7 and Figure 18 As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 each include: a first transistor T1;

[0314] In each sub-pixel, the first electrode of the first transistor T1 is electrically connected to the second electrode of the driving transistor, and the second electrode of the first transistor T1 is electrically connected to the gate of the driving transistor;

[0315] The active pattern of the first transistor T1 includes two semiconductor parts spaced apart from each other, and a first conductor part respectively connecting the two semiconductor parts;

[0316] The projection of the shielding pattern 80 on the substrate also at least partially overlaps with the orthographic projection of the first conductor portion on the substrate.

[0317] Specifically, each sub-pixel further includes a first transistor T1, the gate of the first transistor T1 is electrically connected to the gate line pattern 92, the first electrode of the first transistor T1 is electrically connected to the second electrode of the driving transistor, and the second electrode of the first transistor T1 is electrically connected to the gate of the driving transistor.

[0318] The first transistor T1 is formed into a dual-gate structure. The active pattern of the first transistor T1 includes two semiconductor portions spaced apart and first conductor portions respectively connecting the two semiconductor portions. The orthographic projection of the gate of the first transistor T1 on the substrate covers the orthographic projections of the two semiconductor portions on the substrate. The orthographic projection of the gate of the first transistor T1 on the substrate does not overlap with the orthographic projection of the first conductor portion on the substrate.

[0319] Exemplarily, the shielding pattern 80 further includes a third shielding portion 803 electrically connected to the first shielding portion 801 , and at least a portion of the third shielding portion 803 is a square structure extending along the second direction.

[0320] Exemplarily, the first shielding portion 801 and the third shielding portion 803 form an integrated structure.

[0321] Exemplarily, the shielding pattern 80 further includes a third shielding portion 803 electrically connected to the first shielding portion 801 , and an orthographic projection of the third shielding portion 803 on the substrate overlaps with an orthographic projection of the first conductor portion on the substrate.

[0322] The orthographic projection of the third shielding portion 803 on the substrate overlaps with the orthographic projection of the first conductor portion on the substrate. This arrangement enables the third shielding pattern 80 to shield the first conductor portion, preventing changes in the data signal from affecting the first transistor T1, and further preventing changes in the data signal from affecting the gate signal of the driving transistor.

[0323] In some embodiments, along a direction perpendicular to the substrate, the shielding pattern 80 is located between the first electrode of the second transistor T2 and the first conductive connection portion 961 .

[0324] Exemplarily, the display substrate further includes a second gate insulating layer located between the first electrode of the second transistor T2 and the first conductive connection portion 961. In each sub-pixel, the initialization signal line pattern 94 and the shielding pattern 80 are both located on the surface of the second gate insulating layer facing away from the substrate.

[0325] In the above-mentioned arrangement, the initialization signal line pattern 94 and the shielding pattern 80 are both located on the surface of the second gate insulating layer facing away from the substrate, so that the initialization signal line pattern 94 and the shielding pattern 80 are arranged on the same layer. When the initialization signal line pattern 94 and the shielding pattern 80 are made of the same material, the initialization signal line pattern 94 and the shielding pattern 80 can be formed in the same patterning process, thereby better simplifying the production process of the display substrate and saving production costs.

[0326] like Figure 2 、 Figure 5 and Figure 12As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include: a light-emitting element, an initialization signal line pattern 94, a reset signal line pattern 95, a gate line pattern 92, a light-emitting control signal line pattern 93, and a power signal line pattern 91; at least a portion of the initialization signal line pattern 94, at least a portion of the reset signal line pattern 95, at least a portion of the gate line pattern 92, and at least a portion of the light-emitting control signal line pattern 93 all extend along the first direction; at least a portion of the power signal line pattern 91 extends along the second direction;

[0327] The first subpixel M1, the second subpixel M2, the third subpixel M3 and the fourth subpixel M4 further include: a first transistor T1, a second transistor T2, a driving transistor (such as a third transistor), a data writing transistor (such as a fourth transistor), a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst;

[0328] In each sub-pixel, the gate of the driving transistor is electrically connected to the second electrode of the first transistor T1, the first electrode of the driving transistor is electrically connected to the second electrode of the fifth transistor T5, and the second electrode of the driving transistor is electrically connected to the first electrode of the first transistor T1;

[0329] The gate of the first transistor T1 is electrically connected to the gate line pattern 92;

[0330] The gate of the second transistor T2 is electrically connected to the reset signal line pattern 95, the first electrode of the second transistor T2 is electrically connected to the initialization signal line pattern 94, and the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor;

[0331] The gate of the data writing transistor is electrically connected to the gate line pattern 92, the first electrode of the data writing transistor is electrically connected to the data line pattern included in the sub-pixel, and the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor;

[0332] The gate of the fifth transistor T5 is electrically connected to the light emitting control signal line pattern 93, and the first electrode of the fifth transistor T5 is electrically connected to the power signal line pattern 91;

[0333] The gate of the sixth transistor T6 is electrically connected to the light emitting control signal line pattern 93, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor T6 is electrically connected to the light emitting element;

[0334] The gate of the seventh transistor T7 is electrically connected to the reset signal line pattern 95 in the next sub-pixel adjacent along the second direction, the first electrode of the seventh transistor T7 is electrically connected to the initialization signal line pattern 94 in the next sub-pixel adjacent along the second direction, and the second electrode of the seventh transistor T7 is electrically connected to the light-emitting element;

[0335] The first plate of the storage capacitor is multiplexed as the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the power signal line pattern 91 .

[0336] Exemplarily, each sub-pixel in the display substrate includes a sub-pixel driving circuit, and each sub-pixel driving circuit includes: a first transistor T1, a second transistor T2, a driving transistor (such as a third transistor), a data writing transistor (such as a fourth transistor), a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, a first conductive connection part 961, a second conductive connection part 962, a third conductive connection part 963, a fourth conductive connection part 964 and a fifth conductive connection part 965, etc.

[0337] Specifically, the multiple sub-pixels can be divided into multiple rows of sub-pixels arranged in sequence along the second direction, and multiple columns of sub-pixels arranged in sequence along the first direction, the initialization signal line graphics 94 included in the sub-pixels located in the same row are electrically connected in sequence to form an integrated structure; the gate line graphics 92 included in the sub-pixels located in the same row are electrically connected in sequence to form an integrated structure; the light-emitting control signal line graphics 93 included in the sub-pixels located in the same row are electrically connected in sequence to form an integrated structure; the reset signal line graphics 95 included in the sub-pixels located in the same row are electrically connected in sequence to form an integrated structure; the first data line graphics 981 included in the sub-pixels located in the same column are electrically connected in sequence to form an integrated structure; the second data line graphics 982 included in the sub-pixels located in the same column are electrically connected in sequence to form an integrated structure; the power signal line graphics 91 included in the sub-pixels located in the same column are electrically connected in sequence to form an integrated structure.

[0338] like Figure 2 As shown, a sub-pixel driving circuit is taken as an example. The sub-pixel driving circuit includes 7 thin film transistors and 1 capacitor. Each transistor included in the sub-pixel driving circuit is a P-type transistor, the first electrode of each transistor includes a source electrode, and the second electrode of each transistor includes a drain electrode.

[0339] The first transistor T1 has a dual-gate structure, the gate 201g of the first transistor T1 is electrically connected to the gate line pattern 92, the source S1 of the first transistor T1 is electrically connected to the drain D3 of the third transistor T3 (i.e., the driving transistor), and the drain D1 of the first transistor T1 is electrically connected to the gate 203g of the third transistor T3.

[0340] The second transistor T2 has a dual-gate structure, a gate 202g of the second transistor T2 is electrically connected to the reset signal line pattern 95, a source S2 of the second transistor T2 is electrically connected to the initialization signal line pattern 94, and a drain D2 of the second transistor T2 is electrically connected to the gate 203g of the third transistor T3.

[0341] The gate 204g of the fourth transistor T4 (ie, the data writing transistor) is electrically connected to the gate line pattern 92, the source S4 of the fourth transistor T4 is electrically connected to the first data line pattern 981 or the second data line pattern 982, and the drain D4 of the fourth transistor T4 is electrically connected to the source S3 of the third transistor T3.

[0342] The gate 205g of the fifth transistor T5 is electrically connected to the light emission control signal line pattern 93, the source S5 of the fifth transistor T5 is electrically connected to the power signal line pattern 91, and the drain D5 of the fifth transistor T5 is electrically connected to the source S3 of the third transistor T3.

[0343] The gate 206g of the sixth transistor T6 is electrically connected to the light emitting control signal line pattern 93, the source S6 of the sixth transistor T6 is electrically connected to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is electrically connected to the anode of the light emitting element EL.

[0344] The gate 207g of the seventh transistor T7 is electrically connected to the reset signal line pattern 95' in the next sub-pixel adjacent along the second direction, the drain D7 of the seventh transistor T7 is electrically connected to the anode of the corresponding light-emitting element EL, and the source S7 of the seventh transistor T7 is electrically connected to the initialization signal line pattern 94' in the next sub-pixel adjacent along the second direction.

[0345] The first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203 g of the third transistor T3 , and the second plate Cst2 of the storage capacitor Cst is electrically connected to the power signal line pattern 91 .

[0346] like Figure 3 As shown, when the sub-pixel driving circuit of the above structure is in operation, each working cycle includes a reset period P1, a writing compensation period P2 and a light emitting period P3. Figure 3 In the figure, E1 represents the light-emitting control signal transmitted on the light-emitting control signal line pattern 93 in the current sub-pixel, R1 represents the reset signal transmitted on the reset signal line pattern 95 in the current sub-pixel, D1 represents the data signal transmitted on the data line pattern in the current sub-pixel, G1 represents the gate scanning signal transmitted on the gate line pattern 92 in the current sub-pixel, and R1' represents the reset signal transmitted on the reset signal line pattern 95' in the next sub-pixel adjacent to the current sub-pixel along the second direction.

[0347] During the first reset period P1, the reset signal input by the reset signal line pattern 95 is at an effective level, the second transistor T2 is turned on, and the initialization signal transmitted by the initialization signal line pattern 94 is input to the gate 203g of the third transistor T3, so that the gate-source voltage Vgs maintained on the third transistor T3 in the previous frame is cleared, thereby resetting the gate 203g of the third transistor T3.

[0348] During the write compensation period P2, the reset signal input by the reset signal line pattern 95 is at an inactive level, the second transistor T2 is turned off, and the gate scan signal input by the gate line pattern 92 is at an active level, controlling the first transistor T1 and the fourth transistor T4 to be turned on. The corresponding data line pattern writes the data signal, which is transmitted to the source S3 of the third transistor T3 through the fourth transistor T4. At the same time, the first transistor T1 and the fourth transistor T4 are turned on, so that the third transistor T3 forms a diode structure. Therefore, the threshold voltage of the third transistor T3 is compensated by the cooperation of the first transistor T1, the third transistor T3 and the fourth transistor T4. When the compensation time is long enough, the gate 203g potential of the third transistor T3 can be controlled to eventually reach Vdata+Vth, where Vdata represents the data signal voltage value and Vth represents the threshold voltage of the third transistor T3.

[0349] During the writing compensation period P2, the reset signal inputted by the reset signal line pattern 95' is at an active level, controlling the seventh transistor T7 to be turned on, and the initialization signal transmitted by the initialization signal line pattern 94' is inputted to the anode of the light emitting element EL, controlling the light emitting element EL not to emit light.

[0350] During the light-emitting period P3, the light-emitting control signal written in the light-emitting control signal line pattern 93 is at an effective level, controlling the fifth transistor T5 and the sixth transistor T6 to be turned on, so that the power signal transmitted by the power signal line pattern 91 is input to the source S3 of the third transistor T3. At the same time, since the gate 203g of the third transistor T3 is maintained at Vdata+Vth, the third transistor T3 is turned on. The gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD, where VDD is the voltage value corresponding to the power signal. The leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element EL, driving the corresponding light-emitting element EL to emit light.

[0351] like Figures 6-8 、 Figures 10 to 13a As shown, when manufacturing the above sub-pixels, the layout of each film layer corresponding to the sub-pixel is as follows:

[0352] An active film layer, a first gate insulating layer GI1, a first gate metal layer, a second gate insulating layer GI2, a second gate metal layer, an interlayer insulating layer ILD, a first source-drain metal layer, a first flat layer PLN1, a second source-drain metal layer, a second flat layer PLN2 and an anode layer are stacked in sequence along the direction away from the substrate.

[0353] like Figure 6 As shown, the active film layer is used to form the channel region (the portion covered by the gate of each transistor), source electrodes (such as S1-S7), and drain electrodes (such as D1-D7) of each transistor in the sub-pixel driving circuit. Due to doping, the active film layer corresponding to the source and drain electrodes has better conductivity than the active film layer corresponding to the channel region. The active film layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source and drain electrodes can be doped with n-type impurities or p-type impurities.

[0354] like Figure 6 As shown, the first gate metal layer is used to form the gate of each transistor in the sub-pixel driving circuit (such as: 201g~207g), as well as the gate line pattern 92, the light-emitting control signal line pattern 93, the reset signal line pattern 95 and other structures included in the sub-pixel. The gate 203g of the third transistor T3 in each sub-pixel driving circuit is reused as the first plate Cst1 of the second storage capacitor Cst in the sub-pixel driving circuit.

[0355] like Figure 7 As shown, the second gate metal layer is used to form the second plate Cst2 of the second storage capacitor Cst, the initialization signal line pattern 94 included in the sub-pixel, and the shielding pattern 80.

[0356] like Figure 8 As shown, the first source-drain metal layer is used to form the power signal line pattern 91, the power compensation pattern and some conductive connection parts included in the sub-pixel.

[0357] like Figure 11 As shown, the second source-drain metal layer is used to form a first data line pattern 981, a second data line pattern 982 and some conductive connection parts included in the sub-pixel.

[0358] In addition, if Figure 5As shown, in the display substrate provided by the present disclosure, in the second direction, the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1, and the gate 202g of the second transistor T2 are all located on the first side of the gate of the driving transistor (i.e., the gate 203g of the third transistor T3), and the gate of the seventh transistor T7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 are all located on the second side of the gate of the driving transistor. Exemplarily, the first side and the second side of the gate of the driving transistor are two opposite sides along the second direction. Further, the first side of the gate of the driving transistor can be the upper side of the gate of the driving transistor, and the second side of the gate of the driving transistor can be the lower side of the gate of the driving transistor. The lower side, for example, the side of the display substrate used for binding the IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor that is closer to the IC. The upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor that is farther away from the IC.

[0359] In the first direction, the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, and the gate 201g of the first transistor T1 and the gate 206g of the sixth transistor T6 are both located on the fourth side of the gate of the driving transistor. Exemplarily, the third and fourth sides of the gate of the driving transistor are two opposite sides along the first direction; further, the third side of the gate of the driving transistor can be the right side of the gate of the driving transistor, and the fourth side of the gate of the driving transistor can be the left side of the gate of the driving transistor. For example, in the same sub-pixel, the second data line pattern 982 is located on the right side of the gate of the driving transistor, and the first data line pattern 981 is located on the left side of the gate of the driving transistor.

[0360] An embodiment of the present disclosure further provides a display device, comprising the above-mentioned display substrate.

[0361] In the display substrate provided by the above embodiment, in the first sub-pixel M1, the orthographic projection of the anode pattern on the substrate is set to at least partially overlap with the orthographic projection of the second data line pattern on the substrate, and the orthographic projection of the anode pattern on the substrate is at least partially overlapped with the orthographic projection of the data line pattern adjacent to the second data line pattern along the first direction on the substrate; so that the second data line pattern 982 and its adjacent data line pattern can compensate for the step difference generated by each other under the anode pattern (such as the first anode pattern 71), so that the anode pattern can be formed on a relatively flat surface, so that the anode pattern has a higher flatness, ensuring that the sub-pixel has consistent luminous intensity in all directions, and effectively improving the color deviation problem generated by the display product when the display substrate is used in the display product.

[0362] Therefore, when the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, it also has all the effects of the above-mentioned display substrate, which will not be described in detail here.

[0363] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, or a tablet computer.

[0364] The present disclosure also provides a method for manufacturing a display substrate, which is used to manufacture the display substrate provided in the above embodiment. The method comprises: manufacturing a plurality of sub-pixels distributed in an array on a substrate, wherein the plurality of sub-pixels include:

[0365] A first subpixel M1 and a second subpixel M2 are arranged along the second direction, wherein the first subpixel M1 includes a first data line pattern 981, and the second subpixel M2 includes a second data line pattern 982. The first data line pattern 981 is configured to provide a first data signal to the first subpixel M1, and the second data line pattern 982 is configured to provide a second data signal to the second subpixel M2.

[0366] At least a portion of the first data line pattern 981 and at least a portion of the second data line pattern 982 both extend along the second direction. The first data line pattern 981 is located on a first side of the first sub-pixel M1 in the same column extending along the second direction, and the second data line pattern 982 is located on a second side of the second sub-pixel M2 in the same column extending along the second direction. The first side and the second side are opposite to each other along the first direction, and the first direction intersects the second direction.

[0367] The first subpixel M1 includes a sixth transistor T6, and a third conductive connection portion 963, a fourth conductive connection portion 964, and an anode pattern stacked in a direction away from the substrate; a second electrode of the sixth transistor T6 is electrically connected to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964;

[0368] In the first sub-pixel M1, the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the second data line pattern 982 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the data line pattern adjacent to the second data line pattern 982 along the first direction on the substrate.

[0369] In the display substrate manufactured using the manufacturing method provided by the embodiment of the present disclosure, in the first sub-pixel M1, the orthographic projection of the anode pattern on the substrate is set to at least partially overlap with the orthographic projection of the second data line pattern on the substrate, and the orthographic projection of the anode pattern on the substrate is at least partially overlapped with the orthographic projection of the data line pattern adjacent to the second data line pattern along the first direction on the substrate; so that the second data line pattern 982 and its adjacent data line pattern can compensate for the step difference generated by each other below the anode pattern (such as the first anode pattern 71), so that the anode pattern can be formed on a relatively flat surface, so that the anode pattern has a high flatness, ensuring that the sub-pixel has consistent luminous intensity in all directions, and effectively improving the color deviation problem generated by the display product when the display substrate is used in the display product.

[0370] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0371] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0372] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0373] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0374] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A substrate and a plurality of sub-pixels arrayed on the substrate, the plurality of sub-pixels comprising: a first subpixel and a second subpixel arranged along a second direction, the first subpixel including a first data line pattern, the second subpixel including a second data line pattern, the first data line pattern being configured to provide a first data signal to the first subpixel, and the second data line pattern being configured to provide a second data signal to the second subpixel; At least a portion of the first data line pattern and at least a portion of the second data line pattern both extend along a second direction, the first data line pattern is located on a first side of the first sub-pixels in the same column extending along the second direction, and the second data line pattern is located on a second side of the second sub-pixels in the same column extending along the second direction; the first side and the second side are opposite to each other along the first direction, and the first direction intersects the second direction; The first subpixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; a second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion; In the first subpixel, an orthographic projection of the anode pattern on the substrate at least partially overlaps with an orthographic projection of the second data line pattern on the substrate, and an orthographic projection of a data line pattern adjacent to the second data line pattern along the first direction on the substrate at least partially overlaps.

2. The display substrate according to claim 1, wherein In the first sub-pixel, the anode pattern does not overlap with the first data line pattern.

3. The display substrate according to claim 1, wherein The second sub-pixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; a second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion; In the second sub-pixel, the fourth conductive connection portion includes a solid portion and a hollow portion; The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the first data line pattern on the substrate, and the orthographic projection of the data line pattern adjacent to the first data line pattern along the first direction on the substrate at least partially overlaps; The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the second data line pattern on the substrate, and respectively overlaps with the orthographic projection of the solid portion on the substrate and the orthographic projection of the hollow portion on the substrate.

4. The display substrate according to claim 1, wherein: The plurality of sub-pixels further include: a third sub-pixel and a fourth sub-pixel arranged along the second direction, wherein along the first direction, the third sub-pixel and the first sub-pixel are located in the same row, and the fourth sub-pixel and the second sub-pixel are located in the same row; The third sub-pixel includes a third data line pattern, and the fourth sub-pixel includes a fourth data line pattern. At least a portion of the third data line pattern and at least a portion of the fourth data line pattern extend along a second direction. The third data line pattern is located on a second side of the third sub-pixels in the same column extending along the second direction. The fourth data line pattern is located on a first side of the fourth sub-pixels in the same column extending along the second direction. The third sub-pixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; a second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion; In the third sub-pixel, the fourth conductive connection portion includes a solid portion and a hollow portion; The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the solid portion on the substrate and the orthographic projection of the hollow portion on the substrate; The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the third data line pattern on the substrate, and at least partially overlaps with the orthographic projection of a data line pattern adjacent to the third data line pattern along the first direction on the substrate.

5. The display substrate according to claim 4, wherein: The fourth subpixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; a second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion; In the fourth sub-pixel, the fourth conductive connection portion includes a solid portion and a hollow portion; The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the solid portion on the substrate; The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the third data line pattern on the substrate, and at least partially overlaps with the orthographic projection of a data line pattern adjacent to the third data line pattern along the first direction on the substrate. The display substrate according to claim 5 , wherein: In the fourth sub-pixel, an orthographic projection of the anode pattern on the substrate does not overlap with an orthographic projection of the fourth data line pattern on the substrate.

7. The display substrate according to claim 4, wherein: The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each include: a power signal line pattern, at least a portion of which extends along the second direction; a power compensation pattern, at least a portion of which extends along the first direction, and the power signal line pattern and the power compensation pattern are both located on a side of the first data line pattern, the second data line pattern, the third data line pattern, and the fourth data line pattern close to the substrate; The power compensation pattern is electrically connected to the power signal line pattern in the sub-pixel to which it belongs and the power signal line pattern in the adjacent sub-pixel along the first direction.

8. The display substrate according to claim 7, wherein: The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel all include: a reset signal line pattern, a gate line pattern and a light-emitting control signal line pattern distributed along the second direction; at least a portion of the reset signal line pattern extends along the first direction, at least a portion of the gate line pattern extends along the first direction, and at least a portion of the light-emitting control signal line pattern extends along the first direction; in the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, the orthographic projection of the power compensation pattern on the substrate is located between the orthographic projection of the gate line pattern on the substrate and the orthographic projection of the light-emitting control signal line pattern on the substrate.

9. The display substrate according to claim 7, wherein: In the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, the power signal line pattern in each sub-pixel includes: a power main portion and a power protrusion portion electrically connected to each other, at least a portion of the power protrusion portion extends along the second direction, and a gap is formed between the power protrusion portion and the power main portion; A first end of the power compensation pattern is electrically connected to the power protrusion portion of the sub-pixel to which it belongs; a second end of the power compensation pattern is electrically connected to the power main portion of the adjacent sub-pixel along the first direction.

10. The display substrate according to claim 9, wherein: In the first sub-pixel, the orthographic projection of the power source protrusion on the substrate overlaps with the orthographic projection of the first data line pattern on the substrate, and the orthographic projection of the power source main portion on the substrate at least partially overlaps with the orthographic projection of the data line pattern adjacent along the first direction on the substrate.

11. The display substrate according to claim 9, wherein: In the second sub-pixel, an orthographic projection of the power source protrusion on the substrate does not overlap with an orthographic projection of the second data line pattern on the substrate.

12. The display substrate according to claim 9, wherein: In the third sub-pixel, an orthographic projection of the power source protrusion on the substrate does not overlap with an orthographic projection of the third data line pattern on the substrate.

13. The display substrate according to claim 9, wherein: In the fourth sub-pixel, the orthographic projection of the power source protrusion on the substrate overlaps with the orthographic projection of the fourth data line pattern on the substrate, and the orthographic projection of the power source main portion on the substrate overlaps with the orthographic projection of the data line pattern adjacent along the first direction on the substrate.

14. The display substrate according to claim 4, wherein: The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include: an initialization signal line pattern, a second transistor and a second conductive connection portion; At least a portion of the initialization signal line pattern extends along the second direction, and the initialization signal line pattern is used to transmit an initialization signal; The first electrode of the second transistor is electrically connected to the initialization signal line pattern through the second conductive connection portion, and the second electrode of the second transistor is electrically connected to the gate of the driving transistor; In the first sub-pixel, an orthographic projection of the second conductive connection portion on the substrate overlaps with an orthographic projection of the first data line pattern on the substrate; In the second sub-pixel, an orthographic projection of the second conductive connection portion on the substrate does not overlap with an orthographic projection of the second data line pattern on the substrate; In the third sub-pixel, an orthographic projection of the second conductive connection portion on the substrate does not overlap with an orthographic projection of the third data line pattern on the substrate; In the fourth sub-pixel, an orthographic projection of the second conductive connection portion on the substrate overlaps with an orthographic projection of the fourth data line pattern on the substrate.

15. The display substrate according to claim 4, wherein The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include: an initialization signal line pattern, a shielding pattern, a driving transistor and a second transistor; In the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, a first electrode of the second transistor is electrically connected to the initialization signal line pattern, and a second electrode of the second transistor is electrically connected to the gate of the driving transistor; The shielding pattern is electrically connected to a power signal line pattern in the display substrate, and an orthographic projection of the shielding pattern on the substrate at least partially overlaps with an orthographic projection of the first electrode of the second transistor on the substrate.

16. The display substrate according to claim 15, wherein: The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include: a first conductive connection portion, a fifth conductive connection portion and a data writing transistor, In the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, the second electrode of the second transistor is electrically connected to the gate of the driving transistor through the fifth conductive connection portion; The first conductive connection portion is electrically connected to the first electrode of the data writing transistor; the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor; An orthographic projection of the shielding pattern on the substrate at least partially overlaps with an orthographic projection of the first conductive connection portion on the substrate.

17. The display substrate according to claim 15, wherein: The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include: a first conductive connecting portion and a fifth conductive connecting portion; In the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, the orthographic projection of at least part of the shielding pattern on the substrate is located between the orthographic projection of the first conductive connecting portion on the substrate and the orthographic projection of the fifth conductive connecting portion on the substrate.

18. The display substrate according to claim 4, wherein: The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each include: a light-emitting element, an initialization signal line pattern, a reset signal line pattern, a gate line pattern, a light-emitting control signal line pattern, and a power signal line pattern; at least a portion of the initialization signal line pattern, at least a portion of the reset signal line pattern, at least a portion of the gate line pattern, and at least a portion of the light-emitting control signal line pattern all extend along the first direction, and at least a portion of the power signal line pattern extends along the second direction; The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel further include: a first transistor, a second transistor, a driving transistor, a data writing transistor, a fifth transistor, a sixth transistor, a seventh transistor and a storage capacitor; In each sub-pixel, the gate of the driving transistor is electrically connected to the second electrode of the first transistor, the first electrode of the driving transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the driving transistor is electrically connected to the first electrode of the first transistor; The gate of the first transistor is electrically connected to the gate line pattern; The gate of the second transistor is electrically connected to the reset signal line pattern, the first electrode of the second transistor is electrically connected to the initialization signal line pattern, and the second electrode of the second transistor is electrically connected to the gate of the driving transistor; The gate of the data writing transistor is electrically connected to the gate line pattern, the first electrode of the data writing transistor is electrically connected to the data line pattern in the sub-pixel, and the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor; The gate of the fifth transistor is electrically connected to the light emitting control signal line pattern, and the first electrode of the fifth transistor is electrically connected to the power signal line pattern; The gate of the sixth transistor is electrically connected to the light emitting control signal line pattern, the first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is electrically connected to the light emitting element; The gate of the seventh transistor is electrically connected to the reset signal line pattern in the next sub-pixel adjacent to the second direction, the first electrode of the seventh transistor is electrically connected to the initialization signal line pattern in the next sub-pixel adjacent to the second direction, and the second electrode of the seventh transistor is electrically connected to the light-emitting element; The first plate of the storage capacitor is multiplexed as the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the power signal line pattern.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

20. A method for manufacturing a display substrate, comprising: A plurality of sub-pixels distributed in an array are manufactured on a substrate, wherein the plurality of sub-pixels include: a first subpixel and a second subpixel arranged along a second direction, the first subpixel including a first data line pattern, the second subpixel including a second data line pattern, the first data line pattern being configured to provide a first data signal to the first subpixel, and the second data line pattern being configured to provide a second data signal to the second subpixel; At least a portion of the first data line pattern and at least a portion of the second data line pattern both extend along a second direction, the first data line pattern is located on a first side of the first sub-pixels in the same column extending along the second direction, and the second data line pattern is located on a second side of the second sub-pixels in the same column extending along the second direction; the first side and the second side are opposite to each other along the first direction, and the first direction intersects the second direction; The first subpixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; a second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion; In the first subpixel, an orthographic projection of the anode pattern on the substrate at least partially overlaps with an orthographic projection of the second data line pattern on the substrate, and an orthographic projection of a data line pattern adjacent to the second data line pattern along the first direction on the substrate at least partially overlaps.

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