Display device and method of manufacturing the same

Abstract

The display device includes: a display substrate, which defines a display area and a non-display area adjacent to the display area on the display substrate; a signal pad portion, which overlaps with the non-display area and includes a first signal pad portion and a second signal pad portion, the second signal pad portion faces the first signal pad portion in one direction and is spaced apart from the first signal pad portion on a plane; an insulating layer, which is configured to cover the signal pad portion and is disposed on the display substrate; a connecting pad portion, which is disposed on the insulating layer and includes a first connecting pad portion and a second connecting pad portion, the first connecting pad portion is configured to overlap with the first signal pad portion, the second connecting pad portion is electrically connected to the first connecting pad portion and is electrically in contact with the second signal pad portion through a contact hole defined in the insulating layer; and an electronic component, which includes a protrusion electrically in contact with the first connecting pad portion, wherein the first signal pad portion includes a plurality of signal pad portions spaced apart from each other on a plane.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a display device and a method for manufacturing the same. Background Art

[0002] Various display devices are being developed for use in multimedia equipment such as televisions, mobile phones, desktop computers, navigation devices, and game consoles.

[0003] Such a display device includes a display panel on which an image is displayed. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the plurality of gate lines and the plurality of data lines. The display device may be connected to an electronic component that provides the gate lines or the data lines with the electrical signals required to display the image.

[0004] The electronic component can be electrically connected to the display panel using an anisotropic conductive film or ultrasonic bonding. Among them, in the connection method between the display panel and the electronic component using ultrasonic bonding, the electrical conductivity can be more increased compared to the anisotropic conductive film, and thus the process can be simplified. Summary of the Invention

[0005] Technical issues

[0006] An object of the present invention is to provide a display device capable of improving the connection reliability between an electronic component and a display panel and a method for manufacturing the same.

[0007] Technical Solution

[0008] A display device according to an embodiment for achieving the purpose of the present invention includes: a display substrate, on which a display area and a non-display area adjacent to the display area are defined; a signal pad portion, overlapping with the non-display area and including a first signal pad portion and a second signal pad portion, the second signal pad portion facing the first signal pad portion in one direction and spaced apart from the first signal pad portion on a plane; an insulating layer configured to cover the signal pad portion and disposed on the display substrate; a connecting pad portion, disposed on the insulating layer and including a first connecting pad portion and a second connecting pad portion, the first connecting pad portion being configured to overlap with the first signal pad portion, the second connecting pad portion being electrically connected to the first connecting pad portion and electrically contacting the second signal pad portion through a contact hole defined in the insulating layer; and an electronic component including a protrusion electrically contacting the first connecting pad portion, wherein the first signal pad portion includes a plurality of signal pad portions spaced apart from each other on a plane.

[0009] According to an embodiment of the present invention, the display device further includes a filler disposed between the electronic component and the connection pad portion.

[0010] According to an embodiment of the present invention, the first connection pad portion includes first and second portions alternately and repeatedly arranged along one direction, and each of the first portions contacts the bump, and each of the second portions does not contact the bump.

[0011] According to an embodiment of the present invention, the first portions of the first connection pad parts overlap the signal pad portions, respectively, and the second portions of the first connection pad parts do not overlap the first signal pad parts.

[0012] According to an embodiment of the present invention, the filler is provided in the inner space defined by the first portion, the second portion and the protrusion, and the inner space is connected to a space between the electronic component and the first connection pad portion that does not overlap with the protrusion.

[0013] According to an embodiment of the present invention, the filler overlaps the insulating layer.

[0014] According to an embodiment of the present invention, the signal pad parts are arranged in one direction, and each of the signal pad parts extends in a different direction perpendicular to the one direction.

[0015] According to an embodiment of the present invention, only any one of the signal pad parts directly faces the second signal pad portion in one direction.

[0016] According to an embodiment of the present invention, the signal pad portion also includes a third signal pad portion electrically connected to the signal pad portion and the second signal pad portion, the third signal pad portion includes a first sub-pad portion arranged between the signal pad portions and a second sub-pad portion configured to connect any one of the signal pad portions to the second signal pad portion, and the first signal pad portion and the third signal pad portion are set to an integrated shape.

[0017] According to an embodiment of the present invention, each of the signal pad parts extends in one direction, and the signal pad parts are arranged in different directions perpendicular to the one direction.

[0018] According to an embodiment of the present invention, each of the signal pad parts faces the second signal pad portion in one direction.

[0019] According to an embodiment of the present invention, the first signal pad portion and the second signal pad portion are electrically insulated from each other.

[0020] According to an embodiment of the present invention, the insulating layer includes a plurality of sub-insulating layers, the contact hole passes through the sub-insulating layers, and the second connection pad portion electrically contacts the second signal pad portion through the contact hole.

[0021] According to an embodiment of the present invention, the contact hole does not partially overlap with the first connection pad in plane.

[0022] According to an embodiment of the present invention, the bump includes a first bump portion configured to partially overlap the first connection pad and a second bump portion not partially overlapping the first connection pad and contacting a portion of the insulating layer.

[0023] According to an embodiment of the present invention, the planar area of ​​the second protrusion is 10% to 50% of the total planar area of ​​the protrusion.

[0024] According to another embodiment of the present invention, a method for manufacturing a display device includes providing a display substrate having a pad portion provided thereon, an electronic component, and a filler, wherein the pad portion includes a first pad portion and a second pad portion, the electronic component includes a protrusion facing the first pad portion of the pad portion, and the filler is between the pad portion and the electronic component;

[0025] bringing the bump into contact with the first pad portion by applying pressure to the electronic component while applying heat to the filler; and

[0026] applying ultrasonic vibration to the bump and the first pad portion,

[0027] The first pad portion includes a first portion and a second portion that are alternately and repeatedly arranged in one direction, and

[0028] The first portion contacts the protrusion, and the second portion does not contact the protrusion.

[0029] According to an embodiment of the present invention, the viscosity of the filler decreases during a first period when the temperature of the filler increases from a first reference point to a second reference point by heat, and the filler solidifies during a second period when the temperature of the filler increases above the second reference point.

[0030] According to an embodiment of the present invention, during the first period, the protrusion is in contact with the first portion.

[0031] According to an embodiment of the present invention, when the protrusion contacts the first part, the filler between the protrusion and the first part moves to the inner space between the second part and the protrusion, and during the first period, the filler set in the inner space moves to the outer space not overlapping with the protrusion.

[0032] According to an embodiment of the present invention, applying the ultrasonic vibration is performed during at least one period of the first period.

[0033] According to an embodiment of the present invention, the pad portion includes: a signal pad portion, which is arranged on a display substrate and includes a first signal pad portion and a second signal pad portion, the second signal pad portion faces the first signal pad portion in one direction and is spaced apart from the first signal pad portion on a plane; and a connecting pad portion, which covers the signal pad portion and is arranged on an insulating layer, and the insulating layer is arranged on the display substrate, wherein the connecting pad portion includes a first connecting pad portion and a second connecting pad portion, the first connecting pad portion corresponds to the first pad portion and overlaps with the first signal pad portion, and the second connecting pad portion corresponds to the second pad portion and is electrically contacted with the second signal pad portion through a contact hole defined in the insulating layer.

[0034] Beneficial effects

[0035] According to an embodiment of the present invention, a bump of an electronic component and a connection pad portion of a substrate can be electrically connected to each other by ultrasonic bonding. As a result, the electrical connection characteristics between the bump and the connection pad portion can be improved.

[0036] Furthermore, according to the present invention, the curing of the filler disposed between the bump and the connection pad portion can be performed simultaneously with the ultrasonic bonding process between the bump and the connection pad portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1a is a perspective view of a display device according to an embodiment of the present invention.

[0038] Figure 1b is an exploded perspective view of a display device according to an embodiment of the present invention.

[0039] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present invention.

[0040] Figure 3 is a plan view of a display panel according to an embodiment of the present invention.

[0041] Figure 4a It shows Figure 3 An equivalent circuit diagram of an example of a pixel.

[0042] Figure 4b is an enlarged cross-sectional view of a display panel according to an embodiment of the present invention.

[0043] Figure 4c is a cross-sectional view showing a portion of a display panel according to an embodiment of the present invention.

[0044] Figure 5 According to an embodiment of the present invention Figure 3 Magnified view of area AA.

[0045] Figure 6a It is along Figure 5 A cross-sectional view taken along line II'.

[0046] Figure 6b It is along Figure 5 A cross-sectional view taken along line II-II'.

[0047] Figure 7 is an exploded perspective view of a display device according to an embodiment of the present invention.

[0048] Figure 8 is a plan view of an electronic component according to an embodiment of the present invention.

[0049] Figure 9a It is along Figure 8 A cross-sectional view taken along line III-III'.

[0050] Figure 9b It is along Figure 8 A sectional view taken along line IV-IV'.

[0051] Figure 10a is a plan view of a pad portion according to another embodiment of the present invention.

[0052] Figure 10b is a plan view of a pad portion according to another embodiment of the present invention.

[0053] Figure 11 is a cross-sectional view of a display device according to another embodiment of the present invention.

[0054] Figure 12 is a view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0055] Figure 13 It is a graph showing the characteristics of the filler.

[0056] Figure 14a is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0057] Figure 14b is an exploded perspective view of a display device according to an embodiment of the present invention.

[0058] Figure 14c is a perspective view of a display device according to an embodiment of the present invention.

[0059] Figure 14d is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0060] In this specification, it will also be understood that when a component (or region, layer, part) is referred to as being "on," "connected to" or "coupled to" another component, it can be directly set / connected / coupled to that one component, or there may be a third component in between.

[0061] The same reference numerals refer to the same elements throughout. In addition, in the drawings, the thickness, proportions, and sizes of components are exaggerated for clarity of explanation.

[0062] The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0063] It should be understood that although terms such as "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from other components. For example, a first element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims. Unless otherwise mentioned, terms in the singular may include plural forms.

[0064] In addition, “under”, “below”, “above”, “on”, etc. are used to explain the relationship between components shown in the drawings. These terms may be relative concepts and described based on the directions expressed in the drawings.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. In addition, terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0066] The meaning of “include” or “comprise” specifies properties, fixed numbers, steps, operations, elements, components or a combination thereof, but does not exclude other properties, fixed numbers, steps, operations, elements, components or a combination thereof.

[0067] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0068] Figure 1a is a perspective view of a display device according to an embodiment of the present invention. Figure 1b is an exploded perspective view of a display device according to an embodiment of the present invention. Figure 2 is a cross-sectional view of a display module according to an embodiment of the present invention.

[0069] This specification illustrates a display device DD that can be used in a mobile terminal. Although not shown, electronic modules, camera modules, power modules, and the like mounted on a mainboard can be placed on a bracket / housing together with the display device DD to form the mobile terminal. Display devices DD according to embodiments of the present invention can be applied to large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as tablet PCs, vehicle navigation units, game consoles, and smartwatches.

[0070] Reference Figure 1a , the display device DD can display the image IM through the display surface DD-IS. Figure 1a An icon image as an example of the image IM is shown in FIG. The display surface DD-IS is parallel to the surface defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface DD-IS, that is, the thickness direction of the display device DD is indicated as a third direction DR3. In this specification, "when viewed on a plane or on the plane" may refer to the case when viewed in the third direction DR3. The front surface (or top surface) and the rear surface (or bottom surface) of each of the layers or units described below are distinguished by the third direction DR3. However, the directions indicated as the first direction DR1, the second direction DR2, and the third direction DR3 as relative concepts may be changed to different directions, such as opposite directions.

[0071] Furthermore, the display surface DD-IS includes a display area DD-DA on which an image IM is displayed, and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA may be an area on which no image is displayed. However, embodiments of the present invention are not limited thereto. The non-display area DD-NDA may be adjacent to one side of the display area DD-DA or may be omitted.

[0072] Reference Figure 1b The display device DD may include a window WM, a display module DM, an electronic component DC, and a receiving member BC. The receiving member BC may receive the display module DM and be coupled to the window WM.

[0073] A window WM may be disposed above the display module DM and may transmit an image provided by the display module DM to the outside. The window WM includes a transmissive area TA and a non-transmissive area NTA. The transmissive area TA overlaps with the display area DD-DA and may have a shape corresponding to the display area DD-DA. An image IM displayed on the display area DD-DA of the display device DD may be visible from the outside through the transmissive area TA of the window WM.

[0074] The non-transmission area NTA overlaps with the non-display area DD-NDA and may have a shape corresponding to the non-display area DD-NDA. The non-transmission area NTA may be a region having a relatively lower light transmittance than the light transmittance of the transmission area TA. However, the technical concept of the present disclosure is not limited thereto, and the non-transmission area NTA may be omitted.

[0075] The window WM can be made of glass, sapphire, or plastic. Furthermore, although the window WM is provided as a single layer, the window WM may include multiple layers. The window WM may include a base layer and at least one printed layer, which overlaps with the non-transmissive area NTA and is provided on the rear surface of the base layer. The printed layer may have a predetermined color. For example, the printed layer may be black or a color other than black.

[0076] The display module DM is disposed between the window WM and the receiving member BC. The display module DM includes a display panel DP and an input sensing layer ISU. The display panel DP generates an image and can transmit the generated image to the window WM.

[0077] According to an embodiment of the present invention, the display panel DP may be an emissive display panel, but is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. Below, an organic light-emitting display panel will be described as an example of the display panel DP.

[0078] Hereinafter, a case where the display panel DP according to the present invention is an organic light emitting display panel will be described. However, the technical idea of ​​the present disclosure is not limited thereto, and various display panels may be applied to the present disclosure according to embodiments.

[0079] Reference Figure 2 The display panel DP includes a substrate SUB, a circuit element layer DP-CL, a display element layer DP-OLED, and an insulating layer TFL disposed on the substrate SUB.

[0080] The display panel DP includes a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP corresponds to Figure 1a Display area DD-DA or Figure 1b The transmission area TA, and the non-display area DP-NDA corresponds to Figure 1a Non-display area DD-NDA or Figure 1b The non-transmission area NTA is shown in FIG.

[0081] The substrate SUB may include at least one plastic film. The substrate SUB may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate as a flexible substrate.

[0082] The circuit element layer DP-CL includes at least one intermediate insulating layer and circuit elements. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit elements include signal lines, pixel driver circuits, etc.

[0083] The display element layer DP-OLED may include a plurality of organic light-emitting diodes. The display element layer DP-OLED may also include an organic layer such as a pixel defining layer. According to another embodiment, when the display panel DP is configured as a liquid crystal display panel, the display element layer DP-OLED may be configured as a liquid crystal layer.

[0084] The insulating layer TFL seals the display element layer DP-OLED. For example, the insulating layer TFL may be a thin film encapsulation layer. The insulating layer TFL protects the display element layer DP-OLED from impurities such as moisture, oxygen, and dust particles. However, embodiments of the present invention are not limited thereto. For example, an encapsulation substrate may be provided without the insulating layer TFL. In this case, the encapsulation substrate may be opposite to the substrate SUB, and the circuit element layer DP-CL and the display element layer DP-OLED may be provided between the encapsulation substrate and the substrate SUB.

[0085] The input sensing layer ISU may be provided between the window WM and the display panel DP. The input sensing layer ISU senses externally applied input. Externally applied input may be provided in a variety of ways. For example, external input includes various types of external input, such as a part of the user's body, a stylus, light, heat, pressure, and the like. Furthermore, input through contact with a human body part, such as a user's hand, and adjacent or proximate spatial touch (e.g., hovering) may also be a form of input.

[0086] The input sensing layer ISU can be directly disposed on the display panel DP. In this specification, "component A is directly disposed on component B" may indicate that no adhesive member is disposed between component A and component B. In this embodiment, the input sensing layer ISU can be manufactured together with the display panel DP through a continuous process. However, the technical concepts of the present disclosure are not limited to this. For example, the input sensing layer ISU can be provided as a separate panel and then coupled to the display panel DP via an adhesive layer. In another example, the input sensing layer ISU can be omitted.

[0087] Reference again Figure 1bThe electronic component DC may overlap the non-display area DP-NDA and be disposed on the display panel DP. According to the present invention, the electronic component DC may be a driver chip that transmits drive signals to the display panel DP. For example, the electronic component DC may generate drive signals required for operating the display panel DP based on externally transmitted control signals. The electronic component DC may then transmit the generated drive signals to the circuit element layer DP-CL of the display panel DP.

[0088] According to an embodiment of the present invention, the electronic component DC may be electrically connected to the display panel DP in an ultrasonic bonding manner. For example, a bump included in the electronic component DC and a pad included in the display panel DP may contact each other in an ultrasonic bonding manner.

[0089] Figure 3 is a plan view of a display panel according to an embodiment of the present invention. Figure 4a It shows Figure 3 An equivalent circuit diagram of an example of a pixel. Figure 4b is an enlarged cross-sectional view of a display panel according to an embodiment of the present invention.

[0090] Reference Figure 3 , the display panel DP may include a driving circuit GDC, a plurality of signal lines SGL, a plurality of pads DP-PD, a plurality of first connection pads DPS-PD, and a plurality of pixels PX (hereinafter referred to as pixels). The pixels PX are arranged in the display area DP-DA. Each pixel PX includes an organic light emitting diode and a pixel driving circuit connected to the organic light emitting diode. The driving circuit GDC, the signal lines SGL, the pads DP-PD, the first connection pads DPS-PD, and the pixel driving circuit may be included in Figure 2 The circuit element layer DP-CL is shown in FIG.

[0091] The driving circuit GDC sequentially outputs gate signals to the plurality of gate lines GL. The driving circuit GDC may also output other control signals to the pixels PX. The driving circuit GDC may include a plurality of thin film transistors manufactured using the same process as the driving circuit of the pixels PX, such as a low-temperature polysilicon (LTPS) process or a low-temperature polycrystalline oxide (LTPO) process.

[0092] The signal lines SGL include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. The gate lines GL are connected to corresponding pixels PX, and the data lines DL are connected to corresponding pixels PX. The power lines PL are connected to the pixels PX. The control signal lines CSL can provide control signals to the drive circuit GDC.

[0093] The signal lines SGL overlap the display area DP-DA and the non-display area DP-NDA. Each signal line SGL may include a pad portion and a line portion. The line portion overlaps the display area DP-DA and the non-display area DP-NDA. The pad portion is connected to one end of the line portion. The pad portion is disposed in the non-display area DP-NDA and overlaps a corresponding pad of the pads DP-PD.

[0094] Hereinafter, in this specification, in the non-display area DP-NDA, the area in which the pads DP-PD are provided is defined as the chip area NDA-DC, and the area in which the first connection pads DPS-PD are provided may be defined as the first pad area NDA-PC.

[0095] According to an embodiment of the present invention, Figure 1b The electronic component DC may be mounted in the chip area NDA-DC. The pads DP-PD are electrically connected to the electronic component DC to transmit an electrical signal received from the electronic component DC to the signal line SGL.

[0096] In detail, the pads DP-PD include first pads DP-PD1 arranged in a first row along the first direction DR1 and second pads DP-PD2 arranged in a second row along the first direction DR1. However, embodiments of the present invention are not limited thereto. For example, the pads DP-PD may be arranged in a row along the first direction DR1.

[0097] A portion of the circuit board PCB may be disposed on the first pad area NDA-PC. The first connection pads DPS-PD are electrically connected to the circuit board PCB to transmit electrical signals received from the circuit board PCB to the pads DP-PD. The circuit board PCB may be rigid or flexible. For example, if the circuit board PCB is flexible, the circuit board PCB may be configured as a flexible printed circuit board.

[0098] The circuit board PCB may include a timing control circuit for controlling the operation of the display panel DP. The timing control circuit may be mounted on the circuit board PCB in the form of an integrated chip. In addition, although not shown, the circuit board PCB may include an input sensing circuit for controlling the input sensing layer ISU.

[0099] The circuit board PCB may include a second connection pad DPS-PDz electrically connected to the display panel DP. The second connection pad DPS-PDz may be arranged in a second pad area defined on the circuit board PCB. The second connection pad DPS-PDz is electrically bonded to the first connection pad DPS-PD. For example, the first connection pad DPS-PD and the second connection pad DPS-PDz may be electrically connected to each other via an anisotropic conductive film, or may be in contact with each other by ultrasonic bonding.

[0100] Reference Figure 4a , the display area DP-DA may be defined as an area in which pixels PX are disposed. Each pixel PX includes an organic light emitting diode OLED and a pixel driving circuit connected to the organic light emitting diode OLED.

[0101] In detail, the pixel PX may include a first transistor T1, a second transistor T2, a capacitor CP, and an organic light emitting diode OLED. It is sufficient if the pixel driving circuit includes a switching transistor and a driving transistor, but is not limited to the reference Figure 4a The embodiment described. Figure 4a As shown, although each of the first transistor T1 and the second transistor T2 is configured as a P-MOS transistor, the embodiments of the present invention are not limited thereto. For example, each of the first transistor T1 and the second transistor T2 may be configured as an N-MOS transistor.

[0102] The first transistor T1 is connected to the gate line GL and the data line DL. The organic light emitting diode OLED receives a first power voltage ELVDD and a second power voltage ELVSS supplied from the power line PL. The first power voltage ELVDD is supplied to the first electrode AE ​​of the organic light emitting diode OLED via the second transistor T2, and the second power voltage ELVSS is supplied to the second electrode CE of the organic light emitting diode OLED. The second power voltage ELVSS may be lower than the first power voltage ELVDD.

[0103] Reference Figure 4b , the display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers may be formed by coating, deposition, etc. Thereafter, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography. The semiconductor patterns, conductive patterns, and signal lines provided in the circuit element layer DP-CL and the display element layer DP-OLED may be formed in the above-described manner. Figure 4b In the display panel DP, when Figure 4a Compared to the pixel driving circuit including the first transistor T1 and the second transistor T2, the pixel driving circuit may further include a component. The substrate SUB may be a base substrate supporting the circuit element layer DP-CL and the display element layer DP-OLED. In this specification, the substrate SUB may also be described as a display substrate.

[0104] In detail, the substrate SUB may include a synthetic resin film. The synthetic resin layer may include a thermosetting resin. The substrate SUB may have a multilayer structure. For example, the substrate SUB may have a three-layer structure including a synthetic resin layer, an adhesive layer, and a synthetic resin layer. In particular, the synthetic resin layer may be a polyimide resin layer, and its material is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the synthetic resin layer may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0105] At least one inorganic layer may be disposed on the top surface of the substrate SUB. The inorganic layer may include at least one of titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be provided as a multilayer. The multilayer inorganic layer may constitute a barrier layer and / or a buffer layer. In this embodiment, the display panel DP may include a buffer layer BFL.

[0106] The buffer layer BFL improves the bonding force between the substrate SUB and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0107] The semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, the embodiments of the present invention are not limited thereto. For example, the semiconductor pattern may include amorphous silicon or metal oxide.

[0108] Figure 4b Only a portion of the semiconductor pattern is shown. For example, the semiconductor pattern may be further disposed in other areas of the pixel PX on the plane. The semiconductor pattern may be arranged throughout the pixel PX according to a specific rule. Depending on whether the semiconductor pattern is doped, the semiconductor pattern has different electrical characteristics. The semiconductor pattern may include doped regions and undoped regions. The doped regions may be doped with N-type dopants or P-type dopants. A P-type transistor includes a doped region doped with a P-type dopant.

[0109] The doped region may have a greater conductivity than the non-doped region and may be substantially used as an electrode or a signal line. The non-doped region may substantially correspond to an active region (or channel) of a transistor. That is, a portion of the semiconductor pattern may be an active region of a transistor, another portion may be a source or drain of the transistor, and yet another portion may be a connecting electrode or a connecting signal line.

[0110] like Figure 4bAs shown, the source S1, active area A1, and drain D1 of the first transistor T1 can be formed from a semiconductor pattern, and the source S2, active area A2, and drain D2 of the second transistor T2 can be formed from a semiconductor pattern. The sources S1 and S2 and the drains D1 and D2 extend from the active areas A1 and A2 in opposite directions. Figure 4b A portion of a connection signal line SCL formed of a semiconductor pattern is shown. Although not particularly shown, the connection signal line SCL may be connected to the drain electrode D2 of the second transistor T2 on a plane.

[0111] The first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 overlaps with the plurality of pixels PX and covers the semiconductor pattern. The first insulating layer 10 may include an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 may include a single silicon oxide layer. The insulating layer of the circuit element layer DP-CL, which will be described later, and the first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials.

[0112] Gates G1 and G2 are disposed on the first insulating layer 10. Each of the gates G1 and G2 may be part of a metal pattern. The gates G1 and G2 overlap with the active regions A1 and A2. The gates G1 and G2 may be used as masks in the process of doping the semiconductor pattern.

[0113] A second insulating layer 20 covering gates G1 and G2 is disposed on the first insulating layer 10. The second insulating layer 20 overlaps with the pixel PX. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. In this embodiment, the second insulating layer 20 may include a single silicon oxide layer.

[0114] The upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap the gate G2 of the second transistor T2. The upper electrode UE may be a portion of the metal pattern. A portion of the gate G2 and the upper electrode UE overlapping the portion of the gate G2 may define a capacitor CP (see FIG. Figure 4a ).

[0115] A third insulating layer 30 covering the upper electrode UE is disposed on the second insulating layer 20. In this embodiment, the third insulating layer 30 may be a single silicon oxide layer. A first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal line SCL via a contact hole CNT-1 passing through the first insulating layer 10 to the third insulating layer 30.

[0116] A fourth insulating layer 40, covering the first connection electrode CNE1, is disposed on the third insulating layer 30. The fourth insulating layer 40 may be a single silicon oxide layer. A fifth insulating layer 50 is disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. The second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a contact hole CNT-2 that passes through the fourth insulating layer 40 and the fifth insulating layer 50.

[0117] A sixth insulating layer 60 covering the second connection electrode CNE2 is disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. The first electrode AE ​​is disposed on the sixth insulating layer 60. The first electrode AE ​​is connected to the second connection electrode CNE2 via a contact hole CNT-3 passing through the sixth insulating layer 60. An opening OP is defined in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL exposes at least a portion of the first electrode AE.

[0118] like Figure 4b As shown, the display area DP-PA may include an emission area PXA and a light blocking area NPXA adjacent to the emission area PXA. The light blocking area NPXA may surround the emission area PXA. In this embodiment, the emission area PXA may be defined as a portion exposed by the opening OP in the area corresponding to the first electrode AE.

[0119] The hole control layer HCL may be disposed in both the emission region PXA and the light blocking region NPXA. The hole control layer HCL may include a hole transport layer and may further include a hole injection layer. The emission layer EML is disposed on the hole control layer HCL. The emission layer EML may be disposed in a region corresponding to the opening OP. In other words, the emission layer EML may be formed separately for each pixel.

[0120] The electron control layer (ECL) is disposed on the emission layer (EML). The electron control layer (ECL) may include an electron transport layer and may further include an electron injection layer. The hole control layer (HCL) and the electron control layer (ECL) may be formed together in multiple pixels (PX) using an open mask. The second electrode (CE) is disposed on the electron control layer (ECL). The second electrode (CE) is provided as a single body and is disposed together in multiple pixels (PX).

[0121] The insulating layer TFL is disposed on the second electrode CE. The insulating layer TFL may include a plurality of thin films. Similar to this embodiment, the insulating layer TFL may include a cover layer CPL and a thin film encapsulation layer TFE. The thin film encapsulation layer TFE may include a first inorganic layer IOL1, an organic layer IOL2, and a second inorganic layer IOL3.

[0122] The cover layer CPL is disposed on the second electrode CE to contact the second electrode CE. The cover layer CPL may include an organic material. The first inorganic layer 10L1 is disposed on the cover layer CPL to contact the cover layer CPL. The organic layer 10L-2 is disposed on the first inorganic layer 10L1 to contact the first inorganic layer 10L1. The second inorganic layer 10L3 is disposed on the organic layer 10L2 to contact the organic layer 10L2.

[0123] The cover layer CPL may protect the second electrode CE from subsequent processes such as a sputtering process and improve the light emitting efficiency of the organic light emitting diode OLED. The cover layer CPL may have a refractive index greater than that of the first inorganic layer IOL1.

[0124] The first inorganic layer 10L1 and the second inorganic layer 10L3 can protect the display element layer DP-OLED from oxygen and moisture, and the organic layer 10L2 can protect the display element layer DP-OLED from impurities such as dust particles. Each of the first inorganic layer 10L1 and the second inorganic layer 10L3 can be one of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. According to an embodiment of the present invention, each of the first inorganic layer 10L1 and the second inorganic layer 10L3 can include a titanium oxide layer, an aluminum oxide layer, or the like. The organic layer 10L2 can include, but is not limited to, an acrylic-based organic layer.

[0125] According to an embodiment of the present invention, an inorganic layer such as a LiF layer may be further provided between the capping layer CPL and the first inorganic layer IOL1. The LiF layer may improve the light emission efficiency of the organic light emitting diode OLED.

[0126] Figure 5 According to an embodiment of the present invention Figure 3 Magnified view of area AA. Figure 6a It is along Figure 5 A cross-sectional view taken along line II'. Figure 6b It is along Figure 5 A cross-sectional view taken along line II-II'.

[0127] Reference Figure 5 , as an example shows Figure 3 Among the signal lines SGL shown, two data lines DL (hereinafter referred to as “data lines”) and two pads DP-PD (hereinafter referred to as “pads”) overlap with the non-display area DP-NDA. Although not shown, Figure 3 Each signal line SGL shown in FIG may have Figure 5 Although it has been described Figure 3Each signal line SGL described in the specification includes a line portion and a pad portion, but the line portion and the pad portion may be provided as separate configurations. In the same length along the second direction DR2, the surface area of ​​each pad portion DL-P may be greater than that of each line portion DL-L.

[0128] In detail, the data line DL includes a line portion DL-L and a pad portion DL-P. Hereinafter, in this specification, the pad portion DL-P of the data line DL is described as a signal pad portion, and the line portion DL-L of the data line DL is described as a signal line portion.

[0129] The signal pad portion DL-P includes a first signal pad portion DL-PNA and a second signal pad portion DL-PCA. According to the present invention, the first signal pad portion DL-PNA and the second signal pad portion DL-PCA can be electrically insulated from each other. The first signal pad portion DL-PNA and the second signal pad portion DL-PCA can face each other in a direction and can be spaced apart from each other on a plane. Here, the one direction can refer to the second direction DR2.

[0130] In particular, the first signal pad portion DL-PNA may include a plurality of signal pad portions SPD spaced apart from each other on a plane. According to an embodiment, the signal pad portions SPD may extend in the first direction DR1 and may be arranged to have a shape spaced apart from each other by a predetermined interval in the second direction DR2. For example, although Figure 5 Four signal pad portions SPD are shown in FIG, but the number of the signal pad portions SPD is not limited thereto, and the number of the signal pad portions SPD may be variously changed.

[0131] The second signal pad portion DL-PCA is electrically connected to the signal line portion DL-L. The second signal pad portion DL-PCA may be electrically connected to the signal line portion DL-L. Figure 2 The circuit element layer DP-CL is shown. The second signal pad portion DL-PCA can face any one of the signal pad portions SPD of the first signal pad portion DL-PNA and can be configured as a single piece with the signal line portion DL-L. This single piece design means that the components are formed using the same process. The planar area of ​​the second signal pad portion DL-PCA can be larger than the planar area of ​​each signal pad portion SPD.

[0132] According to an embodiment of the present invention, each signal pad portion SPD of the first signal pad portion DL-PNA can be maintained in an insulated state. For example, the first signal pad portion DL-PNA can be electrically insulated from the second signal pad portion DL-PCA. In addition, the signal pad portions SPD can be arranged in a structure spaced apart from each other in the second direction DR2 and thus can be insulated from each other.

[0133] The pad DP-PD may cover the signal pad portion DL-P. In this specification, the meaning of configuration A covering configuration B may be that configuration A completely overlaps configuration B on a plane. Hereinafter, in this specification, the pad DP-PD will be described as a connection pad portion.

[0134] The connection pad portion DP-PD may include a first connection pad portion DP-PDa overlapping the first signal pad portion DL-PNA and a second connection pad portion DP-PDb overlapping the second signal pad portion DL-PCA. In practice, the first connection pad portion DP-PDa and the second connection pad portion DP-PDb may be configured to be electrically connected to each other in a single, integrated shape. In particular, the second connection pad portion DP-PDb may be electrically connected to the second signal pad portion DL-PCA via a contact hole CNT.

[0135] According to an embodiment of the present invention, the signal pad portion DL-P and the signal line portion DL-L may be provided at Figure 4b As shown, the signal pad portion DL-P and the signal line portion DL-L may be formed on the first insulating layer 10 by the same process as that of the gates G1 and G2.

[0136] For details, refer to Figure 6a , shows the reference Figure 4b The stacked structure of the substrate SUB, the buffer layer BFL, and the first to third insulating layers 10 to 30 is described. The second signal pad portion DL-PCA can electrically contact the second connection pad portion DP-PDb of the connection pad portion DP-PD through a contact hole CNT passing through the second insulating layer 20 and the third insulating layer 30.

[0137] According to the present invention, although the contact hole CNT passes through both the second insulating layer 20 and the third insulating layer 30, the contact hole CNT may have a structure that passes through at least one insulating layer. For example, the signal pad portion DL-P and the signal line portion DL-L may be provided at Figure 4b In this case, the signal pad portion DL-P and the signal line portion DL-L can be formed on the second insulating layer 20 by the same process as the upper electrode UE. Therefore, the second signal pad portion DL-PCA can be electrically contacted with the second connection pad portion DP-PDb of the connection pad portion DP-PD through the contact hole CNT passing through the third insulating layer 30.

[0138] Reference Figure 6bThe signal pad portions SPD of the first signal pad portion DL-PNA are disposed on the first insulating layer 10 to be spaced apart from each other by a predetermined interval in the second direction DR2. The second signal pad portion DL-PCA may be disposed on the first insulating layer 10 and may be spaced apart from the first signal pad portion DL-PNA on a plane.

[0139] The second insulating layer 20 covers a portion of the second signal pad portion DL-PCA and the first signal pad portion DL-PNA, and is disposed on the first insulating layer 10. The third insulating layer 30 is disposed on the second insulating layer 20. The contact hole CNT may overlap with the second signal pad portion DL-PCA and may be defined in each of the second insulating layer 20 and the third insulating layer 30. The contact hole CNT according to the present invention may not overlap with the first signal pad portion DL-PNA.

[0140] The first connection pad portion DP-PDa of the connection pad portion DP-PD may overlap with the first signal pad portion DL-PNA and may be disposed on the third insulating layer 30. The second connection pad portion DP-PDb of the connection pad portion DP-PD may be directly disposed on the second signal pad portion DL-PCA through the contact hole CNT. That is, the second connection pad portion DP-PDb of the connection pad portion DP-PD may be in electrical contact with the second signal pad portion DL-PCA.

[0141] According to an embodiment of the present invention, the first connection pad portion DP-PDa includes first portions P1 and second portions P2 alternately and repeatedly arranged along the second direction DR2. The first portions P1 arranged at predetermined intervals along the second direction DR2 may overlap with the signal pad portion SPD, respectively, and the second portions P2 may not overlap with the signal pad portion SPD.

[0142] Each of the first to third insulating layers 10 to 30 according to the present invention can be configured as an inorganic film. Therefore, a stepped portion may appear between the first portion P1 and the second portion P2 of the first connection pad portion DP-PDa due to the signal pad portion SPD. The second portion P2 may have a shape that is recessed in the direction from the first portion P1 toward the substrate SUB and may overlap the portion between two adjacent signal pad portions SPD. The recessed shape of the second portion P2 may have a shape that extends along the first direction DR1. Hereinafter, the space defined by the two adjacent signal pad portions SPD and the second portion P2 is defined as an inner space SNK.

[0143] Despite Figure 6b 1, but the first portion P1 of the first connection pad portion DP-PDa may be ultrasonically bonded to the Figure 1b The DC electrical contacts of the electronic components shown. This will refer to Figure 7 Describe in more detail.

[0144] Figure 7 is an exploded perspective view of a display device according to an embodiment of the present invention. Figure 8 is a plan view of an electronic component according to an embodiment of the present invention. Figure 9a It is along Figure 8 A cross-sectional view taken along line III-III'. Figure 9b It is along Figure 8 A sectional view taken along line IV-IV'.

[0145] Reference Figure 7 , the electronic component DC includes a top surface DC-US and a bottom surface DC-DS. In this specification, the bottom surface DC-DS of the electronic component DC may be a surface facing the display panel DP.

[0146] The electronic components DC include the reference Figure 3 The bumps DC-BP (hereinafter referred to as "bumps") that contact the pads DP-PD on the substrate SUB are described. The bumps DC-BP include first bumps DC-BP1 arranged in a first row along a first direction DR1 and second bumps DC-BP2 arranged in a second row along the first direction DR1. Each of the first bumps DC-BP1 and the second bumps DC-BP2 may have a shape exposed to the outside from the bottom surface of the electronic component DC.

[0147] In addition, if Figure 8 As shown, the electronic component DC includes a pad area PA in which a bump DC-BP is provided and a non-pad area NPA adjacent to the pad area PA. Although not shown, the electronic component DC may include a signal line provided in the non-pad area NPA and connected to the bump DC-BP.

[0148] Reference again Figure 7 The first bump DC-BP1 and the first pad DP-PD1 are in electrical contact with each other via ultrasonic bonding. The second bump DC-BP2 and the second pad DP-PD2 are in electrical contact with each other via ultrasonic bonding. The first pad DP-PD1 or the second pad DP-PD2 may include a first connection pad portion DP-PDa and a second connection pad portion DP-PDb. Although not shown, the electronic component DC may include a circuit element that provides an electrical signal to each of the first bump DC-BP1 and the second bump DC-BP2.

[0149] A filler RS ​​may be provided between the electronic component DC and the substrate SUB. The filler RS ​​may surround the outer surfaces of the protrusion DC-BP and the pad DP-PD that are joined to each other by ultrasonic bonding, and be provided between the electronic component DC and the substrate SUB. Since the filler RS ​​is provided between the electronic component DC and the display panel DP, the protrusion DC-BP and the connecting pad portion DP-PD may be shielded from external air. As a result, the protrusion DC-BP and the connecting pad portion DP-PD may be prevented from being oxidized by external air. In addition, before the protrusion DC-BP and the connecting pad portion DP-PD are joined to each other by ultrasonic bonding, the filler RS ​​may overlap with the protrusion DC-BP as a whole on a plane.

[0150] According to an embodiment of the present invention, the process of forming the filler material RS between the electronic component DC and the substrate SUB may be performed simultaneously with the ultrasonic bonding process of bonding the electronic component DC and the pads DP-PD.

[0151] Specifically, the filler RS ​​can be a film-type adhesive resin whose curing properties change in response to external heat. For example, during a first period in which the temperature of the filler RS ​​increases from a first reference point to a second reference point due to external heat, the viscosity of the filler RS ​​may decrease. In other words, during the first period, the curing properties of the filler RS ​​may deteriorate. Thereafter, during a second period in which the temperature of the filler RS ​​increases above the second reference point, the viscosity of the filler RS ​​may improve. In other words, the curing properties of the filler RS ​​may improve during the second period.

[0152] Specifically, during the first period, the electronic component DC may be positioned on the chip area NDA-DC of the substrate SUB by external pressure. When external pressure is applied to the electronic component DC, external heat may be transferred to the filler material RS disposed between the electronic component DC and the substrate SUB. Furthermore, during the first period, the bump DC-BP and the connection pad portion DP-PD may contact each other, and an ultrasonic bonding process may be performed.

[0153] refer to Figure 9a The electronic component DC includes a base substrate DC-BS, a driving pad portion DC-P, and a pad insulating layer DC-IL. The driving pad portion DC-P includes a driving pad DC-PD and a bump DC-BP.

[0154] The top surface of the base substrate DC-BS may correspond to the top surface DC-US of the electronic component DC. The bottom surface of the pad insulating layer DC-IL facing the display panel DP may correspond to the bottom surface DC-DS of the electronic component DC. For example, the base substrate DC-BS may include silicon material.

[0155] The driving pad DC-PD may be provided on the bottom surface of the base substrate DC-BS. The driving pad DC-PD may be electrically connected to a circuit element (not shown) of the electronic component DC. The pad insulating layer DC-IL may expose a portion of the driving pad DC-PD and may be provided on the bottom surface of the base substrate DC-BS. In this case, a through hole exposing a portion of the driving pad DC-PD may be defined by the pad insulating layer DC-IL. The protrusion DC-BP may be provided directly on the driving pad DC-PD. Depending on the embodiment, the driving pad DC-PD may be omitted.

[0156] According to an embodiment of the present invention, the protrusion DC-BP can be electrically contacted with the connection pad portion DP-PD by ultrasonic bonding. Specifically, when ultrasonic vibration is applied to the interface between the protrusion DC-BP and the pad DP-PD, frictional heat is generated at the interface. In addition, when external heat / pressure is applied to the top surface of the base substrate DC-BS, the interface between the protrusion DC-BP and the connection pad portion DP-PD can be bonded (or welded) to each other by frictional heat.

[0157] Therefore, when the bump DC-BP and the connection pad portion DP-PD are in electrical contact with each other, the bump DC-BP and the signal pad portion DL-P may be electrically connected to each other.

[0158] Furthermore, the filler material RS may be provided between the pad insulating layer DC-IL and the third insulating layer 30 and may be cured by external heat / pressure. That is, the filler material RS according to the present invention may omit a separate curing process due to external ultraviolet rays, etc. Therefore, since the time required to cure the filler material RS is omitted, the total processing time of the display device DD may be reduced.

[0159] Figure 9b 1 is a view showing a state in which the electronic component DC and the connection pad portion DP-PD are bonded to each other by ultrasonic bonding. The bump DC-BP may overlap with the first connection pad portion DP-PDa of the connection pad portion DP-PD and may not overlap with the second connection pad portion DP-PDb of the connection pad portion DP-PD. Figure 6b As described, the first connection pad portion DP-PDa of the connection pad portion DP-PD includes the first portion P1 and the second portion P2 alternately and repeatedly arranged along the second direction DR2.

[0160] According to an embodiment of the present invention, the first portion P1 may be in electrical contact with the bump DC-BP, and the second portion P2 may not be electrically connected to the bump DC-BP. That is, the drive signal output from the circuit element of the electronic component DC can be transmitted to the first portion P1 through the bump DC-BP. As a result, the drive signal can be transmitted to the second signal pad portion DL-PCA through the first portion P1 and the second connection pad portion DP-PDb.

[0161] Prior to ultrasonic bonding between the bump DC-BP and the first connection pad portion DP-PDa, a film-type filler RS ​​may be provided between the electronic component DC and the substrate SUB. In this case, the filler RS ​​may completely overlap the connection pad portion DP-PD and may also overlap the third insulating layer 30. Subsequently, when external heat is applied to the filler RS ​​during the ultrasonic bonding process, the viscosity of the filler RS ​​may decrease. As a result, the filler RS ​​may have fluid properties.

[0162] External pressure may be applied to the bump DC-BP while heat is applied to the filler RS. The external pressure applied to the bump DC-BP may be a strength at which the bump DC-BP contacts the first portion P1 of the first connection pad portion DP-PDa.

[0163] When the protrusion DC-BP contacts the first portion P1 by external pressure, the filler RS ​​disposed between the protrusion DC-BP and the first portion P1 may be moved to another space by the pressure of the protrusion DC-BP. Hereinafter, in this specification, the filler RS ​​disposed between the protrusion DC-BP and the first portion P1 will be described as a first filling portion, and the filler RS ​​disposed between the protrusion DC-BP and the second portion P2 will be described as a second filling portion.

[0164] Since the filler RS ​​has a flow property due to external heat, the first filling portion may move to the inner space SNK. Here, the inner space SNK may be defined by the first portion P1, the second portion P2, and the protrusion DC-BP.

[0165] On the other hand, unlike the present invention, when the first portion P1 is arranged to surround the second portion P2 in a planar configuration, the internal space SNK is not connected to the external space. In this case, when the first filler portion moves into the internal space SNK due to the pressure of the bump DC-BP, the volume of the internal space may increase due to the bonding of the first and second filler portions. As a result, a lift occurs between the bump DC-BP and the first connection pad portion DP-PDa, deteriorating the electrical connection characteristics.

[0166] According to an embodiment of the present invention, the internal space SNK extends in the first direction DR1 and can be connected to the external space between the electronic component DC and the first connection pad portion DP-PDa. The external space between the electronic component DC and the first connection pad portion DP-PDa can be a space that does not overlap with the bump DC-BP. Since the internal space SNK is connected to the external space, when the first filling portion moves into the internal space SNK, the second filling portion disposed in the current internal space SNK can move to the external space. The second filling portion disposed in the internal space SNK can move along the first direction DR1 to the external space.

[0167] Furthermore, it has been described that the second filling part moves to the external space as the first filling part moves to the internal space SNK, but the present invention is not limited thereto. A portion of the first filling part may also move to the external space.

[0168] As described above, it is possible to prevent the lifting between the bump DC-BP and the first connection pad portion DP-PDa due to the volume of the filler RS ​​provided in the inner space SNK. This will be described later with reference to FIG. Figure 14b and Figure 14c Describe in more detail.

[0169] Figure 10a is a plan view of a pad portion according to another embodiment of the present invention. Figure 10b is a plan view of a pad portion according to another embodiment of the present invention. Figure 11 is a cross-sectional view of a display device according to another embodiment of the present invention.

[0170] refer to Figure 10a , when with Figure 5 Compared with the signal pad portion DL-P shown, the signal pad portion DL-Pa according to another embodiment of the present invention may further include a third signal pad portion DL-PNAz.

[0171] The third signal pad portions DL-PNAz may be arranged at predetermined intervals along the second direction DR2. The third signal pad portions DL-PNAz according to the present invention may electrically connect the signal pad portion SPD to the second signal pad portion DL-PCA. Furthermore, the third signal pad portion DL-PNAz and the first signal pad portion DL-PNA may be integrally formed.

[0172] For example, the third signal pad portion DL-PNAz includes a first sub-pad portion and a second sub-pad portion. The first sub-pad portion is disposed between two adjacent signal pad portions in the signal pad portion SPD. The first sub-pad portion electrically connects the two signal pad portions SPD. A plurality of first sub-pad portions may be provided. The second sub-pad portion includes a second sub-pad portion that electrically connects one of the signal pad portions SPD to the second signal pad portion DL-PCA.

[0173] In particular, connecting to Figure 9b The inner space SNK of the outer space discussed in may be defined by the bump DC-BP, the first portion P1, the second portion P2, and the first sub-pad part of the third signal pad portion DL-PNAz.

[0174] Reference Figure 10b , when with Figure 5 When compared with the signal pad portion DL-P shown, the signal pad portion DL-Pb according to another embodiment of the present invention has substantially the same structure except for a modified structure of the first signal pad portion DL-PNAk.

[0175] The first signal pad portion DL-PNAk includes signal pad portions SPDk spaced apart from each other on a plane. The signal pad portions SPDk may extend in the second direction DR2 and may be spaced apart from each other by a predetermined interval along the first direction DR1. In this case, the signal pad portions SPDk connected to the first signal pad portion DL-PNAk may be spaced apart from each other by a predetermined interval. Figure 9b The inner space SNK of the outer space discussed in the preceding may be defined by the protrusion DC-BP, the first portion P1, and the second portion P2. Figure 10b In the structure of FIG. 5 , the internal space SNK may have a shape extending in the second direction DR2 .

[0176] According to the present invention, each signal pad portion SPDk may face the second signal pad part DL-PCA in the second direction DR2.

[0177] Reference Figure 11 The bump DC-BP includes a first bump portion overlapping with the first connection pad portion DP-PDa and a second bump portion not overlapping with the first connection pad portion DP-PDa. Figure 11 As shown, the second protrusion may be in contact with the third insulating layer 30. Hereinafter, a region CHK where the second protrusion and the third insulating layer 30 are in contact with each other is defined as an inspection region.

[0178] In particular, the plane area of ​​the second protrusion, ie, the inspection area, may be set to 10% to 50% of the total plane area of ​​the protrusion DC-BP.

[0179] According to the present invention, after the ultrasonic bonding process, the contact reliability between the first bump and the first connection pad portion DP-PDa can be grasped by checking the color of the contact area between the second bump and the third insulating layer 30 .

[0180] Figure 12 is a view illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figure 13 It is a graph showing the characteristics of the filler.

[0181] Figure 12 FIG. 1 is an exploded perspective view of ultrasonic bonding between the electronic component DC and the display panel DP of the display device DD. The filler RS ​​is provided between the electronic component DC and the display panel DP and is provided in a film-type. The filler RS ​​can be completely bonded to the display panel DP. Figure 3 The chip region shown is the NDA-DC overlap.

[0182] Reference Figure 12 , a heat / pressure mechanism PS may be provided on the electronic component DC to apply pressure to the electronic component DC. Furthermore, the heat / pressure mechanism PS may apply heat to the filler material RS, the bump DC-BP, and the first connection pad portion DP-PDa provided between the electronic component DC and the display panel DP. According to the present invention, the heat / pressure mechanism PS may apply pressure to the electronic component DC and heat to the filler material RS.

[0183] On the other hand, as described above, the filler RS ​​can change curing characteristics according to the heat transferred from the heat / pressure mechanism PS.

[0184] Reference Figure 13 The horizontal direction of the graph represents temperature T0, and the vertical direction of the graph represents viscosity characteristic HD of the filler RS. During the first period when the temperature of the filler RS ​​increases from the first reference point Ta to the second reference point Tb due to external heat, the viscosity of the filler RS ​​may decrease. For example, the temperature from the first reference point Ta to the second reference point Tb may be 0 degrees Celsius or higher and 30 degrees Celsius or lower.

[0185] Thereafter, the viscosity of the filler RS ​​may increase during the second period, when the temperature of the filler RS ​​increases above the second reference point Tb. That is, the curing characteristics of the filler RS ​​may improve during the second period. Furthermore, when the temperature of the filler RS ​​increases above the third reference point Tc, the viscosity of the filler RS ​​remains substantially unchanged. In other words, by using the third reference point Tc as a reference point, the curing characteristics of the filler RS ​​can be maximized. For example, the temperatures from the second reference point Tb to the third reference point Tc may be 30 degrees Celsius or higher and 190 degrees Celsius or lower.

[0186] As above reference Figure 9bAs described above, when the protrusion DC-BP comes into contact with the first portion P1 by the pressure of the heat / pressure mechanism PS, the first filling portion between the protrusion DC-BP and the first portion P1 may move to the inner space SNK.

[0187] According to the present invention, the flow characteristics of the filler RS ​​can be maintained in the first period when the viscosity characteristics of the filler RS ​​decrease. This is because the solidification characteristics of the filler RS ​​increase when the temperature of the filler RS ​​enters the second period.

[0188] Therefore, during the first period in which the filler RS ​​has the flow property, the second filling portion previously disposed in the inner space SNK may move to the outer space due to the first filling portion moving to the inner space SNK.

[0189] Figure 14a is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figure 14b is an exploded perspective view of a display device according to an embodiment of the present invention. Figure 14c is a perspective view of a display device according to an embodiment of the present invention. Figure 14d is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0190] Reference Figure 14a and Figure 14b A heat / pressure mechanism PS is provided on the electronic component DC to apply pressure and heat HTK to the electronic component DC. The viscosity of the filler RS ​​can be altered by the heat HTK and pressure applied by the heat / pressure mechanism PS. Furthermore, ultrasonic bonding between the bump DC-BP and the first connection pad portion DP-PDa can be performed using the heat HTK and pressure applied by the heat / pressure mechanism PS.

[0191] Since heat is applied to the filler RS ​​by the heat / pressure mechanism PS, the filler RS ​​is provided in a film type. As a result, the filler RS ​​is provided between the first portion P1 of the first connection pad portion DP-PDa and the bump DC-BP. That is, the filler RS ​​may not contact the second portion P2.

[0192] like Figure 14b As shown, the filler RS ​​may be directly disposed on the first portion P1 before ultrasonic bonding. In addition, the inner space SNK defined by the first portion P1, the second portion P2, and the protrusion DC-BP as described above may have a shape extending in the first direction DR1.

[0193] In particular, refer to Figure 14c , heat is applied to the filler RS ​​by the heat / pressure mechanism PS, and pressure is applied to the projections DC-BP by the heat / pressure mechanism PS. This can be seen in reference Figure 13The description is made during the first period.

[0194] During the first period, when the protrusion DC-BP contacts the first portion P1 by external pressure, the first filling portion between the protrusion DC-BP and the first portion P1 may move to the inner space SNK. As a result, the second filling portion disposed between the protrusion DC-BP and the second portion P2 may move in the first direction DR1. Figure 14c As shown in FIG, the filler RSm moving along the first direction DR1 may not overlap with the bump DC-BP.

[0195] Despite Figure 14c Not shown in FIG. 1 , the filler RS ​​may be provided on the second connection pad portion DP-PDb.

[0196] Afterwards, refer to Figure 14d , ultrasonic vibration UK can be applied to the interface between the first part P1 and the protrusion DC-BP. Ultrasonic vibration UK applied to the interface between the first part P1 and the protrusion DC-BP can be applied to the interface between the first part P1 and the protrusion DC-BP. Figure 13 It is performed during at least one of the first time periods shown and may also be performed during the second time period.

[0197] As described above, the embodiments are disclosed in the drawings and the specification. Although specific terms are used, they are not intended to limit the meaning or scope of the invention described in the claims, but are merely used to illustrate the invention. Therefore, those skilled in the art will appreciate from the above that various modifications and other equivalent embodiments are possible. Therefore, the actual scope of protection of the present invention should be determined by the technical scope of the appended claims.

[0198] Industrial Applicability

[0199] The technology of bonding an electronic component to a display panel using ultrasonic bonding can improve the connection reliability between the electronic component and the display panel. Therefore, the present invention for bonding an electronic component to a display panel using ultrasonic bonding has high industrial applicability.

Claims

1. A display device comprising: a display substrate defining a display area and a non-display area adjacent to the display area; a signal pad portion overlapping the non-display area and including a first signal pad portion and a second signal pad portion, the second signal pad portion facing the first signal pad portion in one direction and spaced apart from the first signal pad portion on a plane; an insulating layer configured to cover the signal pad portion and disposed on the display substrate; a connection pad portion disposed on the insulating layer and comprising a first connection pad portion and a second connection pad portion, the first connection pad portion being configured to overlap with the first signal pad portion, the second connection pad portion being electrically connected to the first connection pad portion and in electrical contact with the second signal pad portion through a contact hole defined in the insulating layer; an electronic component comprising a bump in electrical contact with the first connection pad portion; as well as a filler disposed between the electronic component and the connection pad portion, wherein the first signal pad portion includes a plurality of signal pad sections spaced apart from each other on the plane, The first connection pad portion includes a first portion and a second portion alternately and repeatedly arranged along the one direction, The first portions of the first connection pad portions overlap with the signal pad portions, respectively, and the second portions of the first connection pad portions do not overlap with the first signal pad portions. The second portion is recessed in a direction away from the first portion toward the display substrate, and forms a step portion between the first portion and the second portion; as well as The filler is in contact with each of the second portions and is not in contact with each of the first portions.

2. The display device according to claim 1, wherein Each of the first portions is in contact with the projection, and each of the second portions is not in contact with the projection.

3. The display device according to claim 2, wherein: The filler is disposed in an inner space defined by the first portion, the second portion, and the protrusion, and The inner space is connected to a space between the electronic component and the first connection pad portion that does not overlap with the bump.

4. The display device according to claim 1, wherein The filler overlaps the insulating layer.

5. The display device according to claim 1, wherein Each of the signal pad portions is arranged in the one direction and extends in another direction perpendicular to the one direction. The display device according to claim 5 , wherein: Only any one of the signal pad portions directly faces the second signal pad portion in the one direction.

7. The display device according to claim 5, wherein: The signal pad portion further includes a third signal pad portion electrically connected to the signal pad part and the second signal pad portion, the third signal pad portion includes a first sub-pad portion disposed between the signal pad portions and a second sub-pad portion configured to connect any one of the signal pad portions to the second signal pad portion, and The first signal pad portion and the third signal pad portion are provided in an integral shape.

8. The display device according to claim 1, wherein Each of the signal pad portions extends in the one direction, and the signal pad portions are arranged in different directions perpendicular to the one direction.

9. The display device according to claim 8, wherein Each of the signal pad sections faces the second signal pad portion in the one direction.

10. The display device according to claim 1, wherein The first signal pad portion and the second signal pad portion are electrically insulated from each other.

11. The display device according to claim 1, wherein The insulating layer includes a plurality of sub-insulating layers, and The contact hole passes through the sub-insulating layer, and the second connection pad portion is in electrical contact with the second signal pad portion through the contact hole.

12. The display device according to claim 1, wherein The contact hole does not partially overlap with the first connection pad on the plane.

13. The display device according to claim 1, wherein The protrusion includes a first protrusion portion and a second protrusion portion, the first protrusion portion is configured to partially overlap with the first connection pad, and the second protrusion portion does not partially overlap with the first connection pad, and The second protrusion contacts a portion of the insulating layer.

14. The display device according to claim 13, wherein: The planar area of ​​the second protrusion is 10% to 50% of the total planar area of ​​the protrusion.

15. A method for manufacturing a display device, the method comprising: Providing a display substrate having a pad portion provided thereon, an electronic component, and a filler, wherein the pad portion includes a first pad portion and a second pad portion, the electronic component includes a protrusion of the first pad portion facing the pad portion, and the filler is between the pad portion and the electronic component; bringing the bump into contact with the first pad portion by applying pressure to the electronic component while applying heat to the filler; and applying ultrasonic vibration to the protrusion and the first pad portion, The first pad portion includes a first portion and a second portion that are alternately and repeatedly arranged in one direction. The first portion is in contact with the protrusion, and the second portion is not in contact with the protrusion, and When the protrusion comes into contact with the first portion, the filler between the protrusion and the first portion moves to an inner space between the second portion and the protrusion and does not come into contact with the first portion.

16. The method according to claim 15, wherein The viscosity of the filler decreases during a first period when the temperature of the filler increases from a first reference point to a second reference point by the heat, and the filler solidifies during a second period when the temperature of the filler increases above the second reference point.

17. The method according to claim 16, wherein During the first period, the protrusion is in contact with the first portion.

18. The method according to claim 17, wherein: During the first period, the filler disposed in the inner space moves to the outer space not overlapping with the protrusion.

19. The method according to claim 16, wherein The applying of the ultrasonic vibration is performed during at least one of the first time periods.

20. The method according to claim 15, wherein The pad portion includes: a signal pad portion disposed on the display substrate and including a first signal pad portion and a second signal pad portion, the second signal pad portion facing the first signal pad portion in the one direction and spaced apart from the first signal pad portion on a plane; and a connecting pad portion covering the signal pad portion and disposed on an insulating layer disposed on the display substrate, In which, the connecting pad portion includes a first connecting pad portion and a second connecting pad portion, the first connecting pad portion corresponds to the first pad portion and overlaps with the first signal pad portion, and the second connecting pad portion corresponds to the second pad portion and is electrically contacted with the second signal pad portion through a contact hole defined in the insulating layer.

Images