Using multiple quantized digitally controlled supply voltages for multiple amplifier stages

Abstract

A method and system for power amplification using a digitally quantized power supply with multiple amplifiers is disclosed herein. In one embodiment, a time-varying envelope signal is sampled, quantized, and decomposed into several individually amplified component signals, which are then combined to form a desired amplified version of the quantized time-varying envelope. The amplitude, phase, and / or frequency characteristics of one or more signals and the supply voltage and source current of one or more amplifiers are digitally controlled based on information provided by the quantization process and slow and fast power control information. The amplitude, phase, and / or frequency characteristics of the one or more component signals to be amplified are controlled to provide the desired amplitude, phase, frequency, and / or spectral characteristics of the desired quantized version of the time-varying envelope signal.

Description

Technical Field

[0001] The present invention generally relates to amplification of a signal of varying envelope using an amplifier stage having a plurality of amplifiers connected in parallel. The amplifiers are fed by a collection of quantized collector supply voltages or quantized drain voltages (denoted as V dd ) and controlled by a collection of signal amplification performed in a transceiver used in telecommunication equipment for mobile communications, wireless communications, and wired communications systems. Background Art

[0002] In modern wireless communications, spectral efficiency should be fully optimized to be able to support high data rates. In limited bandwidth systems, this is accomplished by employing high-order modulation methods that are characterized by high peak-to-average ratio (PAR) signals that require significant back-off levels for linear operation [1]. This approach is not always suitable for using conventional power amplifiers (PAs) because the PA should be designed so that it can handle peak power levels, while in general, it needs to operate at much lower average output powers [2]. Traditionally, linear PAs are biased to deliver output powers corresponding to the value of the peak radio frequency (RF) output power. The peak RF output power condition generally occurs when the RF input signal to the PA is at a maximum value. The traditional approach to linear amplification of varying envelope modulated signals is to "back-off" the output power of a linear Class A or Class AB PA until the distortion level is within an acceptable range. However, when the PA "backs off" from the peak RF output power condition, the excess direct current (DC) input power must be dissipated by the PA because it is not converted into useful RF output power. As a result, the PA efficiency is significantly reduced, especially for high PAR signals, which is the case for signals typically used in LTE and to be adopted in next generation mobile communication systems.

[0003] Two metrics commonly used to measure the efficiency of a power amplifier include the drain / collector efficiency (η) and the power added efficiency (PAE). The drain / collector efficiency η gives a measure of how much DC input power to the PA is converted to RF output power and is given by the ratio of the PA's RF output power to the PA's DC input power (η = P out / P DC ). The main reason why PAE is different from the drain / collector efficiency η is that it takes into account the power of the input RF signal of the PA. PAE is given by:

[0004]

[0005] Among them, P out is the RF output power of the PA, P DC is the DC input power of the PA, and Pin is the power of the RF input signal to the PA. Therefore, reducing P DC The advantages become obvious.

[0006] The efficiency of an RF power amplifier has a significant impact on the battery life of a portable device, such as a portable transmitter, because the amplifier typically consumes a large amount of the power used by the device. Unfortunately, the traditional trade-off between linearity and efficiency of a power amplifier is such that the more linear the power amplifier, the lower its power efficiency.

[0007] In power amplifiers, there is often a complex trade-off between linearity and power efficiency. Linearity is determined by the operating range of the power amplifier on a characteristic curve that relates the input to the output variable of the power amplifier - the higher the linearity of the operating range, the more linear the PA is said to be. Linearity is a desired characteristic of a PA. In one aspect, for example, it is desirable for a power amplifier to uniformly amplify signals of varying amplitude and / or phase and / or frequency. Accordingly, linearity is an important determinant of the output signal quality of the PA. Modern wired and wireless communication systems with stringent requirements for spectral and power efficiency further emphasize the above trade-off. For example, wireless communication signals, such as orthogonal frequency division multiplexing (OFDM) [3], code division multiple access (CDMA) [4], wideband CDMA (W-CDMA), single carrier with frequency domain equalization (SC-FDE) [5], and orthogonal frequency division multiple access (OFDMA), are characterized by envelope fluctuations and high peak-to-average power ratio (PAPR), which can compromise amplification efficiency [6, 7, 8]. When a nonlinear amplifier is used, the larger the PAPR of the signal, the larger the nonlinear distortion generated. Other multi-carrier technologies, such as filter bank multi-carrier with offset quadrature amplitude modulation (FBMC-OQAM) technology, also have the same disadvantages.

[0008] Since the PA is one of the most important components in the transmitter architecture, it represents the most power-hungry device. For example, in a base station under maximum load, the PA power consumption accounts for more than 50% of the DC power consumption of the entire system. In addition to thermal issues, operating a high-power system at back-off levels also increases system complexity [9].

[0009] Over the years, several techniques have been proposed to improve the efficiency of PAs, for example, envelope elimination and restoration (EER) [10, 11, 12], predistortion [13, 14], Doherty [15, 16, 17], linear amplification with nonlinear control (LINC) [18, 19, 20, 21, 22, 23], and envelope tracking (ET) [24, 25, 26, 27, 28].

[0010] EER technology uses a combination of a switch-mode PA and an envelope remodulation circuit. However, this architecture has several disadvantages. Both the amplitude and phase signals are generated using nonlinear operations. Therefore, the bandwidth of the original I / Q signal is significantly extended in phase and in the envelope signal path. The efficiency of the EER technology depends largely on the efficiency of the envelope amplifier (EA). Since the overall system efficiency is now the product of the efficiency of the envelope amplifier and the RF PA, a decrease in the EA efficiency will offset any improvement in the efficiency of the RF PA.

[0011] In a basic Doherty power amplifier (DPA) scheme, the main amplifier is a class B or class AB amplifier (class AB is preferred for its higher linearity). However, it is designed to maintain its maximum output voltage swing, and therefore its maximum efficiency, for any input power level between the so-called breakpoint and the maximum value. In a classic DPA implementation, the main maximum current contributes half of the maximum total current, which sets the breakpoint to 6dB output power back-off (OBO). The auxiliary device is turned off due to input power below the breakpoint value and turned on when the input power increases above this level. When activated, it injects current into the common load, thereby contributing to the total output power and modulating the load seen by the main amplifier. The disadvantage of this architecture is the limitation in terms of back-off and bandwidth. In addition, due to the non-ideality of the device, practical DPA implementations present other problems in terms of operating frequency and linearity.

[0012] LINC technology separates the input signal S(t) into two constant envelope signals, which are amplified by two high-efficiency nonlinear amplifiers (e.g., class D and class E amplifiers) respectively. In traditional LINC, the input signal S(t) with a time-varying envelope is decomposed into two constant amplitude signals S1(t) and S2(t), which can be summed to provide the desired output signal S out(t). By out-of-phase the two constant envelope signals, a time-varying envelope output signal is created as the sum of two constant envelope signals S1(t), S2(t). Because the two signals S1(t), S2(t) have constant amplitude, they can be synthesized with high-efficiency PAs, including partial and full switch mode designs, such as D, E, F, E / F class and current mode D, inverse F, φ, etc. These amplifiers can be made efficient in part because they do not need to have the ability to provide linear output control. Combining the two constant amplitude outputs S1(t), S2(t) in a power combining network enables the net output amplitude to be controlled via the relative phase of the two constituent components S1(t), S2(t). However, the LINC transmitter scheme is limited by the envelope characteristics of its input signal. Since the amplitude information of the band-limited signal is embedded in the phase of the LINC component, the highly fluctuating envelope produces a constant envelope LINC component with a high phase content, which is the reason for the spectrum expansion of the LINC component. Another challenge with LINC is how to accomplish power combining, especially since many high-efficiency PAs are highly sensitive to load impedance and their performance and efficiency can be severely degraded due to interactions between PAs.

[0013] ET technology uses a linear PA and a supply modulation circuit in which the supply voltage tracks the input envelope. ET systems can improve the efficiency of RF PAs for amplification of modulated RF signals with high PAPRs, even if more complex supply modulators are required. By replacing the fixed supply with a dynamic supply voltage, the DC power consumption of ET PAs is reduced and the efficiency is significantly increased compared to conventional PAs. ET involves using envelope tracking of the input signal to the amplifier and using the detected envelope to vary the amplifier operation. In an ET system, a variable power supply is used to power the amplifier. The envelope power level of the input signal is monitored, and the power supplied to the power amplifier or, typically, to the (multiple) final stages of the power amplifier varies based on the monitored envelope level. More specifically, the power supplied to the amplifier is varied to just enough to reproduce the power level required by the amplifier at a given moment. For low output powers, the supply voltage is reduced, and for high output powers, the supply voltage is increased. However, while envelope tracking amplifiers are easier to implement than their EER counterparts, they offer less efficiency advantages because a linear RF PA needs to be used.

[0014] The device proposed in this application for multiple quantized digitally controlled supply voltages for multiple amplifier stages follows a different approach, since it is applied to the quantized values ​​of the time domain samples of the envelope of the signal. Can vary, and the size of the letters depends only on the number of quantization bits. Therefore, there is no direct relationship between the quantization constellation and the modulation applied to the signal whose time domain samples are quantized. Therefore, the amplification process disclosed herein implements linear amplification of a signal with a time-varying envelope by converting the time domain sample values ​​into quantized values ​​and decomposing the quantized symbols into a sum of quasi-constant or constant envelope signals that can be amplified by a nonlinear amplifier. In addition, since the input to the quantizer is the time domain samples of the envelope of the signal, this decomposition can be applied to any signal and does not have a specific constellation as a target.

[0015] The sample-based quantizer generates quantization bits related to the amplitude and phase of the components, wherein each amplified version of the quantized version of the envelope can be decomposed. In one embodiment, the quantization bits are used to select the number of components to be applied to N in a lookup table. bq An amplifier with V dd N bq values, and to generate a set of in-phase components and quadrature components with different phases and amplitudes, which are combined to generate a set of in-phase components and quadrature components to be applied to N bq N current sources or switching amplifiers bq There are N signals. bq Each V dd Applies only to N bq Thus, amplifier back-off is avoided because each amplifier is specific to the corresponding V dd The amplified version of the quantized envelope is obtained by bq In another embodiment, the quantization bits are used to select the N bq A collection of switching amplifiers with V dd N bq The main difference is the fact that the amplified version of the envelope is N bq The result of combining the outputs of N amplifiers, each of which represents a quantized amplified version of the envelope in which it can be decomposed. Therefore, the method and apparatus disclosed in the present application are not limited to a specific modulation or constellation, and the amplified version of the quantized envelope is in N bq The output of each amplifier is the result of a combination of the complex output signals. Another key difference is that the V dd The control can be constant over time because it depends only on the quantization rule and the total output power required for each transmitted information block. This also means that each amplifier is optimized for a specific power output according to the quantization rule defined by the quantizer and the lookup table, for Nbq Each amplifier in a set of parallel amplifiers is optimized differently. Apart from the above differences, the distortion is mainly due to the quantization error ε QT , the quantization error is defined in terms of the dynamic range of the envelope of the signal received as input. Considering the main features of this new concept of multiple quantized digitally controlled amplifier stages, it follows a completely different technique from that cited in the literature [10-28]. Envelope tracking is not performed by N bq The envelope is a combination of the outputs of the amplifiers. Neither is considered EER because it does not use a combination of switch mode PAs nor an envelope remodulation circuit. Now, the complex amplitude and phase signals are generated by a quantizer that provides control information used to select V that is optimized for each amplifier individually. dd By using a constant envelope signal at the input of each amplifier, bandwidth expansion of the original I / Q signal is also avoided.

[0016] Reference

[29] discloses an integrated transceiver that uses ET techniques using digital signal processing within the transceiver to perform envelope extraction and provide appropriate delay matching of the envelope and main signal paths. The power supply voltage changes in response to changes in the envelope of the input signal directed to the power supply, depending on the power level supplied to the amplifier circuit (by varying the supply voltage). A digital processing unit is used to detect the input signal envelope and provide changes in the power supply level. The processing circuit also includes an envelope predistortion circuit to cope with nonlinearities in the envelope tracking power supply. The multi-V dd The approach of digitally controlled multiple amplifier stages does not require envelope power modulators, which means that the complexity of the amplifier power supply structure is less. Also, since the signal submitted to each amplifier has a constant envelope, nonlinear effects are avoided, which also means that back-off is avoided in each amplifier and switching amplifiers can be used in each branch. Also, according to the concepts disclosed in this application, the quantizer provides digital control information to configure V dd and the desired signal from the output of an amplified version of the control envelope. Distortion occurs primarily due to the V dd There are quantization effects associated with the definition of the set of values, however, these effects can be minimized by increasing the number of quantization levels.

[0017] In document

[30] , a digital control component is used to digitally generate an envelope voltage to the PA by switching a resistor coupled between at least one supply voltage and the PA. The disclosed device uses a digital control component to generate a digital code in response to an envelope input signal received or detected at an envelope input terminal of the digital control component. The digital control code can digitally operate or control various combinations of switches, which can be functions of the envelope input voltage and generated by the digital control code, and can promote envelope tracking to achieve very high modulation bandwidth and reduce output noise levels. Based on the envelope, the digital control component generates a digital control code that promotes switching of a resistor value or resistor that can be defined by a switch group (e.g., a transistor). The digital control code provides different combinations of switches that are coupled between one or more different supply voltages to generate an envelope voltage to the PA and track the input signal. Similarly, for other ET systems, the envelope power level of the input signal is monitored, and the power supplied to the PA or generally to the (multiple) final stages of the power amplifier varies based on the monitored envelope level. In contrast to the embodiment disclosed in

[30] , the multi-V dd The device and corresponding embodiments implement digital control based on a quantizer and a mapper, which maps each envelope sample into several components. The quantizer is used to control N bq The number of amplifiers connected in parallel is N bq Different V dd Similarly, there is no need to dynamically change V according to the sample value of the envelope at each moment. dd This is additional because the V dd The set is defined by a quantizer and a mapper, which should be in N bq The output of the amplifier ensures an amplified version of the quantized value of the envelope sample. Since the quantizer plus mapper can have a V dd The lookup table of different sets of values, so for different information blocks, apply V dd N bq The set of amplifiers may be changed over time according to a slow power control that adapts the transmit power to the channel conditions. Thus, the ET performed by the apparatus of the application is performed on a sample basis by the quantizer, and changes in the samples do not necessarily change the V applied to the amplifiers. dd A collection of V, possibly with a fixed V along each data block dd In addition, we have multi-V with multi-amplifier dd configuration, in which each V dd will affect the corresponding amplifier, which is characterized by power output and its size is similar to N bq The amplifier is different from the other amplifiers in the set.

[0018] Document

[31] discloses an envelope tracking supply modulator for multiple PAs, wherein the envelope tracking supply modulator is configured to provide a separate supply voltage to each of the multiple PAs, the supply voltage being modulated based on the envelope of the corresponding RF input signal to the PA. In this configuration, each modulated supply voltage is composed of a DC component and an alternating current (AC) component, and the DC component for each modulated supply voltage is generated by a main switching regulator shared by multiple PAs (each PA is associated with a different information signal). The envelope tracking supply modulator is configured to provide a separate supply voltage to each of the multiple PAs, the supply voltage being modulated based on the envelope of the corresponding RF input signal to the PA. Each modulated supply voltage is composed of a DC component and an AC component, and the DC component for each modulated supply voltage is generated by a main switching regulator shared by multiple PAs. By sharing the main switching regulator, the implementation complexity is reduced when compared to other implementations using multiple envelope tracking PAs (such as a transmitter with multiple antennas, each of which can be driven by a separate envelope tracking PA). In these cases, each of the multiple envelope tracking PAs are traditionally implemented independently of one another without any sharing of components between them, which can result in higher component count, larger die and / or board area, and increased monetary cost.

[0019] In contrast to the embodiment disclosed in

[31] , the multi-digit V dd The device implements a multi-V dd scheme, in a sense, we have a single one applied to N bq Each amplifier in the set of amplifiers has N bq Different V dd A collection of V dd The values ​​are not independent because the amplified version of the envelope is the result of the sum of all amplifier outputs. The digital mapper quantizer quantizes the envelope and decomposes the quantized value into components with constant amplitude. Changes to the envelope are tracked by changing the phase of the amplified and later combined components. Another key difference is the fact that each V applied to each amplifier dd can be kept fixed over the information block, varying only the phase of the amplified signal over the different samples. Thus, each amplifier can be operated at a fixed operating point near the compression point, and the design and size of each amplifier can be optimized for a specific output power, which varies for each amplification branch. This is possible because the tracking of the envelope is done by a digital mapper consisting of a quantizer and a mapper that selects the V to be applied to the amplifier during the duration of each information block. ddand the phase that may change with the quantization of the sampled values. The quantizer of the digital mapper also controls N bq The number of amplifiers connected in parallel is N bq Different V dd The set of values ​​provides the control information and delays required to implement the different phases of the components. Therefore, each amplifier’s V dd It does not change dynamically according to the sampled value of the envelope at each instant. In addition, the digital mapper can change V by selecting another set in the lookup table according to the information provided by the slow power control. dd , the slow power control adapts the transmitted power to the channel conditions. This means that V dd Different sets of can be selected over time in the lookup table and applied to N bq The ET performed by this device can therefore be viewed as the result of a combination of several amplifier outputs that are fixed along each block. This means that we have multiple V dd configuration, but with different V dd The value will affect different amplifiers having different power outputs, which is not the case for the device disclosed in

[31] .

[0020] Reference

[32] discloses an ET system with a new behavioral model, which has improved performance in the modeling and linearization techniques of ET PA. The proposed model uses a memory polynomial (MP) model of a PA with a fixed supply voltage as a prototype, and modulates the coefficients and the envelope signal that controls the supply voltage of the ET PA. Similarly, the proposed new model can be adopted in the digital predistortion technology applied in the ET PA system. Again, there is no relationship between the ET disclosed in

[32] and the device of this application.

[0021] Reference

[33] also discloses an envelope tracking technique in which a 1.5-bit (level 3) envelope amplifier is used to improve the overall efficiency of a broadband high linearity envelope tracking power amplifier. To improve performance, the authors proposed an envelope amplifier combined with a multi-level quantizer for the switching stage. In order to reduce the switching noise power, an envelope amplifier using a multi-level switching stage is adopted, which allows the ripple current to be reduced at the same switching frequency. The efficiency is improved because the power loss in the switching stage is reduced due to the slightly lower switching frequency, and the linear stage is able to reduce power consumption due to the smaller quantization error.

[0022] A major difference of the device disclosed in this application is the fact that ET is replaced by envelope quantization (EQ) of the envelope samples which defines the envelope quantization to be applied to N parallel connected amplifiers with different power outputs. bq The N bq V ddThe quantizer also provides control information for configuring the phase (delay) of the in-phase and quadrature signal components, where the quantized envelope is decomposed and the control information is transmitted to the quantizer with different V dd N bq In this application, it is not necessary to switch V at the same sampling frequency rate. dd value, because V dd The set of values ​​may remain constant across the entire data block. Slow power control may be applied to vary V between consecutive data blocks. dd Apart from this, fast switching is only required if fast power control is employed for the duration of each block. However, even in this case, only the two highest V dd This also means that the complexity of the supply modulator is reduced, because for each amplifier in the multi-amplifier stage, V dd The value is constant or nearly constant over time.

[0023] In

[12] , a wideband envelope tracking (WBET) based power amplifier system design suitable for OFDM wireless LAN systems is disclosed. Particular emphasis is given to the development of an adaptive time alignment algorithm for time alignment between the envelope and the RF path in order to minimize distortion and EVM that affect both EER and WBET performance. Due to the nonlinear behavior of the WBET amplifier, pre-distortion is also implemented in the proposed system to compensate for the distortion caused by the time mismatch and the resulting nonlinear limiting behavior.

[0024] References

[34] and

[35] also disclose ET systems and methods for improving power modulators. In

[34] , an ET PA analysis is disclosed for characterizing operating behavior and identifying optimal ET operating points. To this end, the PA is modeled by sweeping the input power and supply voltage. A power control stage for optimal ET operation over a wide output power range is also presented. The effect of delay mismatch on the characteristics of the ET PA is also described to assist the time alignment algorithm. Since the supply voltage of the RF PA is modulated by the supply modulator, the overall efficiency of the RF PA is proportional to the efficiency of the supply modulator. Therefore, the supply modulator is optimally designed to have high efficiency without generating significant distortion. In order to achieve high efficiency and broadband operation, a supply modulator has been studied based on a hybrid switching structure. Reference

[36] discloses an ET system digitally controlled by a digital self-oscillating modulator (DiSOM), which is suitable for high-bandwidth digitally controlled envelope tracking power supplies. Compared with conventional counter-based digital PWM (DPWM) modulators, the main advantage of DiSOM is that it allows higher sampling frequencies in digital control schemes for DC-DC converters. The DiSOM is characterized by a purely digital modulator that receives a duty cycle command from an external source and a digital compensator that typically calculates the required duty cycle to adjust the output voltage to a reference set point. Thus, the power consumption of the RF PA is reduced by adapting the supply voltage of the RF PA to the RF output amplitude. The baseband processor and the modulator module generate an RF input and an RF envelope signal for the RF PA, which is used as a reference for the tracking power supply. In this case, the tracking power supply is digitally controlled. The proposed DiSOM includes one or more control loops including a switching output in the control loop and it does not have a free-running counter to set the switching frequency. Contrary to what is mentioned in these two documents, in the device of this application, there is no need to change the supply to each amplifier, since changes in the quantized envelope are reflected in the N bq The sum of the amplifier outputs is equal to the amplified version of the quantized envelope in the phase of the components amplified in the branches. Likewise, the time alignment requirements are relaxed because the multi-V dd No feedback is required in digitally controlled multiple amplifier stages.

[0025] Information Disclosure Statement

[0026] Patents and publications relevant to the patentability of the present claims relate to multiple quantized digitally controlled supply voltages for multiple amplifier stages.

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[0036]

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[0037]

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[0038]

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[0039]

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[0040]

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[0043]

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[0044]

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[0045]

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[0046]

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[0047]

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[0048]

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[0049]

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[0050]

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[0054]

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[0055]

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[0056]

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[0057]

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[0058]

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[0059]

[33] J. H. Kim, G. D. Jo, J. H. Oh, Y. H. Kim, K. C. Lee, and J. H. Jung, “3.54 GHz 10-W envelope tracking amplifier with 43% efficiency utilizing the 1.5-bit-high efficiency envelope amplifier,” in Proceedings of the IEEE Conference on Power Amplifiers for Wireless and Radio Applications, January 2011, pp. 21–24.

[0060]

[35] J. Kim, D. Kim, Y. Cho, D. Kang, B. Park, K. Moon, and B. Kim, “Analysis of envelope-tracking power amplifier using mathematical modeling,” IEEE Transactions on Microwave Theory and Techniques, Vol. 62, No. 6, June 2014, pp. 1352–1362.

[0061]

[36] LT Jakobsen and MAE Andersen, “Digitally controlled envelope tracking power supply for an RF power amplifier,” Proceedings of the IEEE International Telecommunications and Energy Conference (INTELEC), September 2007, pp. 636–642. Summary of the invention

[0062] In one embodiment, a time-varying envelope signal is sampled, quantized, and decomposed into several component signals that are individually amplified and then combined to form a desired amplified version of the quantized time-varying envelope. The amplitude, phase, and / or frequency characteristics of one or more signals and the V dd The and currents are controlled to provide desired amplitude, phase, frequency and / or spectral characteristics of a desired amplified, quantized version of the time-varying envelope signal.

[0063] In another embodiment, the time-varying envelope signal is decomposed into an in-phase component and a quadrature component, which are sampled, quantized, and decomposed into several individually amplified quasi-constant or constant envelope constituent signals, which are then combined to form a desired quantized version of the time-varying complex envelope signal. The amplitude, phase, and / or frequency characteristics of one or more signals are controlled to provide the desired amplitude, phase, frequency, and / or spectral characteristics of the desired quantized version of the time-varying envelope signal.

[0064] In all embodiments, the constituent signals are amplified and then recombined to construct an amplified quantized version of the original time-varying envelope signal.

[0065] Embodiments of the present invention may be practiced with a modulated single-carrier signal or a modulated multi-carrier signal.

[0066] Embodiments of the present invention may be implemented using analog and / or digital control. The present invention may be implemented using analog components or a combination of analog and digital components. Embodiments of the present invention may be implemented as digital circuits and implemented using lookup tables. In modern radio transmission systems, at least a portion of the signal processing is typically performed digitally. Digital processing is also a method for multi-V dd The implementation of a digitally controlled system provides a degree of flexibility. Examples of digital circuits that may be used are a Field Programmable Gate Array (FPGA), a microprocessor or a DSP.

[0067] Additional features and advantages of the present invention will be set forth in the following description. Additional features and advantages will be apparent to those skilled in the art based on the description set forth herein, or may be learned through practice of the present invention. The advantages of the present invention will be realized and obtained through the structures and methods particularly pointed out in the written description and claims thereof and the accompanying drawings.

[0068] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of embodiments of the invention as claimed.

[0069] Embodiments of the invention are defined in the dependent claims. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Various aspects of the embodiments of the present invention will be described with reference to the accompanying drawings, wherein substantially similar reference numerals represent identical or functionally similar elements. Various aspects of the embodiments disclosed herein, including the features and advantages of the present invention summarized above, are more fully described in the detailed description in conjunction with the drawings, wherein:

[0071] Figure 1 is a process flow diagram embodiment of a method of using multiple quantized digitally controlled supply voltages for multiple amplifier stages utilizing current source amplifiers.

[0072] Figure 2A is a block diagram illustrating an exemplary embodiment of an apparatus for using multiple quantized digitally controlled supply voltages for multiple amplifier stages, without requiring that the quadrature component signals be multiplied by a periodic signal at an intermediate frequency before being upconverted for current source amplifiers.

[0073] Figure 2B is a block diagram illustrating an exemplary embodiment of an apparatus for using multiple quantized digitally controlled supply voltages for multiple amplifier stages, where the resulting quadrature component signals are multiplied by a periodic signal at an intermediate frequency before being upconverted for current source amplifiers.

[0074] Figure 3 is a process flow diagram embodiment of a method of using multiple quantized digitally controlled supply voltages for multiple amplifier stages using a switching amplifier.

[0075] Figure 4A is a block diagram illustrating an exemplary embodiment of an apparatus for using multiple quantized digitally controlled supply voltages for multiple amplifier stages, for switching amplifiers, without requiring that polarity-free quadrature component signals be multiplied by a periodic signal at an intermediate frequency prior to being upconverted.

[0076] Figure 4B is a block diagram illustrating an exemplary embodiment of an apparatus for using multiple quantized digitally controlled supply voltages for multiple amplifier stages, for switching amplifiers, where the resulting polarity quadrature component signals are multiplied by a periodic signal at an intermediate frequency before being up-converted.

[0077] Figure 5 is a block diagram illustrating an exemplary embodiment for implementing a digital mapper employed in utilizing multiple quantized digitally controlled supply voltages for multiple amplifier stages.

[0078] Figure 6 is a block diagram illustrating an exemplary embodiment for implementing a class A amplifier stage in a method of using multiple quantized digitally controlled supply voltages for multiple amplifier stages.

[0079] Figure 7is a block diagram illustrating another exemplary embodiment for implementing a class-D amplifier stage when multiple quantized digitally controlled supply voltages are used for multiple amplifier stages. DETAILED DESCRIPTION

[0080] Table of contents

[0081] 1. Introduction

[0082] 1.1. Decomposition of time-varying envelope signals into constant envelope components

[0083] 2. Method and system for using multi-quantized digitally controlled supply voltage for multiple amplifier stages (MQDCPSVMAS)

[0084] 2.1. Using Multi-Quantized Digitally Controlled Supply Voltages for Multiple Amplifier Stages with Current Source Amplifiers

[0085] 2.2. Use of Multi-Quantized Digitally Controlled Supply Voltages for Multiple Amplifier Stages with Switching Amplifiers

[0086] 3. Multiple Amplifier Stages Embodiment

[0087] 4. Summary

[0088] 5. Conclusion

[0089] 1. Introduction

[0090] This article describes methods, apparatus, and systems for using multi-quantized digitally controlled supply voltages for multiple amplifier stages (MQDCPSVMAS). Sections 2 and 3 provide a high-level description of the method and system of MQDCPSVMAS according to embodiments of the present invention.

[0091] Some definitions provided in this section are for convenience only and are not limiting. Based on the overall teaching provided herein, the meanings of these terms will be apparent to those skilled in the art.

[0092] The modulated signal can be expressed as s(t)=s I (t)cos(ω c t)+js Q (t)sin(ω c t), where ω c =2πf c represents the angular frequency, f c represents the carrier frequency and s I (t) and s Q (t) represent the in-phase component and the quadrature component respectively. The signal can also be expressed as To describe, represents the complex envelope, s I (t) represents the in-phase component, sQ (t) represents the orthogonal component, and the signal envelope is given by is given. When e(t) is invariant along time, the signal is called a constant envelope signal. A time-varying envelope signal is one in which e(t) varies with time. Having both non-constant envelope and phase, s(t) is called a time-varying complex envelope signal. The dynamic range (DR) of an envelope represents the range of values ​​over which the envelope of a signal varies. The dynamic range of the in-phase component (DRi) represents the range of values ​​over which the in-phase component varies. The dynamic range of the quadrature component (DRq) represents the range of values ​​over which the quadrature component varies.

[0093] For purposes of convenience and not limitation, a time-varying complex envelope signal is sometimes referred to herein as a time-varying envelope signal.

[0094] 1.1 Decomposition of time-varying envelope signal into constant envelope components

[0095] In a time-varying envelope signal, the envelope value can take any value within the dynamic range, and the number of possible values ​​is infinite. Through the process of quantization, the envelope can be discretized by limiting the possible values ​​to the quantized values. A finite set of N QL Represents the number of quantization levels, that is, the size of the letters of the quantization symbols. s The time domain sample representation of the time-varying envelope signal is s(nT s )=s n , and the corresponding in-phase component and quadrature component are represented as s l (nT s )=s nl and Q (nT s )=s nQ . (nT s )=s n 、s I (nT s )=s nl and Q (nT s )=s nQ The dynamic directions of are DR, DRi and DRq. For the purpose of convenience and not limitation, it is assumed that DRi = DRq.

[0096] The quantizer takes the input signal s n The time domain sampling is converted from The quantized symbol s is obtained from the discrete alphabet of possible quantized symbols n，QT . N bq Quantized bits and The quantization level can be based on the maximum quantization error is defined as, where 2Δ represents the quantization interval between two adjacent quantization symbols. bq Quantization bits Used in N m ≤N bq The polar component (i.e., N m Phase and N m Amplitude), where each quantization level can be decomposed. pass Convert to polar coordinates From quantizer value or sign Each symbol in the finite set of can be represented as N m ≤N bq The sum of polarity components, which are quantized values ​​s n，QT The result of the decomposition into polar or complex components is given by:

[0097]

[0098] use represents the binary representation of i, Represents Bit The polar coordinate representation of Representatives n The i′th polar component of m is the non-empty complex coefficient c of the decomposition equation cited above i The number of coefficients (the total number of ). For example, for N b =6 and a symmetric dynamic range DR (using the value zero as reference), the quantization levels are ±pΔ±jkΔ, where p=1,3,5,7 and k=1,2,35,7, which can be given by:

[0099]

[0100] Among them, for c1=Δ, c2=jΔ, c4=2Δ, c8=j2Δ, c 16 =4Δ,c 32 =j4Δ and c i =0.

[0101] Similarly, quantization can be done by two quantizers, each quantizer is used to quantize the in-phase component and the orthogonal component respectively. nl The time domain samples can be transformed from The quantized symbol s is obtained from a finite alphabet of possible quantized symbols. nQ，QT Similarly, the orthogonal component s nQThe time domain samples can be transformed from The quantized symbol s is obtained from a finite alphabet of possible quantized symbols. nQ，QT . N applied in each component bq quantization bits and The quantization level can be based on the maximum quantization error and is defined as, where 2Δi and 2Δq represent the quantization intervals for the in-phase component and the quadrature component, respectively. For each component, N bq Quantization bits and Adopted in N m ≤N bq Polar components (i.e. N m Phase and N m Amplitude), where each quantization level can be decomposed. and Both sets of and Convert to polar coordinates

[0102] From the symbol Each in-phase symbol in the finite set of can be represented as N ml ≤N bq The sum of polarity components, which are quantized values ​​s nI，QT The result of the decomposition into polar components is given by:

[0103]

[0104] in represents the binary representation of i, and N ml is a non-empty c of the decomposition i The number of real coefficients (the total number of coefficients is ). For example, for N bq =3 and a symmetric dynamic range DR (using zero value as reference), the quantization levels are ±7Δ, ±5Δ, ±3Δ, ±Δ, which can be given by:

[0105]

[0106] where c I，1 =Δ,c I，2 =2Δ,c I，4 =4Δ and c I，0 =c I，3 =c I，5 =c I，6 =c I，7 = 0. For the orthogonal components, the quantizer symbol Each symbol in the finite set of can be represented as N mQ ≤N bq The sum of polarity components, which are quantized values ​​s nq，QT The result of the decomposition into polar components is given by:

[0107]

[0108] in represents the binary representation of i, and N mQ is the non-zero g of the decomposition i The number of imaginary coefficients (the total number of coefficients is ). For example, for N b =3 and a symmetric dynamic range (using zero as reference), the quantization levels are ±j7Δ, ±j5Δ, ±j3Δ, ±jΔ, which can be given by:

[0109]

[0110] where c q，1 =jΔ,c q，2 =j2Δ,c q，4 =j4Δ and c q，0 =c q，3 =c q，5 =c q，6 =c q，7 =0.

[0111] By properly choosing the pulse shape to be applied to the polar components and the time shift between in-phase and quadrature, it is possible to decompose the quantized envelope into a sum of constant envelope components. Since each component is amplified by an amplifier, the signal resulting from the combination of all outputs can be given by Given, where p i represents the output power at the i′th branch. For class A and class AB amplifiers, we have p i =f(V dd , V in , I in ). For a Class D amplifier, p i =f(V dd ). Under this condition, in order to obtain an amplified version of the quantized envelope in class A or class AB, the quantizer needs to provide a V dd N bq values, plus a mapping rule for the components (amplitude and phase). In class D, all components may have the same amplitude, N bq Phase and N bq V dd A collection of values ​​is required.

[0112] The above examples refer to the case where quantized samples are taken from a time-varying envelope signal. However, those skilled in the art will appreciate that by quantizing the envelope values ​​of any time-varying envelope signal and decomposing it into a plurality of quasi-or constant envelope signals, any amplified version of the time-varying quantized version of the envelope signal can be generated as the sum of the amplified constant envelope signals.

[0113] 2. Method and system for using multi-quantized digitally controlled supply voltage for multiple amplifier stages (MQDCPSVMAS)

[0114] The methods and systems of MQDCPSVMAS according to embodiments of the present invention rely on the ability to quantize and decompose any quantized time-varying envelope signal into several substantially constant envelope component signals, or to generate such component signals, amplify the component signals, and then sum the amplified signals to generate an amplified version of the time-varying envelope signal.

[0115] In Sections 2.1-2.2, embodiments of the present invention are provided, including N bq an embodiment of the amplification branch, wherein all V dd The branches are fixed on each block or vary over the block duration, the fast and slow power control units define the V between envelope samples and blocks. dd Selection rules for sets. In the following description, each embodiment is first presented conceptually using a mathematical derivation of the underlying concepts of the embodiment. Two embodiments of the method of operation of the MQDCPSVMAS are then presented, followed by various system level embodiments.

[0116] In all embodiments, for the sake of convenience and not limitation, it is assumed that the quantization rules for both the in-phase and quadrature components of the envelope samples are the same.

[0117] According to one embodiment of the present invention, for the sake of explanation and not limitation, the MQDCPSVMAS using a current source amplifier is referred to herein as (MQDCPSVMASCS), and the time-varying envelope signal is decomposed into N channels with different amplitudes and DRi=DRq. bq In each pair, the in-phase component and the quadrature component are combined to produce a component signal having a constant envelope, which is individually amplified by an amplifier configured with N bq Select V from a set of values dd . N bq These N amplifiers bq The outputs are then summed to construct an amplified version of the quantized time-varying envelope of the signal.

[0118] According to another embodiment of the present invention, for the sake of convenience of explanation and not limitation, the MQDCPSVMAS using a switching amplifier is referred to herein as (MQDCPSVMASSA), and the time-varying envelope signal is decomposed into N sigma-thin envelopes having the same amplitude and DRi=DRq. bq In each pair, the in-phase component and the quadrature component are individually amplified by an amplifier configured with N bq Select V from a set of values dd , where V dd is defined as the coefficient c I，i and c q，i function to ensure different voltage outputs. bq The signals are then summed to construct an amplified version of the quantized time-varying envelope of the signal.

[0119] Note that in these embodiments, a quantizer and N bq amplification branches. For purposes of illustration and not limitation, it is also assumed that DRi=DRq and the number of quantization bits for the in-phase component and the quadrature component is the same. The scope of the present invention covers the use of two quantizers, one for the in-phase component and the other for the quadrature component, and the use of other numbers of branches, which number is different from N. bq , DRi≠DRq, and based on the teachings contained herein, V having a size different from the number of quantization bits dd The set of values ​​and implementation of such variations will be apparent to those skilled in the art.

[0120] Accordingly, in the MQDCPSVMAS embodiment, the signal s n The time domain samples are converted from The quantized symbol s is obtained from a finite alphabet of complex quantized symbols n，QT . N bq quantization bits and The quantization level can be based on the maximum quantization error is defined as, where 2Δ represents the quantization interval. b Quantification bits are used in N m ≤N bq The definition of complex components, where each quantization level can be decomposed. pass Convert to polar coordinates The finite set of quantizer symbols is in is the number of complex quantization levels. From the finite set of complex letters of the quantizer Each symbol in can be represented as N m ≤N bq The sum of components, which are quantized values ​​s n，QT The result of the decomposition of is given by:

[0121]

[0122] N m with amplitude c i Each of the polar components has amplitude and phase information associated with a component in which a quantized envelope can be decomposed. Note that the polar complex components can be modulated by offset modulation, such as offset quadrature phase shift keying (OQPSK), minimum shift keying (MSK), Gaussian MSK (GMSK), or other offset signals with a pulse shape selected to achieve high spectral efficiency and a constant envelope.

[0123] As mentioned before, the complex quantizer can be replaced by two quantizers, one associated with the in-phase component and the other applied to the quadrature component. Under these conditions, from a finite set of symbols Each in-phase symbol in can be represented as N ml ≤N bq The sum of polarity components, which are quantized values ​​s nl，QT The result of the decomposition into polar components is given by:

[0124]

[0125] in represents the binary representation of i, and N ml is a non-empty c of the decomposition I，i The number of real coefficients (the total number of coefficients is ). For the orthogonal component, the quantized value s is obtained. nq，QT to polar components, which is given by:

[0126]

[0127] N mQ is a non-empty c for the decomposition of the reference q，i The number of imaginary coefficients (the total number of coefficients is ). Therefore, it is possible to write:

[0128] s n，QT =s nI，QT +s nq，QT .

[0129] According to the embodiment of MQDCPSVMASCS, for the purpose of illustration only and not limitation, in Nbq A class A current source amplifier is used in each amplification branch. Consider the input signal applied to the i′th amplifier, which is given by:

[0130] v in，i (t) = A i sin(2πf RF t+θ t )*r(t),

[0131] Among them A i =f(c I，t , c q，t ), f RF represents the RF frequency, θ i =g(c I，i , c q，i ) represents the phase of the input signal in the i′th amplification branch, and r(t) represents the impulse response of the filter that performs spectral shaping on the amplifier input signal (the operator * represents convolution). In a linear amplifier based on transconductance, consider the load R L When , the output signal voltage is approximately given by:

[0132] v RL，i (t) = g m，i v in，i (t)r0||R L ,

[0133] where g m represents transconductance, R L represents the load, and r0 is the output resistance of the active device. Through the optimization process, it is possible to set the supply voltage V dd To maximize the amplifier efficiency.

[0134] 2V dd， i=g m，i A i r o ||R L =k i A i ,

[0135] k i Represents a constant factor.

[0136] Under these conditions, efficiency is maximized and the output power is P out，i ∝V dd，i 2 It can be seen that the amplified version of the quantized envelope can be obtained by N bq Output voltage From the quantization process, it is possible to generate a set of quantization bits, a quantization component amplitude A i Nbq amplitude and has N bq Phase θ i A collection of them, which are applied to N bq The phase of the input signal of the amplifier and the optimization of N according to the amplitude and phase of the input signal bq The V dd Value associated.

[0137] According to one embodiment of MQDCPSVMASSA, for illustration purposes only and not limitation, in N bq A class D switching amplifier is used in the first amplification branch. For the switch-mode amplifier, as in the case of class D operation, the output voltage under the fundamental load can be transformed by the following formula:

[0138]

[0139] Among them, V dd，i is the supply voltage applied to the i′th amplifier, α i is the phase shift due to delays in the amplifier circuit, and f(θ i ) is a phase shift function of the phase of the input signal. Since the output voltage is independent of the voltage amplitude of the input signal, each V dd，i The components should correspond to the amplitude A i Proportional, with a proportional factor of k i Under these conditions, from N bq The signal obtained from the combination of the output voltages is an amplified version of the quantized value of the envelope of the input signal by a factor K. Therefore, V dd N bq A set of values, N bq Phase θ i The sum of the components and the amplitude A i Proportional to N bq V dd The value is sufficient to obtain an amplified version of the envelope and at the same time ensure that N used in the amplification stage bq The operating conditions of each amplifier in the set of amplifiers are optimal.

[0140] 2.1 Using Multi-Quantized Digitally Controlled Supply Voltages for Multiple Amplifier Stages with Current Source Amplifiers

[0141] In an embodiment of the MQDCPSVMASCS, the in-phase component and the quadrature component are used to generate a component signal having a constant envelope that is individually amplified. In one embodiment, according to the coefficient c I，i and c q，iIn another embodiment, the in-phase component and the quadrature component have the same amplitude and different phases, and the quantized components are combined to generate a single amplified component signal with a constant envelope.

[0142] Reference Figure 1 The flow chart of further describes the operation of an embodiment of the MQDCPSVMASCS. Optional components are illustrated by dashed lines. The process begins at step 101, which includes receiving a signal carrying information to be amplified. In another embodiment, this step involves receiving an RF signal carrying information. In another embodiment, this step involves receiving a signal carrying information at an intermediate frequency (IF). In another embodiment, this step involves receiving envelope samples of the signal carrying information.

[0143] Step 102 includes receiving a clock signal set according to a signal frequency of an input signal.

[0144] Step 103 includes receiving a clock signal set according to a desired sampling rate of the input signal. Importantly, as will be appreciated by those skilled in the art, the sampling rate may vary depending on the bandwidth of the input signal and the desired temporal resolution of the sampling process.

[0145] Step 104 includes receiving a clock signal at the frequency of the desired output RF signal.

[0146] Step 105 includes receiving slow and fast power control information to select V dd different sets of values ​​and the source current of the amplifier, or choosing V for different samples of the envelope of the input signal that carries the information to be transmitted dd Different sets of values ​​and the source current of the amplifier are used to control the power output level after the amplifier stage.

[0147] Step 106 includes sampling the input signal at a sampling rate to generate samples of the input signal. Figure 1 In an embodiment example, step 106 is implemented by a sampling circuit or a sample-and-hold (S / H) circuit. In an embodiment with a multi-carrier signal, step 106 can be implemented by a fast Fourier transform (FFT) with higher time resolution to meet the sampling rate requirement.

[0148] Step 107 includes processing the signal samples to generate in-phase and quadrature components of the samples.

[0149] Step 108 includes processing the in-phase component and the quadrature component in a quantizer to generate quantization bits corresponding to the quantized value of the in-phase component and quantization bits corresponding to the quantized value of the quadrature component, respectively. As those skilled in the art understand based on the teachings herein, step 108 can be performed by a block using a single quantizer for two component samples or using two quantizers (one quantizer for each component). Likewise, as those skilled in the art understand based on the teachings herein, step 108 can be performed by a comparator and a LUT having corresponding quantization bits of the quantized values.

[0150] Step 109 includes individually processing the quantized bits of the quantized in-phase component to generate a corresponding amplitude and phase of the polarity representation of each quantized bit, and individually processing the quantized bits of the quantized quadrature component to generate a corresponding amplitude and phase of the polarity representation of each quantized bit. The amplitude associated with each quantized bit is defined according to the decomposition of the quantized value into polarity components, the amplitude of the polarity component being determined by N having respective values ​​for the in-phase component and the quadrature component. bq Amplitude|c I，i | and N bq Amplitude|c q，i | is given by a set of |. As will be understood by those skilled in the art based on the teachings herein, step 108 may be performed by a comparator and a LUT having the corresponding amplitude and phase of the quantized bits. It is important to note that in certain embodiments of the present invention, steps 107 and 108 may be completed once by a block that directly quantizes and generates bits, amplitudes of polar components, and phases for in-phase and quadrature components.

[0151] Step 110 includes generating N bq Amplitude|c I，i | and N bq Amplitude|c q，i | is processed to generate a selection to be applied to N bq The V dd N bq As will be appreciated by those skilled in the art based on the teachings herein, step 110 may be performed by providing a corresponding V to be applied to the amplifier. dd It is important to note that in some embodiments of the present invention, steps 107, 108, 109 and 110 may be performed by directly quantizing and generating bits, amplitudes of polar components, phases for in-phase and quadrature components, and for selecting the corresponding V dd The collection of blocks of control information is done once.

[0152] Step 111A includes processing the polar in-phase component by multiplying a pulse signal having a desired spectral shape.

[0153] Step 111B includes processing the polar quadrature components by multiplying by a pulse signal having a desired spectral shape.

[0154] Step 112 is optional and includes multiplying the signals obtained in steps 111A and 111B by a periodic signal having the frequency of the IF signal.

[0155] Step 113 includes processing the in-phase signal and the quadrature signal by summing pairs of signals having the same amplitude to generate a quantized version of N having a constant envelope and a sum equal to the envelope. bq A collection of signals.

[0156] Step 114 includes multiplying the signal obtained in step 113 by a periodic signal having the frequency of the RF signal.

[0157] Step 115 includes converting the V defined in steps 105 and 109 into dd N bq The corresponding set of N values bq Amplifier bias.

[0158] Step 116 includes amplifying each of the component signals individually and summing the amplified signals to generate the desired output signal.

[0159] Figure 2A The block diagram 200A is a diagram illustrating the implementation without the optional step 112. Figure 1 An example of an exemplary embodiment of an MQDCPSVMASCS embodiment is shown in process flow diagram 100. Figure 2A In the example of , optional components are illustrated with dashed lines. In other embodiments, additional components may be optional. In this example, a passband data signal 201 having a time-varying envelope, a clock reference signal 202 for the sampling process, and a channel clock 204 having a desired frequency for the output signal are received as inputs. In another embodiment, the signal 201 may be a sample of a time-varying envelope signal, and S / H is not required inside the digital mapper 205. In other embodiments, the signal 201 may be a baseband signal or an IF signal. Figure 5 , an exemplary embodiment of the digital mapper 205 is illustrated.

[0160] The digital mapper 205, the delay phase shifter polarity converter blocks 212 and 213, and the amplitude adjustment blocks 216 and 217 can use the clock reference signal 202. The common clock signal 202 is used to ensure that the outputs of the quantizers 206-{1, ..., N bq} and 207-{1,...,N bq} is time aligned to ensure that the outputs of blocks 212 and 213 are time synchronized, and the outputs of blocks 216 and 217 are also synchronized. Those skilled in the art will appreciate that the selection of the clock reference signal is made based on the bandwidth of the input signal and the desired output signal.

[0161] In the digital mapper 205, the information-carrying signal is sampled according to the clock signal 202, and an in-phase component and a quadrature component of each sample are generated. Figure 2A , the in-phase component and the quadrature component of each sample are N bq The bit quantizers convert the quantized bit signals into quantized bit signals 206-{1,...,N bq} and 207-{1,...,N bq In 205, quantization bits 206-{1,...,N bq} and 207-{1,...,N bq} is used by an internal mapper which may be a lookup table to generate an in-phase amplitude coefficient |c I，i |Signal 208-{1,...,N bq} and have orthogonal amplitude coefficients |c q，i |Signal 209-{1,...,N bq}, which are used in amplitude adjustment blocks 216 and 217. In 205, the voltage mapper is based on signals 208-{1,...,N bq} and 209-{1,...,N bq}Use control information to generate N bq A set of control signals and using 210-{1, ..., N bq} to select V dd In 238, according to the control signal 210-{1,...,N provided by the fast / slow power control block 236 bq} and control signal 237 to select V dd The digital mapper 205 also provides an optional control signal 211 to the fast / slow power control block 236 to select V dd The fast / slow power control block 236 also receives a control signal 235 having information about the maximum output RF power required for the transmission.

[0162] Signal 206-{1,...,N bq} and 207-{1,...,N bq} is provided to delay phase shifter and polarity converter blocks 212 and 213 to generate a phase rotation associated with each quantization bit and a corresponding polarity representation and adjust the delay between the signals associated with the quantization bits. For purposes of illustration and not limitation, for the quantization bits 206-{1,...,N bq}, bit 0 corresponds to a phase of π, and bit 1 corresponds to a phase of 0. For the quantization bits 207-{1,...,N bq}, bit 0 corresponds to a phase of -π / 2, and bit 1 corresponds to a phase of π / 2. Blocks 212 and 213 are applied to the in-phase signal 214-{1,...,N bq} and orthogonal signal 215-{1,...,N bq} and the desired offset between them and the control signal 246-{1,...,N from the multi-amplifier amplifier stage 231 bq} provides feedback information to adjust the output signal 214-{1,...,N bq} and 215-{1,...,N bq} delay.

[0163] In-phase component signal 214-{1,...,N bq} is provided to block 216, which generates a phase-independent signal according to the in-phase amplitude coefficient |c I，i |Signal 208-{1,...,N bq} to adjust the amplitude of each signal to generate in-phase component signals 218-{1,...,N bq Similarly, the quadrature component signals 215-{1,...,N bq} is provided to block 217, which is based on the orthogonal amplitude coefficients |c q，i |Signal 209-{1,...,N bq} to adjust the amplitude of each signal to generate orthogonal component signals 219-{1,...,N bq}. Signal 218-{1,...,N bq} and 219-{1,...,N bq} can be submitted to filter 220 with the same impulse response - {1, ..., N bq} and 221-{1,...,N bq} to ensure the desired spectral shape.

[0164] In 224-{1,...,N bq}, the in-phase signal 222-{1,...,N bq} and orthogonal signal 223-{1,...,N bq} are combined to generate a signal 225-{1, ..., N bq} is a set of constituent signals. In 228-{1,...,N bq}, signal 225-{1,...,N bq} is up-converted to RF frequency by multiplying with a periodic signal 227 having a desired RF frequency defined by clock 204. Signal 229 having a quasi or constant envelope {1, ..., N bq} is the corresponding power amplifier (PA) 230-{1,...,N bq In another embodiment, PA 230-{1,...,N bq} includes a class A power amplifier. In another embodiment, PA 230-{1, ..., N bq}Includes Class AB, Class B and Class C power amplifiers.

[0165] N bq Each PA in the set of amplifiers 231 has a dd The only V in the set of values dd voltage values, and their bias 242-{1,...,2N bq} is applied to bq The amplifier stage of the amplifier 231 is applied to N bq Amplifiers 230-{1,...,N bq V dd Value 242-{1,...,N bq} and its offset 242-{N bq +1,...,2N bq} is composed of fast and slow power control blocks 236, lookup table 238 power and V dd The output of control block 243, which controls the signal 239-{1, ..., 2N bq} is sent to the DC / DC converter 240, which output defines the V generated by the DC / DC converter dd Value 241-{1,...,2N bq}. Module 241a is an optional low dropout regulator (LDO). When block 241a is not present, signal 241-{1,...,2N bq} and 242-{1,...,2N bq Supply signal 247 is used by DC / DC converter 240 (and optionally LDO 241a) to generate V used in amplifier stage 231. dd Value set and bias signal.

[0166] In combiner 233, PA 232-{1, ..., N bq} are coupled together. Alternatively, PA 232-{1,...,N bq The output of} can be coupled by LC matching to minimize power loss. The amplifier stage embodiment of the power amplification method and system according to the present invention will be further described in Section 3.

[0167] Phase control circuit 245 is employed to generate feedback control signals 246 to blocks 212 and 213 - {1, ..., N bq}, based on the information signal 244-{1,...,N bq} to compensate for the phase mismatch between amplifiers.

[0168] Figure 2B The block diagram 200B is a diagram showing the implementation of the Figure 1 An example of an exemplary embodiment of an MQDCPSVMASCS embodiment is shown in process flow diagram 100. Figure 2B In the example of , optional components are illustrated with dashed lines. In other embodiments, additional components may be optional. In this example, a passband data signal 201 with a time varying envelope, a clock reference signal 202 for the sampling process, an intermediate channel clock 203 with a desired intermediate frequency, and an RF channel clock 204 with a desired frequency for the output signal are received as inputs. In another embodiment, the signal 201 may be a sample of a time varying envelope signal, and S / H is not required inside the digital mapper 205. In other embodiments, the signal 201 may be a baseband signal or an IF signal. Figure 5 , an exemplary embodiment of the digital mapper 205 is illustrated.

[0169] The digital mapper 205, the delay phase shifter polarity converter blocks 212 and 213, and the amplitude adjustment blocks 216 and 217 can use the clock reference signal 202. The common clock signal 202 is used to ensure that the quantizers 206-{1,...,N bq} and 207-{1,...,N bq The output of block 212 is time aligned to ensure that the outputs of block 213 are time synchronized, and the outputs of block 216 and block 217 are also synchronized. It will be appreciated by those skilled in the art that the selection of the clock reference signal is made based on the bandwidth of the input signal and the desired output signal.

[0170] In the digital mapper 205, the information-carrying signal is sampled according to the clock signal 202, and an in-phase component and a quadrature component of each sample are generated. Figure 2B , the in-phase component and the quadrature component of each sample are N bq The bit quantizers convert the quantized bit signals into quantized bit signals 206-{1,...,N bq} and 207-{1,...,N bq In 205, quantization bits 206-{1,...,N bq} and 207-{1,...,N bq} is used by an internal mapper which may be a lookup table to generate an in-phase amplitude coefficient |c I，i |Signal 208-{1,...,N bq} and have orthogonal amplitude coefficients |c q，i |Signal 209-{1,...,N bq}, which are used in amplitude adjustment blocks 216 and 217. In 205, the voltage mapper uses signals 208-{1,...,N bq} and 209-{1,...,N bq} to generate N bq A set of control signals and using 210-{1, ..., N bq} to select V dd In 238, according to the control signal 210-{1,...,N provided by the fast / slow power control block 236 bq} and control signal 237 to select V dd The digital mapper 205 also provides an optional control signal 211 to the fast / slow power control block 236 to select V dd The correct set of values.

[0171] Signal 206-{1,...,N bq} and 207-{1,...,N bq} is provided to the delay phase shifter and polarity converter blocks 212 and 213 to generate a phase rotation associated with each quantization bit and a corresponding polarity representation and adjust the delay between the signals associated with the quantization bits. For purposes of illustration and not limitation, for the quantization bits 206-{1,...,N bq}, bit 0 corresponds to a phase of π, and bit 1 corresponds to a phase of 0. For the quantization bits 207-{1,...,N bq}, bit 0 corresponds to a phase of -π / 2, and bit 1 corresponds to a phase of π / 2. Blocks 212 and 213 are applied to the in-phase signal 214-{1,...,N bq} and orthogonal signal 215-{1,...,N bq} and the desired offset between them and the control signal 246-{1,...,N from the multi-amplifier amplifier stage 231 bq} provides feedback information to adjust the output signal 214-{1,...,N bq} and 215-{1,...,N bq} delay.

[0172] In-phase component signal 214-{1,...,N bq} is provided to block 216, which generates a phase-independent signal according to the in-phase amplitude coefficient |c I，i |Signal 208-{1,...,N bq} to adjust the amplitude of each signal to generate in-phase component signals 218-{1,...,N bq Similarly, the quadrature component signals 215-{1,...,N bq} is provided to block 217, which is based on the orthogonal amplitude coefficients |c q，i |Signal 209-{1,...,N bq} to adjust the amplitude of each signal to generate orthogonal component signals 219-{1,...,N bq}. Signal 218-{1,...,N bq} and 219-{1,...,N bq} can be submitted to filter 220 with the same impulse response - {1, ..., N bq} and 221-{1,...,N bq} to ensure the desired spectral shape.

[0173] The in-phase signal 222b at the intermediate frequency is {1, ..., N bq} is obtained by adding 222a-{1,...,N bq} will be signal 222-{1,...,N bq} is obtained by multiplying the pulse period signal 218b, which has a desired intermediate frequency provided by the oscillator 218a according to the reference signal 203. IF quadrature signal 223b-{1,...,N bq} is obtained by adding 223a-{1,...,N bq} will be signal 223-{1,...,N bq} is multiplied by the pulse period signal 218b.bq}, the in-phase signal 222b-{1,...,N bq} and orthogonal signal 223-{1,...,N bq} are combined to generate a signal 225-{1, ..., N bq} is a set of constituent signals. In 228-{1,...,N bq}, signal 225-{1,...,N bq} is up-converted to RF frequency by multiplying by a periodic signal 227 generated by an oscillator 226 having a desired RF frequency defined by clock 204. Signal 229 having a quasi or constant envelope {1, ..., N bq} is the corresponding PA 230-{1,...,N bq In another embodiment, PA 230-{1,...,N bq} includes a class A power amplifier. In another embodiment, PA230-{1, ..., N bq}Includes Class AB, Class B and Class C power amplifiers.

[0174] N bq Each PA in the set of amplifiers 231 has a dd The only V in the set of values dd voltage values, and their bias 242-{1,...,2N bq} is applied to bq The amplifier stage of the amplifier 231 is applied to N bq Amplifiers 230-{1,...,N bq V dd Value 242-{1,...,N bq} and its offset 242-{N bq +1,...,2N bq} is the power and V dd The output of control block 243, the power and V dd The control block consists of a fast and slow power control block 236, which sends a control signal 239-{1,...,2Nbq} to the DC / DC converter 240, and a lookup table 238 that defines the V to be generated by the DC / DC converter. dd Value 241-{1,...,2N bq}. Block 241a is an optional LDO. When block 241a does not exist, signal 241-{1,...,2N bq} and 242-{1,...,2N bqSupply signal 247 is used by DC / DC converter 240 (and optionally LDO 241a) to generate V used in amplifier stage 231. dd Value set and bias signal.

[0175] In combiner 233, PA 232-{1, ..., N bq} are coupled together. Alternatively, PA 232-{1,...,N bq The output of} can be coupled by LC matching to minimize power loss. The amplifier stage embodiment of the power amplification method and system according to the present invention will be further described in Section 3.

[0176] In another embodiment, phase control circuit 245 may be employed to generate feedback control signals 246-{1, ..., N bq}, based on the information signal 244-{1,...,N bq} to compensate for the phase mismatch between amplifiers.

[0177] 2.2 Using Multi-Quantized Digitally Controlled Supply Voltages for Multiple Amplifier Stages with Switching Amplifiers

[0178] According to an embodiment of the invention for using multiple quantized digitally controlled supply voltages for multiple amplifier stages using switching amplifiers (MQDCPSVMASSA), for the sake of illustration and not limitation, a time-varying envelope signal is decomposed into N discrete letters having the same amplitude and different phases. bq The constituent signals are individually amplified and then summed to obtain an amplified version of the quantized time-varying envelope signal. Note that for purposes of illustration and not limitation, a quantized time-varying envelope signal having N is used in these embodiments. bq quantization bits and N bq quantizer with an amplification branch. dd Each V in the value set dd,i have a coefficient c that is constant over time I，i and c q，i The corresponding set of V is proportional to different values, and the in-phase and quadrature components have the same amplitude and different phases, and the amplified version of the quantized envelope is the result of the sum of all amplifier outputs. In other embodiments, V dd Several sets of V are available, and the set can change between data blocks. dd may vary between samples. The scope of the invention encompasses the use of other numbers of branches, V ddMultiple sets of and DRi=DRq, DRi≠DRq, and based on the teachings contained herein, the implementation of such changes will be obvious to those skilled in the art.

[0179] Reference Figure 3 The operation of the MQDCPSVMASCS embodiment is further described in the flowchart of FIG. Optional steps are illustrated by dashed lines. The process begins at step 301, which includes receiving a time-varying envelope bandpass signal. In another embodiment, this step involves receiving a desired input RF signal. In another embodiment, this step involves receiving a desired IF signal. In another embodiment, this step involves receiving a baseband signal. In another embodiment, this step involves receiving samples of the time-varying envelope signal or receiving samples of the in-phase component and the orthogonal component of the time-varying envelope signal.

[0180] Step 302 includes receiving a clock signal set according to a signal frequency of an input signal.

[0181] Step 303 includes receiving a clock signal set according to a desired sampling rate of the input signal. Importantly, as will be appreciated by those skilled in the art, the sampling rate may vary depending on the bandwidth of the input signal and the desired temporal resolution of the sampling process.

[0182] Step 304 includes receiving a clock signal according to the frequency of the desired output RF signal.

[0183] Step 305 includes receiving slow and fast power control information to select V dd Different sets of values, or selections of V for different samples of the envelope of the input signal that carry the information to be transmitted dd Different sets of values ​​are used to control the power output level after the amplifier stage.

[0184] Step 306 includes sampling the input signal at a sampling rate to generate samples of the input signal. Figure 3 In an embodiment example, step 306 is implemented by a sampling circuit or a sample-and-hold (S / H) circuit. In an embodiment with a multi-carrier signal, step 306 can be implemented by a fast Fourier transform (FFT) with higher time resolution to meet the sampling rate requirement.

[0185] Step 307 includes processing the signal to generate an in-phase component and a quadrature component.

[0186] Step 308 includes processing the in-phase component and the quadrature component individually by a quantizer to generate a quantization bit corresponding to the quantized value of the in-phase component and a quantization bit corresponding to the quantized value of the quadrature component, respectively. As those skilled in the art understand based on the teachings herein, step 308 can be performed by a block using a single quantizer. Similarly, as those skilled in the art understand based on the teachings herein, step 308 can be performed by a comparator and a LUT having corresponding quantization bits of the quantized value.

[0187] Step 309 includes individually processing the quantized bits of the quantized in-phase component to generate a corresponding V associated with the polarity representation of each quantized bit. dd amplitude and phase, and individually processing the quantized bits of the quantized quadrature components to generate a corresponding V associated with the polarity representation of each quantized bit dd Amplitude and phase. Each V associated with each component is obtained based on the decomposition of the quantized value into polar components. dd The amplitude of the polar component is determined by the N bq Amplitude|c I，i | and N for the orthogonal components bq Amplitude|c q，i | is given by a set of |. As will be appreciated by those skilled in the art based on the teachings herein, step 308 may be performed by a comparator and a LUT having a corresponding magnitude and phase for each quantized bit. It is important to note that in certain embodiments of the present invention, steps 307 and 308 may be performed by directly quantizing and generating bits, V associated with each polarity component. dd The magnitude and phase of the in-phase component and the quadrature component are completed once.

[0188] Step 310A includes processing the polar in-phase component by multiplying a pulse signal having a desired spectral shape.

[0189] Step 310B includes processing the polar quadrature components by multiplying by a pulse signal having a desired spectral shape.

[0190] Step 311 is optional and includes multiplying the signals obtained in steps 310A and 310B by a periodic signal having the frequency of the IF signal.

[0191] Step 312 includes processing the in-phase signal and the quadrature signal by summing pairs of signals having the same amplitude to generate a quantized version of N having a constant envelope and a sum equal to the envelope. bq A collection of signals.

[0192] Step 313 includes multiplying the signal obtained in step 312 by a periodic signal having the frequency of the RF signal.

[0193] Step 314 includes converting the V defined in step 309 into dd N bq The corresponding set of N values bq Amplifier bias.

[0194] Step 315 includes amplifying each of the component signals individually and summing the amplified signals to generate the desired output signal.

[0195] Figure 4A The block diagram 400A is a diagram illustrating the implementation without the optional step 311. Figure 3 An example of an embodiment of the MQDCPSVMASSA process flow diagram 300 is shown. Figure 4A In the example of , optional components are illustrated with dashed lines. In other embodiments, additional components may be optional.

[0196] In this example, a time-varying envelope signal 401, a clock reference signal 402 for the sampling process, and a channel clock 404 having a desired frequency for the output signal are received as input. In another embodiment, the signal 401 may be a sample of the time-varying envelope signal, and S / H is not required inside the digital mapper 405. In other embodiments, the signal 401 may be a baseband signal or an IF signal. Figure 5 , an exemplary embodiment of a digital mapper 405 is illustrated.

[0197] The digital mapper 405, delay phase shifter polarity converter blocks 412 and 413 can use the clock reference signal 402. The common clock signal 402 is used to ensure that the output of the quantizer 406-{1,...,N bq} and 407-{1,...,N bq} is time aligned and is used to ensure that the outputs of blocks 412 and 413 are synchronized. Those skilled in the art will appreciate that the selection of clock reference signal 402 is made based on the bandwidth of the input signal and the desired output signal.

[0198] In the digital mapper 405, the information-carrying signal is sampled according to the clock signal 402, and an in-phase component and a quadrature component of each sample are generated. Figure 4A , the in-phase component and the quadrature component of each sample are N bq The bit quantizers convert the quantized bit signals 406-{1,...,N bq} and 407-{1,...,N bq In 405, quantization bits 406-{1,...,N bq} and 407-{1,...,N bq} is used by an internal mapper, which may be a lookup table, to generate the in-phase amplitude coefficient |c I，i | and the orthogonal amplitude coefficient |c q，i |, which are used in the voltage mapper in 405 to generate N bq control signals 410-{1,...,N bq}, thereby selecting V in the lookup table 434 dd In 434, according to the control signal 410-{1,...,N provided by the fast / slow power control block 432 bq} and control signal 433 to select V dd The digital mapper 405 also provides an optional control signal 411 to the fast / slow power control block 432 to select V dd The block 432 also receives a power control signal 431 from the system, which has information about the output power required for the transmission.

[0199] Signal 406-{1,...,N bq} and 407-{1,...,N bq} is provided to delay phase shifter and polarity converter blocks 412 and 413 to generate a phase rotation associated with each quantization bit and a corresponding polarity representation and adjust the delay between the signals associated with the quantization bits. For purposes of illustration and not limitation, for the quantization bits 406-{1,...,N bq}, bit 0 corresponds to a phase of π, and bit 1 corresponds to a phase of 0. For the quantization bits 407-{1,...,N bq}, bit 0 corresponds to a phase of -π / 2, and bit 1 corresponds to a phase of π / 2. Blocks 412 and 413 are applied to the in-phase signal 414-{1,...,N bq} and orthogonal signal 415-{1,...,N bq} and the feedback information provided by the control signals 442-{1, ..., Nbq} from the multi-amplifier amplifier stage 427 to adjust the output signals 414-{1, ..., N bq} and 415-{1,...,N bq} delay.

[0200] Signal 414-{1,...,N bq} and 415-{1,...,N bq} can be submitted to the filter 416-{1,...,N} with the same impulse response. bq} and 417-{1,...,Nbq} to ensure the desired spectral shape.

[0201] In 420-{1,...,N bq}, the in-phase signal 418-{1,...,N bq} and orthogonal signal 419-{1,...,N bq} are combined to generate a signal 421-{1,...,N bq Block 418c-{1,...,N bq} and 419c-{1,...,N bq} is optional, and when not present, signal 418-{1, ..., N bq} and 418d-{1,...,N bq} and 419-{1,...,N bq} and 419d-{1,...,N bq} are equal. In 424-{1,...,N bq}, signal 421-{1,...,N bq} is up-converted to RF frequency by multiplying a periodic signal 423 having a desired RF frequency defined by clock 404. Signal 425 having a quasi or constant envelope {1, ..., N bq} is the corresponding power amplifier (PA) 426-{1,...,N bq In another embodiment, PA 426-{1,...,N bq} includes a class D switching power amplifier. In another embodiment, PA 426-{1, ..., N bq}Including class E, class F, class S switching power amplifiers or other classes of switching power amplifiers.

[0202] N bq Each PA in the set of amplifiers 427 has a PA from which a bq The V of the amplifier stage of the amplifier 427 dd Value 438-{1,...,N bq The only V in the set of dd Voltage value. Applied to N bq Amplifiers 426-{1,...,N bq}V dd Value 438-{1,...,N bq} is the power and V dd The output of control block 439, the power and V ddThe control block is composed of a fast and slow power control block 432 and a lookup table 434. The fast and slow power control block converts the control signal 435-{1,...,N bq} is sent to the DC-DC converter 436, the lookup table defines the V to be generated by the DC / DC converter dd Value 437-{1,...,2N bq}. Block 437a is an optional LDO. When block 437a does not exist, signal 437-{1,...,N bq} and 438-{1,...,N bq Supply signal 443 is used by DC / DC converter 436 (and optionally LDO 437a) to generate V used in amplifier stage 427. dd A collection of values ​​and a bias signal.

[0203] In combiner 429, PA 428-{1, ..., N bq} are coupled together. Alternatively, PA 428-{1,...,N bq The output of} can be coupled by LC matching to minimize power loss. The amplifier stage embodiment of the power amplification method and system according to the present invention will be further described in Section 3.

[0204] Phase control circuit 441 is employed to generate feedback control signals 442-{1, ..., N bq}, based on the information signal 440-{1,...,N bq} to compensate for the phase mismatch between amplifiers.

[0205] In other embodiments, signal 423 may be a sinusoidal signal or a pulse train signal, the frequency of which is selected according to the desired frequency of the output signal.

[0206] In other embodiments, the combiner output signal 430 is submitted to a bandpass filter having a center frequency equal to the desired carrier frequency of the output signal.

[0207] Figure 4B The block diagram 400B is a diagram showing the implementation of the method with optional step 311. Figure 3 An example of an embodiment of the MQDCPSVMASSA process flow diagram 300 is shown. Figure 4B In the example of , optional components are illustrated with dashed lines. In other embodiments, additional components may be optional.

[0208] In this example, a time-varying envelope signal 401, a clock reference signal 402 for the sampling process, an intermediate channel clock 403 having a desired intermediate frequency, and an RF channel clock 404 having a desired frequency for the output signal are received as input. In another embodiment, the signal 401 may be a sample of the time-varying envelope signal, and S / H is not required inside the digital mapper 405. In other embodiments, the signal 401 may be a baseband signal or an IF signal. Figure 5 , an exemplary embodiment of a digital mapper 405 is illustrated.

[0209] The digital mapper 405, delay phase shifter polarity converter blocks 412 and 413 can use the clock reference signal 402. The common clock signal 402 is used to ensure that the output of the quantizer 406-{1,...,N bq} and 407-{1,...,N bq} is time aligned and is used to ensure that the outputs of blocks 412 and 413 are synchronized. Those skilled in the art will appreciate that the selection of clock reference signal 402 is made based on the bandwidth of the input signal and the desired output signal.

[0210] In the digital mapper 405, the information-carrying signal is sampled according to the clock signal 402, and an in-phase component and a quadrature component of each sample are generated. Figure 4B , the in-phase component and the quadrature component of each sample are N bq The bit quantizers convert the quantized bit signals 406-{1,...,N bq} and 407-{1,...,N bq In 405, quantization bits 406-{1,...,N bq} and 407-{1,...,N bq} is used by an internal mapper, which may be a lookup table, to generate the in-phase amplitude coefficient |c I，i | and the quadrature amplitude coefficient |c q，i |, which are used in the voltage mapper in 405 to generate N bq control signals 410-{1,...,N bq}, thereby selecting V in the lookup table 434 dd In 434, according to the control signal 410-{1,...,N provided by the fast / slow power control block 432 bq} and control signal 433 to select V dd The digital mapper 405 also provides an optional control signal 411 to the fast / slow power control block 432 to select V dd The correct set of values.

[0211] Signal 406-{1,...,N bq} and 407-{1,...,N bq} is provided to delay phase shifter and polarity converter blocks 412 and 413 to generate a phase rotation associated with each quantization bit and a corresponding polarity representation and adjust the delay between the signals associated with the quantization bits. For purposes of illustration and not limitation, for the quantization bits 406-{1,...,N bq}, bit 0 corresponds to a phase of π, and bit 1 corresponds to a phase of 0. For the quantization bits 407-{1,...,N bq}, bit 0 corresponds to a phase of -π / 2, and bit 1 corresponds to a phase of π / 2. Blocks 412 and 413 are applied to the in-phase signal 414-{1,...,N bq} and orthogonal signal 415-{1,...,N bq} and the desired offset between them and the control signal 442-{1, ..., N} from the multi-amplifier stage 427 bq} provides feedback information to adjust the output signal 414-{1,...,N bq} and 415-{1,...,N bq} delay.

[0212] Signal 414-{1,...,N bq} and 415-{1,...,N bq} can be submitted to the filter 416-{1,...,N} with the same impulse response. bq} and 417-{1,...,N bq} to ensure the desired spectral shape.

[0213] The in-phase signal 418d in the intermediate frequency {1, ..., N bq} is obtained by adding 418c-{1,...,N bq} Signal 418-{1,...,N bq} is obtained by multiplying the pulse period signal 218b having the desired intermediate frequency. IF quadrature signal 419d-{1,...,N bq} is obtained by adding 419c-{1,...,N bq} will signal 419-{1,...,N bq} is obtained by multiplying the pulse period signal 418b having the desired intermediate frequency. bq}, the in-phase signal 418d-{1,...,N bq} and orthogonal signal 223-{1,...,Nbq} are combined to generate a quasi-envelope or constant envelope signal 421-{1,...,N bq}. In 424-{1,...,N bq}, signal 421-{1,...,N bq} is up-converted to RF frequency by multiplying a periodic signal 423 having a desired RF frequency defined by clock 404. Signal 425 having a quasi or constant envelope {1, ..., N bq} is the corresponding power amplifier (PA) 426-{1,...,N bq In another embodiment, PA 426-{1,...,N bq} includes a class D switching power amplifier. In another embodiment, PA 426-{1, ..., N bq}Including class E, class F, class S switching power amplifiers or other classes of switching power amplifiers.

[0214] N bq Each PA in the set of amplifiers 427 has a PA from which a bq The V of the amplifier stage of the amplifier 427 dd Value 438-{1,...,N bq The only V in the set of dd Voltage value. Applied to N bq Amplifiers 426-{1,...,N bq}V dd The values ​​438-{1, ..., Nbq} are the power and V values ​​composed of the fast and slow power control blocks 432, the lookup table 434, and the dd The output of control block 439, which controls the signal 435-{1, ..., N bq} is sent to the DC-DC converter 436, which output defines the V generated by the DC / DC converter dd Value 437-{1,...,N bq}. Block 437a is an optional LDO. When block 437a does not exist, signal 437-{1,...,N bq} and 438-{1,...,N bq Supply signal 443 is used by DC / DC converter 436 (and optionally LDO 437a) to generate V used in amplifier stage 427. dd A collection of values ​​and a bias signal.

[0215] In combiner 429, PA 428-{1, ..., N bq} are coupled together. Alternatively, PA 428-{1,...,N bq The output of} can be coupled by LC matching to minimize power loss. The amplifier stage embodiment of the power amplification method and system according to the present invention will be further described in Section 3.

[0216] In another embodiment, phase control circuit 441 may be employed to generate feedback control signals 442-{1, ..., N bq}, based on the information signal 440-{1,...,N bq} to compensate for the phase mismatch between amplifiers.

[0217] In other embodiments, signal 423 may be a sinusoidal signal or a pulse train signal, the frequency of which is selected according to the desired frequency of the output signal.

[0218] In other embodiments, the combiner output signal 430 is submitted to a bandpass filter having a center frequency equal to the desired carrier frequency of the output signal.

[0219] Figure 5 The block diagram 500 is a diagram illustrating Figure 2A and Figure 2B The digital mapper block (block 205) and Figure 4A and Figure 4B 4. An example of an embodiment of a digital mapper block (block 405) of FIG. 4. In this example, a time-varying envelope signal 501 and a clock reference signal 502 for a sampling process are received as inputs. In another embodiment, 501 may be a sample of a time-varying envelope signal, and S / H 503 is not required. In another embodiment, the input signal 501 may be a sample of an in-phase component and a quadrature component of a time-varying envelope signal, and a phase splitter 505 and S / H are not required.

[0220] S / H block 503, I / Q block 505, quantizer 508, amplitude component mapper 513 and V dd Voltage mapper 517 may use clock reference signal 502. Samples 504 are provided to phase splitter 505, which generates an in-phase component 506 and a quadrature component 507 for each sample. Signals 506 and 507 are fed to quantizer 508, which generates quantized bits 511 - {1, ..., N bq} and 512-{1,...,N bq}, which are used by the component amplitude mapper 513, which may be a lookup table, to generate the in-phase amplitude coefficients |cI，i | and the quadrature amplitude coefficient |c q，i |.

[0221] In-phase quantization bits 509-{1,...,N bq} and orthogonal quantization bits 510-{1,...,N bq}yes Figure 2A and Figure 2B The inputs of blocks 212 and 213. Figure 4A and Figure 4B , signal 509-{1,...,N bq} and 510-{1,...,N bq} corresponds to the input of blocks 412 and 413.

[0222] With amplitude coefficients 514-{1,...,N bq} and 515-{1,...,N bq Two sets of signals of} are generated as fixed amplitude components according to the decomposition rule applied to the quantized values ​​of the in-phase component and the orthogonal component and are sent to Figure 2A Block 216 and Figure 2B Block 217. Reference Figure 2A and Figure 2B , signal 514-{1,...,N bq} and 515-{1,...,N bq} corresponds to signal 208-{1,...,N bq} and 209-{1,...,N bq}. refer to Figure 4A and Figure 4B , signal 514-{1,...,N bq} and 515-{1,...,N bq} No amplitude adjustment of the control signal component is required. Generate a control signal 516 proportional to the amplitude coefficient {1, ..., N bq} and is delivered to V dd Voltage mapper 517. In 517, these signals are dd The voltage mapper is used to generate N bq control signals 518-{1,...,N bq}, the N bq The control signal corresponds to Figure 2A and Figure 2B The signal 210-{1,...,N bq} or corresponding to Figure 4A and Figure 4B The signal 410-{1,...,N bq}. Vdd Value 518-{1,...,N bq} according to the control signal 516-{1,...,N bq} to generate. V dd The voltage mapper 517 also provides Figure 2A and Figure 2B The fast / slow power control block provides an optional control signal 519 ( Figure 2A and 2B The signal in 211 or Figure 4A and 4B signal 411 in).

[0223] Those skilled in the art will appreciate that the selection of the clock reference signal is made according to the bandwidth of the input signal and the desired output signal. As those skilled in the art will appreciate, different blocks can use other reference clock signals and different reference clock signals. Note that for purposes of illustration and not limitation, a quantizer is adopted together with two mappers. The scope of the present invention encompasses the use of more quantizers and different numbers of mappers, and based on the teachings contained herein, the implementation of such variations is apparent to those skilled in the art. In yet other exemplary embodiments, the device for the digital mapper block may include an FPGA and a lookup table. A phase splitter may increase an offset between an in-phase sample and a quadrature sample.

[0224] 3. Parallel Amplifier Stage Embodiment

[0225] Figure 6 The block diagram 600 illustrates a parallel and multiple power amplifier stage embodiment with a transconductance based amplifier (ie, for class A operation) according to an embodiment of the present invention. Figure 6 In the example of FIG. 6 , optional components are illustrated by dashed lines. In other embodiments, additional components may be optional. The amplifier stage embodiment 600 includes a plurality of PA branches 608-{1, ..., N bq}. The signal 601-{1,...,N} is entered by the periodic signal from the corresponding mixed product of the constituent signal components. bq} represents the input for the entire amplifier stage 600. Figure 2A and Figure 2B , the input signal is signal 229-{1,...,N bq}.

[0226] Depending on the power supply V applied to each amplifier branch dd , since each signal 601-{1,...,N bq}, PA branch 608-{1,...,N bq Each PA branch 608-{1,...,Nbq} power amplification level according to the input signal and the power supply signal and the input control signal 242-{1,...,2N bq}(See Figure 2A and Figure 2B ) to set.

[0227] Control signal 610-{1,...,N bq} is biased and controls circuit block 611-{1,...,N bq This block sets the power amplifier unit 606-{1,...,N bq}'s desired operating point. Figure 2A and Figure 2B , the control signal is the signal 606-{1,...,N provided by LUT 238 bq}.

[0228] exist Figure 6 In the embodiment, each PA branch 608-{1,...,N bq} includes limiter 602-{1,...,N bq}、Optional driver 603-{1,...,N bq}, optional output matching network 604-{1,...,N bq} and power amplifier unit 606-{1,...,N bq}. In other embodiments, an input matching network may also be used. In other embodiments, such as Figure 6 The illustrated driver 603-{1,...,N bq} can also be added in the PA branch before the power amplifier element to enhance the input signal 605-{1,...,N bq}. When the driver 603-{1,...,N is not used bq}, the signal 602a-{1,...,N bq} is equal to signal 603a-{1,...,N bq In an embodiment, a driver is used whenever the required output power level cannot be achieved in a single amplifier stage due to insufficient drive power. According to an embodiment, PA 606-{1, ..., N bq} includes transconductance-based amplifiers. Figure 6 In the example of FIG. 6 , the power amplifier 606-{1, ..., N bq} includes transconductance devices, namely field effect transistors (FETs) T-{1,...,N bq}、Inductor L-{1,...,N bq} and supply voltage Vsupply-{1,...,Nbq}, the supply voltage is determined by signal 609-{1,...,N bq} Provided. Reference Figure 2A and 2B , the supply and bias signals are signals 242-{1,...,2N bq}, and PA branch 607-{1,...,N bq The outputs of} are coupled at combiner 233 to generate output signal 234.

[0229] Figure 7 Block diagram 700 illustrates another multiple power amplifier output stage with switch-based amplifier branches (i.e., class D operation) according to an embodiment of the present invention. Figure 7 In the example of , optional components are illustrated with dashed lines. In other embodiments, additional components may be optional. Figure 6 An embodiment of Figure 7 The output stage 700 includes a plurality of PA branches 708-{1, ..., N bq}. The signal 701-{1,...,N} is entered from the corresponding products of the constituent signal components through the periodic signal. bq} represents the input for the amplifier stage 700. Figure 4A and Figure 4B , the input signal is the signal 425-{1,...,N bq According to this embodiment of the present invention, the signal 701-{1,...,N bq} represents a constant including component signal at the input of the power amplifier.

[0230] Each PA branch 708-{1,...,N bq} may include a limiter 702-{1,...,N bq} represents a plurality of power amplifier stages, the limiter provides parallel drivers 703-{1,...,N bq} and 704-{1,...,N bq} Provide signal 702a-{1,...,N bq}, each driver supplies a signal to each power amplifier 706-{1,...,N bq} corresponding switch TP-{1,...,N bq} and TN-{1,...,N bq} Provide input signal 703a-{1,...,N bq} and 704a-{1,...,N bq Each signal power amplifier 706-{1,...,N bq} includes two complementary switches TP-{1,...,N bq} and TN-{1,...,N bq}, i.e. transistor-based switches, followed by bandpass filters BP-{1,...,N bq}, the bandpass filter is composed of passive reactance elements such as capacitors and inductors. Signal power amplifier 706-{1,...,N bq} has a signal 709-{1,...,N bq} provides a power supply voltage Vsupply-{1,...,N bq}. refer to Figure 4A and 4B , these signals are signals 438-{1,...,N bq To generate the desired output signal, the PA branches 707-{1,...,N bq The output of} is Figure 4A and Figure 4B are coupled to the combiner 429 to generate the output signal 430. Accordingly, the PA 707-{1,...,N bq In other embodiments, input and output matching networks may also be used.

[0231] Embodiments are not limited to switches based on FET channel N and P device types. Those skilled in the art will appreciate that, for example, embodiments of the present invention may be implemented using bipolar junction transistors (BJT), complementary MOS (CMOS), N-type MOS (NMOS), P-channel MOS (PMOS), lateral diffusion MOS (LDMOS), BiCMOS or other types of semiconductor-based transistors. In addition, embodiments may be implemented using gallium arsenide (GaAs), gallium nitride (GaN) and / or silicon germanium (SiGe) and silicon transistors with desired transistor switching speeds and on-resistances.

[0232] In an embodiment, the number of transistors included in each PA is set according to the maximum output power level required of the power amplifier. In other embodiments, the number of transistors in the PA is such that the number of transistors in the pre-driver, driver, and PA stages conforms to an optimized development.

[0233] Although the preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-mentioned specific configurations. Various changes and modifications may be made without departing from the scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and changes may be made, depending on design requirements and other factors, as long as they are within the scope of the attached claims or their equivalents.

[0234] 4. Summary

[0235] This article provides a mathematical basis for new concepts related to processing signals to provide power amplification. These new concepts allow arbitrary waveforms to be constructed from the sum of waveforms with essentially constant envelopes. The desired output signal and waveform can be composed of an amplified version of a basic constant envelope component signal, which can be generated by the knowledge and quantization of the time-varying envelope of the input signal and the use of multiple power amplifiers with multiple output powers. The amplified version of the quantized signal is generated by using multiple amplifiers with different power outputs, which are summed using new technologies that are not commercially available, not taught or found in the literature or related art. In addition, the hybrid of various techniques and circuits provided in this disclosure provides unique aspects of the present invention, which allows superior linearity, efficiency of power increase, constant supply voltage on the power amplifier and low cost. Embodiments of the present invention can be implemented by a hybrid of hardware, software and firmware. Both digital and analog techniques can be used with or without a microprocessor and DSP (digital signal processor), or with or without an FPGA. Digital processing also provides a multi-V dd The implementation of digitally controlled systems provides greater flexibility.

[0236] Embodiments of the present invention may be implemented for communication systems and electronic devices in general. Additionally, but not limited to, mechanics, electromechanics, electro-optics, and fluid mechanics may utilize the same principles for effectively amplifying and converting signals.

[0237] 5. Conclusion

[0238] The present invention has been described above with the aid of functional building blocks that illustrate their functions and relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries may be defined so long as the specified functions and their relationships are properly performed. Therefore, any such alternative boundaries are within the scope and spirit of the claimed invention. Those skilled in the art will recognize that these functional building blocks may be implemented by discrete components, application specific integrated circuits, processors running appropriate software, and the like, and combinations thereof.

[0239] Although various embodiments of the present invention have been described above, it should be understood that they are presented by way of example only and not limitation. Therefore, the breadth and scope of the present invention should not be limited by any of the above exemplary embodiments, but should only be defined in accordance with the following claims and their equivalents.

Claims

1. A method for using multiple quantized digitally controlled supply voltages for power amplification of multiple amplifier stages, the method comprising the following steps: Receiving an input signal (101) carrying information bits to be transmitted; receiving a first clock signal (102) having a value set according to a signal frequency of the input signal; Receiving a second clock signal (103) having a value set according to a desired sampling rate of the input signal; receiving a third clock signal (104) having a desired output signal frequency according to the desired output signal; By selecting the bits to be applied to N on different information blocks or on each data block of the input signal carrying the information bits bq N power amplifiers bq Voltage supply value V dd to receive slow and fast power control signals to control the power having N bq The output power of the amplifier stage of a power amplifier; Sampling the input signal carrying the information bits at the desired sampling rate to generate samples of the input signal (106); processing the samples to generate an in-phase component and a quadrature component (107) for each sample; Processing quantization, using N in the quantizer bq The in-phase component and the quadrature component of each sample are processed by quantizing bits to generate N corresponding to the quantized values ​​of the in-phase component and the quadrature component, respectively. bq quantization bits (108); The N quantized values ​​of the in-phase component are individually mapped in a digital mapper. bq The N quantized bits are processed to generate a corresponding magnitude and phase of the polarity representation of each quantized bit, and the N quantized values ​​of the orthogonal components are individually mapped in the digital mapper. bq quantized bits are processed to generate a corresponding amplitude and phase of the polarity representation of each quantized bit, wherein the corresponding amplitude associated with each quantized bit is defined according to the decomposition of the quantized value into polarity in-phase component and quadrature component, and for the in-phase component, the amplitude is determined by N bq Amplitude|c I，i | is given by the set of |, for the orthogonal components, the amplitude is given by N bq Amplitude|c q，i | is given by (109); For the in-phase component N bq Amplitude|c I，i | and N for the orthogonal components bq Amplitude|c q，i | is processed to generate a selection to be applied to the N bq N power amplifiers bq Voltage supply value V dd The control information (110) of the corresponding set of the polarity in-phase component is processed by multiplying a pulse signal having a desired spectral shape (111A), and the polarity quadrature component is processed by multiplying a pulse signal having a desired spectral shape (111B); The in-phase and quadrature signals are processed by summing pairs of signals with the same amplitude to generate N signals with a constant envelope and a sum equal to a quantized version of the input signal. bq A collection of signals (113); The obtained N with a constant envelope bq multiplying a set of signals by a periodic signal (114) having a frequency of a radio frequency (RF) signal; Based on the decomposition of the quantized value and the slow and fast power control signals, N bq Voltage supply value V dd The corresponding set and / or drive current of the amplifier stage N bq A power amplifier is biased (115); In the amplifier stage N bq In each of the power amplifiers, N bq Each of the component signals is amplified, and the amplified N constant envelope component signals are combined in the combiner. bq The component signals are summed to produce a desired output signal that is an amplified, quantized version of the sampled input signal carrying the information bits (116).

2. The method according to claim 1, wherein: The step of receiving the input signal (101) carrying the information bits comprises: Receive a band-limited information signal with a time-varying envelope, or receive an in-phase component and a quadrature-phase component of a band-limited information signal with a time-varying envelope, or receive samples of an in-phase component and a quadrature component of a band-limited information signal with a time-varying envelope, or include receiving samples of a band-limited information signal with a time-varying envelope.

3. The method according to claim 1, wherein: The quantizer and the digital mapper are performed by a block using a quantizer followed by a mapper for samples of both the in-phase component and the orthogonal component, or using two quantizers followed by two mappers, one quantizer for each in-phase component and the orthogonal component and for quantization, and wherein the mapping rules are performed by a comparator and a lookup table (LUT) having corresponding quantization bits of the quantized values.

4. The method according to claim 1, wherein: The step of quantizing said samples of said input signal carrying information bits to generate said quantization bits uses a number of quantization bits that can vary between different samples of said input signal carrying said information bits.

5. The method according to claim 1, wherein: The quantization and polarity of each quantization bit are represented by a comparator and having the N bq The N quantization bits can be performed by using a lookup table (LUT) of the corresponding amplitude and phase of the polarity component of the quantized bits, or by directly quantizing and generating the N bq This is done once for blocks of quantized bits, magnitudes and phases of polarity components of the quantized values ​​of the in-phase component and the quadrature component.

6. The method according to claim 1, wherein: Select the N bq N power amplifiers bq Voltage supply value V dd The generation of the corresponding set of control information is performed by having a corresponding V to be applied to each power amplifier dd , or by direct quantization and generation of N bq quantization bits, the amplitude and phase of the polarity components for the in-phase component and the quadrature component, and the voltage supply value V dd The corresponding set of control information blocks is completed once.

7. The method according to claim 1, wherein: The step of sampling the input signal includes sampling the input signal at the desired sampling rate to generate samples of the in-phase component and the quadrature component of the input signal; The quantization step comprises two quantizers, wherein one quantizer is used in the quantization of each sample of the in-phase component and generates N corresponding to the quantized version of said sample. bq quantization bits, and another quantizer is used to quantize each sample of the orthogonal component and generate N corresponding to the quantized version of the sample of the orthogonal component bq quantization bits; For the in-phase component N bq Amplitude|c I，i | and N for the orthogonal components bq Amplitude|c q，i | is processed to generate a selection to be applied to N bq N amplifiers bq Voltage supply value V dd The step of generating the control information corresponding to the phase set to be applied to the N bq The bias current of the amplifier is N bq A collection of values.

8. The method according to claim 1, wherein: Feedback is coupled to each power amplifier branch to give the information required for digital predistortion to compensate for the amplifier impairments.

9. An apparatus for using multiple quantized digitally controlled supply voltages for power amplification of multiple amplifier stages, the apparatus comprising: input signal circuitry for receiving an input signal carrying information bits to be transmitted; a first clock input circuit for receiving a first clock signal having a value set according to a signal frequency of the input signal; a second clock input circuit for receiving a second clock signal having a value set according to a desired sampling rate of the input signal; a third clock input circuit for receiving a third clock signal at a desired output signal frequency of the desired output signal; a sampling circuit for sampling the input signal carrying the information bits at the desired sampling rate to generate samples of the input signal; A digital mapper circuit for receiving the samples of the input signal and generating an in-phase component and a quadrature component of each sample, the in-phase component and the quadrature component of each sample being N bq The bit quantizer converts it into two sets of parallel quantized bit signals, which are used by a mapper that is a lookup table to generate a signal with in-phase amplitude coefficients |c I，i | gives the polarity of the amplitude signal and has a quadrature amplitude coefficient given by |c q，i |Polarity of the given amplitude signal; V dd A voltage mapper circuit generates N based on the slow and fast power control signals using the signal provided by the digital mapper circuit. bq A set of control signals, the N bq A set of control signals is used to select the voltage supply value V to be applied to the amplifier dd A collection of; a circuit having a phase shifter and a polarity converter, the circuit generating a phase rotation associated with each quantized bit and a corresponding polarity representation and adjusting a delay between the polarity signals associated with the quantized bits; For the in-phase amplitude coefficient |c I，i | to adjust the amplitude of each in-phase polarity signal to generate N bq a circuit for forming in-phase components of the signal, and for determining the quadrature amplitude coefficient |c q，i | to adjust the amplitude of each orthogonal polarity signal to generate N bq A circuit that forms orthogonal signals; a set of filters having the same impulse response, the set of filters receiving the in-phase component signal and the quadrature component signal and filtering them to ensure a desired spectral shape; It is used to combine the in-phase component signal and the orthogonal component signal pair to generate an N-type signal with a quasi-constant envelope or a constant envelope. bq A circuit that forms a collection of signals; For receiving the N with a quasi-constant envelope or a constant envelope bq component signals and up-converting them by multiplying each component signal by a periodic signal having the frequency of the desired output signal; With parallel N bq An amplifier stage circuit of a power amplifier, the amplifier stage circuit receiving an up-converted quasi-constant envelope or constant envelope component signal, including at least N with different power output levels bq The power output level is determined by the voltage supply value V provided by the digital mapper circuit. dd wherein each of the substantially constant envelope constituent signal components is amplified by the power amplifier of its branch; Fast and slow power control block circuits that control the power to be applied to the N bq The voltage supply value V of the active power amplifier branch dd Choice; The DC / DC converter circuit receives control information from the fast and slow power control block circuits to generate N used in the amplifier stage circuit. bq Voltage supply value V dd The collection and bias signals of Coupled to the amplifier stage circuit N bq A combiner circuit with branches, wherein the combiner circuit is configured to generate a plurality of branches according to the N bq The set of control signals will be connected in parallel to N bq The outputs of the power amplifiers are combined.

10. The device according to claim 9, wherein: Receiving, by the input signal circuit, an input signal carrying the information bit comprises: A band-limited information signal with a time-varying envelope, or an in-phase component and a quadrature component of a band-limited information signal with a time-varying envelope, or samples of an in-phase component and a quadrature component of a band-limited information signal with a time-varying envelope, or samples of a band-limited information signal with a time-varying envelope.

11. The device according to claim 9, wherein: N bq The quantizer circuit includes two quantizer circuits connected in parallel, wherein one quantizer circuit is a sample of the in-phase component and generates N corresponding to a quantized version of the sample. bq quantization bits, and another quantizer quantizes each sample of the orthogonal component and generates N corresponding to the quantized version of the sample of the orthogonal component bq quantization bits; The digital mapper circuit includes two polarity converters, one with the in-phase component N bq One quantized bit is associated with the polarity signal, and the other is associated with the quadrature component N bq The polarity signal of each quantized bit is associated; The digital mapper circuit includes two signal mapper circuits connected in parallel, each signal mapper circuit is coupled to a quantizer, and one of the two signal mapper circuits generates N bq component signal components, wherein the quantized samples of the in-phase component are decomposed and the second generates N bq constituent signal components, wherein the quantized samples of the orthogonal components are decomposed, the constituent signal components having only a discrete number of amplitudes and a discrete number of phases belonging to two sets of phase and amplitude values ​​having a maximum size equal to the number of quantization bits; Circuitry for combining in-phase and quadrature constituent signal components with the same amplitude derived from the digital mapper circuit to generate a set of substantially constant envelope constituent signals that sum to equal the quantized samples of the signal.

12. The device according to claim 9, wherein: The digital mapper circuit comprises: a phase splitter circuit for receiving the samples and generating an in-phase component and a quadrature component for each sample; a digital mapper circuit that receives the quantization bits from the quantizer and generates the in-phase amplitude coefficient |c based on a decomposition of the quantized values ​​of the in-phase component and the quadrature component for each sample as a sum of fixed amplitude components I，i | and the orthogonal amplitude coefficient |c q，i |, and generate V dd a set of control signals proportional to the amplitude coefficients to be used by the voltage mapper; V dd voltage mapper, the V dd The voltage mapper generates the voltage supply value V dd The corresponding set of N bq A collection of control signals and digital control signals to the fast and slow power control block circuits.

13. The device according to claim 9, wherein: The input signal circuit, the first clock input circuit, the second clock input circuit, the third clock input circuit, the sampling circuit, the digital mapper circuit, the voltage mapper circuit, the phase shifter, the polarity converter and the circuit for combining in-phase component signals and orthogonal component signal pairs having the same amplitude are implemented by discrete electronic components, a digital signal processor or software in a field programmable gate array (FPGA).

14. The device according to claim 9, wherein: The N bq Each of the power amplifiers has a unique voltage supply value Vdd from the set of Vdd values ​​and is applied to the N bq The bias of the amplifier stage of the amplifier is applied to the N bq The V dd The value and the bias are composed of the fast and slow power control block circuit power and V dd The output of the control block sends a control signal to the DC / DC converter circuit, which defines the V to be generated by the DC / DC converter circuit. dd A collection of values.

15. The apparatus according to claim 9, further comprising: A low dropout regulator (LDO) is used to generate the V used in the amplifier stage. dd A collection of voltage supply values ​​and bias signals.

16. The device according to claim 9, wherein: The amplifier stage circuit N bq The outputs of the power amplifiers have different power levels due to the amplification of the respective input signals and according to each voltage supply value V applied to each power amplifier. dd And get it.

17. The device according to claim 9, wherein: Each power amplification branch comprises a plurality of power amplification stages represented by limiters of signals provided to parallel power drivers, each power amplification stage providing an input signal to a corresponding switch of each power amplifier, Each power amplifier comprises two complementary switches based on transistors, followed by a bandpass filter consisting of passive reactive elements.

18. The device according to claim 9, wherein: The digital mapper circuit includes one or more lookup tables that are used to process the quantized bits.

19. The device according to claim 9, wherein: With parallel N bq The amplifier stage circuit of the power amplifier includes multiple power amplifiers, and the multiple power amplifiers are current source amplifiers or switching amplifiers.

20. The device according to claim 9, wherein: With N bq The amplifier stage circuit of a power amplifier comprises: A plurality of bipolar junction transistors (BJTs) of NPN type or PNP type; or A plurality of field effect transistors (FETs) having N-channel or P-channel; or A plurality of field effect transistors (FETs) with N-channel or P-channel using silicon based metal oxide semiconductor (MOS) technology; or A plurality of field effect transistors (FETs) with N-channel or P-channel using gallium arsenide (GaAs) technology, gallium nitride (GaN) technology and / or silicon germanium (SiGe) technology.

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