Scan test circuit, scan test method and test system

Abstract

An embodiment of the present disclosure provides a scan test circuit, comprising an input pin, N clock control units and 2N shift units, where N is a positive integer; the input pin receives a test input signal and outputs it to the 2N shift units; the Mth clock control unit receives a first clock signal and outputs it to the 2M-1th shift unit; the 2M-1th shift unit outputs a first test output signal according to the first clock signal and the test input signal, and outputs a first test result according to a first feedback signal received from a first circuit to be tested; the Mth clock control unit generates a second clock signal complementary to the first clock signal according to the first clock signal and outputs it to a coupled 2Mth shift unit; the 2Mth shift unit outputs a second test output signal according to the second clock signal and the test input signal, and outputs a second test result according to a second feedback signal received from a second circuit to be tested.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of electronic technology, and in particular to a scan test circuit, a scan test method, and a test system. Background Art

[0002] Integrated circuits integrate various digital and analog components and may have manufacturing defects, such as short circuits, open circuits, material defects, and damaged vias. Such manufacturing defects may cause the integrated circuit to fail. Therefore, it is important to test for manufacturing defects. However, the steadily decreasing size and increasing density and complexity of integrated circuit devices such as processors have made testing more difficult and expensive. In the field of scan testing, there is a problem of low scan test efficiency. Summary of the invention

[0003] According to a first aspect of an embodiment of the present disclosure, a scan test circuit is provided, wherein the scan test circuit comprises an input pin, N clock control units and 2N shift units, where N is a positive integer; wherein,

[0004] The input pins are respectively coupled to the input ends of the 2N shift units, and are configured to receive a test input signal and output the test input signal to the 2N shift units;

[0005] The output end of the Mth clock control unit is coupled to the clock input end of the 2M-1th shift unit and the clock input end of the 2Mth shift unit respectively; wherein the output ends of different clock control units are coupled to the clock input ends of different shift units, and M is a positive integer less than or equal to N;

[0006] The Mth clock control unit is configured to receive a first clock signal and output the first clock signal to the 2M-1th shift unit;

[0007] The 2M-1th shift unit is configured to output a first test output signal according to the received first clock signal and the test input signal; the 2M-1th shift unit is further configured to output a first test result according to a first feedback signal sent by the received first circuit under test; wherein the first circuit under test generates the first feedback signal according to the first test output signal;

[0008] The Mth clock control unit is further configured to generate a second clock signal complementary to the first clock signal according to the received first clock signal, and output the second clock signal to the coupled 2Mth shift unit;

[0009] The 2Mth shift unit is configured to output a second test output signal based on the received second clock signal and the test input signal; the 2Mth shift unit is also configured to output a second test result based on the received second feedback signal sent by the second circuit under test; wherein the second circuit under test generates the second feedback signal based on the second test output signal.

[0010] According to a second aspect of an embodiment of the present disclosure, a scan test method is provided, the method comprising:

[0011] receiving a first clock signal, and outputting the first clock signal to a coupled shift unit;

[0012] generating a second clock signal complementary to the first clock signal, and outputting the second clock signal to another coupled shift unit;

[0013] receiving a test input signal;

[0014] outputting a first test output signal according to the received first clock signal and the test input signal;

[0015] Outputting a first test result according to a first feedback signal sent by a first circuit under test; wherein the first circuit under test generates the first feedback signal according to the first test output signal;

[0016] outputting a second test output signal according to the received second clock signal and the test input signal;

[0017] Outputting a second test result according to a received second feedback signal sent by a second circuit under test; wherein the second circuit under test generates the second feedback signal according to the second test output signal.

[0018] According to a third aspect of an embodiment of the present disclosure, a test system is provided, including:

[0019] The scan test circuit as described in the above embodiment;

[0020] a memory device coupled to the scan test circuit;

[0021] A test device, the test device is coupled to the scan test circuit and is configured to provide a test input signal and a first clock signal to the scan test circuit to test the memory device; wherein the time for the scan test circuit to perform a scan shift operation is recorded as a scan clock cycle, and the clock cycle of the first clock signal is 2N times the scan clock cycle.

[0022] The embodiment of the present disclosure provides a scan test circuit, including an input pin, N clock control units and 2N shift units, where N is a positive integer. The Mth clock control unit receives a first clock signal and outputs it to the 2M-1th shift unit; the Mth clock control unit also generates a second clock signal complementary to the first clock signal according to the first clock signal and outputs it to the coupled 2Mth shift unit. In the embodiment of the present disclosure, different shift units are connected to the same input pin, and two complementary clock signals are obtained by the clock control unit and respectively input to two different shift units. Therefore, compared with coupling with different shift units through different input pins to provide test input signals for different shift units, the embodiment of the present disclosure can provide test input signals for two different shift units through one input pin, and use the complementary first clock signal and the second clock signal to enable the 2M-1th and 2Mth shift units to capture the signals input by the same input pin respectively, thereby reducing the number of required input pins.

[0023] In addition, compared to an input pin that can only provide a test input signal to a shift unit for scan testing, forming a scan channel, an input pin in the embodiment of the present disclosure can provide a test input signal to multiple shift units for scan testing, forming multiple scan channels. Therefore, with the same number of chip pins, the number of scan channels used for scan testing in the embodiment of the present disclosure is significantly increased. Since the more scan channels there are, the higher the scan quality, the embodiment of the present disclosure can significantly improve the quality of the scan test. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a circuit structure diagram of a scan test circuit according to an exemplary embodiment;

[0025] Figure 2 yes Figure 1 A timing diagram of a scan test circuit;

[0026] Figure 3 is a block diagram of another scan test circuit according to an exemplary embodiment;

[0027] Figure 4a is a first schematic diagram of a circuit structure of another scan test circuit according to an exemplary embodiment;

[0028] Figure 4b is a second schematic diagram of a circuit structure of another scan test circuit according to an exemplary embodiment;

[0029] Figure 5 yes Figure 4a A timing diagram of another scan test circuit;

[0030] Figure 6 yes Figure 4b A timing diagram of another scan test circuit;

[0031] Figure 7 It is a flowchart of a scanning test method according to an exemplary embodiment. DETAILED DESCRIPTION

[0032] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0033] The present disclosure is described in more detail in the following paragraphs by way of examples with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer based on the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure. In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions recorded in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0034] Figure 1 FIG. 1 is a schematic diagram of a circuit structure of a scan test circuit according to an exemplary embodiment. Figure 1 As shown, the scan test circuit includes: 2 input pins, denoted as IN1 and IN2; 2 output pins, denoted as OUT1 and OUT2; 1 scan clock input terminal, denoted as SCAN_CLK; 1 enable input terminal, denoted as SCAN_EN; 2 triggers, denoted as D1 and D2; and 4 scan registers, denoted as F0, F1, F2 and F3 respectively; among which,

[0035] The scan input terminal SD of the trigger D1 is coupled to the input pin IN1, the output terminal Q of the trigger D1 is coupled to the scan input terminal SD of the scan register F0, the output terminal Q of the scan register F0 is coupled to the scan input terminal SD of the scan register F1, the output terminal Q of the scan register F1 is coupled to the output pin OUT1, and the combinational logic unit CL is respectively coupled to the scan input terminal SD of the scan register F1, the data input terminal D of the scan register F1, the output terminal Q of the scan register F0 and the output terminal Q of the scan register F1.

[0036] The scan input terminal SD of the trigger D2 is coupled to the input pin IN2, the output terminal Q of the trigger D2 is coupled to the scan input terminal SD of the scan register F2, the output terminal Q of the scan register F2 is coupled to the scan input terminal SD of the scan register F3, and the output terminal Q of the scan register F3 is coupled to the output pin OUT2. It should be noted that there is another combinational logic unit ( Figure 1 The first and second terminals (not shown) are respectively coupled to a scan input terminal SD of the scan register F3, a data input terminal D of the scan register F3, an output terminal Q of the scan register F2 and an output terminal Q of the scan register F3.

[0037] The scan clock input terminal SCAN_CLK is respectively coupled to the clock terminal CLK of each flip-flop and each scan register, and the enable input terminal SCAN_EN is respectively coupled to the enable terminal SE of each flip-flop and each scan register.

[0038] Specifically, there is a scan chain between the input pin IN1 and the output pin OUT1, and another scan chain between the input pin IN2 and the output pin OUT2. Figure 1 The number of scan chains formed is 2. The first-level scan unit (i.e., trigger D1 or trigger D2) of each scan chain receives a clock signal input from the scan clock input terminal SCAN_CLK, and at the rising edge of the clock signal, the trigger D1 receives data input from the input pin IN1, and the trigger D2 receives data input from the input pin IN2.

[0039] Figure 2 1 is a timing diagram of a scan test circuit according to an exemplary embodiment. In order to assign the four scan registers F0, F1, F2, and F3 to the 4-bit binary value 1001 when shifting, the waveform diagram of the input signal of the scan clock input terminal SCAN_CLK and the two input pins IN1 and IN2 is as shown in FIG. Figure 2 shown.

[0040] Specifically, data is captured for the input signals of the two input pins IN1 and IN2 at the rising edge of the input clock signal at the scan clock input terminal SCAN_CLK, wherein the values ​​of the input signals of the two input pins IN1 and IN2 remain unchanged within a clock cycle (e.g., T0, T1, T2, or T3, etc.), and the rising edge is a process of switching from a logic low level (e.g., 0) to a logic high level (e.g., 1). The above process of capturing data at the rising edge of the input signal at the scan clock input terminal SCAN_CLK needs to meet the "Setup / Hold Time Check" condition, and the "Setup / Hold Time Check" condition includes a setup time condition, a hold time condition, a setup check condition, and a hold check condition.

[0041] The "setup and hold time check" condition is used to check whether a timing path in a scan test circuit has one or more of a setup time violation, a hold time violation, a setup check violation, and a hold check violation.

[0042] The setup time condition refers to the minimum time that the data signal input to the data end of the register needs to remain stable before the rising edge of the clock signal at the clock end of the register arrives. The preset setup time can be set to 1ns considering the chip power consumption and area. For example, the setup time violation includes: the setup time of the device in the timing path in the scan test circuit is less than 1ns.

[0043] The Hold Time condition refers to the shortest time that the data signal at the data end continues to remain stable after the rising edge of the clock signal at the clock end arrives. The preset setup time can be set to 2ns in consideration of chip power consumption and area. For example, a Hold Time violation includes: the Hold Time of a device in a timing path in a scan test circuit is less than 2ns.

[0044] For the Setup Check condition, for example, the Setup Check violation includes when data is transferred from register 1 to register 2, the data transfer path between the two registers is too long, and the data may invade the setup time of register 2, causing register 2 to fail to accurately latch the data. The Setup Check condition requires that the data transfer cannot be too slow.

[0045] For the Hold Check condition, for example, a Hold Check violation includes when register 1 transfers data to register 2, the data transmission path between the two registers is too short, and the data will reach the data end of register 2 in a very short time. At this time, register 2 may still be latching the previous data, and the data invades the Hold Time of register 2, resulting in register 2 being unable to accurately latch the previous data. The Hold Check condition requires that data transmission cannot be too fast. Here, the violation of the "Establish Hold Time Check" condition is an exemplary explanation, and it needs to be judged according to the specific situation of the timing path in the actual circuit.

[0046] For the half waveform after the rising edge of the input clock signal at the scan clock input terminal SCAN_CLK ( Figure 2 As shown in “useless” in the figure, on the premise that the duration of the half-segment waveform meets the above-mentioned “setup and hold time check” condition, the duration of the half-segment waveform can be shortened, thereby reducing the clock period of the scan clock input terminal SCAN_CLK input clock signal and reducing the test time.

[0047] Due to the limitation of the maximum output speed of the test machine ATE and the limitation of the scan mode shift power and other factors, the clock cycle of the scan clock input terminal SCAN_CLK input clock signal often needs to be slowed down when the test machine performs scan testing. Therefore, the half waveform after the rising edge of the scan clock input terminal SCAN_CLK input clock signal ( Figure 2 The “useless” in the figure does not capture data of the input signals of the input pins IN1 and IN2, which is a waste.

[0048] For example, at the rising edge of the input clock signal at the scan clock input terminal SCAN_CLK, the input signals of the two input pins IN1 and IN2 are captured data, and the clock period of the clock signal that meets the "setup and hold time check" condition may be 10ns.

[0049] The frequency of the clock signal input to the scan clock input terminal SCAN_CLK can be 100MHz, but this clock signal frequency is very fast for the test machine ATE. In addition, due to factors such as scan mode shift power and probe card, the final test machine ATE basically cannot achieve an output clock signal with a frequency of 100MHz, and the test machine ATE needs to be slowed down. For example, the test machine ATE finally outputs a clock signal with a frequency of 25MHz, that is, the clock period of the clock signal input to the scan clock input terminal SCAN_CLK is 40ns.

[0050] The half waveform after the rising edge of the clock signal input at the scan clock input terminal SCAN_CLK ( Figure 2 The clock period of the half-segment waveform is 40ns to 10ns, and the clock period of the half-segment waveform is 30ns, which is a redundancy added during design. Therefore, in order to reduce the clock period of the scan clock input terminal SCAN_CLK input clock signal and thus reduce the test time, the present disclosure improves the above "useless" area.

[0051] Here, the design for test (DFT) technology can be used to test the combinational logic units in the chip. In the design for testability technology, scan testing is a test technology that tests the logic circuit by verifying the output data based on the input scan pattern data. Scan testing can be used to identify the faults of the combinational logic unit, such as stuck faults, transition delay faults, etc.

[0052] In the field of scan testing for testability design, scan chain is a common technology for testing chip logic circuits. The maximum number of scan chains composed of scan input channels and scan output channels is often limited by the number of general-purpose input and output pins (GPIO PADs) that can be used for scan testing on the chip itself. In order to improve the quality of scan testing, the number of scan chains should be increased as much as possible during design.

[0053] In view of this, an embodiment of the present disclosure provides another scan test circuit.

[0054] Figure 3 is a block diagram of another scan test circuit according to an exemplary embodiment. Figure 3 As shown, the scan test circuit includes an input pin 100, N clock control units 200 and 2N shift units 300, where N is a positive integer;

[0055] The input pins 100 are respectively coupled to the input terminals of the 2N shift units 300 , and are configured to receive a test input signal and output the test input signal to the 2N shift units 300 ;

[0056] The output end of the Mth clock control unit 200 is coupled to the clock input end of the 2M-1th shift unit 300 and the clock input end of the 2Mth shift unit 300 respectively; wherein the output ends of different clock control units 200 are coupled to the clock input ends of different shift units 300, and M is a positive integer less than or equal to N;

[0057] The Mth clock control unit 200 is configured to receive the first clock signal and output the first clock signal to the 2M-1th shift unit 300;

[0058] The 2M-1 shift unit 300 is configured to output a first test output signal according to a received first clock signal and a test input signal; the 2M-1 shift unit 300 is further configured to output a first test result according to a received first feedback signal sent by a first circuit under test; wherein the first circuit under test generates a first feedback signal according to the first test output signal;

[0059] The Mth clock control unit 200 is further configured to generate a second clock signal complementary to the first clock signal according to the received first clock signal, and output the second clock signal to the coupled 2Mth shift unit 300;

[0060] The 2Mth shift unit 300 is configured to output a second test output signal based on the received second clock signal and the test input signal; the 2Mth shift unit 300 is also configured to output a second test result based on the received second feedback signal sent by the second circuit under test; wherein the second circuit under test generates a second feedback signal based on the second test output signal.

[0061] Reference Figure 3 and Figure 4a , N=1 is used for illustration. However, the present disclosure is not limited thereto.

[0062] like Figure 3 In the circuit architecture shown, the input ends of the first shift unit and the second shift unit are coupled to the same input pin 100 to receive the test input signal. The first shift unit and the second shift unit can constitute two scan chains of the scan test circuit. The clock control unit 200 can receive a first clock signal and output it to the first shift unit; the clock control unit also generates a second clock signal complementary to the first clock signal based on the first clock signal and outputs it to the coupled second shift unit.

[0063] The following will refer to Figure 4a and Figure 5 The specific operating principle of the shift unit is explained.

[0064] For example, for a large-scale system-on-chip (SOC), assuming that the first clock signal inputted by the scan clock input terminal PAD_SCAN_CLK satisfies the minimum clock period of the setup and hold time of 10ns, and the clock period of the clock signal outputted by the test machine ATE is 20ns, namely 50MHz.

[0065] Here, L may be used to represent L stages in one clock cycle. One clock cycle of the first clock signal input by the test equipment ATE may be decomposed into L stages, wherein L is greater than or equal to 2.

[0066] Specifically, according to Figure 4aThe circuit architecture shown can convert a clock cycle of the first clock signal (for example Figure 5 In the figure, T0) is divided into two phases, namely phase 1 and phase 2. In each phase of a clock cycle, if the test input signal inputted by the input pin PAD_SCAN_IN1 needs to capture data at the rising edge or falling edge of the first clock signal, the "setup and hold time check" condition must be met. Therefore, the time length of each phase in a clock cycle is at least 10ns.

[0067] The clock cycle of the first clock signal output by the test machine ATE is 20ns, and the clock cycle of each stage is 10ns. One clock cycle of the first clock signal can be divided into two stages, such as Figure 5 As shown, the clock cycle T0 is divided into phase 1 and phase 2, and the clock cycles of phase 1 and phase 2 are 10ns. Similarly, if the clock cycle of the first clock signal output by the test machine ATE is 40ns, the clock cycle T0 can be divided into 4 phases.

[0068] Specifically, Figure 5 As shown, in a clock cycle T0, for phase 1, the first shift unit captures data of the test input signal at the rising edge of the first clock signal. For phase 2, at the falling edge of the first clock signal, no matter how the test input signal changes, since the first shift unit is not triggered by the rising edge, it will not affect the first shift unit.

[0069] The two complementary clock signals obtained by the clock control unit 200 are respectively input into two different shift units, that is, the second shift unit receives the second clock signal. For the second shift unit, the test input signal is captured at the rising edge of the second clock signal, that is, the second shift unit is triggered at the falling edge of the first clock signal. Therefore, in phase 1, no matter how the test input signal changes, since the second shift unit is not triggered by the falling edge, it will not have any effect on the second shift unit.

[0070] To achieve Figure 4a An input pin PAD_SCAN_IN1 is connected to the input ends of two shift units, and a circuit architecture for inputting a test input signal at the same time is disclosed. The embodiment of the present disclosure can provide a test input signal to two shift units through an input pin, and use a complementary first clock signal and a second clock signal to enable the first and second shift units to capture the signal input by the same input pin, respectively, thereby reducing the number of required input pins. That is, in stage 1, the first shift unit captures data of the test input signal at the rising edge of the first clock signal, and in stage 2, the second shift unit captures data of the test input signal at the falling edge of the first clock signal.

[0071] In the related art, please refer to Figure 1 , usually different shift units are coupled to different input pins. For example, the first shift unit is coupled to an input pin IN1, and the second shift unit is coupled to another input pin IN2 different from the input pin IN1. Figure 1 Based on the illustrated architecture, if the number of test chains needs to be increased, the number of input pins, shift units, and output pins needs to be increased, which will increase the cost. Specifically, for every two test chains added, the number of input pins, shift units, and output pins needs to be increased by two.

[0072] By using the technical solution provided by the embodiment of the present disclosure, two complementary clock signals can be obtained through one clock control unit and input into the first shift unit and the second shift unit respectively. At this time, the first shift unit and the second shift unit can be connected to the same input pin IN1. The existing input pin IN2 can be reused as a pin for constituting a scan output channel, or as a pin for other purposes. The technical solution provided by the embodiment of the present disclosure is highly compatible with the prior art.

[0073] Further, in Figure 1 Based on the architecture shown, if two test chains need to be added, only two shift units and two output pins need to be added, and the existing input pin IN2 and the added shift unit and output pin can be used to form a scan chain, which is beneficial to reduce the number of pins compared to the prior art.

[0074] Reference Figure 3 and Figure 4b , explained with N=2.

[0075] like Figure 4b In the circuit architecture shown, the input ends of the first shift unit, the second shift unit, the third shift unit, and the fourth shift unit are all coupled to the same input pin PAD_SCAN_IN1 to receive the test input signal. One input pin PAD_SCAN_IN1 can be connected to four scan chains.

[0076] At this time, multiple scan clocks are required to implement the use of different clock rising edges or falling edges at different stages in a clock cycle to simultaneously input test input signals to two different shift units.

[0077] Specifically, the first clock control unit can receive the first clock signal and output it to the first shift unit; the first clock control unit also generates a second clock signal complementary to the first clock signal based on the first clock signal and outputs it to the coupled second shift unit.

[0078] The second clock control unit can receive the third clock signal and output it to the third shift unit; the second clock control unit also generates a fourth clock signal complementary to the third clock signal according to the third clock signal and outputs it to the coupled fourth shift unit.

[0079] In the related art, based on the existing scan test circuit architecture composed of four shift units, different shift units are usually coupled to different input pins. For example, the first shift unit is coupled to an input pin IN1, the second shift unit is coupled to another input pin IN2, the third shift unit is coupled to another input pin IN3, and the fourth shift unit is coupled to another input pin IN4. Based on the existing scan test circuit architecture composed of four shift units, if the number of test chains needs to be increased, the number of input pins, shift units and output pins needs to be increased, which will increase the cost. Specifically, for every two test chains added, the number of input pins, shift units and output pins needs to be increased by two.

[0080] By using the technical solution provided by the embodiment of the present disclosure, two complementary clock signals can be obtained through the first clock control unit and input to the first shift unit and the second shift unit respectively, and two complementary clock signals can be obtained through the second clock control unit and input to the third shift unit and the fourth shift unit respectively. At this time, the first shift unit, the second shift unit, the third shift unit and the fourth shift unit can be connected to the same input pin IN1. The existing input pins IN2, IN3 and IN4 can be reused as pins for constituting a scan output channel, or as pins for other purposes. The technical solution provided by the embodiment of the present disclosure is highly compatible with the prior art.

[0081] Furthermore, based on the existing scan test circuit architecture composed of four shift units, if two test chains need to be added, only two shift units and two output pins need to be added, and the existing input pin IN2 (or input pin IN3, or input pin IN4) can be used with the added shift unit and output pin to form a scan chain, which is beneficial to reduce the number of pins compared to the existing technology.

[0082] The operating principle of each shift unit when N=2 can refer to the analysis when N=1 above, and will not be repeated here.

[0083] The shifting operation when each shift unit 300 receives a test input signal to perform a scan test is specifically analyzed in the following embodiments.

[0084] In the embodiment of the present disclosure, for the test circuit structure of asymmetric scan channels, that is, the number of scan input channels is not equal to the number of scan output channels. In this case, the utilization rate of the scan input channels can be increased by L times. For the test circuit structure of symmetric scan channels, that is, the number of scan input channels is equal to the number of scan output channels, the input pins and output pins are recombined, and the number of scan chains can be increased by (L-1) / (L+1) times, where L is greater than or equal to 2.

[0085] The circuit architecture of the scan test circuit provided in the embodiment of the present disclosure can be widely used in the DFT scan test circuit architecture used by software such as Electronic Design Automation (EDA). The embodiment of the present disclosure improves the quality of scan testing as much as possible without increasing the design burden. For example, for a SOC chip, the original number of scan chains is 30 groups. If the scan test circuit architecture of L=2 of the present disclosure is adopted, the number of scan chains can be increased to 40 groups. If the scan test circuit architecture of L=4 of the present disclosure is adopted, the number of scan chains can be increased to 48 groups. The effect of increasing the number of scan chains is very obvious, thereby improving the quality of scan testing. In addition, the circuit architecture of the scan test circuit provided in the embodiment of the present disclosure can also be used for low pin count chips. The scan test circuit of the embodiment of the present disclosure reduces the input pins used for scan testing, effectively saving the number of chip pins.

[0086] In the embodiment of the present disclosure, different shift units are connected to the same input pin, and two complementary clock signals are obtained through the clock control unit and respectively input into two different shift units. Therefore, compared with coupling with different shift units through different input pins to provide test input signals for different shift units, the embodiment of the present disclosure can provide test input signals for two shift units through one input pin, and use the complementary first clock signal and the second clock signal to enable the 2M-1th and 2Mth shift units to capture the signals input to the same input pin respectively, thereby reducing the number of required input pins.

[0087] In addition, compared to an input pin that can only provide a test input signal to a shift unit for scan testing, forming a scan channel, an input pin in the embodiment of the present disclosure can provide a test input signal to multiple shift units for scan testing, forming multiple scan channels. Therefore, with the same number of chip pins, the number of scan channels used for scan testing in the embodiment of the present disclosure is significantly increased. Since the more scan channels there are, the higher the scan quality, the embodiment of the present disclosure can significantly improve the quality of the scan test.

[0088] In one embodiment, referring to Figure 4a, the clock control unit 200 includes: a clock input pin PAD_SCAN_CLK and an inverter 201; wherein,

[0089] The clock input pin PAD_SCAN_CLK is configured to receive a first clock signal and output the first clock signal to a clock input terminal of the 2M-1th shift unit;

[0090] The inverter 201 is coupled to the clock input pin PAD_SCAN_CLK, and is configured to generate a second clock signal according to the received first clock signal, and output the second clock signal to the clock input terminal of the 2Mth shift unit.

[0091] Specifically, when N=1, refer to Figure 4a , the first clock signal is input to the first shift unit through the clock input pin PAD_SCAN_CLK. The first clock signal is also output to the second shift unit after passing through the inverter 201. By capturing data at different stages of a clock cycle for the same test input signal at different clock edges, one input pin PAD_SCAN_IN1 can be coupled to multiple shift units, thereby reducing the number of input pins used for scan input.

[0092] Specifically, when N=2, refer to Figure 4b , the first clock signal is input to the first shift unit through the first clock input pin PAD_SCAN_CLK1. The first clock signal is also output to the second shift unit through the inverter 201. The third clock signal is input to the third shift unit through the second clock input pin PAD_SCAN_CLK2. The third clock signal is also output to the fourth shift unit after passing through the inverter 201.

[0093] Reference Figure 6 , in one clock cycle T0, for stage 1, the first shift unit ( Figure 4b In the embodiment, the test input signal is captured at the rising edge of the first clock signal (composed of D1, F0 and F1). For stage 4, at the falling edge of the first clock signal, no matter how the test input signal changes, since the first shift unit has no rising edge trigger, it will not affect the first shift unit.

[0094] For stage 4, the 4th shift unit ( Figure 4b The test input signal is captured at the rising edge of the second clock signal, that is, the fourth shift unit is triggered at the falling edge of the first clock signal. Therefore, in phase 1, no matter how the test input signal changes, since the fourth shift unit is not triggered by the falling edge, it will not have any effect on the fourth shift unit.

[0095] For stage 2, the second shift unit ( Figure 4b In the embodiment, the test input signal is captured at the rising edge of the third clock signal. For stage 3, at the falling edge of the third clock signal, no matter how the test input signal changes, the second shift unit will not be affected because there is no rising edge trigger on the second shift unit.

[0096] For stage 3, the third shift unit ( Figure 4b In the embodiment, the test input signal is captured at the rising edge of the fourth clock signal, that is, the third shift unit is triggered at the falling edge of the third clock signal. Therefore, in phase 2, no matter how the test input signal changes, since the third shift unit is not triggered by the falling edge, it will not have any effect on the third shift unit.

[0097] Here, the embodiment of the present disclosure is described with reference to the inverter 201. However, the present disclosure is not limited thereto, and the second clock signal complementary to the first clock signal may also be generated by other circuits.

[0098] In the disclosed embodiment, different shift units are connected to the same input pin, and two complementary clock signals are obtained through the inverter in the clock control unit and respectively input into two different shift units. Therefore, it is realized that at different stages of a clock cycle, the test input signals are respectively input into two different shift units with different clock edges for scan testing. Moreover, the above-mentioned function of the clock control unit is realized only by adding an inverter, which can reduce the occupied area of ​​the scan test circuit on the SOC chip and save costs.

[0099] In one embodiment, the scan test circuit further includes an enable input pin PAD_SCAN_EN; wherein,

[0100] The enable input pin PAD_SCAN_EN is respectively coupled to the enable input terminal SE of the shift unit and is configured to transmit the enable input signal to the shift unit;

[0101] a shift unit configured to receive a test input signal inputted from a scan input terminal SD when the received enable input signal is a first signal value, and execute a scan test mode according to the test input signal;

[0102] The shift unit is further configured to receive a logic input signal input from the data input terminal D when the received enable input signal is a second signal value, and execute a logic function mode according to the logic input signal; wherein the second signal value is different from the first signal value.

[0103] In the embodiment of the present disclosure, the shift unit may include an enable input terminal SE, a scan input terminal SD, a data input terminal D, a clock input terminal CLK, and an output terminal Q. The shift unit may selectively store data input from the data input terminal D or the scan input terminal SD according to signals input from the enable input terminal SE and the clock input terminal CLK, and may output the stored data as output data from the output terminal Q.

[0104] Here, the shift unit can execute two operation modes: a scan test mode and a logic function mode. The first signal value is a high level, and the second signal value is a low level.

[0105] Specifically, the scan test mode means that the shift unit stores the data input at the scan input terminal SD at the rising edge (or falling edge) of the clock signal input at the clock input terminal CLK based on the high-level enable input signal input at the enable input terminal SE, and outputs the stored data as output data at the output terminal Q.

[0106] The logic function mode means that the shift unit stores the data input at the data input terminal D at the rising edge (or falling edge) of the clock signal input at the clock input terminal CLK based on the low-level enable input signal input at the enable input terminal SE, and outputs the stored data as output data at the output terminal Q.

[0107] In the disclosed embodiment, the shift unit can execute two operation modes: scan test mode and logic function mode. When scan test is not required, the shift unit can execute logic function mode to realize the logic function of the shift unit itself, thereby improving the utilization rate of the scan test circuit during the period when scan test is not performed.

[0108] In one embodiment, the shift unit includes a trigger and P scan registers; wherein P is a positive integer;

[0109] When P is greater than 1, the trigger, coupled to the scan input terminal of the first scan register, is configured to generate a first shift signal or a second shift signal according to the received test input signal and output it to the first scan register;

[0110] The output end of the first scan register is coupled to the scan input end of the Pth scan register, and the output end of the Pth scan register is coupled to the test output pin;

[0111] The P scan registers are configured to generate a first test output signal according to the first shift signal; or the P scan registers are configured to generate a second test output signal according to the second shift signal;

[0112] The Pth scan register is configured to output a first test result according to a received first feedback signal; or the Pth scan register is configured to output a second test result according to a received second feedback signal;

[0113] When P is equal to 1, the flip-flop, coupled to the scan input terminal of the scan register, is configured to generate a first shift signal or a second shift signal according to a received test input signal and output it to the scan register;

[0114] The output end of the scan register is coupled to the test output pin;

[0115] The scanning register is configured to generate a first test output signal according to a first shift signal; or, the scanning register is configured to generate a second test output signal according to a second shift signal; the scanning register is also configured to output a first test result according to a received first feedback signal; or, the scanning register is configured to output a second test result according to a received second feedback signal.

[0116] When P is greater than 1, the shift unit includes a trigger and P scan registers, the first circuit to be tested includes at least one combinational logic unit CL, and the combinational logic unit CL is the object to be tested of the scan test. The combinational logic unit CL is coupled between the Pth scan register and the P-1th scan register.

[0117] Specifically, when P=2, refer to Figure 4a or Figure 4b , the first shift unit includes a trigger D1, a scan register F0 and a scan register F1. Based on the high-level enable input signal inputted by the enable input terminal SE, the trigger D1, the scan register F0 and the scan register F1 are in a serial shift state, in which the test input signal is preset into the scan register F0 and the scan register F1 in a serial shift manner. Among them, the test input signal is obtained according to the characteristics of the object under test and the fault model, and represents the required assignment of the address line, the data line and the control line when the test vector is written to the set address of the object under test.

[0118] This embodiment is described by assigning a four-bit binary value 1001 in the serial shift state, that is, the test input signal is a test vector 1001. The test vector 1001 is respectively input in parallel to the first shift unit and the second shift unit, the test vector 10 is serially shifted in the first shift unit, and the test vector 01 is serially shifted in the second shift unit, and finally the scan register F0 and the scan register F1 in the first shift unit output the first test output signal in parallel to the coupled combinational logic unit CL. The scan register F2 and the scan register F3 in the second shift unit output the second test output signal in parallel to the coupled combinational logic unit CL.

[0119] Reference Figure 4a and Figure 5 The shift operation of the first shift unit is described. Specifically, the first shift unit serially shifts the test vector 10. In the clock cycle T0, the trigger D1 stores 0 according to the test input signal, and the output sequence of the first shift unit is 0XX. And the trigger D1 generates a shift signal 0 and outputs it to the scan register F0.

[0120] In clock cycle T1, trigger D1 stores 1 according to the test input signal, and scan register F0 receives and stores the shift signal 0. At this time, the output sequence of the first shift unit is 10X. In addition, scan register F0 outputs the stored shift signal 0 to scan register F1, and trigger D1 generates a shift signal 1 and outputs it to scan register F0.

[0121] In clock cycle T2, trigger D1 stores 0 according to the test input signal, scan register F0 receives and stores the shift signal 1, and scan register F1 receives and stores the shift signal 0 of scan register F0. At this time, the output sequence of the first shift unit is 010.

[0122] In clock cycle T3, the first shift unit is in the parallel output stage, wherein the scan register F0 and the scan register F1 output the first test output signal, i.e., the test vector 10, to the combinatorial logic unit CL in parallel for scan testing. The scan register F1 receives the first feedback signal output by the combinatorial logic unit CL based on the test vector 10, and outputs the first test result according to the received first feedback signal.

[0123] Here, the test machine ATE determines whether the scan test item has passed. The test output pin PAD_SCAN_OUT1 outputs the first test result to the test machine ATE, and the test machine ATE compares the first test result with the input test vector 10, and determines whether the test item corresponding to the test vector has passed according to the comparison result.

[0124] Here, the principle of the shifting operation of the second shifting unit can refer to the analysis of the first shifting unit mentioned above, and will not be repeated here.

[0125] When P is equal to 1, the shift unit includes a trigger and a scan register, and the first circuit to be tested includes at least one combinational logic unit CL, which can be a test object of the scan test. The combinational logic unit CL is coupled between the trigger and the scan register.

[0126] The operating principle of the shift unit when P=1 can refer to the analysis of the first shift unit when P=2, which will not be repeated here.

[0127] In the disclosed embodiment, a test input signal can be provided to two different shift units through one input pin, and by utilizing complementary first clock signals and second clock signals, the 2M-1th and 2Mth shift units can respectively capture the signals input to the same input pin, thereby reducing the number of required input pins.

[0128] In addition, compared to an input pin that can only provide a test input signal to a shift unit for scan testing, forming a scan channel, an input pin in the embodiment of the present disclosure can provide a test input signal to multiple shift units for scan testing, forming multiple scan channels. Therefore, with the same number of chip pins, the number of scan channels used for scan testing in the embodiment of the present disclosure is significantly increased. Since the more scan channels there are, the higher the scan quality, the embodiment of the present disclosure can significantly improve the quality of the scan test.

[0129] In one embodiment, the trigger in the 2M-1th shift unit is specifically configured to perform a serial shift operation on the test input signal when the enable input signal is the first signal value and at the rising edge of the first clock signal, generate a first shift signal and output it to the coupled P scan registers;

[0130] The Pth scan register is specifically configured to output a first test output signal according to the received first shift signal when the enable input signal is a first signal value and at a rising edge of the first clock signal;

[0131] The Pth scan register is further specifically configured to output a first test result according to a received first feedback signal.

[0132] Reference Figure 4a and Figure 5 , the first shift unit serially shifts the test vector 10. In clock cycle T0, the trigger D1 stores 0 according to the test input signal when the enable input signal is high and at the rising edge of the first clock signal, and the output sequence of the first shift unit is 0XX. And the trigger D1 generates a shift signal 0 and outputs it to the scan register F0.

[0133] In clock cycle T1, when the enable input signal is high, trigger D1 stores 1 according to the test input signal at the rising edge of the first clock signal, and when the enable input signal is high, scan register F0 receives and stores the shift signal 0 at the rising edge of the first clock signal. At this time, the output sequence of the first shift unit is 10X. In addition, scan register F0 outputs the stored shift signal 0 to scan register F1, and trigger D1 generates a shift signal 1 and outputs it to scan register F0.

[0134] In clock cycle T2, when the enable input signal is high, trigger D1 stores 0 according to the test input signal at the rising edge of the first clock signal; when the enable input signal is high, scan register F0 receives and stores the shift signal 1 at the rising edge of the first clock signal; when the enable input signal is high, scan register F1 receives and stores the shift signal 0 of scan register F0 at the rising edge of the first clock signal. At this time, the output sequence of the first shift unit is 010.

[0135] In clock cycle T3, the first shift unit is in the parallel output stage, and when the enable input signal is at a low level, the scan register F0 and the scan register F1 output the first test output signal, i.e., the test vector 10, in parallel to the combinatorial logic unit CL for scan testing. The scan register F1 receives the first feedback signal output by the combinatorial logic unit CL based on the test vector 10, and outputs the first test result according to the received first feedback signal.

[0136] Here, the first test result is output to the test equipment ATE through the test output pin PAD_SCAN_OUT1. The test equipment ATE compares the first test result with the input test vector 10 and determines whether the test item corresponding to the test vector passes according to the comparison result.

[0137] In the disclosed embodiment, different shift units are connected to the same input pin, and two complementary clock signals are obtained through the clock control unit and input into two different shift units respectively. The trigger in the first shift unit can perform a serial shift operation at the rising edge of the first clock signal to implement a scan test on the combinational logic unit.

[0138] In one embodiment, the trigger in the 2Mth shift unit is specifically configured to perform a serial shift operation on the test input signal when the enable input signal is the first signal value and at the rising edge of the second clock signal, generate a second shift signal and output it to the coupled P scan registers;

[0139] The Pth scan register is specifically configured to output a second test output signal according to the received second shift signal when the enable input signal is the first signal value and at a rising edge of the first clock signal;

[0140] The Pth scan register is further specifically configured to output a second test result according to the received second feedback signal.

[0141] Reference Figure 4a and Figure 5, the second shift unit serially shifts the test vector 01. In clock cycle T0, the trigger D2 stores 1 according to the test input signal when the enable input signal is high and at the rising edge of the second clock signal, that is, the falling edge of the first clock signal. At this time, the output sequence of the second shift unit is 1XX. And the trigger D2 generates a shift signal 1 and outputs it to the scan register F2.

[0142] In clock cycle T1, when the enable input signal is high, trigger D2 stores 0 according to the test input signal at the rising edge of the second clock signal, i.e., the falling edge of the first clock signal. When the enable input signal is high, scan register F2 receives and stores the shift signal 1 at the rising edge of the first clock signal. At this time, the output sequence of the second shift unit is 01X. In addition, scan register F2 outputs the stored shift signal 1 to scan register F3, and trigger D2 generates a shift signal 0 and outputs it to scan register F2.

[0143] In clock cycle T2, trigger D2 stores 1 according to the test input signal when the enable input signal is high and at the rising edge of the second clock signal, that is, the falling edge of the first clock signal. Scan register F2 receives and stores the shift signal 0 when the enable input signal is high and at the rising edge of the first clock signal. Scan register F3 receives and stores the shift signal 1 of scan register F2 when the enable input signal is high and at the rising edge of the first clock signal. At this time, the output sequence of the second shift unit is 101.

[0144] In clock cycle T3, the second shift unit is in the parallel output stage. When the enable input signal is at a low level, the scan register F2 and the scan register F3 output the second test output signal, i.e., the test vector 01, to the combinational logic unit for scan testing in parallel. The scan register F3 receives the second feedback signal output by the combinational logic unit based on the test vector 01, and outputs the second test result according to the received second feedback signal.

[0145] Here, the second test result is output to the test equipment ATE through the test output pin PAD_SCAN_OUT2. The test equipment ATE compares the second test result with the input test vector 01, and determines whether the test item corresponding to the test vector passes according to the comparison result.

[0146] In the embodiment of the present disclosure, the trigger in the second shift unit can perform a serial shift operation at the rising edge of the second clock signal, that is, at the falling edge of the first clock signal, to implement a scan test of the combinational logic unit. The embodiment of the present disclosure can provide a test input signal for two different shift units through an input pin, and use the complementary first clock signal and the second clock signal so that the 2M-1st and 2Mth shift units respectively capture the signal input by the same input pin, thereby reducing the number of required input pins. In addition, compared with an input pin that can only provide a test input signal to a shift unit for scan testing, forming a scan channel, an input pin in the embodiment of the present disclosure can provide a test input signal to multiple shift units for scan testing, forming multiple scan channels. Therefore, in the case of the same number of chip pins, the number of scan channels used for scan testing in the embodiment of the present disclosure is significantly increased. Since the more the number of scan channels, the higher the scan quality, the embodiment of the present disclosure can significantly improve the quality of the scan test.

[0147] Figure 7 FIG. 1 is a flow chart of a scanning test method according to an exemplary embodiment. Figure 7 As shown, the method includes:

[0148] S100: receiving a first clock signal, and outputting the first clock signal to a coupled shift unit;

[0149] S200: Generate a second clock signal complementary to the first clock signal, and output the second clock signal to another coupled shift unit;

[0150] S300: receiving a test input signal;

[0151] S400: Outputting a first test output signal according to the received first clock signal and the test input signal;

[0152] S500: Outputting a first test result according to a first feedback signal received from a first circuit under test; wherein the first circuit under test generates the first feedback signal according to the first test output signal;

[0153] S600: Output a second test output signal according to the received second clock signal and the test input signal;

[0154] S700: Output a second test result according to a received second feedback signal sent by a second circuit under test; wherein the second circuit under test generates the second feedback signal according to the second test output signal.

[0155] In the disclosed embodiment, different shift units are connected to the same input pin, and two complementary clock signals are obtained by a clock control unit and respectively input into two different shift units.

[0156] Here, L can be used to represent L stages in one clock cycle, and one clock cycle of the input first clock signal can be decomposed into L stages, where L is greater than or equal to 2.

[0157] Specifically, according to Figure 4a The circuit architecture shown can convert a clock cycle (eg Figure 5 In the example, T0) is divided into two phases, namely phase 1 and phase 2. In each phase of a clock cycle, if data needs to be captured for the input test input signal at the rising edge or falling edge of the first clock signal, the "setup and hold time check" condition must be met. Therefore, the time length of each phase in a clock cycle is at least 10ns.

[0158] The clock cycle of the first clock signal output by the test machine is 20ns, and the clock cycle of each stage is 10ns. One clock cycle of the first clock signal can be divided into two stages, such as Figure 5 As shown, the clock cycle T0 is divided into phase 1 and phase 2, and the clock cycles of phase 1 and phase 2 are 10ns. Similarly, if the clock cycle of the first clock signal output by the test machine ATE is 40ns, the clock cycle T0 can be divided into 4 phases.

[0159] Specifically, within a clock cycle T0, for phase 1, the first shift unit captures data of the test input signal at the rising edge of the first clock signal. For phase 2, at the falling edge of the first clock signal, no matter how the test input signal changes, since the first shift unit is not triggered by the rising edge, it will not affect the first shift unit.

[0160] The two complementary clock signals obtained by the clock control unit 200 are respectively input into two different shift units, that is, the second shift unit receives the second clock signal. For the second shift unit, the test input signal is captured at the rising edge of the second clock signal, that is, the second shift unit is triggered at the falling edge of the first clock signal. Therefore, in phase 1, no matter how the test input signal changes, since the second shift unit is not triggered by the falling edge, it will not have any effect on the second shift unit.

[0161] The disclosed embodiment realizes a circuit architecture in which one input pin is connected to the input ends of two shift units and a test input signal is input at the same time, thereby reducing the number of input pins used for scanning input. That is, in stage 1, the first shift unit captures data of the test input signal at the rising edge of the first clock signal, and in stage 2, the second shift unit captures data of the test input signal at the falling edge of the first clock signal.

[0162] In the related art, please refer to Figure 1 , usually different shift units are coupled to different input pins. For example, the first shift unit is coupled to an input pin IN1, and the second shift unit is coupled to another input pin IN2 different from the input pin IN1. Figure 1 Based on the illustrated architecture, if the number of test chains needs to be increased, the number of input pins, shift units, and output pins needs to be increased, which will increase the cost. Specifically, for every two test chains added, the number of input pins, shift units, and output pins needs to be increased by two.

[0163] By using the technical solution provided by the embodiment of the present disclosure, two complementary clock signals can be obtained through one clock control unit and input into the first shift unit and the second shift unit respectively. At this time, the first shift unit and the second shift unit can be connected to the same input pin IN1. The existing input pin IN2 can be reused as a pin for constituting a scan output channel, or as a pin for other purposes. The technical solution provided by the embodiment of the present disclosure is highly compatible with the prior art.

[0164] Further, in Figure 1 On the basis of the shown architecture, if two test chains need to be added, only two shift units and two output pins need to be added, and the existing input pin IN2 can be used with the additional shift unit and output pin to form a scan chain, which is beneficial to reduce the number of pins compared to the prior art. In the disclosed embodiment, for the test circuit structure of the asymmetric scan channel, that is, the number of scan input channels is not equal to the number of scan output channels. At this time, the utilization rate of the scan input channel can be increased by L times. For the test circuit structure of the symmetric scan channel, that is, the number of scan input channels is equal to the number of scan output channels, the input pins and output pins are recombined, and the number of scan chains can be increased by (L-1) / (L+1) times, where L is greater than or equal to 2.

[0165] The circuit architecture of the scan test circuit provided by the embodiment of the present disclosure can be widely used in the DFT scan test circuit architecture used by software such as EDA. The embodiment of the present disclosure improves the quality of scan testing as much as possible without increasing the design burden. For example, for a SOC chip, the original number of scan chains is 30 groups. If the scan test circuit architecture of L=2 of the present disclosure is adopted, the number of scan chains can be increased to 40 groups. If the scan test circuit architecture of L=4 of the present disclosure is adopted, the number of scan chains can be increased to 48 groups. The effect of increasing the number of scan chains is very obvious, thereby improving the quality of scan testing. In addition, the circuit architecture of the scan test circuit provided by the embodiment of the present disclosure can also be used for low pin count chips. The scan test circuit of the embodiment of the present disclosure reduces the input pins used for scan testing, effectively saving the number of chip pins.

[0166] Therefore, compared to coupling different shift units through different input pins to provide test input signals for different shift units, the embodiment of the present disclosure can provide test input signals for two shift units through one input pin, and use the complementary first clock signal and the second clock signal to enable the 2M-1 and 2M shift units to capture the signals input by the same input pin, respectively, thereby reducing the number of required input pins. In addition, compared to an input pin that can only provide a test input signal to one shift unit for scan testing, forming a scan channel, in the embodiment of the present disclosure, one input pin can provide a test input signal to multiple shift units for scan testing, forming multiple scan channels. Therefore, with the same number of chip pins, the number of scan channels used for scan testing in the embodiment of the present disclosure is significantly increased. Since the more the number of scan channels, the higher the scan quality, the embodiment of the present disclosure can significantly improve the quality of the scan test.

[0167] In some embodiments, the method further includes

[0168] receiving an enable input signal;

[0169] When the enable input signal is a first signal value and at a rising edge of the first clock signal, performing a serial shift operation on the test input signal to generate a first shift signal;

[0170] When the enable input signal has a first signal value and at a rising edge of the first clock signal, a first test output signal is output according to the first shift signal.

[0171] In the embodiment of the present disclosure, the shift unit may include an enable input terminal, a scan input terminal, a data input terminal, a clock input terminal and an output terminal. The shift unit may selectively store data input from the data input terminal or the scan input terminal according to the signals input from the enable input terminal and the clock input terminal, and may output the stored data as output data from the output terminal.

[0172] Here, the shift unit can execute two operation modes: a scan test mode and a logic function mode. The first signal value is a high level, and the second signal value is a low level.

[0173] Specifically, the scan test mode means that the shift unit stores the data input at the scan input terminal based on the high-level enable input signal input at the enable input terminal at the rising edge (or falling edge) of the clock signal input at the clock input terminal, and outputs the stored data as output data at the output terminal.

[0174] The logic function mode means that the shift unit stores the data input at the data input terminal based on the low-level enable input signal input at the enable input terminal at the rising edge (or falling edge) of the clock signal input at the clock input terminal, and outputs the stored data as output data at the output terminal.

[0175] In the disclosed embodiment, the shift unit can execute two operation modes: scan test mode and logic function mode. When scan test is not required, the shift unit can execute logic function mode to realize the logic function of the shift unit itself, thereby improving the utilization rate of the scan test circuit during the period when scan test is not performed.

[0176] In the disclosed embodiment, different shift units are connected to the same input pin, and two complementary clock signals are obtained by the clock control unit and respectively input into two different shift units. The first shift unit can perform a serial shift operation at the rising edge of the first clock signal to implement a scan test on the combinational logic unit.

[0177] In some embodiments, the method further comprises, when the enable input signal is a first signal value and at a rising edge of the second clock signal, performing a serial shift operation on the test input signal to generate a second shift signal;

[0178] When the enable input signal is a first signal value and at a rising edge of the first clock signal, a second test output signal is output according to the second shift signal.

[0179] In the disclosed embodiment, different shift units are connected to the same input pin, and two complementary clock signals are obtained through the clock control unit and respectively input into two different shift units. The second shift unit can perform a serial shift operation at the rising edge of the second clock signal, that is, at the falling edge of the first clock signal, to implement a scan test on the combinational logic unit.

[0180] The present disclosure also provides a testing system, including:

[0181] The scan test circuit as described in the above embodiment;

[0182] a memory device coupled to the scan test circuit;

[0183] A test device, the test device is coupled to the scan test circuit and is configured to provide a test input signal and a first clock signal to the scan test circuit to test the memory device; wherein the time for the scan test circuit to perform a scan shift operation is recorded as a scan clock cycle, and the clock cycle of the first clock signal is 2N times the scan clock cycle.

[0184] Here, L can be used to represent L stages in a clock cycle, and a clock cycle of the input first clock signal can be decomposed into L stages, where L is greater than or equal to 2. Specifically, according to Figure 4a The circuit architecture shown can convert a clock cycle (eg Figure 5 In the example, T0) is divided into two phases, namely phase 1 and phase 2. In each phase of a clock cycle, if data needs to be captured for the input test input signal at the rising edge or falling edge of the first clock signal, the "setup and hold time check" condition must be met. Therefore, the time length of each phase in a clock cycle is at least 10ns.

[0185] The clock period of the first clock signal can be Figure 5 In T0, one scan clock cycle can be the clock cycle of stage 1. The clock cycle of the first clock signal output by the test machine is 20ns, and the scan clock cycle of each stage is 10ns. One clock cycle of the first clock signal can be divided into two stages, such as Figure 5 As shown, the clock cycle T0 is divided into phase 1 and phase 2, and the clock cycles of phase 1 and phase 2 are 10ns. The clock cycle of the first clock signal is twice the scan clock cycle.

[0186] By analogy, if the clock period of the first clock signal output by the test equipment is 40ns, the clock period T0 can be divided into 4 stages. The clock period of the first clock signal is 4 times the scanning clock period.

[0187] It should be understood that the "some embodiments" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification may not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present disclosure. The above-mentioned sequence numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. It should be noted that in this article, the terms "including", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the element.

[0188] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0189] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, the functional units in the various embodiments of the present disclosure may all be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0190] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A scan test circuit, characterized in that: The scan test circuit includes an input pin, N clock control units and 2N shift units, where N is a positive integer; The input pins are respectively coupled to the input ends of the 2N shift units, and are configured to receive a test input signal and output the test input signal to the 2N shift units; The output end of the Mth clock control unit is coupled to the clock input end of the 2M-1th shift unit and the clock input end of the 2Mth shift unit respectively; wherein the output ends of different clock control units are coupled to the clock input ends of different shift units, and M is a positive integer less than or equal to N; The Mth clock control unit is configured to receive a first clock signal and output the first clock signal to the 2M-1th shift unit; The 2M-1th shift unit is configured to output a first test output signal according to the received first clock signal and the test input signal; the 2M-1th shift unit is further configured to output a first test result according to a first feedback signal sent by the received first circuit under test; wherein the first circuit under test generates the first feedback signal according to the first test output signal; The Mth clock control unit is further configured to generate a second clock signal complementary to the first clock signal according to the received first clock signal, and output the second clock signal to the coupled 2Mth shift unit; The 2Mth shift unit is configured to output a second test output signal based on the received second clock signal and the test input signal; the 2Mth shift unit is also configured to output a second test result based on the received second feedback signal sent by the second circuit under test; wherein the second circuit under test generates the second feedback signal based on the second test output signal.

2. The scan test circuit according to claim 1, characterized in that: The clock control unit comprises: a clock input pin and an inverter; wherein, The clock input pin is configured to receive a first clock signal and output the first clock signal to a clock input terminal of the 2M-1th shift unit; The inverter is coupled to the clock input pin, and is configured to generate the second clock signal according to the received first clock signal, and output the second clock signal to the clock input terminal of the 2Mth shift unit.

3. The scan test circuit according to claim 1, characterized in that: The scan test circuit also includes an enable input pin; wherein, The enable input pins are respectively coupled to the enable input terminals of the shift units and are configured to transmit the enable input signal to the shift units; The shift unit is configured to receive the test input signal input from the scan input terminal when the received enable input signal is a first signal value, and execute a scan test mode according to the test input signal; The shift unit is further configured to receive a logic input signal input from a data input terminal when the received enable input signal is a second signal value, and execute a logic function mode according to the logic input signal; wherein the second signal value is different from the first signal value.

4. The scan test circuit according to claim 1, characterized in that: The shift unit includes a trigger and P scan registers; wherein P is a positive integer; When P is greater than 1, the trigger is coupled to the scan input terminal of the first scan register and is configured to generate a first shift signal or a second shift signal according to the received test input signal and output it to the first scan register; The output end of the first scanning register is coupled to the scanning input end of the P-th scanning register, and the output end of the P-th scanning register is coupled to the test output pin; The P scan registers are configured to generate the first test output signal according to the first shift signal; or the P scan registers are configured to generate the second test output signal according to the second shift signal; The Pth scanning register is configured to output the first test result according to the received first feedback signal; or the Pth scanning register is configured to output the second test result according to the received second feedback signal; When P is equal to 1, the trigger, coupled to the scan input terminal of the scan register, is configured to generate a first shift signal or a second shift signal according to the received test input signal and output it to the scan register; The output end of the scan register is coupled to the test output pin; The scanning register is configured to generate a first test output signal according to the first shift signal; or, the scanning register is configured to generate the second test output signal according to the second shift signal; the scanning register is also configured to output the first test result according to the first feedback signal received; or, the scanning register is configured to output the second test result according to the second feedback signal received.

5. The scan test circuit according to claim 4, characterized in that: The trigger in the 2M-1th shift unit is specifically configured to perform a serial shift operation on the test input signal when the enable input signal is a first signal value and at a rising edge of the first clock signal, generate the first shift signal and output it to the coupled P scan registers; The Pth scanning register is specifically configured to output a first test output signal according to the received first shift signal when the enable input signal is a first signal value and at a rising edge of the first clock signal; The Pth scanning register is further configured to output the first test result according to the received first feedback signal.

6. The scan test circuit according to claim 5, characterized in that: The trigger in the 2Mth shift unit is specifically configured to perform a serial shift operation on the test input signal when the enable input signal is the first signal value and at the rising edge of the second clock signal, generate the second shift signal and output it to the coupled P scan registers; The Pth scanning register is specifically configured to output a second test output signal according to the received second shift signal when the enable input signal is a first signal value and at a rising edge of the first clock signal; The Pth scanning register is further configured to output the second test result according to the received second feedback signal.

7. A scanning test method, characterized in that: The method comprises: receiving a first clock signal, and outputting the first clock signal to a coupled shift unit; generating a second clock signal complementary to the first clock signal, and outputting the second clock signal to another coupled shift unit; receiving a test input signal; outputting a first test output signal according to the received first clock signal and the test input signal; Outputting a first test result according to a first feedback signal sent by a first circuit under test; wherein the first circuit under test generates the first feedback signal according to the first test output signal; outputting a second test output signal according to the received second clock signal and the test input signal; Outputting a second test result according to a received second feedback signal sent by a second circuit under test; wherein the second circuit under test generates the second feedback signal according to the second test output signal.

8. The method according to claim 7, characterized in that The method further comprises: receiving an enable input signal; When the enable input signal is a first signal value and at a rising edge of the first clock signal, performing a serial shift operation on the test input signal to generate a first shift signal; When the enable input signal has a first signal value and at a rising edge of the first clock signal, a first test output signal is output according to the first shift signal.

9. The method according to claim 8, characterized in that The method further comprises: When the enable input signal is a first signal value and at a rising edge of the second clock signal, performing a serial shift operation on the test input signal to generate a second shift signal; When the enable input signal is a first signal value and at a rising edge of the first clock signal, a second test output signal is output according to the second shift signal.

10. A testing system, characterized in that: include: The scan test circuit according to any one of claims 1 to 7; a memory device coupled to the scan test circuit; A test device, the test device is coupled to the scan test circuit and is configured to provide a test input signal and a first clock signal to the scan test circuit to test the memory device; wherein the time for the scan test circuit to perform a scan shift operation is recorded as a scan clock cycle, and the clock cycle of the first clock signal is 2N times the scan clock cycle.

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