A method and system for reconstructing a storage module in digital integrated circuit design

Abstract

The present invention provides a method and system for reconstructing a storage module in digital integrated circuit design. The method extracts the instantiation parameters of the storage module from the RTL (Register Transfer Level) source code, then parses the instantiation parameters according to global parameters to generate a front-end storage module library file that meets the design timing requirements. Next, it calculates the number of times of instantiation required to complete the reconstruction of the storage module, and according to the mapping relationship of port names before and after the reconstruction of the storage module, splits and reconnects signal lines to form a new storage module instantiation structure. Finally, it replaces the corresponding code in the RTL source code file with the new storage module instantiation structure to complete the reconstruction of the storage module. The present invention realizes the RTL behavioral-level reconstruction of the storage module, has the characteristics of high accuracy and can be quickly and repeatedly iteratively optimized, and can improve the efficiency of digital integrated circuit design.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital integrated circuit design, and more specifically, relates to a method and system for reconstructing a storage module in digital integrated circuit design. Background Art

[0002] Memory is a common information storage module in digital circuits. It has various attributes such as data port width, storage depth, and address width, and is usually used to solve the problem of temporarily storing data inside a chip, such as data Cache and instruction Cache used as data caching functions. The memory in the IP release package issued by IP vendors is generally built in the form of registers and is sometimes also called sram (static random access memory). They have the characteristics of high-speed random access and are very suitable for the design of high-speed digital circuits. However, sram also has its disadvantages, mainly large area and high power consumption. Therefore, during the front-end functional design process, sram is replaced with a storage module generated by a dedicated memory design tool under the target process to achieve the purpose of reducing area and power consumption.

[0003] The traditional method for replacing the memory instantiation structure in RTL (Register Transfer Level) is shown in Figure 1 and it includes the following steps:

[0004] Step 1: In all RTL (Register Transfer Level) source files, search for the positions where the memory instantiation structure to be replaced appears, and manually calculate the data width, storage depth, and address width parameters in each instantiation parameter.

[0005] Step 2: According to each memory instantiation parameter, generate a new memory library file for the digital front-end design stage in the memory compilation tool, and after multiple parameter iterations, meet the timing performance requirements of the design.

[0006] Step 3: Use a text editor to open an RTL source file in the RTL source file directory that has not undergone memory replacement.

[0007] Step 4: For each memory instantiation code to be replaced in the RTL source code, manually replace the instantiation name of the memory one by one and reconnect the signal lines according to the memory name and port definition in the generated memory library file.

[0008] Step 5: Determine whether all RTL source files have been replaced. If not, go to Step 3; if so, go to Step 6.

[0009] Step 6: The operation ends.

[0010] The above operation steps have been simplified. It can be seen that the main difficulties in replacing the memory instantiation structure mainly include two aspects:

[0011] 1. In step 1, it is necessary to search for globally defined parameters, substitute them into the position where the memory module is instantiated in the RTL source code, and calculate parameters such as data bit width and storage depth to facilitate the generation of a new memory. In the traditional method, this step is usually carried out manually. The number of operations increases linearly with the number of memory instantiations, with high repeatability and prone to errors.

[0012] 2. In step 4, it is necessary to replace the instantiation structure of the original memory with a new memory. It is necessary to disconnect the original port connection signals of the memory and reconnect them to the new memory. This operation is relatively cumbersome. If the memory generation process considers the timing optimization problem, the size of the newly generated memory may be smaller than the original memory. Then, the memory cutting problem also needs to be considered during the replacement process. In the traditional method, modifying the RTL source code manually to complete the memory splicing and replacement is not reliable and time-consuming, which is not conducive to timing iteration. Summary of the Invention

[0013] Aiming at the defects of the prior art, the purpose of the present invention is to provide a method and system for reconstructing a storage module in digital integrated circuit design, aiming to solve the problems that the traditional method for reconstructing a storage module manually searches for globally defined parameters and manually modifies the RTL source code to complete the memory splicing and replacement, which is error-prone, time-consuming, and not conducive to timing iteration.

[0014] To achieve the above object, in the first aspect, the present invention provides a method for reconstructing a storage module in digital integrated circuit design, including the following steps:

[0015] In all RTL source files, search for all parameter parameters, parse the searched parameter parameters and store them in a global parameter table; the parameter parameters are global parameters;

[0016] Search for the name of the original storage module in all RTL source files, find the instantiation structure of the original storage module based on the name of the original storage module, extract the information of the instantiation structure of the original storage module, and save the extracted information into a custom hash table to complete the initialization of the hash table; the hash table is used to store the information of the original storage module, the information of the new storage module, and the matching relationship information between the original storage module and the new storage module;

[0017] Update the instantiation parameters of the original storage module in the hash table to the parsed decimal parameters based on the global parameter table; the instantiation parameters include: data port width, storage depth, and address width;

[0018] Fix the two instantiation parameters of the storage depth and address width of the new storage module to the corresponding preset values, design the data port width value of the new storage module by the iterative method until the designed new storage module meets the timing design requirements, and use the data port width value at this time as the data port width design value of the new storage module; keep the name of the new storage module in the hash table;

[0019] Obtain the port lists of the original storage module and the new storage module respectively, establish the matching relationship between the ports of the original storage module and the new storage module, and save the matching relationship to the hash table;

[0020] Determine the instantiation times after the new storage module replaces the original storage module according to the data port width value of the original storage module and the data port width design value of the new storage module, generate the instantiation structure of the new storage module accordingly, and save the instantiation structure of the new storage module to the hash table;

[0021] Replace the instantiation structure of the original storage module in the RTL source file with the instantiation structure of the new storage module in the hash table, output the updated RTL source file, and complete the reconstruction of the original storage module.

[0022] Optionally, the step of designing the data port width value of the new storage module by the iterative method until the designed new storage module meets the timing design requirements specifically includes the following steps:

[0023] S10. Determine the initial value of the data port width of the new storage module;

[0024] S20. Preset the width division coefficient, and set the initial value of the width division coefficient to 1;

[0025] S30. Divide the initial value of the data port width by the width division coefficient and round up to obtain a new data port width value;

[0026] S40. Generate a new storage module according to the preset values of the storage depth and address width, and the new data port width value;

[0027] S50. Determine whether the new storage module generated in step S40 meets the timing design requirements. If it meets the requirements, use the new data port width value as the data port width design value of the new storage module. If it does not meet the requirements, multiply the width division coefficient by 2 as the new width division coefficient, and enter step S30.

[0028] Optionally, the data structure of a hash table of the customization includes:

[0029] Instantiate an index storage area for the storage module, an instantiation parameter storage area for the original storage module, a name storage area for the original storage module, a name storage area for the new storage module, a connection relationship storage area between the original storage module and external signals, a port mapping relationship storage area for the storage module, an instantiation code range storage area for the original storage module, and an instantiation code storage area for the new storage module;

[0030] The instantiation index storage area of the storage module is used to store the RTL source file name and the instantiation name of the storage module in the RTL source file;

[0031] The instantiation parameter storage area of the original storage module is used to store the data end bit width, storage depth, and address bit width of the original storage module;

[0032] The connection relationship storage area between the original storage module and external signals is used to store the port name of the original storage module, external signals, and the corresponding connection relationship between the port name and external signals;

[0033] The port mapping relationship storage area of the storage module is used to store the port list of the original storage module and the port list of the new storage module, as well as the corresponding mapping relationship between the two lists; the port list includes: clock port, write enable port, write data port, read enable port, read data port, and address port;

[0034] The instantiation code range storage area of the original storage module is used to store the instantiation start line number and instantiation end line number of the original storage module.

[0035] Optionally, according to the data port bit width value of the original storage module and the data port bit width design value of the new storage module, determine the number of instantiations after the new storage module replaces the original storage module, and generate the instantiation structure of the new storage module accordingly. The specific steps are as follows:

[0036] Divide the data port bit width value of the original storage module by the data port bit width design value, and round up to obtain the number of instantiations;

[0037] The instantiation name of the new storage module is composed of the instantiation name of the original storage module and the instantiation index. The instantiation index is incremented by 1 each time the new storage module is instantiated until the instantiation index value is the number of instantiations minus 1. At this time, the generation of the instantiation structure of the new storage module is completed; when the generation of a new instantiation structure is completed, the instantiation index is reset to 0;

[0038] The signals of the clock port, write enable port, read enable port, and address port in the original storage module instantiation structure are not bit-split and are directly connected to the new instantiation structure; except for the last instantiation of the new storage module, the signals of the write data port and read data port need to be split using the instantiation index and then connected to the new instantiation structure;

[0039] In the last instantiation of the new storage module, for the write data port, in addition to splitting the signal using the instantiation index, its high bits also need to be filled with 0s according to the characteristic of bit-width matching. Multiply the designed value of the data port bit-width by the number of instantiations minus the data port bit-width value of the original storage module to determine the number of 0s to be filled in the high bits; for the read data port, a signal matching the bit-width of the read data port of the new storage module needs to be defined separately and connected to the new instantiation structure, and then this signal is truncated by bit-width and connected to the original read data signal.

[0040] Optionally, the parsing and storing the searched parameter parameters into the global parameter table specifically includes the following steps:

[0041] For each RTL source file, match the parameter definition syntax line by line and classify it semantically: for those with parameter values defined as numerical values, convert the numerical values to decimal and classify them into the parsed parameter table; for those with parameter values not defined as numerical values, if they do not contain operators, classify them into the indirect parameter table, and if they contain operators, classify them into the undefined parameter table;

[0042] Iteratively parse the indirect parameter table. In each round, complete the parameter value replacement of the indirect parameter table by looking up the parsed parameter table, and merge it into the parsed parameter table after each replacement until all parameters in the indirect parameter table are parsed;

[0043] Iteratively parse the undefined parameter table. In each round, first complete the parameter value replacement of the undefined parameter table by looking up the parsed parameter table, then calculate based on the replaced parameter values, and merge the calculation results of the parameter values into the parsed parameter table until all parameters in the undefined parameter table are parsed.

[0044] Optionally, updating the instantiation parameters of the original storage module in the hash table to the parsed decimal parameters based on the global parameter table specifically includes the following steps:

[0045] For each instantiation parameter of the original storage module in the hash table, first extract the operators therein, including arithmetic operators and logical operators; use the extracted operators as the delimiters of the instantiation parameters to further separate the sub-parameters that make up the instantiation parameters;

[0046] By querying the global parameter table, replace each of the separated sub-parameters with the decimal value in the global parameter table for calculation;

[0047] Based on the operator composed of instantiation parameters and the replaced sub-parameters, calculate the final decimal value of the instantiation parameters and update it to the corresponding position in the hash table.

[0048] Optionally, replace the instantiation structure of the original storage module in the RTL source file with the instantiation structure of the new storage module stored in the hash table, and output the updated RTL source file, which specifically includes the following steps:

[0049] Use the name of the RTL source file to filter out the linked list of all new instantiation structures belonging to this RTL source file from the hash table;

[0050] Take the starting line number of the instantiation structure to be replaced as the keyword, and sort the elements of the linked list in descending order;

[0051] Take out each instantiation structure in the sorted linked list in turn, and replace the code between the starting line and the ending line of the instantiation of the original storage module in the RTL source file.

[0052] In a second aspect, the present invention provides a reconstruction system for a storage module in digital integrated circuit design, including

[0053] An instantiation parameter parsing unit, which is used to search for all parameter parameters in all RTL source files, parse the searched parameter parameters and store them in the global parameter table; the parameter parameters are global parameters;

[0054] A hash table initialization unit, which is used to search for the name of the original storage module in all RTL source files, find the instantiation structure of the original storage module based on the name of the original storage module, extract the information of the instantiation structure of the original storage module, and save the extracted information to a custom hash table to complete the initialization of the hash table; the hash table is used to store the information of the original storage module, the information of the new storage module, and the matching relationship information between the original storage module and the new storage module;

[0055] An instantiation parameter update unit, which is used to update the instantiation parameters of the original storage module in the hash table to the parsed parameters in decimal based on the global parameter table; the instantiation parameters include: data end width, storage depth, and address width;

[0056] A new storage module design unit, which is used to fix the two instantiation parameters of the storage depth and address width of the new storage module to the corresponding preset values, design the data port width value of the new storage module through the iterative method until the designed new storage module meets the timing design requirements, and use the data port width value at this time as the data port width design value of the new storage module; keep the name of the new storage module in the hash table;

[0057] A port relationship determination unit, configured to obtain the port lists of the original storage module and the new storage module respectively, establish a matching relationship between the ports of the original storage module and the new storage module, and save the matching relationship into a hash table;

[0058] A new instantiation structure generation unit, configured to determine the instantiation times of the new storage module after replacing the original storage module according to the data port bit width value of the original storage module and the designed value of the data port bit width of the new storage module, generate the instantiation structure of the new storage module accordingly, and save the instantiation structure of the new storage module into a hash table;

[0059] A storage module reconstruction unit, configured to replace the instantiation structure of the original storage module in the RTL source file with the instantiation structure of the new storage module in the hash table, and output the updated RTL source file to complete the reconstruction of the original storage module.

[0060] Optionally, the new storage module design unit designs the data port bit width value of the new storage module by means of an iterative method until the designed new storage module meets the timing design requirements, which specifically includes the following steps:

[0061] S10. Determine the initial value of the data port bit width of the new storage module; S20. Preset a width division coefficient, and set the initial value of the width division coefficient to 1; S30. Divide the initial value of the data port bit width by the width division coefficient and round up to obtain a new data port bit width value; S40. Generate a new storage module according to the preset values of the storage depth and the address bit width, and the new data port bit width value; S50. Determine whether the new storage module generated in step S40 meets the timing design requirements. If it meets the requirements, use the new data port bit width value as the designed value of the data port bit width of the new storage module. If it does not meet the requirements, multiply the width division coefficient by 2 to obtain a new width division coefficient, and enter step S30.

[0062] Optionally, the new instantiation structure generation unit determines the number of instantiations after the new storage module replaces the original storage module according to the data port bit width value of the original storage module and the designed value of the data port bit width of the new storage module, and generates the instantiation structure of the new storage module accordingly. The specific steps are as follows: Divide the data port bit width value of the original storage module by the designed value of the data port bit width, and round up to obtain the number of instantiations; the instantiation name of the new storage module is formed by concatenating the instantiation name of the original storage module and the instantiation index. Each time the new storage module is instantiated, the instantiation index is incremented by 1 until the instantiation index value is the number of instantiations minus 1. At this time, the generation of the instantiation structure of the new storage module is completed; when the generation of a new instantiation structure is completed, the instantiation index is reset to 0; the signals of the clock port, write enable port, read enable port, and address port in the instantiation structure of the original storage module are not bit-split and are directly connected to the new instantiation structure; except for the last instantiation of the new storage module, the signals of the write data port and the read data port need to be split using the instantiation index and then connected to the new instantiation structure; and in the last instantiation of the new storage module, for the write data port, in addition to splitting the signal using the instantiation index, its high bits also need to be filled with 0 according to the characteristic of bit width matching. Multiply the designed value of the data port bit width by the number of instantiations and subtract the data port bit width value of the original storage module to determine the number of 0s to be filled in the high bits; for the read data port, a signal matching the bit width of the read data port of the new storage module needs to be defined and connected to the new instantiation structure, and the signal is truncated by bit width and then connected to the original read data signal.

[0063] Generally speaking, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:

[0064] The present invention provides a method and system for reconstructing a storage module in digital integrated circuit design. The method extracts the instantiation parameters of the storage module in the RTL (Register Transfer Level) source code, then parses the instantiation parameters according to the global parameters to generate a front-end storage module library file that meets the design timing requirements. Next, calculate the number of instantiations required to complete the reconstruction of the storage module, and perform signal line splitting and reconnection according to the mapping relationship of the port names before and after the reconstruction of the storage module to form a new storage module instantiation structure. Finally, replace the corresponding code in the RTL source code file with the new storage module instantiation structure to complete the reconstruction of the storage module. The present invention realizes the RTL behavioral-level reconstruction of the storage module, has the characteristics of high accuracy and can be quickly and iteratively optimized, and can improve the efficiency of digital integrated circuit design.

[0065] The present invention provides a method and system for reconstructing a storage module in digital integrated circuit design. The extracted storage parameters can generate a report, which is convenient for inspection and secondary development. The reconstruction speed is fast. Since timing iteration can be performed repeatedly, the optimal storage module reconstruction parameters can be found quickly, improving the circuit performance. Compared with the method of manually rewriting RTL code, the present invention is less error-prone, while manual rewriting is prone to code writing errors. Description of the Drawings

[0066] Figure 1 is a flowchart of the method for replacing the memory instantiation structure in a traditional RTL file;

[0067] Figure 2 is a flowchart of the method for reconstructing the storage module provided by an embodiment of the present invention;

[0068] Figure 3 is a schematic diagram of a main process of the method for reconstructing a storage module in digital integrated circuit design provided by an embodiment of the present invention;

[0069] Figure 4 is a schematic diagram of the memdict data structure provided by an embodiment of the present invention;

[0070] Figure 5 is a schematic diagram of step S1 in the main process provided by an embodiment of the present invention;

[0071] Figure 6 is a schematic diagram of step S2 in the main process provided by an embodiment of the present invention;

[0072] Figure 7 is a schematic diagram of step S3 in the main process provided by an embodiment of the present invention;

[0073] Figure 8 is a schematic diagram of step S4 in the main process provided by an embodiment of the present invention;

[0074] Figure 9 is a schematic diagram of step S5 in the main process provided by an embodiment of the present invention;

[0075] Figure 10 is a schematic diagram of step S6 in the main process provided by an embodiment of the present invention;

[0076] Figure 11 is a schematic diagram of step S7 in the main process provided by an embodiment of the present invention;

[0077] Figure 12 is an architecture diagram of the system for reconstructing the storage module provided by an embodiment of the present invention. Detailed Embodiments

[0078] To make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not used to limit the present invention.

[0079] Figure 2 is a flowchart of a method for reconstructing a storage module provided by an embodiment of the present invention. As Figure 2 shown, it includes the following steps:

[0080] S101, in all RTL source files, search for all parameter parameters, parse the searched parameter parameters and store them in a global parameter table; the parameter parameters are global parameters;

[0081] S102, search for the name of the original storage module in all RTL source files, find the instantiation structure of the original storage module based on the name of the original storage module, extract the information of the original storage module instantiation structure, and save the extracted information to a custom hash table to complete the initialization of the hash table; the hash table is used to store the information of the original storage module, the information of the new storage module, and the matching relationship information between the original storage module and the new storage module;

[0082] S103, based on the global parameter table, update the instantiation parameters of the original storage module in the hash table to the parsed parameters in decimal; the instantiation parameters include: data port width, storage depth, and address width;

[0083] S104, fix the two instantiation parameters of the storage depth and address width of the new storage module to the corresponding preset values, design the data port width value of the new storage module through the iterative method until the designed new storage module meets the timing design requirements, and use the data port width value at this time as the data port width design value of the new storage module; save the name of the new storage module to the hash table;

[0084] S105, respectively obtain the port lists of the original storage module and the new storage module, establish the matching relationship between the ports of the original storage module and the new storage module, and save the matching relationship to the hash table;

[0085] S106, according to the data port width value of the original storage module and the data port width design value of the new storage module, determine the instantiation times after the new storage module replaces the original storage module, generate the instantiation structure of the new storage module accordingly, and save the instantiation structure of the new storage module to the hash table;

[0086] S107, use the instantiation structure of the new storage module in the hash table to replace the instantiation structure of the original storage module in the RTL source file, output the updated RTL source file, and complete the reconstruction of the original storage module.

[0087] Before explaining this technical solution, it is necessary to first introduce the following typical memory instantiation structure grammar examples to facilitate the understanding of the subsequent methods:

[0088]

[0089] In the above memory instantiation structure grammar, dynamic_sram is the module name of the memory. Immediately following the # sign, inside a pair of parentheses is the instantiation parameter table of this memory. From the second line to the fourth line of this parameter table, three instantiation parameters are separated by commas, which are the address bit width ($clog2(ORG_DEPTH*2)) of this memory, the storage depth (ORG_DEPTH*2), and the data port bit width (CMD1_WIDTH+CMD2_WIDTH). The values of these three instantiation parameters are obtained by their respective sub-parameters (such as ORG_DEPTH, CMD1_WIDTH, CMD2_WIDTH) through operations (including logarithmic operations, multiplication, addition). The u_ram on the fifth line is the instantiation name of this memory. When the memory is instantiated, in order to make a distinction grammatically, its instantiation names are different. For the same group of memories, it is customary to use the method of adding numbers after the instantiation name as a suffix, such as u_ram_0, u_ram_1, etc. Immediately following u_ram, inside a pair of parentheses is the connection relationship between the ports and external signals: among them, for the clock port (clk), the port name is clkin, which connects to the external signal ram_clk, and so on. For the write enable port (wren), the port name is wr, which connects to the external signal cmd_wen; for the write data port (D), the port name is d_in, which connects to the external signal cmd_datain; for the read enable port (rden), the port name is rd, which connects to the external signal cmd_ren; for the address port (A), the port name is addr, which connects to the external signal cmd_addr; for the read data port (Q), the port name is q_out, which connects to the external signal cmd_dataout.

[0090] Figure 3 The main process of a method for reconstructing a storage module in the digital integrated circuit design of the present invention is as follows:

[0091] Step S1: In all RTL source files, search for all parameter parameters, classify and save them, then perform parameter parsing and store the parsing results in the global parameter table parsed_dict.

[0092] Step S2: Search for the original memory module name old_module_name in all RTL source files to find the memory instantiation structure, then extract the required information and save it to the corresponding position in memdict to complete the initialization of memdict.

[0093] Step S3: Query the global parameter table, replace the sub-parameters of the memory instantiation parameter parameter in memdict, then calculate the decimal representation of the parameter, and update the parameter in memdict.

[0094] Step S4: Fix the storage depth and address bit width, use the data port bit width as a variable parameter, import it into the memory compilation tool, iterate until the generated memory meets the design timing requirements, and then save the new memory name to new_module_name in memdict.

[0095] Step S5: Obtain the port list of the memory module, establish the matching relationship between the new memory and the original memory ports, and save it to port_map in memdict.

[0096] Step S6: Generate the instantiation structure of the new memory and save it to new_rtl in memdict.

[0097] Step S7: Use new_rtl in memdict to replace the original memory instantiation structure in the RTL file and output the updated RTL file.

[0098] In this technical solution, the memdict used in Steps S1 to S7 includes the following information:

[0099] inst_id, which stores the primary key used to index the elements in memdict. It is equal to "RTL file name / inst_name", and inst_name is the memory instantiation name in the RTL source code.

[0100] parameter, which stores the original memory instantiation parameters, including the data port bit width data_width, the storage depth depth, and the address bit width addr_width.

[0101] old_module_name, which stores the original memory module name.

[0102] new_module_name, which stores the new memory module name.

[0103] port_connect_signal stores the connection relationship between the original memory port and external signals. It consists of key-value pairs port_connect formed by the port name port_name and external signal port_signal in sequence.

[0104] port_map stores the memory port mapping relationship. It includes the original memory port table old_port_list and the new memory port table new_port_list. The elements of the two port tables correspond in sequence. The ports include: clock (clk), write enable (wren), write data (D), read enable (rden), address (A), and read data (Q).

[0105] instance_range stores the range of code lines for the instantiation structure of the original memory. It includes the instantiation start line number inst_start_no and the instantiation end line number inst_end_no.

[0106] new_rtl stores the instantiation code of the new memory. It includes one or more of signal line definition statements, signal line connection statements, and memory instantiation statements.

[0107] Figure 4 For Figure 3 The memdict data structure used is explained as follows.

[0108] memdict is essentially a hash table, which is generally implemented using the dict() dictionary type in scripting languages such as Python. It contains a dictionary primary key (key), which is the memory instantiation index inst_id. inst_id = "RTL file name / inst_name", where inst_name is the memory instantiation name in the RTL source code. The purpose of not using inst_name alone as inst_id is to prevent the duplication of inst_id primary keys because the hardware description language Verilog allows the use of the same instantiation name in different modules, while the instantiation names in the same module must be different. Therefore, the RTL file name can be added for differentiation. Then, a data element in memdict can be selected in the form of memdict[inst_id] (where the square brackets [] are called the membership operator and will be used many times later). In addition to the primary key, the memdict structure also includes other data elements:

[0109] Original memory instantiation parameters. It includes data port width data_width, storage depth depth, and address width addr_width. These parameters are extracted from the parameter table of the memory instantiation structure and then parsed and calculated through the global parameter table parsed_dict, represented in decimal. To facilitate retrieving the corresponding parameters, the instantiation parameter can also be designed as a dictionary-like data structure, with the key names being data_width, depth, and addr_width, and the key values being the decimal numbers obtained after parameter parsing and calculation.

[0110] Original memory module name (old_module_name). It is a pre-specified string. In a single IP distribution package, the RTL source code generally uses a unified sram behavior model, and all original memory module names are the same, with only the instantiation parameters being different. Therefore, this memory module name only needs to be specified once.

[0111] New memory module name (new_module_name). It is a string that is determined after the memory compilation tool generates the new memory. To improve the recognition of the new memory module name and facilitate batch processing by other tools, the naming rule for generating the module is generally specified in the memory design tool, such as "memory name + storage depth + data width + process node".

[0112] Connection relationship between the original memory ports and external signals (port_connect_signal). It is a dictionary data structure that stores key-value pairs of the port name port_name (key name) and the port connection signal port_signal (key value). Since the ports in the module are non-repeating, they can be used as key names to directly retrieve the signal name connected to this port in the RTL source code through the original memory port in the dictionary.

[0113] Memory port mapping relationship (port_map). It includes the original port list old_port_list and the new port list new_port_list, with the elements of the two port lists corresponding in sequence. The port elements in the two port_lists are: clock clk, write enable wren, write data D, read enable rden, address A, and read data Q. The port_map uses a linked list to solve the mapping relationship in the order of positions because the port types between the new memory and the original memory are generally the same, and the number of ports is also the same.

[0114] The original memory instantiation code range (instance_range). It includes the instantiation start line number inst_start_no and the instantiation end line number inst_end_no. Since the instantiation structure in the hardware description language Verilog starts with the module name and ends with the symbol ") ;". Then, by searching for the line starting with old_module_name, the start line inst_start_no of all memories can be located, and the first ") ;" can be found going down from the start line, that is, the instantiation end line inst_end_no is found.

[0115] The new memory instantiation code (new_rtl). new_rtl is the Verilog code used to directly replace the original memory instantiation structure in the RTL source code. The generation process of new_rtl is shown in step S6.

[0116] Figure 5 For Figure 3 Step S1 is explained as follows.

[0117] Step S1-1: Create parameter tables, parsed_dict (stores parsed parameters), indirect_dict (stores indirect parameters), and undefined_dict (stores undefined parameters). Proceed to step S1-2.

[0118] Step S1-2: Read the first line from an RTL source file that has not been parameter-parsed. Proceed to step S1-3.

[0119] Step S1-3: Does the code line match the parameter syntax? If yes, proceed to step S1-4, otherwise proceed to step S1-9.

[0120] Step S1-4: Is the parameter value numeric? If yes, proceed to step S1-5, otherwise proceed to step S1-6.

[0121] Step S1-5: Convert the parameter value to decimal and store it in parsed_dict. Proceed to step S1-9.

[0122] Step S1-6: Does the parameter value contain operators? If yes, proceed to step S1-7, otherwise proceed to step S1-8.

[0123] Step S1-7: Store the parameter value in indirect_dict. Proceed to step S1-9.

[0124] Step S1-8: Store the parameter value in undefined_dict, prepare for replacement and calculation. Proceed to step S1-9.

[0125] Step S1-9: Is there a next line in the source file? If yes, go to Step S1-10; otherwise, go to Step S1-11.

[0126] Step S1-10: Read the next line of the source file. Go to Step S1-3.

[0127] Step S1-11: Are there any files to be parsed? If yes, go to Step S1-2; otherwise, go to Step S1-12.

[0128] Step S1-12: Is indirect_dict empty? If yes, go to Step S1-15; otherwise, go to Step S1-13.

[0129] Step S1-13: Query from parsed_dict and replace the parameter value of indirect_dict. Go to Step S1-14.

[0130] Step S1-14: Move the replaced parameter from indirect_dict to parsed_dict. Go to Step S1-15.

[0131] Step S1-15: Is undefined_dict empty? If yes, go to Step S1-18; otherwise, go to Step S1-16.

[0132] Step S1-16: Query from parsed_dict and replace the parameter value of undefined_dict. Go to Step S1-17.

[0133] Step S1-17: After calculating the replaced parameter of undefined_dict, move it to parsed_dict. Go to Step S1-12.

[0134] Step S1-18: The parsing of all memory parameters is completed, and the parsing results are stored in the global parameter table parsed_dict.

[0135] In the above step S1, the parameter tables parsed_dict, indirect_dict, and undefined_dict are preferably implemented in dictionary types, which facilitates directly retrieving parameter values by parameter names. The indirect parameters stored in indirect_dict are obtained by directly querying parsed_dict to get the specific parameter values and do not require calculation; the undefined parameters stored in undefined_dict need to be first queried and replaced in parsed_dict and then calculated for evaluation. The parameters parsed by indirect_dict and undefined_dict are finally merged into parsed_dict for subsequent parsing of memory instantiation parameters. Step S1 is similar to recursion, and a recursive structure is preferably considered during implementation.

[0136] Figure 6 For Figure 3 step S2 is explained as follows.

[0137] Step S2-1: Create a data structure memdict for memory instantiation. Proceed to step S2-2.

[0138] Step S2-2: Set the original memory module name old_module_name. Proceed to step S2-3.

[0139] Step S2-3: Read the first line from the RTL source file where instantiation parameters have not been extracted. Proceed to step S2-4.

[0140] Step S2-4: Does the code line start with old_module_name? If yes, proceed to step S2-7; otherwise, proceed to step S2-5.

[0141] Step S2-5: Is there a next line in the source file? If yes, proceed to step S2-6; otherwise, proceed to step S2-16.

[0142] Step S2-6: Read the next line. Proceed to step S2-4.

[0143] Step S2-7: Record the line number to the instantiation start line number inst_start_no. Proceed to step S2-8.

[0144] Step S2-8: Does the code line end with ")?"? If yes, proceed to step S2-10; otherwise, proceed to step S2-9.

[0145] Step S2-9: Read the next line. Proceed to step S2-8.

[0146] Step S2-10: Record the line number to the instantiation end line number inst_end_no, and save the RTL code between inst_start_no and inst_end_no to the instantiation structure inst_body. Proceed to step S2-11.

[0147] Step S2-11: Extract the memory instantiation name inst_name in inst_body, and record the memory instantiation index inst_id = RTL file name / inst_name. Proceed to step S2-12.

[0148] Step S2-12: Extract the instantiation parameters in inst_body and save them to memdict[inst_id][parameter]. Proceed to step S2-13.

[0149] Step S2-13: Extract all port names port_name and the connected external signals port_signal in inst_body. Add them one by one to memdict[inst_id][port_connect_signal] with port_name as the key name and port_signal as the key value. Proceed to step S2-14.

[0150] Step S2-14: Save inst_start_no and inst_end_no to memdict[inst_id][instance_range]. Proceed to step S2-15.

[0151] Step S2-15: Switch the line number to inst_end_no. Proceed to step S2-16.

[0152] Step S2-16: Have all RTL source files been extracted? If yes, proceed to step S2-17; otherwise, proceed to step S2-3.

[0153] Step S2-17: The initialization of memdict is completed.

[0154] In the old_module_name in the above step S2, there is generally only one name in the original RTL code, which is called the parameterized memory module, such as Figure 11 dynamic_sram in, and this name is predictable. Therefore, in most cases, it only needs to be set once for old_module_name. If there are multiple parameterized memory modules in the original RTL code, each parameterized memory module needs to be substituted into step S2.

[0155] In the above step S2, the process of extracting the instantiation name, instantiation parameters, ports, and external signals from inst_body can be implemented using regular expressions.

[0156] Figure 7 For Figure 3 step S3, the explanation is as follows.

[0157] Step S3-1: Start traversing memdict, starting from the first primary key (inst_id). Proceed to step S3-2.

[0158] Step S3-2: Select the data member memdict[inst_id]. Proceed to step S3-3.

[0159] Step S3-3: Obtain the memory instantiation parameter memdict[inst_id][parameter]. Proceed to step S3-4.

[0160] Step S3-4: Take out the memory instantiation parameters, including the data port width data_width, storage depth depth, and address width addr_width. Proceed to step S3-5.

[0161] Step S3-5: Call figure(x), where x takes data_width, depth, and addr_width in sequence. Proceed to step S3-8 until step S3-12 is completed, then proceed to step S3-6.

[0162] Step S3-6: Has memdict been traversed completely? If yes, proceed to step S3-14; otherwise, proceed to step S3-7.

[0163] Step S3-7: Select the next inst_id. Proceed to step S3-2.

[0164] Step S3-8: Enter the method figure(x). Proceed to step S3-9.

[0165] Step S3-9: Extract the operator op in x. Proceed to step S3-10.

[0166] Step S3-10: Use op as the delimiter to separate the sub-parameters from x. Proceed to step S3-11.

[0167] Step S3-11: Query parsed_dict and replace the sub-parameters with decimal representations. Proceed to step S3-12.

[0168] Step S3-12: Obtain the decimal result of x through calculation. Proceed to step S3-13.

[0169] Step S3-13: Update the result to the instantiation parameter memdict[inst_id][parameter]. Proceed to Step S3-6.

[0170] Step S3-14: The calculation and update of the memory instantiation parameters in memdict are completed.

[0171] In the above Step S3-9, the operator op includes basic algebraic operations "addition, subtraction, multiplication, division" and "logarithm operation with base 2".

[0172] Figure 8 For Figure 3 Step S4 is explained as follows.

[0173] Step S4-1: Start traversing memdict, starting from the first primary key (inst_id). Proceed to Step S4-2.

[0174] Step S4-2: Select the data member memdict[inst_id][parameter]. Proceed to Step S4-3.

[0175] Step S4-3: Fetch the memory instantiation parameters, including the data port width data_width, the storage depth depth, and the address width addr_width. Proceed to Step S4-4.

[0176] Step S4-4: Set the width division coefficient ratio = 1. Proceed to Step S4-5.

[0177] Step S4-5: The new memory data port width The result of the division is rounded up. Proceed to Step S4-6.

[0178] Step S4-6: Import new_data_width, depth, and addr_width into the memory compilation tool to generate a new memory library file. Proceed to Step S4-7.

[0179] Step S4-7: Does the new memory meet the timing requirements? If yes, proceed to Step S4-9; otherwise, proceed to Step S4-8.

[0180] Step S4-8: ratio = ratio × 2. Proceed to Step S4-5.

[0181] Step S4-9: Save the name of the newly compiled memory to memdict[inst_id][new_module_name]. Proceed to Step S4-10.

[0182] Step S4-10: Has memdict been traversed completely? If yes, go to step S4-12; otherwise, go to step S4-11.

[0183] Step S4-11: Select the next inst_id. Go to step S4-2.

[0184] Step S4-12: The generation of the new memory library file is completed.

[0185] In the above step S4-6, the memory compilation tool generally refers to the memoryCompiler tool. The process library will provide this tool to generate memory library files under different sizes and process corners. These library files still belong to the RTL type and can be used together with other source files in the RTL directory to implement the front-end logic design. When the memory library file is generated, the corresponding timing reports for each memory are generated simultaneously. By querying the data in the reports, it can be confirmed whether the new memory meets the timing requirements of the design.

[0186] Figure 9 For Figure 3 step S5, the explanation is as follows.

[0187] Step S5-1: Start traversing memdict, starting from the first primary key (inst_id). Go to step S5-2.

[0188] Step S5-2: Obtain the new memory module port list new_port_list. Go to step S5-3.

[0189] Step S5-3: Obtain the original memory module port list old_port_list. Go to step S5-4.

[0190] Step S5-4: Match the clock ports, new_port_list[clk] corresponds to old_port_list[clk]. Go to step S5-5.

[0191] Step S5-5: Match the write enable ports, new_port_list[wren] corresponds to old_port_list[wren]. Go to step S5-6.

[0192] Step S5-6: Match the write data ports, new_port_list[D] corresponds to old_port_list[D]. Go to step S5-7.

[0193] Step S5-7: Match the read enable ports, new_port_list[rden] corresponds to old_port_list[rden]. Go to step S5-8.

[0194] Step S5-8: Match the read data port, where new_port_list[Q] corresponds to old_port_list[Q]. Proceed to Step S5-9.

[0195] Step S5-9: Match the address port, where new_port_list[A] corresponds to old_port_list[A]. Proceed to Step S5-10.

[0196] Step S5-10: Store the correspondence between new_port_list and old_port_list into memdict[inst_id][port_map]. Proceed to Step S5-11.

[0197] Step S5-11: Has memdict been traversed completely? If yes, proceed to Step S5-13; otherwise, proceed to Step S5-12.

[0198] Step S5-12: Select the next inst_id. Proceed to Step S5-2.

[0199] Step S5-13: The memory port matching is completed.

[0200] In the above Steps S5-2 and S5-3, the process of obtaining the memory module port list can be directly extracted from the memory instantiation structure using regular expressions. For the original memory, the memory instantiation structure is located in the module statement block of the RTL source file that defines the memory, and the file location is performed using memdict[inst_id][old_module_name]; for the new memory, it is located in the module statement block of the newly generated memory library file, and the location is performed using memdict[inst_id][new_module_name]. Here, there is no essential difference between the memory source file and the memory library file, and they are both described in Verilog syntax.

[0201] Since the order in which the ports of the original memory and the new memory appear in the instantiated structure may be inconsistent, it is necessary to re - establish the port correspondence. This can be achieved by adjusting the positions of the ports in the two port lists, new_port_list and old_port_list, so that the ports are sequentially corresponded from front to back in the list data structure; or an additional dictionary data structure can be used to store the port mapping relationship. In this embodiment, the former is used to correspond the port relationship, so that memdict[inst_id][port_map] only needs to directly store the adjusted lists new_port_list and old_port_list, and the port relationship is actually corresponded through the order of the elements in the list.

[0202] Figure 10 For Figure 3 step S6 is explained as follows.

[0203] Step S6 - 1: Start traversing memdict, starting from the first primary key (inst_id). Proceed to step S6 - 2.

[0204] Step S6 - 2: According to the data port widths new_data_width and data_width of the new memory and the original memory, calculate the number of instantiations after memory replacement (round up by division). Proceed to step S6 - 3.

[0205] Step S6 - 3: Obtain the memory instantiation name inst_name, and set the initial instantiation index inst_no = 0. Proceed to step S6 - 4.

[0206] Step S6 - 4: Construct a new instantiation name new_inst_name, new_inst_name = inst_name+inst_no (concatenate as strings). Proceed to step S6 - 5.

[0207] Step S6 - 5: Obtain the memory port lists new_port_list and old_port_list from memdict[inst_id][port_map], and obtain the connection relationship port_connect from memdict[inst_id][port_connect_signal]. Proceed to step S6 - 6.

[0208] Step S6 - 6: Is inst_no equal to (inst_times - 1)? If yes, proceed to step S6 - 8; otherwise, proceed to step S6 - 7.

[0209] Step S6-7: right_index = new_data_width × inst_no, left_index = right_index + new_data_width - 1. Proceed to Step S6-10.

[0210] Step S6-8: right_index = new_data_width × inst_no, left_index = data_width - 1. Proceed to Step S6-9.

[0211] Step S6-9: Append "wire[new_data_width×inst_times-1:right_index]port_connect[old_port_list[Q]]_; assign port_connect[old_port_list[Q]][left_index:right_index] = port_connect[old_port_list[Q]]_[left_index:right_index]" to memdict[inst_id][new_rtl]. Proceed to Step S6-10.

[0212] Step S6-10: Append "new_module_name new_inst_name(" to memdict[inst_id][new_rtl]. Proceed to Step S6-11.

[0213] Step S6-11: Append ".new_port_list[clk](port_connect[old_port_list[clk]]),.new_port_list[wren](port_connect[old_port_list[wren]]),.new_port_list[rden](port_connect[old_port_list[rden]]),.new_port_list[A](port_connect[old_port_list[A]])," to memdict[inst_id][new_rtl].

[0214] Step S6-12: Is inst_no equal to (inst_times - 1)? If yes, proceed to Step S6-15; otherwise, proceed to Step S6-13.

[0215] Step S6-13: Append ".new_port_list[D](port_connect[old_port_list[D]][left_index:right_index]),.new_port_list[Q](port_connect[old_port_list[Q]][left_index:right_index]));" to memdict[inst_id][new_rtl]. Proceed to Step S6-14.

[0216] Step S6-14: Increment the instantiation index: inst_no = inst_no + 1. Proceed to Step S6-4.

[0217] Step S6-15: Calculate the number of 0s to be padded at the high bit of the write data port D: pads = new_data_width × inst_times - data_width. Proceed to Step S6-16.

[0218] Step S6-16: Append ".new_port_list[D]({{pads{1'b0}},port_connect[old_port_list[D]][left_index:right_index]})," to memdict[inst_id][new_rtl]. Proceed to Step S6-17.

[0219] Step S6-17: Append ".new_port_list[Q](port_connect[old_port_list[Q]]_));" to memdict[inst_id][new_rtl]. Proceed to Step S6-18.

[0220] Step S6-18: Has memdict been traversed completely? If yes, proceed to Step S6-20; otherwise, proceed to Step S6-19.

[0221] Step S6-19: Select the next inst_id. Proceed to Step S6-2.

[0222] Step S6-20: The generation of new_rtl in memdict is completed.

[0223] In the above step S6-2, since the data port width of the new memory may be smaller than that of the original memory, multiple new memories need to be concatenated by data bits to achieve the function of the original memory. After concatenation, there may be a situation where some data bits cannot correspond to the high data bits. In this embodiment, it is solved by filling 0 in the high bits, and the number of 0s filled in the data port D needs to be calculated, as shown in step S6-15. After concatenation, the total number of bits of Q may also be expanded. Therefore, it is necessary to redefine the wire-type external signal connecting Q. The newly defined wire signal is achieved by adding an underscore "_" after the name of the original Q-terminal external signal, and the Q-terminal signal needs to be intercepted and connected to the original signal, as shown in step S6-9. In addition, due to the reason of concatenating memories, the instantiation name needs to be redefined. The method in this embodiment is to add the instantiation index (concatenated as a string) after the original instantiation name for distinction, as shown in steps S6-3 and S6-14. When the instantiation index inst_no reaches inst_times-1 (see step S6-12), it means that the concatenation of this memory is completed and the next instantiation structure can be processed.

[0224] In the above step S6-5, port_connect = memdict[inst_id][port_connect_signal]. Port_connect is preferably implemented with a dictionary data structure, so that the external signal (key value) corresponding to each port (key name) of the original port list old_port_list can be directly retrieved, which is convenient for connection in the instantiation structure of the new memory.

[0225] Figure 11 For Figure 3 step S7, the explanation is as follows.

[0226] Step S7-1: Enter the RTL directory and open the first RTL source file. Proceed to step S7-2.

[0227] Step S7-2: Traverse the primary key inst_id of memdict to find those with the "RTL file name" the same as the current RTL source file name, and save them as the linked list inst_id_list. Proceed to step S7-3.

[0228] Step S7-3: Use memdict[inst_id][instance_range][inst_start_no] as the sorting key to sort the inst_id in inst_id_list in descending order. After sorting, inst_id_list becomes sorted_inst_id_list. Proceed to step S7-4.

[0229] Step S7-4: Store the current RTL source file code line by line into the linked list rtl_list. Proceed to Step S7-5.

[0230] Step S7-5: Obtain the top and bottom of the replacement position of the new memory instantiation code: top_row = memdict[inst_id][instance_range][inst_start_no] bot_row = memdict[inst_id][instance_range][inst_end_no]. Proceed to Step S7-6.

[0231] Step S7-6: Sequentially take out inst_id from sorted_inst_id_list, and replace the code between top_row and bot_row in rtl_list with the new memory instantiation code memdict[inst_id][new_rtl]. Proceed to Step S7-7.

[0232] Step S7-7: Write the updated rtl_list to the new RTL source file. Proceed to Step S7-8.

[0233] Step S7-8: Has the RTL source file been traversed completely? If yes, proceed to Step S7-10; otherwise, proceed to Step S7-9.

[0234] Step S7-9: Open the next RTL source file. Proceed to Step S7-2.

[0235] Step S7-10: The reconstruction of the storage modules of all RTL source files is completed.

[0236] In the above Step S7-2, since the memory instantiation index adopted in this embodiment already includes the RTL file name, all inst_ids belonging to this RTL file can be filtered out through the RTL file name, and thus the code range instance_range and the specific instantiation code new_rtl that need to be replaced in this RTL file can be found. In this way, it is not necessary to traverse memdict for each RTL file.

[0237] In the above Step S7-3, use the descending order of the starting line numbers of the instantiation structures, and first replace the memory instantiation codes with larger line numbers into the RTL file. In this way, it will not affect the replacement of the memory instantiation codes with smaller line numbers. If no sorting is performed, the line numbers of the instantiation codes may change after each replacement, and the position of the next replacement needs to be recalculated, resulting in unnecessary computational work. This also reduces the possibility of code update errors.

[0238] Figure 12This is the reconstructed system architecture diagram of the storage module provided by the embodiments of the present invention. As Figure 12 shown, it includes:

[0239] An instantiation parameter parsing unit 1210, which is used to search for all parameter parameters in all RTL source files, parse the searched parameter parameters and store them in the global parameter table; the parameter parameters are global parameters;

[0240] A hash table initialization unit 1220, which is used to search for the name of the original storage module in all RTL source files, find the instantiation structure of the original storage module based on the name of the original storage module, extract the information of the original storage module instantiation structure, and save the extracted information to a custom hash table to complete the initialization of the hash table; the hash table is used to store the information of the original storage module, the information of the new storage module, and the matching relationship information between the original storage module and the new storage module;

[0241] An instantiation parameter update unit 1230, which is used to update the instantiation parameters of the original storage module in the hash table to the parsed parameters in decimal based on the global parameter table; the instantiation parameters include: data end bit width, storage depth, and address bit width;

[0242] A new storage module design unit 1240, which is used to fix the two instantiation parameters of the storage depth and address bit width of the new storage module to the corresponding preset values, design the data port bit width value of the new storage module through the iteration method until the designed new storage module meets the timing design requirements, and use the data port bit width value at this time as the data port bit width design value of the new storage module; keep the name of the new storage module in the hash table;

[0243] A port relationship determination unit 1250, which is used to obtain the port lists of the original storage module and the new storage module respectively, establish the matching relationship between the ports of the original storage module and the new storage module, and save the matching relationship to the hash table;

[0244] A new instantiation structure generation unit 1260, which is used to determine the instantiation times of the new storage module after replacing the original storage module according to the data port bit width value of the original storage module and the data port bit width design value of the new storage module, generate the instantiation structure of the new storage module accordingly, and save the instantiation structure of the new storage module to the hash table;

[0245] A storage module reconstruction unit 1270, which is used to replace the instantiation structure of the original storage module in the RTL source file with the instantiation structure of the new storage module in the hash table, output the updated RTL source file, and complete the reconstruction of the original storage module.

[0246] Specifically, Figure 12For the detailed function implementation of each unit, reference can be made to the introduction in the foregoing method embodiments, which will not be elaborated herein.

[0247] Those skilled in the art can easily understand that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for reconstructing a storage module in digital integrated circuit design, characterized in that, The steps are as follows: Search for all parameter parameters in all RTL source files, parse the searched parameter parameters and store them in the global parameter table; the parameter parameters are global parameters; Search for the name of the original storage module in all RTL source files, find the instantiation structure of the original storage module based on the name of the original storage module, extract the information of the original storage module instantiation structure, and save the extracted information to a custom hash table to complete the initialization of the hash table; The hash table is used to store the information of the original storage module, the information of the new storage module, and the matching relationship information between the original storage module and the new storage module; Update the instantiation parameters of the original storage module in the hash table to the parsed parameters in decimal based on the global parameter table; The instantiation parameters include: data port bit width value, storage depth, and address bit width; Fix the two instantiation parameters of the storage depth and address bit width of the new storage module to the corresponding preset values, design the data port bit width value of the new storage module by the iterative method until the designed new storage module meets the timing design requirements, and use the data port bit width value at this time as the data port bit width design value of the new storage module; keep the name of the new storage module in the hash table; Obtain the port lists of the original storage module and the new storage module respectively, establish the matching relationship between the ports of the original storage module and the new storage module, and save the matching relationship to the hash table; Determine the instantiation times after the new storage module replaces the original storage module according to the data port bit width value of the original storage module and the data port bit width design value of the new storage module, generate the instantiation structure of the new storage module accordingly, and save the instantiation structure of the new storage module to the hash table; Replace the instantiation structure of the original storage module in the RTL source file with the instantiation structure of the new storage module in the hash table, and output the updated RTL source file to complete the reconstruction of the original storage module.

2. The reconstruction method according to claim 1, characterized in that The iterative method for designing the data port bit width value of the new storage module until the designed new storage module meets the timing design requirements specifically includes the following steps: S10. Determine the initial value of the data port bit width of the new storage module; S20. Preset the width division coefficient, and set the initial value of the width division coefficient to 1; S30. Divide the initial value of the data port bit width by the width division coefficient and round up to obtain a new data port bit width value; S40. Generate a new storage module according to the preset values of the storage depth and address bit width and the new data port bit width value; S50. Determine whether the new storage module generated in step S40 meets the timing design requirements. If it meets the requirements, use the new data port bit width value as the data port bit width design value of the new storage module. If it does not meet the requirements, multiply the width division coefficient by 2 as the new width division coefficient, and go to step S30.

3. The reconstruction method according to claim 1 or 2, characterized in that, The data structure of the custom hash table includes: The storage module instantiates an index storage area, an original storage module instantiation parameter storage area, an original storage module name storage area, a new storage module name storage area, a connection relationship storage area between the original storage module and external signals, a storage module port mapping relationship storage area, an original storage module instantiation code range storage area, and a new storage module instantiation code storage area; The storage module instantiation index storage area is used to store the RTL source file name and the instantiation name of the storage module in the RTL source file; The original storage module instantiation parameter storage area is used to store the data port bit width value, storage depth, and address bit width of the original storage module; The connection relationship storage area between the original storage module and external signals is used to store the port name of the original storage module, external signals, and the corresponding connection relationship between the port name and external signals; The storage module port mapping relationship storage area is used to store the port list of the original storage module and the port list of the new storage module, as well as the mapping relationship between the two lists; the port list includes: clock port, write enable port, write data port, read enable port, read data port, and address port; The original storage module instantiation code range storage area is used to store the instantiation start line number and instantiation end line number of the original storage module.

4. The reconstruction method according to claim 3, characterized in that Determine the number of instantiations of the new storage module after replacing the original storage module according to the data port bit width value of the original storage module and the designed data port bit width value of the new storage module, and generate the instantiation structure of the new storage module accordingly. The specific steps are as follows: Divide the data port bit width value of the original storage module by the designed data port bit width value and round up to obtain the number of instantiations; The instantiation name of the new storage module is concatenated by the instantiation name of the original storage module and the instantiation index. The instantiation index is incremented by 1 each time the new storage module is instantiated until the instantiation index value is the number of instantiations minus 1. At this time, the generation of the new storage module instantiation structure is completed; when the generation of a new instantiation structure is completed, the instantiation index is reset to 0; The signals of the clock port, write enable port, read enable port, and address port in the original storage module instantiation structure are not bit-split and are directly connected to the new instantiation structure; except for the last instantiation of the new storage module, the signals of the write data port and read data port need to be split using the instantiation index before being connected to the new instantiation structure; At the last instantiation of the new storage module, for the write data port, in addition to splitting the signal using the instantiation index, its high bits also need to perform a high-bit filling operation of filling 0 according to the characteristic of bit width matching. Multiply the designed data port bit width value by the number of instantiations and subtract the data port bit width value of the original storage module to determine the number of 0s to be filled in the high bits; for the read data port, a signal matching the read data port bit width of the new storage module needs to be defined and connected to the new instantiation structure, and the signal is truncated by bit width and then connected to the original read data signal.

5. The reconstruction method according to claim 4, characterized in that The parsing and storing of the searched parameter parameters into the global parameter table specifically include the following steps: For each RTL source file, match the parameter definition syntax line by line and classify it semantically: for the parameter value defined as a numerical value, convert the numerical value to decimal and classify it into the parsed parameter table; For those parameter values that are not defined as numerical values, if the parameter value does not contain an operator, it is classified into the indirect parameter table; if the parameter value contains an operator, it is classified into the undefined parameter table; Iteratively parse the indirect parameter table. In each round, complete the replacement of the parameter values in the indirect parameter table by looking up the parsed parameter table. After each replacement, merge the parameter values into the parsed parameter table until all the parameters in the indirect parameter table are parsed; Iteratively parse the undefined parameter table. In each round, first complete the replacement of the parameter values in the undefined parameter table by looking up the parsed parameter table, and then calculate based on the replaced parameter values. Merge the calculation results of the parameter values into the parsed parameter table until all the parameters in the undefined parameter table are parsed.

6. The reconstruction method according to claim 5, wherein Updating the instantiation parameters of the original storage module in the hash table to the parsed parameters in decimal based on the global parameter table specifically includes the following steps: For each instantiation parameter of the original storage module in the hash table, first extract the operators therein, including arithmetic operators and logical operators; use the extracted operators as the delimiters of the instantiation parameter to further separate each sub-parameter that makes up the instantiation parameter; By querying the global parameter table, respectively replace each separated sub-parameter with the decimal value in the global parameter table for calculation; Based on the operators and the replaced sub-parameters that make up the instantiation parameter, calculate the final decimal numerical value of the instantiation parameter and update it to the corresponding position in the hash table.

7. The reconstruction method according to claim 6, characterized in that, Replacing the instantiation structure of the original storage module in the RTL source file with the instantiation structure of the new storage module in the hash table and outputting the updated RTL source file specifically includes the following steps: Using the name of the RTL source file, filter out all the linked lists of new instantiation structures belonging to the RTL source file from the hash table; Taking the starting line number of the instantiation structure to be replaced as the keyword, sort the elements of the linked list in descending order; Take out each instantiation structure in the sorted linked list in turn and replace the code between the starting line and the ending line of the instantiation of the original storage module in the RTL source file.

8. A reconstruction system for a storage module in digital integrated circuit design, characterized in that, including An instantiation parameter parsing unit, which is used to search all parameter parameters in all RTL source files, parse the searched parameter parameters and store them in the global parameter table; the parameter parameters are global parameters; A hash table initialization unit, which is used to search for the name of the original storage module in all RTL source files, find the instantiation structure of the original storage module based on the name of the original storage module, extract the information of the instantiation structure of the original storage module, and save the extracted information into a custom hash table to complete the initialization of the hash table; The hash table is used to store the information of the original storage module, the information of the new storage module, and the matching relationship information between the original storage module and the new storage module; An instantiation parameter updating unit, which is used to update the instantiation parameters of the original storage module in the hash table to the parsed parameters in decimal based on the global parameter table; The instantiation parameters include: data port bit width value, storage depth, and address bit width; A new storage module design unit is used to fix two instantiation parameters, namely the storage depth and the address bit width of the new storage module, to corresponding preset values, and design the data port bit width value of the new storage module through the iterative method until the designed new storage module meets the timing design requirements. Then, the data port bit width value at this time is used as the data port bit width design value of the new storage module; the name of the new storage module is stored in the hash table; A port relationship determination unit is used to obtain the port lists of the original storage module and the new storage module respectively, establish the matching relationship between the ports of the original storage module and the new storage module, and save the matching relationship in the hash table; A new instantiation structure generation unit is used to determine the number of instantiations of the new storage module after replacing the original storage module according to the data port bit width value of the original storage module and the data port bit width design value of the new storage module, generate the instantiation structure of the new storage module accordingly, and save the instantiation structure of the new storage module in the hash table; A storage module reconstruction unit is used to replace the instantiation structure of the original storage module in the RTL source file with the instantiation structure of the new storage module in the hash table, and output the updated RTL source file to complete the reconstruction of the original storage module.

9. The reconstruction system according to claim 8, characterized in that, The new storage module design unit designs the data port bit width value of the new storage module through the iterative method until the designed new storage module meets the timing design requirements, which specifically includes the following steps: S10. Determine the initial value of the data port bit width of the new storage module; S20. Preset a width division coefficient and set the initial value of the width division coefficient to 1; S30. Divide the initial value of the data port bit width by the width division coefficient and round up to obtain a new data port bit width value; S40. Generate a new storage module according to the preset values of the storage depth and the address bit width, and the new data port bit width value; S50. Determine whether the new storage module generated in step S40 meets the timing design requirements. If it meets the requirements, use the new data port bit width value as the data port bit width design value of the new storage module. If it does not meet the requirements, multiply the width division coefficient by 2 as the new width division coefficient, and enter step S30.

10. The reconstruction system according to claim 8 or 9, characterized in that The new instantiation structure generation unit determines the number of instantiations after the new storage module replaces the original storage module according to the data port bit width value of the original storage module and the designed value of the data port bit width of the new storage module, and generates the instantiation structure of the new storage module. The specific steps are as follows: Divide the data port bit width value of the original storage module by the designed value of the data port bit width and round up to obtain the number of instantiations; the instantiation name of the new storage module is formed by concatenating the instantiation name of the original storage module and the instantiation index. Each time the new storage module is instantiated, the instantiation index is incremented by 1 until the instantiation index value is the number of instantiations minus 1. At this time, the generation of the instantiation structure of the new storage module is completed; when the generation of a new instantiation structure is completed, the instantiation index is reset to 0; the signals of the clock port, write enable port, read enable port, and address port in the instantiation structure of the original storage module are not bit-split and are directly connected to the new instantiation structure; except for the last instantiation of the new storage module, the signals of the write data port and the read data port need to be split using the instantiation index and then connected to the new instantiation structure; and at the last instantiation of the new storage module, for the write data port, in addition to splitting the signal using the instantiation index, its high bits also need to be filled with 0 according to the bit width matching characteristic. Multiply the designed value of the data port bit width by the number of instantiations minus the data port bit width value of the original storage module to determine the number of 0s to be filled in the high bits; for the read data port, a signal matching the read data port bit width of the new storage module needs to be defined and connected to the new instantiation structure, and the signal is truncated by bit width and then connected to the original read data signal.

Images