Design and Application Method of Power-Specific DSP Instruction Set

Abstract

The present invention belongs to the technical field of DSP design, and specifically relates to a design and application method of a DSP instruction set dedicated to electric power. The design method includes designing a general register, using a very long instruction word technology to design a scalar instruction into a VILW instruction, and using a single instruction multiple data flow technology to design a vector instruction. The present invention designs a vector instruction, which can optimize a large number of vector operations in electric power application algorithms. And using the very long instruction word (VLIW) technology, the compiler determines the execution order between instructions, avoiding the design of a complex hardware instruction scheduler, and supports two instruction formats: four-slot VLIW instructions and two-slot immediate instructions; multiple instruction formats can realize more compact instruction encoding, optimize the situation where the encoding space cannot be fully utilized when the operand is insufficient, and limit the supported type of each operation when the instruction format is defined, rather than supporting all operations, which can reduce the design complexity and fully utilize registers and computing resources.

Description

Technical Field

[0001] The invention belongs to the technical field of DSP design, and in particular relates to a design and application method of a DSP instruction set dedicated to electric power. Background Art

[0002] At present, DSP has been widely used in wireless communication, voice recognition, multimedia, Internet and national defense fields with its powerful real-time data processing capabilities. The executable program of general DSP does not have the characteristics of power-specific. The traditional CPU adopts a scalar architecture without pipelines and has no vector operations. It executes one instruction at a time in sequence, which will lead to problems such as low resource utilization efficiency and poor performance. Summary of the invention

[0003] In order to solve the above problems, the present invention provides a design and application method of a power-specific DSP instruction set, and the specific technical solution is as follows:

[0004] A design method for a power-specific DSP instruction set includes the following steps:

[0005] S1: Design the general registers of DSP; the general registers include 16 32-bit data registers, 8 address registers, 8 index registers, 1 PC register, 1 SP register, 1 LR register, 8 1-bit condition registers and 2 256-bit vector registers;

[0006] S2: Design scalar instructions for DSP, wherein the scalar instructions are designed as VILW instructions using very long instruction word technology; two instruction formats are supported: four-slot VLIW instructions and two-slot immediate instructions;

[0007] S3: Designing vector instructions, wherein the vector instructions are designed using single instruction multiple data flow technology.

[0008] Preferably, the 256-bits vector register is an 8*32-bits vector register.

[0009] Preferably, the eight 1-bit condition registers and the two 256-bit vector registers are specifically used for single instruction multiple data stream operations.

[0010] Preferably, the scalar instructions include control instructions, scalar arithmetic instructions, scalar read and write instructions, and scalar logic instructions.

[0011] Preferably, it also includes designing a load operation for loading 8 32-bit data into a vector register at one time and a multiplication-addition operation in vector mode.

[0012] Preferably, the multiplication and addition operation is to first calculate the product of two 8*32-bits data to obtain 8*64-bits data, and then output the addition result of the 8*64-bits data and the input 8*64-bits data.

[0013] Preferably, the vector instructions mainly include vector arithmetic instructions and vector read and write instructions.

[0014] An application method of a power-specific DSP instruction set comprises the following steps:

[0015] S1: The main CPU prepares the calculation parameters and coefficient table, configures the DSP mode and initializes the DSP instruction memory and data memory;

[0016] S2: The main CPU selects and calls the vector arithmetic instructions, vector read and write instructions, scalar read and write instructions, and scalar logic instructions in the design method according to any one of claims 1 to 7 in sequence according to the needs of the executable code segment;

[0017] S3: write the corresponding selected or called vector arithmetic instruction, vector read / write instruction, scalar read / write instruction, and scalar logic instruction into the instruction register, write the variable data segment into the data register, and store the custom data segment into the data register;

[0018] S4: The main CPU configures the DSP register to start the DSP and waits for the interrupt signal indicating that the calculation is completed. The DSP supports the Ping-Pong operation mode, that is, the next data to be calculated is written during the calculation of the current data to be calculated;

[0019] S5: After receiving the interrupt signal indicating that the DSP has completed execution, the main CPU reads out the calculation result and, based on the completion status of the task, chooses whether to configure and start the DSP again.

[0020] The beneficial effects of the present invention are as follows: the present invention provides a design and application method of a DSP instruction set for electric power, the design method includes designing general registers, using very long instruction word technology to design scalar instructions into VILW instructions, and using single instruction multiple data flow technology to design vector instructions. The present invention designs vector instructions, which can optimize a large number of vector operations in electric power application algorithms, such as fast Fourier transform, mean square error, full cycle integration algorithm, etc. And using very long instruction word (VLIW) technology, the compiler determines the execution order between instructions, avoiding the design of complex hardware instruction scheduler, and supports two instruction formats: four-slot VLIW instructions and two-slot immediate instructions; multiple instruction formats can realize more compact instruction encoding, optimize the situation that the encoding space cannot be fully utilized when the number of operands is insufficient, and the instruction format defines the supported type of each operation instead of supporting all operations, which can reduce the design complexity and make full use of registers and computing resources.

[0021] The application method customizes and designs vector operation instructions according to the calculation requirements of power equipment, which improves the calculation and processing speed of the equipment for specific calculation requirements and rapidly improves the response capability of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0023] Figure 1 Design a flow chart for the instruction set of the present invention;

[0024] Figure 2 Design schematics for vector instructions;

[0025] Figure 3 is an application flow chart of the instruction set of the present invention;

[0026] Figure 4 The structure diagram of the DSP core designed for power industry;

[0027] Figure 5 This is a diagram of the software and hardware environment for designing and applying a power-specific DSP. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0030] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0031] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0032] like Figure 1 As shown, a specific embodiment of the present invention provides a design method for a power-specific DSP instruction set, comprising the following steps:

[0033] S1: Design the general registers of DSP; the general registers include 16 32-bit data registers, 8 address registers, 8 index registers, 1 PC register, 1 SP register, 1 LR register, 8 1-bit condition registers and 2 256-bit vector registers; the 256-bit vector registers are 8*32-bit vector registers. The 8 1-bit condition registers and 2 256-bit vector registers are specifically used for single instruction multiple data stream operations.

[0034] S2: Design scalar instructions for DSP, which are designed as VILW instructions using very long instruction word technology; the scalar instructions include control instructions, scalar arithmetic instructions, scalar read and write instructions, and scalar logic instructions. Instruction examples and operation objects are shown in Table 2 below. The power-specific DSP adopts very long instruction word (VLIW) technology, integrates 4-way VLIW decoders, 2-way data reading and writing, and 2-way logic operations, and uses instruction set parallelism to improve processor performance. VILW instructions mainly include arithmetic instructions, comparison instructions, bool instructions, three types of data move instructions, zero-overhead loop instructions, control instructions, and long instructions with 32-bits immediate values.

[0035] The compiler determines the execution order between instructions, avoiding the need to design a complex hardware instruction scheduler. Therefore, the power-specific DSP only needs to execute operations in parallel in the order of program compilation. VLIW is a multiple instruction multiple data (MIMD) structure. A VLIW instruction can encode multiple operations, and one operation occupies at least one operation unit. The designed power-specific DSP mainly supports two instruction formats: four-slot VLIW instructions and two-slot immediate instructions, as shown in Table 1. The four-slot VLIW instruction has the highest parallelism and can support 4 operations at the same time, of which the two read and write operations M0 / M1 can be read memory, write memory, or move between registers. Instruction examples and operation objects are shown in Table 1.

[0036] In order to improve processor performance, pipeline technology breaks instructions into multiple steps to achieve asynchronous parallel execution of multiple sequential instructions. VLIW processors can provide powerful computing power while maintaining low hardware complexity, simplifying the processor structure and removing many complex control circuits inside the processor. A VLIW instruction can encode multiple operations, and one operation occupies at least one computing unit.

[0037] Multiple instruction formats can achieve more compact instruction encoding and optimize the situation where the encoding space cannot be fully utilized when the operands are insufficient. In addition, the instruction format defines the supported types of each operation. For example, in a four-slot VLIW instruction, the first two slots are limited to support only read and write operations instead of supporting all operations. This can reduce design complexity and make full use of registers and computing resources.

[0038] Table 1 Designed power-specific DSP instruction format

[0039]

[0040] S3: Design vector instructions, which are designed using single instruction multiple data (SIMD) technology. Vector instructions are designed using single instruction multiple data (SIMD) technology, using multiple processing elements (PE) to perform the same operation on multiple sets of data at the same time, which can fully utilize the parallelism of data sets, but only one instruction is executed at any time, such as Figure 2 shown.

[0041] According to the vector operation characteristics of the power parameter algorithm, a load operation that can load 8 32-bit data into the vector register at one time and a multiplication and addition operation in the vector mode are designed. The multiplication and addition operation specifically calculates the multiplication of two 8*32-bits data first to obtain 8*64-bits data, and then outputs the addition result of the data and the input 8*64-bits data, which can optimize the vector operations that exist in large numbers in the power application algorithm, such as fast Fourier transform, mean square error, full cycle integration algorithm, etc. The vector instructions mainly include vector arithmetic instructions and vector read and write instructions. Instruction examples and operation objects are shown in Table 2 below.

[0042] Table 2 Designed power-specific DSP instruction set

[0043]

[0044] Given the C / C++ code of the power application algorithm, a binary file that can be run on the power-specific DSP is generated through the supporting compiler, assembler, and linker. The program space of the power-specific DSP is divided into an executable code segment, a variable data segment, and a custom data segment, wherein the executable code segment is written into the instruction memory, the variable data segment and the custom data segment are written into the data memory, and the custom data segment contains configuration parameters, coefficient tables (such as trigonometric functions, nonlinear operation data, etc.) and data to be calculated. The specific embodiment of the present invention also provides an application method of the power-specific DSP instruction set, such as Figure 3 As shown, the following steps are included:

[0045] S1: The main CPU prepares the calculation parameters and coefficient table, configures the DSP mode and initializes the DSP instruction memory and data memory;

[0046] S2: The main CPU selects and calls the vector arithmetic instructions, vector read and write instructions, scalar read and write instructions, and scalar logic instructions in the design method according to any one of claims 1 to 7 in sequence according to the needs of the executable code segment;

[0047] S3: write the corresponding selected or called vector arithmetic instruction, vector read / write instruction, scalar read / write instruction, and scalar logic instruction into the instruction register, write the variable data segment into the data register, and store the custom data segment into the data register;

[0048] S4: The main CPU configures the DSP register to start the DSP and waits for the interrupt signal indicating that the calculation is completed. The DSP supports the Ping-Pong operation mode, that is, the next data to be calculated is written during the calculation of the current data to be calculated;

[0049] S5: After receiving the interrupt signal indicating that the DSP has completed execution, the main CPU reads out the calculation result and, based on the completion status of the task, chooses whether to configure and start the DSP again.

[0050] Figure 4 The structural block diagram of the DSP core specially customized for electric power. The DSP core specially designed for electric power by the present invention comprises three bus interfaces, which are respectively used to access the instruction memory, the data memory and the control register.

[0051] The power-specific DSP core is designed with a three-stage pipeline, namely instruction fetch (IF), decode (ID), and execute (EX). In the instruction fetch stage, a new instruction is read from the instruction memory; in the decoding stage, the previous instruction has been decoded, and the address registers corresponding to the read and store operations are updated. The instruction decoder transmits control signals to the data read and write module and the operation module, among which the data read and write module has the functions of data alignment and packaging, and transfers the data to the register stack of the operation module; the operation module contains scalar operations and vector operations, which are composed of register stacks and processing units respectively; in the execution stage, all data calculations and write-back operations are performed.

[0052] The power-specific DSP supports C language programming, and has customized SIMD instruction sets to accelerate power-specific algorithms. It is particularly important to note that the power DSP supports C language programming, but the required compiler and other tools are customized tools, that is, the custom instruction set is not used, and the binary files generated by the general compiler cannot run on the DSP. Common feasibility programs divide program data into executable code segments, initialized data segments, uninitialized data segments, and custom data segments. The program space of the power-specific DSP is different from the common program space:

[0053] The specific space is divided into ① executable code segment, which is used to write instruction memory;

[0054] ②Variable data segment, used to write data into memory;

[0055] ③ Custom data segment, used to write data memory, save configuration parameters, coefficient table and data to be calculated. The coefficient area stores commonly used coefficient tables, such as trigonometric functions, nonlinear operation data, etc. The data area contains variable area, configuration data area and calculation data area, which are usually used to store initialization data, initialization data, data to be calculated and calculation results.

[0056] Figure 5 The software and hardware environment for designing and applying a DSP CPU core specifically for electric power is shown. The software and hardware environment system used by a DSP CPU core specifically for electric power designed by the present invention can be divided into a user layer, a software layer, and a hardware layer. The user layer is responsible for inputting the C / C++ code of the target electric power application algorithm. In the software layer, the input algorithm code is generated into binary machine code in the ELF format through a C / C++ optimization compiler, an assembler, and a linker. The debugger connects to the JTAG debugging interface on the chip or FPGA, and imports the binary machine code in the ELF format into the chip or FPGA, thereby debugging and developing the DSP CPU core specifically for electric power. The hardware layer mainly refers to the DSP chip specifically for electric power designed by the present invention, which opens a JTAG hardware debugging interface to the outside world.

[0057] The design of the power-specific DSP CPU core is divided into two steps: architecture design and chip design. The architecture design adopts the "Compiler-In-The-Loop" method of algorithm-driven architecture exploration, and the input files are the target power application algorithm C / C++ code and the initial architecture description file of the power-specific DSP CPU core.

[0058] The initial architecture description file of the power-specific DSP CPU core contains various information such as the instruction set, instruction pipeline, very long instruction word processor, vector processor, programmable data path, microprocessor and I / O interface designed by the design method of the present invention. Similar to the application scenario of the power-specific DSP CPU core, the input file is generated into binary machine code in ELF format through the C / C++ optimization compiler, assembler and linker, and then the ELF file is imported into the instruction set simulator for simulation through the debugger, and the performance is analyzed through the analyzer to find out the bottleneck operation of the target power algorithm under the current architecture.

[0059] Designers use the analysis report of the profiler to optimize the design of bottleneck operations, such as increasing the number of instructions or operation units, to obtain the adjusted power-specific DSP CPU core architecture. Repeat the above process, iteratively find the most suitable architecture parameters under the constraints of the target power algorithm, and complete the power-specific DSP CPU core architecture design for power application algorithms.

[0060] The instruction set simulator uses real-time compilation technology to achieve cycle-accurate rapid simulation of the supported architecture, and the test generator structure can support source code-level debugging. The analyzer records and analyzes key contents such as instructions, storage, functional units, and pipeline hazards, forming a closed-loop process for architecture version iteration, realizing rapid exploration of DSP CPU core architecture, and completing the design of the optimal DSP CPU core architecture for power applications. When the optimal power-specific DSP CPU core architecture in the search space is obtained, the corresponding synthesizable RTL code is obtained through the RTL generator, and the chip design stage is entered:

[0061] First, the synthesizable RTL of the power-specific DSP CPU core is integrated into the SoC of the power-specific chip;

[0062] Secondly, VCS tools are used to perform front-end simulation and functional verification, where some test stimuli for the power-specific DSP CPU core can be provided by the test generator;

[0063] Build the FPGA prototype platform again and perform FPGA testing according to the process of the previous power-specific DSP CPU core application;

[0064] Finally, DC synthesis is performed on the SoC RTL of the power-specific chip, clock constraints are performed according to the chip target parameters, the final chip layout design is completed, and it is handed over to a third party for chip tape-out. After the test sample is completed, chip-level testing of the power-specific DSP CPU core is carried out.

[0065] Those of ordinary skill in the art will appreciate that the units of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition of each example has been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0066] In the embodiments provided in the present application, it should be understood that the division of units is merely a logical function division, and there may be other division methods in actual implementation, for example, multiple units may be combined into one unit, one unit may be split into multiple units, or some features may be ignored.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention.

Claims

1. A design method for a power-specific DSP instruction set, characterized in that: The following steps are involved: S1: Design the general registers of DSP; the general registers include 16 32-bit data registers, 8 address registers, 8 index registers, 1 PC register, 1 SP register, 1 LR register, 8 1-bit condition registers and 2 256-bit vector registers; S2: Design scalar instructions for DSP, wherein the scalar instructions are designed as VILW instructions using very long instruction word technology; two instruction formats are supported: four-slot VLIW instructions and two-slot immediate instructions; the scalar instructions include control instructions, scalar arithmetic instructions, scalar read and write instructions, and scalar logic instructions; S3: Design vector instructions, wherein the vector instructions are designed using single instruction multiple data flow technology; the vector instructions mainly include vector arithmetic instructions and vector read and write instructions.

2. The design method of a power-specific DSP instruction set according to claim 1, characterized in that: The 256-bit vector register is an 8*32-bit vector register.

3. The design method of a power-specific DSP instruction set according to claim 2, characterized in that: The eight 1-bit condition registers and the two 256-bits vector registers are specifically used for SIMD operations.

4. The design method of a power-specific DSP instruction set according to claim 3 is characterized in that: It also includes the design of a load operation for loading 8 32-bit data into a vector register at one time and a multiplication-addition operation in vector mode.

5. The design method of a power-specific DSP instruction set according to claim 4 is characterized in that: The multiplication and addition operation specifically calculates the multiplication of two 8*32-bits data first to obtain 8*64-bits data, and then outputs the addition result of the 8*64-bits data and the input 8*64-bits data.

6. An application method of a power-specific DSP instruction set, characterized in that: The following steps are involved: S1: The main CPU prepares the calculation parameters and coefficient table, configures the DSP mode and initializes the DSP instruction memory and data memory; S2: The main CPU selects and calls the vector arithmetic instructions, vector read and write instructions, scalar read and write instructions, and scalar logic instructions in the design method according to any one of claims 1 to 5 in sequence according to the needs of the executable code segment; S3: write the corresponding selected or called vector arithmetic instruction, vector read / write instruction, scalar read / write instruction, and scalar logic instruction into the instruction register, write the variable data segment into the data register, and store the custom data segment into the data register; S4: The main CPU configures the DSP register to start the DSP and waits for the interrupt signal indicating that the calculation is completed. The DSP supports the Ping-Pong operation mode, that is, the next data to be calculated is written during the calculation of the current data to be calculated; S5: After receiving the interrupt signal indicating that the DSP has completed execution, the main CPU reads out the calculation result and, based on the completion status of the task, chooses whether to configure and start the DSP again.

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