Execution method and device for cache global flushing instruction, terminal equipment and medium

Abstract

The invention discloses an execution method and device for a cache global flushing instruction, terminal equipment and a medium, and relates to the technical field of electronics. The method comprises the following steps: monitoring a memory access instruction bus in response to a pre-write-back operation function; identifying all dirty data in the cache system under the condition that the global buffer instruction is monitored; determining a target cache line according to the life count value of the dirty data in each cache line of the cache system; and pre-writing back operation is performed on the target cache line according to the dirty data corresponding to the target cache line. According to the execution method, dirty data can be screened and written back in advance by detecting the global buffer instruction in the instruction stream in real time, so that the operation burden of a CPU in the execution stage is reduced, it is ensured that Cache cleaning and other calculation tasks are conducted in parallel, the overall write-back time is shortened, the utilization efficiency of system resources is improved, and the system performance is improved. Therefore, the delay problem of the flashing operation is obviously reduced, and the response speed and the performance consistency of the system are improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a method for executing a cache global flush instruction, an execution device for executing a cache global flush instruction, a computer-readable storage medium, and a terminal device. Background Art

[0002] In high-performance processor architectures, cache management is critical to improving system performance and energy efficiency, especially in high-performance platforms and real-time embedded systems. By effectively managing cache, memory access latency can be significantly reduced and system efficiency can be improved. Cache Flush refers to the operation of forcibly writing data in the cache to the main memory or the next level of storage hierarchy. Global Flush has important applications in many scenarios. For example, when the system is reset or the operating system is started, all caches need to be refreshed to ensure that there is no legacy data in the cache to prevent old data from affecting new operations. In situations where it is necessary to ensure that the memory and cache are fully synchronized, such as DMA (Direct Memory Access) operations, global flushing can ensure that all caches in the system are consistent with the main memory. When data in the memory is updated in batches, the old data in the cache needs to be invalidated to avoid data inconsistency problems. In multi-core systems, global flushing is also used to ensure the consistency of shared data between different cores.

[0003] In the related technology, cache flush operations have the problem of high execution latency. Global flush instructions are used to write dirty data back to the main memory to ensure data consistency. However, when the amount of data stored in the cache is large, the traditional global flush write-back method will significantly increase latency, which will greatly affect the system's throughput and response speed, especially in high-performance computing. Summary of the invention

[0004] The present application aims to solve one of the technical problems in the related art to at least a certain extent. To this end, the first purpose of the present application is to propose a method for executing a cache global flush instruction, the method comprising: monitoring the memory access instruction bus in response to a pre-write back operation function; identifying all dirty data in the cache system when a global buffer instruction is detected; determining the target cache line according to the life count value of the dirty data in each cache line of the cache system; and performing a pre-write back operation on the target cache line according to the dirty data corresponding to the target cache line. The execution method of the present application can filter and write back dirty data in advance by real-time detection of global buffer instructions in the instruction stream, thereby reducing the operating burden of the CPU (Central Processing Unit) in the execution stage, ensuring that the cleaning of the cache is carried out in parallel with other computing tasks, not only reducing the overall write back time, but also improving the utilization efficiency of system resources, thereby significantly reducing the delay problem of the flush operation and improving the response speed and performance consistency of the system.

[0005] The second objective of the present application is to provide an execution device for a cache global flush instruction.

[0006] The third object of the present application is to provide a computer-readable storage medium.

[0007] The fourth objective of the present application is to provide a terminal device.

[0008] To achieve the above-mentioned objectives, the first aspect of the present application proposes a method for executing a cache global flush instruction, the method comprising: monitoring a memory access instruction bus in response to a pre-write back operation function; identifying all dirty data in the cache system when a global buffer instruction is detected; determining a target cache line based on a life count value of dirty data in each cache line of the cache system; and performing a pre-write back operation on the target cache line based on the dirty data corresponding to the target cache line.

[0009] According to one embodiment of the present application, a target cache line is determined based on a life count value of dirty data in each cache line of a cache system, including: taking a cache line corresponding to a life count value greater than or equal to a preset life threshold as the target cache line.

[0010] According to an embodiment of the present application, the above method further includes: when the pre-write back operation is completed, increasing the preset life threshold.

[0011] According to one embodiment of the present application, the above method also includes: determining a corresponding life count value based on the activity level of each cache line, wherein the activity level is negatively correlated with the access frequency of the data in the cache line, and the last access time of the data in the cache line is negatively correlated.

[0012] According to one embodiment of the present application, in response to a pre-write back operation function, the method includes: detecting a status value of a target register, wherein the pre-write back operation function is pre-stored in the target register; determining that the pre-write back operation function is in an enabled state when the status value of the target register is a preset value; and determining that the pre-write back operation function is in a disabled state when the status value of the target register is not a preset value.

[0013] According to an embodiment of the present application, the above method further includes: when the life count values ​​of all cache lines are less than a preset life threshold, exiting the pre-write back operation function.

[0014] According to an embodiment of the present application, when performing a pre-write back operation, the method further includes: when there are multiple target cache lines, obtaining a priority order of dirty data, and performing a pre-write back operation on the corresponding target cache lines according to the priority order.

[0015] To achieve the above-mentioned purpose, the second aspect of the embodiment of the present application proposes a device for executing a cache global flush instruction, the device comprising: a monitoring module, used to monitor the memory access instruction bus in response to a pre-write back operation function; an identification module, used to identify all dirty data in the cache system when a global cache instruction is detected; a determination module, used to determine the target cache line according to the life count value of the dirty data in each cache line of the cache system; and an operation module, used to perform a pre-write back operation on the target cache line according to the dirty data corresponding to the target cache line.

[0016] To achieve the above-mentioned objectives, the third aspect embodiment of the present application proposes a computer-readable storage medium, on which an execution program of a cache global flush instruction is stored. When the execution program of the cache global flush instruction is executed by a processor, the execution method of the cache global flush instruction described above is implemented.

[0017] To achieve the above-mentioned objectives, the fourth aspect embodiment of the present application proposes a terminal device, including a memory, a processor, and an execution program of a cache global flush instruction stored in the memory and executable on the processor. When the processor executes the execution program of the cache global flush instruction, the aforementioned execution method of the cache global flush instruction is implemented.

[0018] According to the execution method, device, terminal device and medium of the cache global flush instruction of the embodiment of the present application, the memory access instruction bus is monitored in response to the pre-write back operation function; when the global buffer instruction is detected, all dirty data in the cache system is identified; the target cache line is determined according to the life count value of the dirty data in each cache line of the cache system; the target cache line is pre-written back according to the dirty data corresponding to the target cache line. The execution method of the present application can filter the dirty data and write it back in advance by real-time detection of the global buffer instruction in the instruction stream, thereby reducing the operating burden of the CPU in the execution stage, ensuring that the cleaning of the cache is carried out in parallel with other computing tasks, not only reducing the overall write back time, but also improving the utilization efficiency of system resources, thereby significantly reducing the delay problem of the flush operation and improving the response speed and performance consistency of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of a data cache architecture according to some embodiments of the present application;

[0020] Figure 2 A flowchart of a method for executing a cache global flush instruction according to some embodiments of the present application;

[0021] Figure 3 A schematic diagram of a dynamic control process of a PLRU algorithm in cache management according to some embodiments of the present application;

[0022] Figure 4 A schematic diagram of a process for determining a life count value of dirty data in each cache line according to some embodiments of the present application;

[0023] Figure 5 A flowchart of a method for executing a cache global flush instruction according to other embodiments of the present application;

[0024] Figure 6 It is a block diagram of a device for executing a cache global flush instruction according to some embodiments of the present application;

[0025] Figure 7 A block diagram of a terminal device according to some embodiments of the present application. DETAILED DESCRIPTION

[0026] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0027] The following describes in detail the execution method, apparatus, terminal device and medium of the cache global flush instruction according to the embodiments of the present application with reference to the accompanying drawings.

[0028] In some embodiments, reference Figure 1 , the cache system is organized in a set-associative manner, where a cache set is a set of cache lines that are used to store specific memory data. Each cache set contains multiple cache ways, which are cache lines that store data and are responsible for storing different data blocks from the same group. When memory data is loaded into the cache, it is mapped to a specific cache set according to the group index in the address, and multiple cache ways store these data blocks. Each cache line is the smallest storage unit in the cache, storing a fixed-size data block, and comes with tag information to identify its corresponding memory address. Through this set-associative design, the cache can effectively manage and replace data in multiple ways, reduce cache conflicts, and improve access efficiency.

[0029] Figure 2 Flowchart of a method for executing a cache global flush instruction according to some embodiments of the present application. Figure 2 The method for executing the cache global flush instruction of the embodiment of the present application may include the following steps:

[0030] S110 , in response to the pre-write back operation function, monitoring the memory access instruction bus.

[0031] Specifically, after the cache system is started, if the pre-write back operation function is enabled, the memory access instruction bus is monitored. For example, the instruction cache will automatically monitor the instruction stream read from the memory and monitor whether there is a global cache instruction in the memory access instruction bus. If a global cache instruction is detected, the optimized flushing operation process will be started immediately, and the data cache will be prompted to enter the pre-execution mode. This process is completely transparent to the CPU and does not require its additional intervention or waiting.

[0032] S120, when a global buffer instruction is detected, identifying all dirty data in the cache system.

[0033] Specifically, the cache system will traverse all cache lines and check the status of each cache line. Each cache line usually has status bits, such as a valid bit, a dirty bit, a shared bit, etc., where the dirty bit is used to mark whether the cache line contains dirty data. Therefore, all dirty data in the cache system can be identified by checking the dirty bit of each cache line. Exemplarily, for each cache line, the cache system will check whether its dirty bit is set to 1. If the dirty bit is 1, it is determined that the cache line contains dirty data.

[0034] S130, determining a target cache line according to the life count value of dirty data in each cache line of the cache system.

[0035] Specifically, dirty data in each cache line has a life count value, and each cache line can be equipped with a dedicated register for storing its life count value. After determining the cache line containing dirty data, the life count value of the dirty data in the cache line can be read by accessing the register corresponding to the cache line containing dirty data, and the target cache line can be determined according to the life count value of the dirty data in the cache line.

[0036] Exemplarily, if the life count value of dirty data in the cache line is relatively large, the cache line is determined to be a target cache line; if the life count value of dirty data in the cache line is relatively small, the cache line is determined to be a non-target cache line.

[0037] S140, performing a pre-write back operation on the target cache line according to the dirty data corresponding to the target cache line.

[0038] Specifically, for the target cache line, a pre-write back operation needs to be performed immediately to reduce the amount of dirty data before the global cache instruction is formally executed, so as to reduce the burden on the CPU when executing the global cache instruction; for non-target cache lines, they will be skipped to avoid repeated write back.

[0039] The execution method of the present application can filter dirty data and write it back in advance by real-time detection of global buffer instructions in the instruction stream, thereby reducing the operating burden of the CPU during the execution phase, ensuring that cache cleaning is carried out in parallel with other computing tasks, not only reducing the overall write-back time, but also improving the utilization efficiency of system resources, thereby significantly reducing the delay problem of flushing operations and improving the system's response speed and performance consistency.

[0040] In some embodiments, the target cache line is determined according to the life count value of dirty data in each cache line of the cache system, including: taking the cache line corresponding to the life count value greater than or equal to a preset life threshold as the target cache line.

[0041] Specifically, the cache system determines the target cache line according to a preset life threshold given by each Cache Set. For example, the target cache line may be determined by comparing the life count value of dirty data in each cache line with the preset life threshold.

[0042] Exemplarily, if the life count value of dirty data in a cache line is greater than or equal to a preset life threshold, the cache line is used as a target cache line, and a pre-write back operation is performed on the target cache line to reduce the amount of dirty data before the global buffer instruction is formally executed; if the life count value of dirty data in the cache line is less than the preset life threshold, the cache line is used as a non-target cache line and the cache line will be retained, thereby ensuring that more frequently accessed data is retained in the cache and improving access efficiency.

[0043] In some embodiments, the above method further includes: when the pre-write back operation is completed, increasing the preset life threshold.

[0044] Specifically, during the pre-execution process of the global cache instruction, the cache system not only performs selective write-back of data, but also dynamically adjusts the preset life threshold of the Cache Set according to the access situation of the data during the pre-execution process.

[0045] For example, if the cache writes back subsequently accessed data during the pre-write back phase, it can be considered that the write back strategy is too aggressive. At this time, the cache system needs to re-mark the relevant dirty data and stop the write back operation of the corresponding Cache Set. The control logic will then increase the preset life threshold of this Cache Set to avoid premature write back of the cache line and reduce meaningless memory access operations. If the cache line written back is not modified again before the global buffer instruction is executed, the cache system can adopt a more optimistic strategy, and choose to lower or maintain the preset life threshold of the Cache Set on the basis of completing the write back.

[0046] In this way, the preset life threshold of the Cache Set is dynamically adjusted by utilizing the access characteristics of the Cache Set to reduce invalid write-backs and improve the accuracy of pre-execution.

[0047] It should be noted that in an embodiment of the present application, the order of cache line write back can be determined based on PLRU (Pseudo Least Recently Used). The main advantage of the PLRU algorithm is that it reduces storage and computing overhead. The algorithm usually uses a tree structure or a fixed number of bit tags to track the usage of cache items without fully maintaining the access order of all entries. When processing cache access, when the requested item exists in the cache, PLRU will update the relevant mark to indicate that the item is recently used; if it misses, the least used item is replaced based on the bit mark or tree structure. This approximate method is relatively simple to implement and is suitable for application in hardware environments, especially in processor caches and storage devices. It can effectively improve cache hit rates and reduce hardware costs.

[0048] In the following description, the preset life threshold of 3 is taken as an example, but it is not a limitation to the present application. Figure 3 The tree structure in is composed of multiple binary bits, each of which represents the usage status of a specific cache path (way). When a path is accessed, the PLRU will update these bit marks accordingly to record that the path is recently used. For example, when way3 is accessed, the control logic will update the mark bit connected by the red arrow, and the mark bits of other paths will remain the same. In this way, the PLRU can effectively track the usage of cache items, so that when a cache miss occurs, the most appropriate replacement path can be determined based on the most recent access records.

[0049] In the dynamic management process combined with the PLRU algorithm, the data cache control logic will refer to the preset life threshold of the Cache Set to manage the write-back of dirty data. When writing back the cache, the system will first filter the data in the cache according to the preset life threshold, and use the PLRU algorithm to determine which data needs to be written back first. Figure 3 In the example, way 4 is finally selected for replacement because its lifetime value is already at the preset lifetime threshold, while way 3, which has been recently accessed, remains in the cache and is not affected by the global cache instruction.

[0050] In addition, refer to Figure 4 , each cache line assists multiple bits for recording. The bits can be divided into life count and access count, which are dispersed into fused data. When data is accessed, the access count increases and the life count is cleared, which is reflected in the corresponding bit of the fused data. When the pre-write back execution starts, the fused data can be sorted according to the size, and the data above the preset life threshold can be written back after being inverted.

[0051] In some embodiments, the above method also includes: determining a corresponding life count value according to the activity level of each cache line, wherein the activity level is negatively correlated with the access frequency of the data in the cache line, and the last access time of the data in the cache line is negatively correlated.

[0052] Specifically, when each cache line is stored in the cache, a dedicated register can be used to obtain the life count value of the cache line to indicate the activity level of the cache line, where the activity level is determined by the access frequency of the data in the cache line and the last access time of the data in the cache line.

[0053] Exemplarily, when data is first cached in a cache line or accessed, its life count value will be cleared. If the data in the cache line has not been accessed for a long time, or the last access time of the data in the cache line is long, it is predicted that the data in the cache line is unlikely to be accessed again in the near future, that is, the activity level of the cache line is low, and the life count value of the cache line will gradually increase; if the data in the cache line is frequently accessed, or the last access time of the data in the cache line is relatively recent, that is, the activity level of the cache line is high, and the life count value of the cache line will remain at a low level.

[0054] In this way, when pre-executing global cache instructions, data with long life count values ​​but no longer frequently accessed can be selected for priority write-back, thereby reducing the overall write-back cost, reducing invalid write-back operations, and optimizing the accuracy and efficiency of data management.

[0055] In some embodiments, in response to the pre-write back operation function, the pre-write back operation function includes: detecting a state value of a target register, wherein the pre-write back operation function is pre-stored in the target register; determining that the pre-write back operation function is in an enabled state when the state value of the target register is a preset value; and determining that the pre-write back operation function is in a disabled state when the state value of the target register is not a preset value. The preset value may be determined according to actual conditions, and is not specifically limited here.

[0056] Specifically, during the operating system startup phase, it is usually necessary to frequently use global buffer instructions to clear the cache and ensure data consistency. In order to improve the startup speed, the state value of the target register, such as the state value of the CSR (Control and Status Register) register, can be detected to determine whether to enable the pre-write back operation function.

[0057] Exemplarily, if it is detected that the state value of the target register is a preset value, it is determined that the pre-write back operation function is in an enabled state, and the cache system will perform the pre-write back operation of the cache data in advance, and execute it in parallel with other tasks, thereby reducing the execution delay of the global buffer instruction and speeding up the system startup time; if the state value of the target register is not the preset value, it is determined that the pre-write back operation function is in a disabled state, and the cache system reverts to the traditional write back method to ensure the determinism of execution.

[0058] In addition, the preset life threshold dynamic adjustment function can be turned on or off according to the specific application scenario.

[0059] In this way, in different application scenarios, the pre-write back operation function and the preset life threshold dynamic adjustment function can be flexibly enabled or disabled according to real-time needs, thereby improving the adaptability and performance of the system.

[0060] In some embodiments, the above method further includes: when the life count values ​​of all cache lines are less than a preset life threshold, exiting the pre-write back operation function.

[0061] Specifically, if the life count values ​​of all cache lines are less than the preset life threshold, it means that the dirty data corresponding to the cache line does not need to be pre-written back, and the pre-write back operation function is exited.

[0062] In some embodiments, when performing the pre-write back operation, the method further includes: when there are multiple target cache lines, obtaining a priority order of dirty data, and performing the pre-write back operation on the corresponding target cache lines according to the priority order.

[0063] Specifically, the cache controller writes back dirty data in multiple stages, including data analysis, data write back, write back confirmation, etc. Whenever a global buffer instruction is detected and there are multiple target cache lines, the cache controller divides the dirty data into multiple batches according to priority in units of cache sets, and the write back operation of each batch is performed in a pipeline manner, so that while a batch of data is being written back, the cache controller can start analyzing the next batch of data.

[0064] In this way, the corresponding target cache lines are pre-written back according to the priority order of dirty data, which can significantly improve the write-back efficiency and reduce the time the CPU waits for the Flush operation to complete. In addition, while the cache controller is performing the pre-write-back operation, the processor can continue to execute other irrelevant instructions, thus avoiding the idle time caused by waiting for the write-back operation to a certain extent, thereby maximizing the utilization of system resources.

[0065] As a specific example, see Figure 5 The method for executing the cache global flush instruction of the embodiment of the present application may further include the following steps:

[0066] S201, system starts.

[0067] S202, instruction cache access.

[0068] S203, the Flush instruction detection module sniffs the instruction stream.

[0069] S204, determine whether a global buffer instruction is detected. If yes, execute S205; otherwise, execute S202.

[0070] S205, query the current preset life threshold.

[0071] S206, executing the behavior of writing back dirty data that is higher than a preset lifespan threshold.

[0072] S207, monitoring whether the CPU accesses the write-back data before executing the global buffer instruction.

[0073] S208, determining whether access to write-back data is detected. If yes, executing S209; otherwise, executing S210.

[0074] S209, increasing the preset lifespan threshold and suspending the write-back.

[0075] S210, reducing or maintaining a preset life threshold.

[0076] S211, the CPU executes the global buffer instruction.

[0077] S212, the data cache transfers the Flush execution permission.

[0078] S213, complete all data flushing work.

[0079] S214, end.

[0080] In summary, the execution method of the present application optimizes the global cache instruction execution and dirty data write-back process in cache management, overcomes the execution delay and performance fluctuation problems faced by related technologies, and brings significant beneficial effects; when a global cache instruction is detected, data write-back is executed in advance, thereby reducing the waiting time of the CPU in the global cache instruction execution stage, so that the cache write-back can be overlapped with other processor operations, significantly reducing the overall delay. Compared with the traditional one-by-one write-back method, the pre-execution method can perform data analysis and selective write-back at the same time as the global cache instruction is detected, which can reduce the system's dependence on the execution of the global cache instruction. By pre-writing back some dirty data, the negative impact of flushing operations on system performance is reduced, so that the system can maintain stable performance under high load conditions, especially in scenarios with high real-time requirements, effectively reducing performance fluctuations caused by flushing and improving the consistency and stability of system performance; by selectively writing back dirty data in advance, intensive write-back operations can be avoided to a certain extent, reducing memory access pressure, and reasonably adjusting the write-back strategy to reduce unnecessary data transmission, extend battery life, improve energy efficiency, and reduce instantaneous power consumption.

[0081] Corresponding to the above embodiment, the present application also proposes an execution device for a cache global flush instruction.

[0082] Reference Figure 6 The execution device 600 of the cache global flush instruction includes: a monitoring module 610, an identification module 620, a determination module 630 and an operation module 640.

[0083] Among them, the monitoring module 610 is used to monitor the memory access instruction bus in response to the pre-write back operation function. The identification module 620 is used to identify all dirty data in the cache system when a global buffer instruction is detected. The determination module 630 is used to determine the target cache line according to the life count value of the dirty data in each cache line of the cache system. The operation module 640 is used to perform a pre-write back operation on the target cache line according to the dirty data corresponding to the target cache line.

[0084] According to an embodiment of the present application, the determination module 630 is specifically configured to use a cache line corresponding to a life count value greater than or equal to a preset life threshold as a target cache line.

[0085] According to an embodiment of the present application, when the pre-write back operation is completed, the preset life threshold is increased.

[0086] According to an embodiment of the present application, the corresponding life count value is determined according to the activity level of each cache line, wherein the activity level is negatively correlated with the access frequency of the data in the cache line, and the last access time of the data in the cache line is negatively correlated.

[0087] According to one embodiment of the present application, a state value of a target register is detected, wherein a pre-write back operation function is pre-stored in the target register; when the state value of the target register is a preset value, it is determined that the pre-write back operation function is in an enabled state; when the state value of the target register is not a preset value, it is determined that the pre-write back operation function is in a disabled state.

[0088] According to an embodiment of the present application, when the life count values ​​of all cache lines are less than a preset life threshold, the pre-write back operation function is exited.

[0089] According to an embodiment of the present application, when there are multiple target cache lines, the priority order of dirty data is obtained, and a pre-write back operation is performed on the corresponding target cache lines according to the priority order.

[0090] It should be pointed out that the above-mentioned explanation of the embodiment and beneficial effects of the method for executing the cache global flush instruction is also applicable to the execution device of the cache global flush instruction in the embodiment of the present application. To avoid redundancy, it will not be expanded here in detail.

[0091] Corresponding to the above embodiments, the present application also proposes a computer-readable storage medium.

[0092] The computer-readable storage medium of the present application stores thereon an execution program of a cache global flush instruction, and when the execution program of the cache global flush instruction is executed by a processor, the execution method of the cache global flush instruction described above is implemented.

[0093] It should be pointed out that the above-mentioned explanation of the embodiment and beneficial effects of the execution method of the cache global flush instruction is also applicable to the computer-readable storage medium of the embodiment of the present application. In order to avoid redundancy, it will not be expanded in detail here.

[0094] Corresponding to the above embodiment, the present application also proposes a terminal device.

[0095] See also Figure 7 As shown, the terminal device 700 of the present application includes a memory 710, a processor 720, and an execution program of a cache global flush instruction stored in the memory 710 and executable on the processor 720. When the processor executes the execution program of the cache global flush instruction, the aforementioned execution method of the cache global flush instruction is implemented.

[0096] It should be pointed out that the above-mentioned explanation of the implementation example and beneficial effects of the method for executing the cache global flush instruction is also applicable to the terminal device of the embodiment of the present application. In order to avoid redundancy, it will not be expanded here in detail.

[0097] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0098] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0099] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0100] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0101] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0102] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for executing a cache global flush instruction, characterized in that: The method comprises: In response to the pre-write back operation function, monitoring the memory access instruction bus; In case of monitoring global buffering instructions, all dirty data in the cache system are identified; Determine a target cache line according to a lifetime count value of dirty data in each cache line of the cache system; A pre-write back operation is performed on the target cache line according to the dirty data corresponding to the target cache line.

2. The method for executing a cache global flush instruction according to claim 1, characterized in that: Determining a target cache line according to a life count value of dirty data in each cache line of the cache system includes: The cache line corresponding to the life count value being greater than or equal to the preset life threshold is used as the target cache line.

3. The method for executing a cache global flush instruction according to claim 2, characterized in that: The method further comprises: When the pre-write back operation is completed, the preset life threshold is increased.

4. The method for executing a cache global flush instruction according to claim 1, characterized in that: The method further comprises: The corresponding life count value is determined according to the activity level of each cache line, wherein the activity level is negatively correlated with the access frequency of data in the cache line and the last access time of the data in the cache line is negatively correlated.

5. The method for executing a cache global flush instruction according to claim 1, characterized in that: Functions in response to pre-write back operations include: Detecting a state value of a target register, wherein the pre-write-back operation function is pre-stored in the target register; In a case where the state value of the target register is a preset value, determining that the pre-write back operation function is in an enabled state; When the state value of the target register is not the preset value, it is determined that the pre-write back operation function is in a closed state.

6. The method for executing a cache global flush instruction according to claim 2, characterized in that: The method further comprises: When the life count values ​​of all cache lines are less than the preset life threshold, the pre-write back operation function is exited.

7. The method for executing a cache global flush instruction according to claim 1, characterized in that: When performing the pre-write back operation, the method further includes: In the case where there are multiple target cache lines, the priority order of the dirty data is obtained, and a pre-write back operation is performed on the corresponding target cache lines according to the priority order.

8. A device for executing a cache global flush instruction, characterized in that: The device comprises: A monitoring module, used for monitoring a memory access instruction bus in response to a pre-write back operation function; An identification module, used to identify all dirty data in the cache system when a global cache instruction is detected; A determination module, configured to determine a target cache line according to a life count value of dirty data in each cache line of the cache system; An operation module is used to perform a pre-write back operation on the target cache line according to dirty data corresponding to the target cache line.

9. A computer-readable storage medium, characterized in that: An execution program of a cache global flush instruction is stored thereon, and when the execution program of the cache global flush instruction is executed by a processor, an execution method of the cache global flush instruction according to any one of claims 1-7 is implemented.

10. A terminal device, characterized in that: The invention comprises a memory, a processor and an execution program of a cache global flush instruction which is stored in the memory and can be run on the processor. When the processor executes the execution program of the cache global flush instruction, the execution method of the cache global flush instruction according to any one of claims 1 to 7 is implemented.

Images