Electronic device and scanning driving circuit

Abstract

The present disclosure provides an electronic device and a scan driving circuit. The electronic device includes a shift register and a demultiplexer. The demultiplexer is electrically connected to the shift register. The demultiplexer includes at least one scan unit. The at least one scan unit includes a switch circuit and a buffer. The input end of the buffer is electrically connected to the switch circuit. The output end of the buffer is electrically connected to the scan line. Therefore, the electronic device and the scan driving circuit disclosed in the present disclosure can enable the panel to provide good image quality.

Description

Technical Field

[0001] The present disclosure relates to a device and a circuit, in particular to an electronic device and a scan driving circuit. Background Art

[0002] As users' demands for image quality continue to increase, the frequency of the signal used to drive the pixel circuit in the display panel is constantly increased to meet the demand for image quality. However, in the existing data drive circuit design, especially when the display panel operates in a high-frequency drive mode, the pixel charging time is shortened, which will cause the pixels of the display panel to fail to charge easily, thereby affecting the image quality. Summary of the invention

[0003] In view of this, the present disclosure provides an electronic device and a scan driving circuit which can effectively drive a pixel array of a panel.

[0004] The present disclosure is directed to an electronic device. The electronic device includes a shift register and a demultiplexer. The demultiplexer is electrically connected to the shift register. The demultiplexer includes at least one scanning unit. The at least one scanning unit includes a switch circuit and a buffer. The input end of the buffer is electrically connected to the switch circuit. The output end of the buffer is electrically connected to the scan line.

[0005] The present disclosure is directed to a scan driving circuit. The scan driving circuit includes a shift register and a demultiplexer. The demultiplexer is electrically connected to the shift register. The demultiplexer includes at least one scan unit. The at least one scan unit includes a switch circuit and a buffer. The input end of the buffer is electrically connected to the switch circuit, and the output end of the buffer is electrically connected to the scan line.

[0006] Based on the above, the electronic device and the scan driving circuit disclosed in the present invention can enable the panel to provide good image quality.

[0007] In order to make the above features and advantages of the present disclosure more obvious and understandable, embodiments are given below with reference to the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram of an electronic device according to some embodiments of the present disclosure;

[0009] Figure 2A A schematic diagram of a scan driving circuit according to some embodiments of the present disclosure;

[0010] Figure 2B Schematic diagram of signal waveforms of some embodiments of the present disclosure;

[0011] Figure 3A schematic diagram of a scan driving circuit according to some embodiments of the present disclosure;

[0012] Figure 4 A schematic diagram of a scan driving circuit according to some embodiments of the present disclosure;

[0013] Figure 5 A circuit configuration diagram of an electronic device according to some embodiments of the present disclosure;

[0014] Figure 6 A circuit configuration diagram of an electronic device according to some embodiments of the present disclosure;

[0015] Figure 7 A circuit configuration diagram of an electronic device according to some embodiments of the present disclosure;

[0016] Figure 8 Schematic diagram of signal waveforms according to some embodiments of the present disclosure.

[0017] Description of Reference Numerals

[0018] 100: electronic device;

[0019] 110: pixel array;

[0020] 120: scanning driving circuit;

[0021] 130: data driving circuit;

[0022] 210, 310, 410, 510, 610, 710: shift registers;

[0023] 220, 320, 420, 520, 620, 720: demultiplexer;

[0024] 221, 222, 223, 321, 322, 323, 421, 422, 423: scanning unit;

[0025] 224, 225, 324, 424: inverter;

[0026] 2211, 2221, 2231, 3211, 3221, 3231, 4211, 4221, 4231: switch circuit;

[0027] 2212, 2222, 2232, 3212, 3222, 3232, 4212, 4222, 4232: buffer;

[0028] 2213, 2223, 2233, 3213, 3223, 3233, 4213, 4223, 4233, 531, 532, 631, 632, 731, 732, 741, 742: pull-down transistors;

[0029] AA: active area;

[0030] VH: high operating voltage;

[0031] VL: low operating voltage;

[0032] G1~G3: scanning lines;

[0033] GAS: global control signal;

[0034] Sout: output signal;

[0035] Sg1~Sg3: scanning signal;

[0036] Sd: data signal;

[0037] t0~t3: time;

[0038] XCKH1~XCKH3: control signal. DETAILED DESCRIPTION

[0039] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0040] Certain words are used throughout the specification and claims to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, the words "including" and "comprising" are open-ended words and should be interpreted as "including but not limited to...".

[0041] In some embodiments of the present disclosure, terms such as "connection" and "interconnection" may refer to two structures being in direct contact, or two structures not being in direct contact, with another structure disposed between the two structures, unless otherwise specified. Such terms may also include situations where both structures are movable or both structures are fixed. In addition, the term "electrically connected" includes any direct and indirect electrical connection means.

[0042] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify components. They do not imply or represent that the component or components have any previous ordinal numbers, nor do they represent the order of a component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The claims and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the claims. It should be noted that the following embodiments can replace, reorganize, and mix the technical features in multiple different embodiments to complete other embodiments without departing from the spirit of the present disclosure.

[0043] The electronic device disclosed herein may include a display device, an antenna device, a sensing device, a touch display, a curved display, or a free shape display, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The electronic device may, for example, include a liquid crystal, a light emitting diode, a quantum dot (QD), fluorescence, phosphorescence, other suitable display media, or a panel of a combination of the above materials, but is not limited thereto. The light emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light emitting diode (Mini LED), a micro light emitting diode (Micro LED), or a quantum dot light emitting diode (QLED or QDLED) or other suitable materials, and the materials thereof may be arranged and combined in any manner, but are not limited thereto. The display device may, for example, include a spliced ​​display device, but is not limited thereto. The antenna device may, for example, be a liquid crystal antenna, but is not limited thereto. The antenna device may, for example, include an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any combination of the above, but is not limited thereto. In addition, the appearance of the electronic device can be rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. The electronic device can have peripheral systems such as a drive system, a control system, a light source system, a shelf system, etc. to support a display device, an antenna device or a splicing device. The following will illustrate the present disclosure with a display device, but the present disclosure is not limited thereto.

[0044] It should be noted that the following embodiments can replace, reorganize, or mix features in multiple different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Features between embodiments can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0045] Figure 1Schematic diagram of an electronic device according to some embodiments of the present disclosure. Figure 1 , the electronic device 100 may be a panel, but the present disclosure is not limited thereto. The electronic device 100 includes a pixel array 110, a scan driving circuit 120, and a data driving circuit 130. The scan driving circuit 120 is electrically connected to the pixel array 110 via a plurality of scan lines, and is used to output a scan signal to a plurality of sub-pixels in the pixel array 110. The data driving circuit 130 is electrically connected to the pixel array 110 via a plurality of data lines, and is used to output a data signal to a plurality of sub-pixels in the pixel array 110. In the present embodiment, the pixel array 110 may be formed, for example, using a one data triple gate (ODTG) architecture, but the present disclosure is not limited thereto. In the present embodiment, the pixel array 110 may correspond to an active area (AA) of the panel, and the scan driving circuit 120 and the data driving circuit 130 may be formed in a peripheral area of ​​the panel. The scan driving circuit 120 may be formed, for example, in a peripheral region of the panel on at least one of the left and right sides of the pixel array 110, and the data driving circuit 130 may be formed, for example, in a peripheral region of the panel on the lower side of the pixel array 110. However, the present disclosure does not limit the configuration positions of the pixel array 110, the scan driving circuit 120, and the data driving circuit 130 on the electronic device 100 or the panel. The configuration positions of the pixel array 110, the scan driving circuit 120, and the data driving circuit 130 on the electronic device 100 or the panel may be designed accordingly according to the type of the electronic device 100, the panel type, or the panel shape.

[0046] Figure 2A FIG. 1 is a schematic diagram of a scan driving circuit according to some embodiments of the present disclosure. Figure 1 as well as Figure 2A , Figure 1 The scan driving circuit 120 of the embodiment may include one or more switching circuits, and the one or more switching circuits may be used to drive a plurality of pixels in the pixel array 110. In the embodiment, each of the one or more switching circuits may include: Figure 2AThe shift register (SR) 210 and the demultiplexer (DEMUX) 220 are shown. In the present embodiment, the demultiplexer 220 is electrically connected to the shift register 210. The demultiplexer 220 includes scanning units 221-223 and inverters 224 and 225, wherein the scanning units 221-223 are electrically connected to the scanning lines G1-G3 of the pixel array 110, respectively. The scanning lines G1-G3 may correspond to three sub-pixel columns, respectively, and the three sub-pixel columns may include, for example, a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels, respectively. However, the number of scanning units of the demultiplexer 220 disclosed in the present invention is not limited to Figure 2A In some embodiments, the demultiplexer 220 may include at least one scanning unit, but the disclosure is not limited thereto.

[0047] In the present embodiment, the scanning unit 221 includes a switch circuit 2211, a buffer 2212 and a pull-down transistor 2213. The switch circuit 2211 may be a transmission gate (TG) circuit and is used to control the buffer 2212. The input end of the switch circuit 2211 is used to receive the control signal XCKH1. The input end of the buffer 2212 is electrically connected to the switch circuit 2211, and the output end of the buffer 2212 is electrically connected to the scan line G1. The buffer 2212 may be electrically connected to the high operating voltage VH and the low operating voltage VL to operate between the high operating voltage VH and the low operating voltage VL. In the present embodiment, the control end of the pull-down transistor 2213 is electrically connected to the output end of the inverter 224. The first end of the pull-down transistor 2213 is electrically connected to the output end of the buffer 2212. The second end of the pull-down transistor 2213 is electrically connected to the global control signal GAS, wherein the global control signal GAS can be used to provide a low potential (pull-down voltage). In this embodiment, the output end of the inverter 224 is electrically connected to the input end of the inverter 225. The output end of the inverter 225 is electrically connected to the first control end (positive control end) of the switch circuit 2211 (transmission gate). The output end of the inverter 224 is electrically connected to the second control end (negative control end) of the switch circuit 2211 (transmission gate).

[0048] In the present embodiment, the scanning unit 222 includes a switch circuit 2221, a buffer 2222 and a pull-down transistor 2223, and the scanning unit 223 includes a switch circuit 2231, a buffer 2232 and a pull-down transistor 2233. The pull-down transistors 2213, 2223 and 2233 are N-type transistors. The switch circuits 2221 and 2231 are transmission gate circuits and are used to control the buffers 2222 and 2232. In the present embodiment, the input end of the switch circuit 2221 is used to receive the control signal XCKH2, and the input end of the switch circuit 2231 is used to receive the control signal XCKH3. The input end of the buffer 2222 is electrically connected to the switch circuit 2221, and the output end of the buffer 2222 is electrically connected to the scan line G2. The input end of the buffer 2232 is electrically connected to the switch circuit 2231, and the output end of the buffer 2232 is electrically connected to the scan line G3. The circuit connection relationship of the scanning units 222 and 223 can be inferred from the circuit connection relationship of the scanning unit 221, so no further details are given. In addition, the control signals XCKH1-XCKH3 and the global control signal GAS of this embodiment can be provided by other timing circuits or control circuits in the scanning driving circuit 120, and the present disclosure is not limited thereto.

[0049] Figure 2B Schematic diagram of signal waveforms of some embodiments of the present disclosure. Figure 2A as well as Figure 2B , Figure 2A The relevant signal waveforms in the circuit can be shown as Figure 2B As shown. In the present embodiment, the shift register 210 can output an output signal Sout, wherein the output signal Sout is at a high potential from time t0 to time t3. In this regard, the output signal Sout is input to the first control terminals of the switch circuits 2211, 2221, 2231 and the second control terminals of the switch circuits 2211, 2221, 2231 via the inverters 224 and 225, respectively, so that the switch circuits 2211, 2221, 2231 are in an on state from time t0 to time t3. Therefore, from time t0 to time t3, the switch circuits 2211, 2221, 2231 output control signals XCKH1~XCKH3 to the buffers 2212, 2222, 2232, and after being inverted by the buffers 2212, 2222, 2232, the buffers 2212, 2222, 2232 output scan signals Sg1~Sg3 to the scan lines G1~G3. As shown Figure 2BAs shown, the input ends of the buffers 2212, 2222, and 2232 receive the control signals XCKH1-XCKH3 of 2211, 2221, and 2231 through the switch circuit, which are inversely related to the scan signals Sg1-Sg3 outputted from the output ends of the buffers 2212, 2222, and 2232. The scan signals Sg1-Sg3 are high potentials in different periods to charge the scan lines G1-G3 in time division. In addition, one or more sub-pixels electrically connected to the scan lines G1-G3 can receive the data signals Sd provided by the data driving circuit through multiple data lines from time t0 to time t3 in conjunction with the charging period of the scan signals Sg1-Sg3. In addition, the pull-down transistors 2213, 2223, and 2233 can correspondingly pull down the potentials of the scan lines G1-G3 to a low potential after time t3.

[0050] For example, the scan line G1 may be electrically connected to one or more red sub-pixels. From time t0 to time t1, the scan line G1 charges the one or more red sub-pixels according to the scan signal Sg1, and the data signal Sd simultaneously provides a red data signal to the one or more red sub-pixels. The scan line G2 may be electrically connected to one or more green sub-pixels. From time t1 to time t2, the scan line G2 charges the one or more green sub-pixels according to the scan signal Sg2, and the data signal Sd simultaneously provides a green data signal to the one or more green sub-pixels. The scan line G3 may be electrically connected to one or more blue sub-pixels. From time t2 to time t3, the scan line G3 charges the one or more blue sub-pixels according to the scan signal Sg3, and the data signal Sd simultaneously provides a blue data signal to the one or more blue sub-pixels.

[0051] Therefore, since the control signals XCKH1-XCKH3 can increase the signal thrust of the scan lines G1-G3 via the buffers 2212, 2222, 2232, when the electronic device or panel operates in the high-frequency driving mode, even if the charging time of the pixels is shortened, the scanning units 221-223 of the present embodiment can still fully charge the scan lines G1-G3, and the rising time of the signal waveform of the scan signal transmitted by the scan lines G1-G3 can be effectively shortened, which helps to fully charge the scan lines G1-G3. In other words, the electronic device or panel designed with the demultiplexer 220 of the present embodiment can provide good image display quality in the high-frequency driving mode. In addition, the scanning units 221-223 of the present embodiment do not need to receive other control signals to pull down the potential of the scan lines G1-G3, and can effectively reduce the circuit configuration space.

[0052] Figure 3 FIG. 1 is a schematic diagram of a scan driving circuit according to some embodiments of the present disclosure. Figure 1 as well as Figure 3 , Figure 1 The scan driving circuit 120 of the embodiment may include one or more switching circuits, and the one or more switching circuits may be used to drive a plurality of pixels in the pixel array 110. In the embodiment, each of the one or more switching circuits may include: Figure 3 The shift register 310 and the demultiplexer 320 are shown. In the present embodiment, the demultiplexer 320 is electrically connected to the shift register 310. The demultiplexer 320 includes scanning units 321-323 and an inverter 324, wherein the scanning units 321-323 are electrically connected to the scanning lines G1-G3 of the pixel array 110, respectively. The scanning lines G1-G3 may correspond to three sub-pixel columns, respectively, and the three sub-pixel columns may include, for example, a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels, respectively. However, the number of scanning units of the demultiplexer disclosed in the present invention is not limited to Figure 3 In some embodiments, the demultiplexer 320 may include at least one scanning unit, but the disclosure is not limited thereto.

[0053] In the present embodiment, the scanning unit 321 includes a switch circuit 3211, a buffer 3212 and a pull-down transistor 3213. The switch circuit 3211 is an N-type transistor and is used to control the buffer 3212. The first end of the switch circuit 3211 is used to receive the control signal XCKH1. The input end of the buffer 3212 is electrically connected to the second end of the switch circuit 3211, and the output end of the buffer 3212 is electrically connected to the scan line G1. The buffer 3212 can be electrically connected to the high operating voltage VH and the low operating voltage VL to operate between the high operating voltage VH and the low operating voltage VL. In the present embodiment, the control end of the pull-down transistor 3213 is electrically connected to the output end of the inverter 324. The first end of the pull-down transistor 3213 is electrically connected to the output end of the buffer 3212. The second end of the pull-down transistor 3213 is electrically connected to the global control signal GAS, wherein the global control signal GAS can be used to provide a low potential (pull-down voltage). In this embodiment, the shift register 310 is electrically connected to an input terminal of the inverter 324 and a control terminal of the switch circuit 3211 .

[0054] In the present embodiment, the scanning unit 322 includes a switch circuit 3221, a buffer 3222 and a pull-down transistor 3223, and the scanning unit 323 includes a switch circuit 3231, a buffer 3232 and a pull-down transistor 3233. The switch circuits 3221 and 3231 may be N-type transistors and are used to control the buffers 3222 and 3232. In the present embodiment, the input end of the switch circuit 3221 is used to receive the control signal XCKH2, and the input end of the switch circuit 3231 is used to receive the control signal XCKH3. The input end of the buffer 3222 is electrically connected to the switch circuit 3221, and the output end of the buffer 3222 is electrically connected to the scan line G2. The input end of the buffer 3232 is electrically connected to the switch circuit 3231, and the output end of the buffer 3232 is electrically connected to the scan line G3. The circuit connection relationship between the scanning units 322 and 323 can be inferred from the circuit connection relationship between the scanning unit 321, so it is not repeated. In addition. The control signals XCKH1-XCKH3 and the global control signal GAS of this embodiment may be provided by other timing circuits or control circuits in the scan driving circuit 120, and the disclosure is not limited thereto. The pull-down transistors 3213, 3223, and 3233 of this embodiment may be N-type transistors, but the disclosure is not limited thereto.

[0055] refer to Figure 2B as well as Figure 3 , Figure 3 The relevant signal waveform in the circuit can also be expressed as Figure 2B As shown. In the present embodiment, the shift register 310 can output an output signal Sout, wherein the output signal Sout is at a high potential from time t0 to time t3. In this regard, the output signal Sout is input to the control end of the switch circuits 3211, 3221, and 3231, so that the switch circuits 3211, 3221, and 3231 are in an on state from time t0 to time t3. Therefore, from time t0 to time t3, the switch circuits 3211, 3221, and 3231 output control signals XCKH1 to XCKH3 to the buffers 3212, 3222, and 3232, and after being inverted by the buffers 3212, 3222, and 3232, the buffers 3212, 3222, and 3232 output scan signals Sg1 to Sg3 to the scan lines G1 to G3. As shown Figure 2B As shown, the scanning signals Sg1-Sg3 are high potentials in different periods to charge the scanning lines G1-G3 in time division. In addition, one or more sub-pixels electrically connected to the scanning lines G1-G3 can receive the data signals Sd provided by the data driving circuit through multiple data lines from time t0 to time t3 in conjunction with the charging period of the scanning signals Sg1-Sg3. In addition, the pull-down transistors 3213, 3223, and 3233 can correspondingly pull the potentials of the scanning lines G1-G3 down to a low potential after time t3.

[0056] Therefore, since the control signals XCKH1-XCKH3 can increase the signal thrust of the scan lines G1-G3 via the buffers 3212, 3222, 3232, when the electronic device or panel operates in the high-frequency driving mode, even if the charging time of the pixels is shortened, the scanning units 321-323 of this embodiment can still fully charge the scan lines G1-G3, and the rise time of the signal waveform of the scan signal transmitted by the scan lines G1-G3 can be effectively shortened, which helps to fully charge the scan lines G1-G3. In other words, the electronic device or panel designed with the demultiplexer 320 of this embodiment can provide good image display quality in the high-frequency driving mode. In addition, the scanning units 321-323 of this embodiment do not need to receive other control signals to pull down the potential of the scan lines G1-G3, and can effectively reduce the circuit configuration space.

[0057] Figure 4 FIG. 1 is a schematic diagram of a scan driving circuit according to some embodiments of the present disclosure. Figure 1 as well as Figure 4 , Figure 1 The scan driving circuit 120 of the embodiment may include one or more switching circuits, and the one or more switching circuits may be used to drive a plurality of pixels in the pixel array 110. In the embodiment, each of the one or more switching circuits may include: Figure 4 The shift register 410 and the demultiplexer 420 are shown. In the present embodiment, the demultiplexer 420 is electrically connected to the shift register 410. The demultiplexer 420 includes scanning units 421-423 and an inverter 424, wherein the scanning units 421-423 are respectively electrically connected to the scanning lines G1-G3 of the pixel array 110. The scanning lines G1-G3 may, for example, correspond to three sub-pixel columns in a column of pixels, and the three sub-pixel columns may, for example, respectively include a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels. However, the number of scanning units of the demultiplexer disclosed in the present invention is not limited to Figure 4 In some embodiments, the demultiplexer 420 may include at least one scanning unit, but the disclosure is not limited thereto.

[0058] In the present embodiment, the scanning unit 421 includes a switch circuit 4211, a buffer 4212 and a pull-down transistor 4213. The switch circuit 4211 may be a P-type transistor and is used to control the buffer 4212. The first end of the switch circuit 4211 is used to receive the control signal XCKH1. The input end of the buffer 4212 is electrically connected to the second end of the switch circuit 4211, and the output end of the buffer 4212 is electrically connected to the scan line G1. The buffer 4212 is also electrically connected to the high operating voltage VH and the low operating voltage VL to operate between the high operating voltage VH and the low operating voltage VL. In the present embodiment, the control end of the pull-down transistor 4213 is electrically connected to the output end of the inverter 424. The first end of the pull-down transistor 4213 is electrically connected to the output end of the buffer 4212. The second end of the pull-down transistor 4213 is electrically connected to the global control signal GAS, wherein the global control signal GAS can be used to provide a low potential (pull-down voltage). In this embodiment, the shift register 410 is electrically connected to the input terminal of the inverter 424 .

[0059] In the present embodiment, the scanning unit 422 includes a switch circuit 4221, a buffer 4222, and a pull-down transistor 4223, and the scanning unit 423 includes a switch circuit 4231, a buffer 4232, and a pull-down transistor 4233. The switch circuits 4221 and 4231 may be P-type transistors and are used to control the buffers 4222 and 4232. In the present embodiment, the input end of the switch circuit 4221 is used to receive the control signal XCKH2, and the input end of the switch circuit 4231 is used to receive the control signal XCKH3. The input end of the buffer 4222 is electrically connected to the switch circuit 4221, and the output end of the buffer 4222 is electrically connected to the scan line G2. The input end of the buffer 4232 is electrically connected to the switch circuit 4231, and the output end of the buffer 4232 is electrically connected to the scan line G3. The circuit connection relationship between the scanning units 422 and 423 can be inferred from the circuit connection relationship between the scanning unit 421, so it is not repeated. In addition. The control signals XCKH1-XCKH3 and the global control signal GAS of this embodiment may be provided by other timing circuits or control circuits in the scan driving circuit 120, and the disclosure is not limited thereto. The pull-down transistors 4213, 4223, 4233 of this embodiment may be N-type transistors, but the disclosure is not limited thereto.

[0060] refer to Figure 2B as well as Figure 4 , Figure 4 The relevant signal waveform in the circuit can also be expressed as Figure 2BAs shown. In the present embodiment, the shift register 410 can output an output signal Sout, wherein the output signal Sout is at a high potential from time t0 to time t3. In this regard, the output signal Sout is respectively input to the control terminals of the switch circuits 4211, 4221, and 4231 via the inverter 424, so that the switch circuits 4211, 4221, and 4231 are in an on state from time t0 to time t3. Therefore, from time t0 to time t3, the switch circuits 4211, 4221, and 4231 output control signals XCKH1 to XCKH3 to the buffers 4212, 4222, and 4232, and after being inverted by the buffers 4212, 4222, and 4232, the buffers 4212, 4222, and 4232 output scan signals Sg1 to Sg3 to the scan lines G1 to G3. As shown Figure 2B As shown, the scanning signals Sg1-Sg3 are high potentials in different periods to charge the scanning lines G1-G3 in time division. In addition, one or more sub-pixels electrically connected to the scanning lines G1-G3 can receive the data signals Sd provided by the data driving circuit through multiple data lines from time t0 to time t3 in conjunction with the charging period of the scanning signals Sg1-Sg3. In addition, the pull-down transistors 4213, 4223, 4233 can correspondingly pull the potentials of the scanning lines G1-G3 down to a low potential after time t3.

[0061] Therefore, since the control signals XCKH1-XCKH3 can increase the signal thrust of the scan lines G1-G3 via the buffers 4212, 4222, 4232, when the electronic device or panel operates in the high-frequency driving mode, even if the charging time of the pixels is shortened, the scanning units 421-423 of this embodiment can still fully charge the scan lines G1-G3, and the rise time of the signal waveform of the scan signal transmitted by the scan lines G1-G3 can be effectively shortened, which helps to fully charge the scan lines G1-G3. In other words, the electronic device or panel designed with the demultiplexer 420 of this embodiment can provide good image display quality in the high-frequency driving mode. In addition, the scanning units 421-423 of this embodiment do not need to receive other control signals to pull down the potential of the scan lines G1-G3, and can effectively reduce the circuit configuration space.

[0062] Figure 5 A circuit configuration diagram of an electronic device according to some embodiments of the present disclosure. Figure 8 Schematic diagram of signal waveforms of some embodiments of the present disclosure. Figure 1 , Figure 5 as well as Figure 8 , the circuit configuration of the electronic device 100 may be as follows Figure 5In this embodiment, the shift register 510 is electrically connected to the demultiplexer 520. The demultiplexer 520 is electrically connected to the pixel array in the active area AA (eg, Figure 1 In the present embodiment, the control end of the pull-down transistor 531 is electrically connected to the scan line G2, and the first end of the pull-down transistor 531 is electrically connected to the scan line G1. The control end of the pull-down transistor 532 is electrically connected to the scan line G3, and the first end of the pull-down transistor 532 is electrically connected to the scan line G2. The pull-down transistors 531 and 532 may be N-type transistors, but the present disclosure is not limited thereto. In the present embodiment, when the scan signal operation of the scan lines G1 to G3 is as follows: Figure 8 As shown, at time t1, when the corresponding scan signal Sg1 starts to fall, the corresponding scan signal Sg2 starts to rise. The scan signal Sg2 turns on the pull-down transistor 531, which can help the scan line G1 pull down its potential. In this embodiment, at time t1, the corresponding scan signal Sg1 falls and the corresponding scan signal Sg2 rises at the same time. At time t2, when the corresponding scan signal Sg2 starts to fall, the corresponding scan signal Sg3 starts to rise. The scan signal Sg3 turns on the pull-down transistor 532, which can help the scan line G2 pull down its potential. In this embodiment, at t2, the corresponding scan signal Sg2 falls and the corresponding scan signal Sg3 rises at the same time. Similarly, the scan line G3 can also be pulled down by another pull-down transistor (not shown) and in combination with other scan lines, and the present disclosure is not limited thereto. Furthermore, one or more sub-pixels electrically connected to the scan lines G1 - G3 may receive data signals Sd provided by the data driving circuit through a plurality of data lines from time t0 to time t3 in conjunction with the charging period of the scan signals Sg1 - Sg3 .

[0063] It is worth noting that the circuit configuration diagram of this embodiment can be applied to the above Figure 2A , Figure 3 as well as Figure 4 The shift registers 210, 310, 410 and the demultiplexers 220, 320, 420 of the embodiment. In this embodiment, Figure 2A , Figure 3 as well as Figure 4 The shift registers 210, 310, 410 of the embodiment can be used to output Figure 8 The output signal Sout shown in FIG. 1 and the demultiplexers 220, 320, 420 can be used to receive the output signal Sout as shown in FIG. Figure 8In the present embodiment, since one end of the scan lines G1-G3 between the demultiplexer 520 and the active area AA is additionally provided with pull-down transistors 531, 532, the falling time of the signal waveform of the scan signal transmitted by the scan lines G1-G3 of the present embodiment can be effectively shortened, which helps to fully charge the scan lines G1-G3.

[0064] Figure 6 The circuit configuration diagram of the electronic device of some embodiments of the present disclosure is shown in FIG. Figure 6 , similar to the above Figure 5 The shift register 610 of this embodiment is electrically connected to the demultiplexer 620. The demultiplexer 620 is electrically connected to the pixel array (eg, Figure 1 In the present embodiment, the control end of the pull-down transistor 631 is electrically connected to the scan line G2, and the first end of the pull-down transistor 631 is electrically connected to the scan line G1. The control end of the pull-down transistor 632 is electrically connected to the scan line G3, and the first end of the pull-down transistor 632 is electrically connected to the scan line G2. The pull-down transistors 631 and 632 may be N-type transistors, but the present disclosure is not limited thereto.

[0065] Different from Figure 5 In the electronic device of this embodiment, the other end of the scan lines G1-G3 located at the other side of the active area AA away from the demultiplexer 630 is additionally provided with pull-down transistors 631 and 632. In this regard, the potential pull-down effect of the pull-down transistors 631 and 632 of this embodiment can be obtained by Figure 5 and Figure 8 In this embodiment, since the other ends of the scan lines G1-G3 on the other side of the active area AA are additionally provided with pull-down transistors 631 and 632, the falling time of the signal waveform of the scan signal of the scan lines G1-G3 of this embodiment can be effectively shortened, which helps to fully charge the scan lines G1-G3.

[0066] Figure 7 The circuit configuration diagram of the electronic device of some embodiments of the present disclosure is shown in FIG. Figure 7 , similar to the above Figure 5 and Figure 6 The shift register 710 of this embodiment is electrically connected to the demultiplexer 720. The demultiplexer 720 is electrically connected to the pixel array (eg, Figure 1Pixel array 110). In the present embodiment, the control end of the pull-down transistor 731 is electrically connected to the scan line G2, and the first end of the pull-down transistor 731 is electrically connected to the scan line G1. The control end of the pull-down transistor 732 is electrically connected to the scan line G3, and the first end of the pull-down transistor 732 is electrically connected to the scan line G2. The pull-down transistors 731 and 732 may be N-type transistors, but the present disclosure is not limited thereto. In the present embodiment, the control end of the pull-down transistor 741 is electrically connected to the scan line G2, and the first end of the pull-down transistor 741 is electrically connected to the scan line G1. The control end of the pull-down transistor 742 is electrically connected to the scan line G3, and the first end of the pull-down transistor 742 is electrically connected to the scan line G2. The pull-down transistors 741 and 742 are N-type transistors.

[0067] The electronic device of this embodiment is provided with pull-down transistors 731, 732, 741, 742 at both ends of the scan lines G1-G3 on one side and the other side of the active area AA. Figure 5 , Figure 6 and Figure 8 In this embodiment, since pull-down transistors 731, 732, 741, 742 are additionally provided at both ends of the scan lines G1-G3 on both sides of the active area AA, the falling time of the signal waveform of the scan signal of the scan lines G1-G3 of this embodiment can be effectively shortened, which helps to fully charge the scan lines G1-G3.

[0068] In addition, when analyzing or demonstrating an electronic product, for example, by viewing it through a light source microscope, if the data driving circuit of the electronic product is provided with circuit components or circuit configurations as in the above-mentioned embodiments, or if a signal measurement is performed to obtain a signal having the above-mentioned characteristics, Figure 2B or Figure 8 The signal waveform characteristics of the electronic product can be regarded as a circuit design architecture for implementing the electronic device or scan driving circuit claimed in the present disclosure.

[0069] In summary, the electronic device and the scan driving circuit disclosed in the present invention can effectively charge the pixels in the pixel array of the driving panel, especially when the panel is operated in a high-frequency driving mode, such as shortening at least one of the signal rise time and signal fall time of the scan signal, so that the panel can provide good image quality in the high-frequency driving mode. Alternatively, the electronic device and the scan driving circuit disclosed in the present invention can effectively save the number of signal lines and the output of control signals in the electronic device and the scan driving circuit based on the special pull-down transistor configuration proposed in the present invention.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An electronic device, characterized in that: include: Shift register; as well as A demultiplexer is electrically connected to the shift register, and the demultiplexer includes at least one scanning unit and a first inverter, wherein the at least one scanning unit includes: Switching circuit; a buffer, wherein an input end of the buffer is electrically connected to the switch circuit, and an output end of the buffer is electrically connected to the scan line; and a first pull-down transistor, wherein a control terminal of the first pull-down transistor is electrically connected to an output terminal of the first inverter, and a first terminal of the first pull-down transistor is electrically connected to the output terminal of the buffer, The input end of the first inverter is electrically connected to the shift register, and the input end or the output end of the first inverter is electrically connected to the switch circuit.

2. The electronic device according to claim 1, characterized in that: The switching circuit is a transmission gate circuit, and the electronic device also includes a second inverter, wherein the output end of the first inverter is electrically connected to the input end of the second inverter, and the output end of the second inverter is electrically connected to the first control end of the transmission gate circuit, wherein the output end of the first inverter is electrically connected to the second control end of the transmission gate circuit.

3. The electronic device according to claim 1, characterized in that: The switch circuit is an N-type transistor, wherein a control end of the N-type transistor is electrically connected to the shift register and the input end of the first inverter.

4. The electronic device according to claim 1, characterized in that: The switch circuit is a P-type transistor, wherein a control end of the P-type transistor is electrically connected to the shift register and the output end of the first inverter.

5. The electronic device according to claim 1, characterized in that: Also includes: A second pull-down transistor, wherein a control terminal of the second pull-down transistor is electrically connected to another scan line, and a first terminal of the second pull-down transistor is electrically connected to the scan line.

6. The electronic device according to claim 5, characterized in that: Also includes: a third pull-down transistor, wherein a control end of the third pull-down transistor is electrically connected to the other scan line, and a first end of the third pull-down transistor is electrically connected to the scan line, wherein the second pull-down transistor and the third pull-down transistor are respectively located at one end and the other end of the scan line and the other scan line.

7. The electronic device according to claim 1, characterized in that: The control signal received by the input end of the buffer via the switch circuit is in anti-phase with the scan signal output by the output end of the buffer.

8. A scanning driving circuit, characterized in that: include: Shift register; as well as A demultiplexer is electrically connected to the shift register, and the demultiplexer includes at least one scanning unit and a first inverter, wherein the at least one scanning unit includes: Switching circuit; a buffer, wherein an input end of the buffer is electrically connected to the switch circuit, and an output end of the buffer is electrically connected to the scan line; and a first pull-down transistor, wherein a control terminal of the first pull-down transistor is electrically connected to an output terminal of the first inverter, and a first terminal of the first pull-down transistor is electrically connected to the output terminal of the buffer, The input end of the first inverter is electrically connected to the shift register, and the input end or the output end of the first inverter is electrically connected to the switch circuit.

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