Apparatus and method for generating refresh addresses

Abstract

This application relates to apparatus and methods for generating refresh addresses. Apparatus and methods for computing target refresh addresses can include circuitry that can be used to compute victim line addresses that have a variety of spatial relationships with an aggressor line. The spatial relationship of the victim line addresses computed by the circuitry can be based at least in part on the state of a control signal provided to the circuitry. That is, the circuitry can be used to compute different victim line addresses by changing the state of the control signal.

Description

Technical Field

[0001] Embodiments of the present application relate to refreshing information in a memory, and more particularly, to an apparatus and method for generating refresh addresses. Background Art

[0002] Information can be stored as physical signals (e.g., charge on a capacitive element) on individual memory cells of a memory. The memory can be volatile, and the physical signals can decay over time (which can degrade or destroy the information stored in the memory cells). It may be necessary to periodically refresh the information in the memory cells, for example, by rewriting the information to restore the physical signals to their original values.

[0003] As the size of memory storage devices decreases, the density of memory cells increases significantly. An auto-refresh operation may be performed in which a sequence of memory cells is periodically refreshed. Repeated access to a particular memory cell or group of memory cells (often referred to as "row hammer") may result in an increased rate of data degradation in nearby memory cells. In addition to the auto-refresh operation, it may be necessary to identify and refresh memory cells affected by row hammer in a targeted refresh operation. Summary of the Invention

[0004] According to an embodiment of the present disclosure, a device is provided, and the device includes: a control signal generator circuit configured to provide a plurality of control signals; and a conversion circuit configured to receive a plurality of bits of an aggressor row address and the plurality of control signals, and provide a plurality of flip signals, wherein the plurality of flip signals indicate whether to flip individual bits of the plurality of bits of the aggressor row address to generate a plurality of bits of a victim row address, wherein the victim row address corresponds to a victim row having a spatial relationship with an aggressor row corresponding to the aggressor row address, the spatial relationship being indicated by the plurality of control signals.

[0005] According to an embodiment of the present disclosure, a method is provided, and the method includes: receiving a plurality of control signals, wherein logic states of the plurality of control signals indicate a spatial relationship between an aggressor row and a victim row; receiving a plurality of bits of an aggressor row address corresponding to the aggressor row; and generating a plurality of flip signals, wherein individual flip signals of the plurality of flip signals correspond to individual bits of the plurality of bits of the aggressor row address, and states of the individual flip signals of the plurality of flip signals indicate whether the individual bits of the plurality of bits of the aggressor row address should be flipped to generate a plurality of bits of a victim row address corresponding to the victim row having the spatial relationship indicated by the control signals.

[0006] According to embodiments of the present disclosure, an apparatus is provided and includes a scrambler circuit; and a plurality of row hammer count circuits configured to provide a corresponding plurality of most significant bits of a victim row address based at least in part on a carry bit, wherein the scrambler circuit is configured to provide a plurality of least significant bits of a victim row address corresponding to a victim row having a spatial relationship with an aggressor row, the spatial relationship indicated by a control signal, wherein the circuit is to generate all of the plurality of least significant bits of the victim row address regardless of the spatial relationship indicated by the control signal; and provide a carry bit based at least in part on the control signal. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor device according to embodiments of the present disclosure.

[0008] Figure 2 is a block diagram of a refresh control circuit according to embodiments of the present disclosure.

[0009] Figure 3 is a block diagram of a refresh address generator according to embodiments of the present disclosure.

[0010] Figure 4 is a block diagram showing a configuration of a target refresh address generator according to embodiments of the present disclosure.

[0011] Figure 5 is a circuit diagram of a configuration of a row hammer count circuit according to embodiments of the present disclosure.

[0012] Figure 6 is a block diagram of a scrambler circuit according to embodiments of the present disclosure.

[0013] Figure 7 is a circuit diagram of a conversion circuit according to embodiments of the present disclosure.

[0014] Figure 8 is a table illustrating logic states of a control signal for indicating a spatial relationship between an aggressor row and a victim row according to embodiments of the present disclosure.

[0015] Figure 9 is a table illustrating logic states of flip and carry signals for generating a target refresh address from a matching address according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] The following descriptions of certain embodiments are merely exemplary in nature and are in no way intended to limit the scope of the present disclosure or its application or use. In the following detailed description of embodiments of the systems and methods of the present invention, reference is made to the accompanying drawings that form a part hereof, and specific embodiments of the described systems and methods are shown by way of illustration in which they may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the systems and methods disclosed herein, and it is understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the sake of clarity, detailed descriptions of certain features will not be discussed when they would be obvious to those skilled in the art so as not to obscure the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be understood in a restrictive sense, and the scope of the present disclosure is limited solely by the appended claims.

[0017] Information in a volatile memory device can be stored in memory cells (e.g., as charge on a capacitive element) and can decay over time. Memory cells can be organized into rows (word lines) and columns (bit lines). To prevent information from being lost or corrupted due to this decay, the memory can implement a refresh operation. During a refresh operation, information can be rewritten to the memory cells of a word line to restore their initial state. Memory cells can be refreshed row by row (on a word line by word line basis). An auto-refresh operation can be performed on the word lines of the memory in a sequence so that the word lines of the memory are refreshed at a rate faster than the expected rate of data degradation over time.

[0018] Repeated accesses to a particular row of memory (e.g., an aggressor row) can result in an increase in the decay rate of rows proximate to the aggressor row (e.g., a victim row). These repeated accesses can be part of an intentional attack against the memory and / or can be due to the memory's 'natural' access pattern. The increase in the decay rate in the victim row can necessitate refreshing the victim row as part of a targeted refresh operation. The victim row can be a row immediately adjacent to the aggressor row or further away (+ / - 1), for example, adjacent to a row immediately adjacent to the aggressor row (+ / - 2).

[0019] Once the aggressor row has been identified, the row address of each victim row is determined. The victim row address for the victim row can then be used to perform a refresh operation on the victim row. Due to space limitations, layout limitations, and other factors in the memory, the physical row address may not correspond to the logical row address, sometimes referred to as address scrambling. Therefore, when the aggressor row is identified, a conversion (e.g., scrambling) between the physical address of the row and the logical address of the row is performed to determine the row address of the adjacent victim row. This may require complex circuitry including counters with latches or other components that require considerable layout space. Additionally or alternatively, time-consuming scrambling operations may be required, such as comparing the physical and / or logical addresses to a lookup table.

[0020] U.S. Patent No. 10,580,475, which is incorporated herein by reference for any purpose, describes a technique for calculating the victim row address of a victim row that is directly adjacent (+ / - 1) to an aggressor row. However, as the size of memory cells and the physical space between rows in a memory array continue to decrease, if a row hammer attack occurs, rows that are further away from the aggressor row (e.g., + / - 2, + / - 3, + / - 4, + / - 8) may become victim rows. Consequently, additional rows may need to be refreshed during a targeted refresh operation. Therefore, a technique for calculating the row address of a more distant victim row may be desirable.

[0021] The present disclosure is directed to apparatus, systems, and methods for calculating victim row addresses for victim rows having multiple spatial relationships to an aggressor row. The spatial relationship of the victim row to the aggressor row for which the victim row address is addressed can be calculated based, at least in part, on one or more control signals. In some embodiments, the same circuitry can be used to calculate different victim row addresses by varying the states of the control signals. The apparatus and methods disclosed herein can reduce or eliminate the need for scrambling circuitry with latches and / or other complex circuitry that can require more layout area. The apparatus and methods disclosed herein can reduce or eliminate the need for lookup tables and / or other scrambling operations that can require more computation time.

[0022] Figure 1 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0023] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. Figure 1 In the embodiment of the present invention, the memory array 118 is shown to include sixteen memory banks BANK0 to BANK15. More or fewer memory banks may be included in the memory array 118 of other embodiments. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL and / BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL and / BL. The selection of the word lines WL is performed by the row decoder circuit 108, and the selection of the bit lines BL and / BL is performed by the column decoder circuit 110. Figure 1In an embodiment of the present invention, row decoder circuit 108 includes a corresponding row decoder circuit for each memory bank, and column decoder circuit 110 includes a corresponding column decoder for each memory bank. Bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMPs). Read data from bit line BL or / BL is amplified by sense amplifier SAMP and transmitted to read / write amplifier 120 via a complementary local data line (LIOT / B), a transfer gate (TG), and a complementary main data line (MIOT / B). Conversely, write data output from read / write amplifier 120 is transmitted to sense amplifier SAMP via a complementary main data line MIOT / B, a transfer gate TG, and a complementary local data line LIOT / B, and is written into memory cell MC coupled to bit line BL or / BL.

[0024] The semiconductor device 100 may employ a plurality of external terminals, including: a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses and a CS signal; a clock terminal receiving clocks CK_t and CK_c; a data terminal DQ providing data; and a power supply terminal receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0025] The clock terminal is supplied with external clocks CK_t and CK_c, which are provided to input circuit 112. The external clocks may be complementary. Input circuit 112 generates an internal clock ICLK based on the CK_t and CK_c clocks. The ICLK clock is provided to command decoder circuit 110 and to internal clock generator 114. Internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time operations of various internal circuits. The internal data clock LCLK is provided to input / output circuit 122 to time the operation of circuits included in input / output circuit 122, for example, to a data receiver to time the receipt of write data.

[0026] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder circuit 108 and supplies the decoded column address YADD to the column decoder circuit 110. The address decoder 104 may also supply a decoded group address BADD, which may indicate the memory bank of the memory array 118 containing the decoded row address XADD and column address YADD. A command may be supplied to the C / A terminal. Examples of commands include access commands for accessing memory, such as commands for performing read operations and commands for performing write operations. The access command may be associated with one or more of the row address XADD, the column address YADD and / or the memory bank address BADD to indicate the memory cell to be accessed. In some embodiments, the command and / or address may be provided by a component external to the device 100, such as a Figure 1 Memory controller 101 is shown in communication with device 100.

[0027] Commands may be provided as internal command signals via command / address input circuit 102 to command decoder circuit 106. Command decoder circuit 106 includes circuitry to decode the internal command signals to generate various internal signals and commands for performing operations. For example, command decoder circuit 106 may provide row command signals to select word lines and column command signals to select bit lines.

[0028] Device 100 can receive an access command for performing a read operation. When the command is received and the bank address, row address, and column address are supplied in a timely manner, read data is read from the memory cell corresponding to the row address and column address in memory array 118. The command is received by command decoder circuit 106, which provides an internal command, so that the read data from memory array 118 is provided to read / write amplifier 120. The read data is output to the outside from data terminal DQ via input / output circuit 122.

[0029] The device 100 can receive an access command for performing a write operation. When the command is received and the bank address, row address, and column address are supplied with the command, write data supplied to the data terminals DQ is written to the memory cells in the memory array 118 corresponding to the row and column addresses. The command is received by the command decoder circuit 106, which provides an internal command to cause the write data to be received by the data receivers in the input / output circuit 122. A write clock can also be provided to the external clock terminals for timing the reception of the write data by the data receivers of the input / output circuit 122. The write data is supplied to the read / write amplifiers 120 via the input / output circuit 122 and through the read / write amplifiers 120 to the memory array 118 to be written into the memory cells MC.

[0030] As part of the self-refresh mode, the device 100 can also receive a command to cause it to perform one or more refresh operations. The device 100 can be placed in the refresh mode periodically. Thus, the refresh operations can be performed periodically whenever the memory device is in the refresh mode. In some embodiments, a refresh command can be issued to the memory device 100 externally. In some embodiments, components of the device can generate the refresh mode command periodically. In some embodiments, the refresh signal AREF can also be activated when an external signal indicates a refresh mode entry command (e.g., an external refresh command). The refresh signal AREF can be a pulsed signal that is activated when the command decoder circuit 106 receives a signal indicating entry into the self-refresh mode. The refresh signal AREF can be activated immediately after the command input, and thereafter can be activated for a desired internal timing cycle. In some embodiments, the refresh signal AREF can cause more than one refresh operation to be performed, which can be referred to as "multiple pump" refresh. In some embodiments, the refresh signal AREF can be active during the refresh mode. In some embodiments, the refresh signal AREF can be active during multiple refresh operations. The refresh signal AREF can be used to control the timing of the refresh operations during the refresh mode. A self-refresh exit command can stop the automatic activation of the refresh signal AREF and can return the device 100 to an idle state and / or resume other operations.

[0031] As used herein, activation of a signal can refer to any portion of a signal waveform to which a circuit responds. For example, if a circuit responds to a rising edge, a signal that switches from a low level to a high level can be an activation. One example type of activation is a pulse, in which a signal switches from a low level to a high level for a period of time, and then returns to a low level. This can trigger a circuit that responds to a rising edge, a falling edge, and / or a signal that is at a high logic level.

[0032] A refresh signal AREF is supplied to refresh control circuit 116. Refresh control circuit 116 supplies a refresh row address RXADD to row decoder circuit 108, which can refresh one or more word lines WL indicated by refresh row address RXADD. In some embodiments, refresh address RXADD can represent a single word line. In some embodiments, refresh address RXADD can represent multiple word lines, which can be refreshed sequentially or simultaneously by row decoder circuit 108. In some embodiments, the number of word lines represented by refresh address RXADD can vary from one refresh address to another. Refresh control circuit 116 can control the timing of refresh operations, and can generate and supply refresh address RXADD. Refresh control circuit 116 can be controlled, for example, by control signals provided by command decoder circuit 106 to vary the details of refresh address RXADD (e.g., how refresh addresses are calculated, the timing of refresh addresses, the number of word lines represented by addresses), or can operate based on internal logic.

[0033] Refresh control circuit 116 can selectively output a target refresh address (e.g., based on one or more victim addresses specified by an aggressor) or an automatic refresh address (e.g., from a sequence of automatic refresh addresses) as refresh address RXADD. Based on the type of refresh address RXADD, row decoder circuit 108 can perform a target refresh operation or an automatic refresh operation. Automatic refresh addresses can come from a sequence of addresses provided by a pump in response to activation of refresh signal AREF and / or generation of AREF. Refresh control circuit 116 can cycle through the sequence of automatic refresh addresses at a rate determined by AREF. In some embodiments, automatic refresh operations can generally occur with timing such that the sequence of automatic refresh addresses is cycled through so that, for a given word line, no information degradation is expected in the time between automatic refresh operations. In other words, automatic refresh operations can be performed so that each word line is refreshed at a rate faster than the expected rate of information decay.

[0034] Refresh control circuit 116 can also determine a target refresh address based on the access pattern of nearby addresses (e.g., aggressor addresses corresponding to aggressor rows) in memory array 118, which is an address that needs to be refreshed (e.g., a victim address corresponding to a victim row). Refresh control circuit 116 can use one or more signals of device 100 to calculate the target refresh address. For example, refresh address RXADD can be calculated based on row address XADD provided by address decoder 104.

[0035] According to embodiments of the present disclosure, refresh control circuitry 116 may calculate one or more victim addresses. The victim addresses may correspond to victim rows that have different spatial relationships with respect to the aggressor row. For example, the victim addresses may correspond to victim rows that are immediately adjacent to the aggressor row (+ / - 1) or to victim rows that are spatially further away from the aggressor row (e.g., + / - 2, + / - 3, + / - 4, etc.). The victim row addresses calculated for the aggressor row may be based at least in part on the states of one or more control signals. The control signals may be generated internally by refresh control circuitry 116 or another component of device 100 (e.g., command decoder circuitry 106) and / or externally (e.g., memory controller 101). In some embodiments, the circuitry used to calculate the victim addresses for the victim rows may be the same for all victim rows, regardless of their spatial relationship. In some embodiments, the states of one or more control signals may determine the spatial relationship of the victim row for which the victim row address is calculated. For example, the control signals may have one or more states for calculating + / - 2 victim row addresses and another one or more states for calculating + / - 4 victim row addresses. The calculated victim row address can be used as the target refresh address provided as RXADD during a target refresh operation.In some applications, using the same circuitry to calculate all victim row addresses can reduce the layout space required for the address calculation circuitry.

[0036] In some embodiments, the refresh control circuit 116 may sample the current value of the row address XADD provided by the address decoder 104 along the row address bus and determine a target refresh address based on one or more of the sampled addresses. The sampled addresses may be stored in a data storage unit of the refresh control circuit. When the row address XADD is sampled, the row address XADD may be compared with the stored address in the data storage unit. In some embodiments, the aggressor address may be determined based on the sampled address and / or the stored address. For example, the comparison between the sampled address and the stored address may be used to update a count value (e.g., an access count) associated with the stored address, and the aggressor address may be calculated based on the count value. The refresh address RXADD may then be used based on the aggressor address. In other embodiments, other techniques for determining the aggressor address may be used.

[0037] While generally speaking, the present disclosure relates to determining aggressor and victim word lines and addresses, it should be understood that, as used herein, an aggressor word line need not necessarily cause data degradation in adjacent word lines, and a victim word line need not necessarily experience such degradation. The refresh control circuitry 116 can use criteria to determine whether an address is an aggressor address, thereby capturing potential aggressor addresses rather than deterministically determining which addresses are causing data degradation in nearby victims. For example, the refresh control circuitry 116 can determine potential aggressor addresses based on access patterns to the addresses, and this criteria can include some addresses that are not aggressors while missing some addresses that are. Similar victim addresses can be determined based on which word lines are expected to be affected by the aggressor, rather than deterministically determining which word lines are experiencing increased data decay rates.

[0038] The refresh address RXADD may be provided with timing based on the timing of the refresh signal AREF. During the periodic refresh operation of the refresh mode, the refresh control circuit 116 may have time slots corresponding to the timing of AREF and may provide one or more refresh addresses RXADD during each time slot. In some embodiments, the target refresh address may be issued in a time slot that would otherwise be allocated to the auto-refresh address (e.g., "stolen") In some embodiments, certain time slots may be reserved for the target refresh address, and the refresh control circuit 116 may determine whether to provide the target refresh address, or not provide an address during that time slot, or instead provide the auto-refresh address during that time slot.

[0039] The refresh control circuit 116 can use a variety of methods to determine the timing of the target refresh operation. The refresh control circuit 116 can have a periodic target refresh operation during the refresh mode, where the refresh control circuit 116 performs an automatic refresh operation and a target refresh operation based on a periodic schedule (e.g., by providing the target refresh address as the refresh address RXADD). For example, after entering the refresh mode, the refresh control circuit 116 can perform a certain number of automatic refresh operations and then perform (e.g., steal) a certain number of target refresh operations. For multi-pump refresh operation, each time the active refresh signal AREF is received, the refresh control circuit 116 can perform M different refresh operations by providing M different refresh addresses RXADD. The refresh control circuit 116 can have a fixed mode in which some pumps are assigned to automatic refresh operations and some pumps are assigned to target refresh operations.

[0040] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder circuit 108, the internal voltages VOD and VARY are mainly used in the sense amplifier SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.

[0041] The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input / output circuit 122 so that power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0042] Figure 2 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure. In some embodiments, the refresh control circuit 216 may be included in Figure 1 216. Certain internal components and signals of the refresh control circuit 216 are shown to illustrate the operation of the refresh control circuit 216. Dashed line 218 is shown to indicate that in some embodiments, each of the components (e.g., refresh control circuit 216 and row decoder 208) may correspond to a specific bank of memory, and these components may be repeated for each of the banks of memory. Thus, there may be multiple refresh control circuits 216 and row decoders 208. For the sake of brevity, only the components for a single bank will be described.

[0043] DRAM interface 226 may represent one or more components that provide signals to components of a memory bank. In some embodiments, DRAM interface 226 may represent a device coupled to a semiconductor memory device (e.g., Figure 1 In some embodiments, DRAM interface 226 may represent, for example, a memory controller (e.g., memory controller 101) of device 100. Figure 1Components such as the command address input circuit 102, the address decoder 104 and / or the command decoder 106 of the DRAM interface 226. The DRAM interface 226 can provide a row address XADD, a refresh signal AREF, and access signals such as an activation signal ACT and a precharge signal Pre. The refresh signal AREF can be a periodic signal that indicates when an auto-refresh operation occurs. The access signals ACT and Pre can typically be provided together with the row address XADD as part of the access operation. The activation signal ACT can be provided to activate a given bank of the memory. The precharge signal Pre can be provided to precharge a given bank of the memory. The row address XADD can be a signal containing multiple bits (which can be transmitted serially or in parallel) and can correspond to a specific row of activated memory banks.

[0044] The refresh control circuit 216 may include a sampling timing circuit 230, an aggressor detector circuit 232, a row hammer refresh (RHR) state control circuit 236, and a refresh address generator 234. The refresh control circuit 216 provides timing to the refresh addresses RXADD based on a refresh signal AREF, where some of the refresh addresses are based on the received row address XADD.

[0045] Aggressor detector circuit 232 can sample the current row address XADD in response to activation of sampling signal ArmSample. In some embodiments, the sampled address can be stored in aggressor circuit 232 and / or compared with a previously stored address. Aggressor detector circuit 232 can provide a matching address HitXADD based on the currently sampled row address XADD and / or a previously sampled row address. RHR state control circuit 236 can provide signal RHR to indicate that a row hammer refresh (e.g., a refresh of a victim row corresponding to an identified aggressor row) should occur. RHR state control circuit 236 can also provide internal refresh signal IREF to indicate that an auto-refresh should occur. In response to activation of RHR or IREF, refresh address generator 234 can provide a refresh address RXADD, which can be an auto-refresh address or one or more victim addresses corresponding to a victim row of the aggressor row corresponding to the matching address HitXADD. Row decoder 208 can perform a refresh operation in response to refresh address RXADD and row hammer refresh signal RHR. The row decoder 208 may perform an auto-refresh operation based on the refresh address RXADD and the internal refresh signal IREF. In some embodiments, the row decoder 208 may be included in the row decoder circuit 108.

[0046] In embodiments where row accesses are monitored by sampling (as opposed to monitoring every access operation), the sampling timing circuit 230 provides a sample preparation signal, ArmSample. Signal ArmSample can be a binary signal that can be at a high logic level (which can be represented by a first voltage, such as VDD) or at a low logic level (which can be represented by a second voltage, such as ground or VSS). Activation of ArmSample can be a 'pulse', where ArmSample rises to a high logic level and then returns to a low logic level. In some embodiments, the sampling timing circuit 230 can use one or more mechanisms to determine whether to provide activation of signal ArmSample regularly (e.g., non-randomly), randomly, semi-randomly, or pseudo-randomly. In some embodiments, the sampling timing circuit 230 can receive access signals ACT and Pre. In some embodiments, activation of signal ArmSample can be further based on signals ACT and Pre to ensure that each activation of signal ArmSample is associated with an access operation.

[0047] Aggressor detector circuit 232 may receive row address XADD from DRAM interface 226 and signal ArmSample from sampling timing circuit 230. When DRAM interface 226 directs access operations (eg, read and write operations) to memory cell array (eg, Figure 1 When aggressor detector circuit 232 accesses a different row of memory cell array 118, row address XADD on row address bus 232 may change. Whenever aggressor detector circuit 232 receives activation (e.g., a pulse) of signal ArmSample, aggressor detector circuit 232 may sample the current value of XADD. In some embodiments, aggressor detector circuit 232 may provide the current sampled value of XADD as match address HitXADD.

[0048] In some embodiments, in response to activation of signal ArmSample, aggressor detector circuit 232 may determine whether one or more rows are aggressor rows based on the sampled row address XADD and may provide the identified aggressor row as a matching address HitXADD. As part of this determination, aggressor detector circuit 232 may record (e.g., by latching and / or otherwise storing) the current value of XADD in response to activation of signal ArmSample. The current value of XADD may be compared with previously recorded addresses in aggressor detector circuit 232 (e.g., addresses stored in a latch / register) to determine access patterns of the sampled addresses over time. If aggressor detector circuit 232 determines that an address (which, in some embodiments, may be a current address or a previously stored address) is an aggressor address, the identified aggressor row may be provided as a matching address HitXADD. In some embodiments, the matching address HitXADD may be provided in response to signal ArmSample. In some embodiments, the matching address (eg, aggressor address) HitXADD may be stored in a latch circuit for later retrieval by the refresh address generator 234 when the refresh address generator 234 determines that a matching address is needed.

[0049] In one example embodiment, to determine whether the current row address XADD is an aggressor address, a sampled value of the current row address XADD may be stored (e.g., latched in a latch circuit). Activation of ArmSample may also cause the aggressor detector circuit 232 to compare the current sampled row address XADD with a previously stored address in the aggressor detector circuit 232. If the current row address XADD matches the stored address, the current row address XADD may be provided as a matched address HitXADD.

[0050] In another example embodiment, the aggressor detector circuit 232 may store the values ​​of the sampled addresses in a register and may have a counter associated with each stored address. When ArmSample is activated, if the current row address XADD matches one of the stored addresses, the counter value may be incremented. In response to the activation of ArmSample, the aggressor detector circuit 232 may provide the address associated with the highest value counter as the matching address HitXADD. Other methods of identifying aggressor addresses may be used in other examples.

[0051] In embodiments where every row access command is monitored, sampling timing circuit 230 may be omitted. In these embodiments, aggressor detector circuit 232 may perform the above functions in response to the ACT / Pre signal rather than the ArmSample signal.

[0052] The RHR state control circuit 236 can receive a refresh signal AREF and provide a row hammer refresh signal RHR. The refresh signal AREF can be generated periodically and can be used to control the timing of refresh operations. The memory device can perform a sequence of auto-refresh operations in order to periodically refresh the rows of the memory device. The RHR signal can be generated in order to indicate that the device should refresh a particular target row (e.g., a victim row) rather than an address from the auto-refresh address sequence. The RHR state control circuit 236 can use internal logic to provide the RHR signal. In some embodiments, the RHR state control circuit 236 can provide the RHR signal based on certain activations of AREF (e.g., every 4 activations of AREF, every 1 or 2 pumps of a double pump refresh operation). The RHR state control circuit 236 can also provide an internal refresh signal IREF, which can indicate that an auto-refresh operation should occur. In some embodiments, the signals RHR and IREF can be generated such that they are not active at the same time (e.g., both are not at a high logic level at the same time).

[0053] In some embodiments, the refresh control circuit 216 can perform multiple refresh operations in response to an activation of the refresh signal AREF. For example, each time the refresh signal AREF is received, the refresh control circuit 216 can perform M different refresh operations by providing M different refresh addresses RXADD. Each refresh operation can be referred to as a ‘pump.’ In some embodiments, the refresh control circuit 216 can have a fixed pattern in which some pumps are assigned to auto-refresh operations and some pumps are assigned to target refresh operations. For example, in some embodiments, for a double pump refresh operation, the RHR state control circuit 236 can activate the row hammer refresh signal RHR for a first pump and activate the internal refresh signal IREF for a second pump. Thus, in some embodiments, RHR and / or IREF can be referred to as pump signals for a multi-pump refresh operation. In some embodiments, the refresh control circuit 216 can dynamically determine whether a given pump is associated with an auto-refresh operation, a target refresh operation, or no refresh operation.

[0054] The refresh address generator 234 can receive the row hammer refresh signal RHR, the internal refresh signal IREF, and the matching address HitXADD. The matching address HitXADD can represent the aggressor row. The refresh address generator 234 can determine the location of one or more victim rows based on the matching address HitXADD and provide associated addresses (e.g., victim row addresses, target refresh addresses) as refresh addresses RXADD when the signal RHR indicates a target refresh operation. In some embodiments, the victim rows can include rows that are physically adjacent to the aggressor row (e.g., HitXADD+1 and HitXADD-1). In some embodiments, the victim rows can also include rows that are physically adjacent to the physically adjacent rows of the aggressor row (e.g., HitXADD+2 and HitXADD-2). Alternative or additional relationships between victim rows and the identified aggressor row can be used in other instances. For example, HitXADD + / - 3, HitXADD + / - 4, and / or other victim rows can also or alternatively be refreshed.

[0055] In some embodiments, which victim rows are used to provide target refresh addresses (e.g., HitXADD + / - 2, HitXADD + / - 3, etc.) can be based on certain activation counts of the RHR signal. For example, the refresh address generator 234 can provide victim row addresses corresponding to HitXADD+1 and HitXADD-1 every other RHR signal activation, and sequentially provide victim row addresses corresponding to more distant victim rows during the remaining RHR activations (e.g., HitXADD + / - 2 after every other HitXADD + / - 1, HitXADD + / - 3 after every other HitXADD + / - 2, etc.). In some embodiments, which victim rows are refreshed can be based at least in part on a predetermined sequence programmed into the refresh address generator 234. In some embodiments, the sequence can be hard-coded (e.g., fuse / anti-fuse), or can be configurable by one or more components of the DRAM interface 226 (e.g., a mode register write command or other write command). In some embodiments, which victim rows are refreshed can be based on signals and / or commands received from the DRAM interface 226 (not shown) associated with the active AREF signal. The calculation of target refresh addresses will be described in more detail with reference to the following figures. Figure 2

[0056] ​Refresh address generator 234 can determine a value of refresh address RXADD based on row hammer refresh signal RHR. In some embodiments, refresh address generator 234 can provide one of an automatic refresh address sequence when internal refresh signal IREF is active. Refresh address generator 234 can provide a target refresh address, such as a victim address, as refresh address RXADD when signal RHR is active. In some embodiments, refresh address generator 234 can count activations of signal RHR and can provide victim lines closer to a victim address (e.g., HitXADD + / - 1) more frequently than victim lines further away from the victim address (e.g., HitXADD + / - 2).

[0057] Row decoder 208 can perform one or more operations on a memory array (not shown) based on received signals and addresses. For example, in response to activation signal ACT and row address XADD (and IREF and RHR at a low logic level), row decoder 208 can direct one or more access operations (e.g., read operations) to the specified row address XADD. In response to RHR signal being active, row decoder 208 can refresh refresh address RXADD.

[0058] Figure 3 is a block diagram of a refresh address generator according to embodiments of the present disclosure. In some embodiments, refresh address generator 334 can be used to implement refresh address generator 234. Refresh address generator 334 can include target refresh address generator 342, automatic refresh (AREF) address generator 344, and multiplexer (MUX) 346.

[0059] Target refresh address generator 342 receives a match address HitXADD, which can correspond to a victim row address, and a row hammer refresh RHR signal. The match address can be received from a victim detector circuit, such as victim detector circuit 232, and the RHR signal can be received from an RHR state control circuit, such as RHR state control circuit 236. Based at least in part on match address HitXADD, target refresh address generator 342 can calculate one or more target refresh addresses TXADD, which can correspond to victim word lines of victim word lines associated with match address HitXADD.

[0060] The physical address of a row may not be equal to the logical address of a row in a memory device. Therefore, as will be described in more detail with reference to the following figures, the target refresh address generator 342 may need to perform a conversion between physical addresses and logical addresses to determine the address of the victim row corresponding to the aggressor row matching the address HitXADD. In some embodiments, a known logical relationship between physical and logical row addresses may be employed to calculate the victim row address from the aggressor row address using logic circuitry rather than a scrambling conversion operation (e.g., a lookup table, a latched counter circuit, etc.).

[0061] AREF address generator 344 generates an auto-refresh address AXADD in response to an internal refresh signal IREF, which may be provided by an RHR state control circuit, such as RHR state control circuit 236. The auto-refresh address AXADD may be part of a sequence of addresses to be refreshed as part of an auto-refresh operation. In some embodiments, the auto-refresh address AXADD may correspond to multiple word lines. Refresh address generator 344 may update the current auto-refresh address AXADD to the next address in the sequence in response to an active IREF signal. AREF address generator 344 is also provided with a row hammer refresh signal RHR from the state control circuit. When the RHR signal is active, AREF address generator 344 may stop updating the auto-refresh address AXADD. As described herein, since an active RHR signal indicates that a target refresh operation is to be performed rather than an auto-refresh operation, this allows the auto-refresh operation to be paused while a target refresh is being performed and to be resumed when the RHR signal is inactive.

[0062] MUX 346 receives the target refresh address TXADD and the auto-refresh address AXADD and outputs one of them as the refresh address RXADD to a row decoder (not shown), such as row decoder 208 and / or 108. MUX 346 may receive the IREF and / or RHR signals to control the output of MUX 346. In some embodiments, when the RHR signal is active and / or the IREF signal is inactive, MUX 346 may provide the target refresh address TXADD as RXADD. In some embodiments, when the RHR signal is inactive and / or the IREF signal is active, MUX 346 may provide the auto-refresh address AXADD.

[0063] Figure 4is a block diagram showing a configuration of a target refresh address generator according to an embodiment of the present disclosure. In some embodiments, a target refresh address generator 442 may be used to implement the target refresh address generator 342. The target refresh address generator 442 receives the HitXADD address A11:A0 and provides the target refresh address TXADD address AO11:AO0. The target refresh address generator 442 may include a scrambler circuit 450 that provides the AO3:AO0 address bits and further includes a series of row hammer count circuits 448(0) to 448(7) that provide the AO11:AO4 address bits, respectively. The scrambler circuit 450 may receive a row hammer refresh signal RHR (e.g., from the RHR state control circuit 236) and provide the AO3:AO0 bits and a carry bit COUT3 based on the A3:A0 address bits. Although the example shown depicts a refresh address having 12 bits, in other embodiments, addresses including more or fewer bits may be used. Furthermore, in other embodiments, the scrambler circuit 450 may receive a different number of least significant bits.

[0064] Row hammer count circuits 448(0) through 448(7) may each receive corresponding address bits A11:A4; a carry-out bit COUT from a preceding row hammer count circuit 448(0) through 448(7), wherein row hammer count circuit 448(0) receives carry bit COUT3 from scrambler circuit 450; and an inverted A0 bit (via inverter 440) as a polarity bit P indicating addition or subtraction. Each row hammer count circuit 448(0) through 448(7) may calculate a corresponding one of the AO11:AO4 signals based on the received input signals.

[0065] Figure 5is a circuit diagram of a configuration of a row hammer count circuit according to an embodiment of the present disclosure. Row hammer count circuit 548 may be used to implement one or more of row hammer count circuits 448(0) to 448(7). Row hammer count circuit 548 may be used to calculate address output bit AOX based on address bit AX (where X is an integer from 4 to 11), carry out bit COUTX-1 from a previous row hammer counter circuit or scrambler circuit (e.g., scrambler circuit 450), and polarity bit P. Row hammer count circuit 548 includes an XOR logic gate 513 configured to receive address bit AX and carry out bit COUTX-1 (and the AX bit inverted via inverter 510 and the COUTX-1 bit inverted via inverter 511) to provide address output bit AOX using XOR logic. The row hammer count circuit 548 further includes an XOR logic gate 514 configured to receive the polarity bit and the carry output COUTX-1 bit (and the polarity bit inverted via inverter 512 and the COUTX-1 bit inverted via inverter 511) to provide input to a NAND logic gate 515 using XOR logic. The NAND logic gate 515 can use NAND logic on the output of the XOR logic gate 514 and the inverted COUTX-1 bit to provide the COUTX bit. Table 501 depicts the logical combinations of AX, COUTX-1, and the polarity bit, and the resulting AX and COUTX bits.

[0066] return Figure 4 , the output address bits AO11:AO0 can be provided to the downstream circuit as the target refresh address TXADD for the target refresh operation, which can mitigate the impact of self-hammering attacks. Figure 4 and 5 The logic circuits depicted in are exemplary, and other logic circuits may be implemented without departing from the scope of the present disclosure.

[0067] Figure 66 is a block diagram of a scrambler circuit according to an embodiment of the present disclosure. In some embodiments, scrambler circuit 650 may be used to implement scrambler circuit 450. Scrambler circuit 650 may include control signal generator circuit 652, conversion circuit 654, and address output circuit 656. Scrambler circuit 650 may be used to provide the least significant bits (e.g., 4 bits in the example shown) of a target refresh address TXADD, which may be a row address associated with a victim row of an aggressor row (e.g., an aggressor row determined by aggressor detector circuit 232). Control signal generator circuit 652 may provide a control signal to indicate the spatial relationship between the aggressor row and the victim row for which the target refresh address should be calculated. Based at least in part on the spatial relationship indicated by the control signal, conversion circuit 654 may provide a toggle signal to indicate how to convert the aggressor row address into one or more target refresh addresses. Address output circuit 656 may invert one or more bits of the aggressor row address based on the toggle signal and output the target refresh address.

[0068] The control signal generator circuit 652 may receive a row hammer refresh signal RHR, which may be provided by an RHR state control circuit, such as the RHR state control circuit 236. The control signal generator circuit 652 may provide various control signals P1 through P3. The logic states of the control signals P1 through P3 may be based, at least in part, on the RHR signal. The control signals P1 through P3 may indicate the physical relationship of one or more victim rows to the aggressor row for which the target refresh address (e.g., the victim row address) is to be calculated. For example, different combinations of the logic states of the control signals P1-3 may correspond to different physical relationships (e.g., HitXADD+ / -1, HitXADD+ / -2, HitXADD+ / -3, ..., HitXADD+ / -8).

[0069] In some embodiments, the control signal generator circuit 652 may include internal logic to determine which spatial relationship is indicated via the control signals P1 to P3. For example, a counter circuit may count the activations of the RHR signal, and the control signals P1 to P3 may be repeatedly incremented through all possible combinations when the count of the counter circuit changes. In another example, additional counters and / or other logic may be used so that some spatial relationships are indicated by the control signals P1 to P3 more frequently than other spatial relationships. For example, the target refresh address corresponding to HitXADD+ / -1 may be calculated more frequently than HitXADD+ / -2, which in turn may be calculated more frequently than HitXADD+ / -3. These examples are provided for illustration only, and the present disclosure is not limited to these examples. Alternatively, the states of P1 to P3 may be set at least in part based on a signal provided by another component (not shown), such as a command decoder, such as the command decoder 106.

[0070] In some embodiments, the states of P1 to P3 may indicate whether the first target refresh address or the second target refresh address is calculated. For example, the states of P1 to P3 may indicate whether HitXADD+4 or HitXADD-4 should be calculated. In some embodiments, the control signal generator circuit 652 may further receive the least significant bit A0 of the matching address HitXADD. The states of the control signals P1 to P3 may also be based at least in part on the state of A0. In some embodiments, when A0=0 (for example, HitXADD is an even address), P1 to P3 may indicate that HitXADD+Y is calculated first and HitXADD-Y is calculated second (where Y is a natural number). That is, the +Y address is the first address and -Y is the second address. When A0=1 (for example, HitXADD is an odd address), P1 to P3 may indicate that HitXADD-Y is calculated first and HitXADD+Y is calculated second. Similarly, -Y is the first address and +Y is the second address.

[0071] The conversion circuit 654 may receive the three least significant bits A3:A0 of the matching address HitXADD. The bits A3:A0 may be received from an aggressor row detector circuit, such as the aggressor row detector circuit 236. The conversion circuit 654 may receive control signals P1 through P3. Based at least in part on the control signals P1 through P3 and the bits A3:A0, the conversion circuit 654 may provide a carry bit COUT and rollover signals M1 through M3. The carry bit COUT may be provided to one or more row hammer counter circuits, such as the row hammer counter circuit 548 and / or the row hammer counter circuits 448(0)-(7), as described with reference to FIG. Figures 4 to 5 The description calculates the high order bits of the target refresh address. The carry bit COUT may take into account the special case, for example, at A3:A0=0000, where HitXADD-1 cannot be further decreased by one without involving the next high order bit (eg, A4).

[0072] Flip signals M1-M3 may indicate whether a bit of the matching address HitXADD should be flipped (eg, changed from '1' to '0' or from '0' to '1') to generate a victim row address for a victim row address having a physical relationship with the aggressor row indicated by control signals P1-P3.

[0073] In some embodiments, the inversion signals M1 to M3 may correspond only to bits A1:A3, respectively. In some embodiments, an inversion signal for the least significant bit A0 may not be necessary because the row addresses of two victim rows (e.g., victim rows on either side of the aggressor row) that have the same spatial relationship to the aggressor row may be known based on the spatial relationship. For victim rows that have an odd relationship (e.g., + / -1, + / -3) to the aggressor row, A0 may be inverted for the victim row address. For victim rows that have an even relationship (e.g., + / -2, + / -4), A0 may not be inverted.

[0074] The address output circuit 656 may receive the toggle signals M1-M3 and the matching address HitXADD. Based at least in part on the toggle signals M1-M3, the address output circuit 656 may invert one or more bits A3:A1 of the matching address HitXADD to generate the target refresh address TXADD (e.g., convert HitXADD to TXADD). In some embodiments, the address output circuit 656 may invert individual bits A3:A1 by performing an XOR operation on the bits using the corresponding toggle signals M1-3. However, in other embodiments, other logic may be used to invert the appropriate bits A3:A1 based on the toggle signals M1-M3. The target refresh address TXADD may correspond to one or more victim rows having the same spatial relationship as the aggressor row corresponding to the matching address HitXADD. The spatial relationship may be the spatial relationship indicated by the control signals P1-P3.

[0075] In some embodiments, the same circuitry can be used to generate the target refresh address TXADD regardless of the matching address HitXADD and the spatial relationship of the victim row corresponding to TXADD. In some embodiments, this can reduce circuit layout requirements where separate circuitry is used to calculate victim row addresses associated with victim rows that have a different spatial relationship to the aggressor row associated with the matching address HitXADD.

[0076] Figure 7 is a circuit diagram of a conversion circuit according to an embodiment of the present disclosure. In some embodiments, conversion circuit 754 may be used to implement conversion circuit 654. Figure 7 The logic circuits depicted in FIG. 7 are exemplary, and other logic circuits may be implemented without departing from the scope of the present disclosure. Conversion circuit 754 may be used to generate a signal for generating a target refresh address corresponding to a victim row having a different spatial relationship to an aggressor row. In some applications, conversion circuit 754 may eliminate the need for scrambling conversions using latch circuits and / or conversion table lookups. In some applications, this may save layout area and / or reduce target refresh address calculation time.

[0077] exist Figure 7In the example shown in FIG, the conversion circuit 754 can receive the least significant bits of the match address HitXADD, bits A0:A3. The match address HitXADD can be received from an aggressor row detector circuit, such as the aggressor row detector circuit 232, and corresponds to the aggressor row. Although four bits are received in the example shown, more or fewer least significant bits can be received in other examples.

[0078] exist Figure 7 In the example shown in , the control conversion circuit 754 may receive one or more control signals, control signals P1 to P3. The control signals may be received from a control signal generator circuit, such as the control signal generator circuit 652. The control signals P1 to P3 may indicate a victim row for which a row address (e.g., a target refresh address) should be generated. The victim rows may be indicated based on their spatial relationship to the aggressor rows (e.g., + / - 1, + / - 2, + / - 3, + / - 4, + / - 5, + / - 6, + / - 7, and / or + / - 8), where + / - 1 indicates a victim row that is immediately adjacent to the aggressor row, and + / - 8 indicates a victim row where there are seven other rows physically located between the victim row and the aggressor row. Although in Figure 7 In the example shown in FIG, three control signals and eight spatial relationships may be indicated by the control signals, but in other examples, more or fewer control signals and / or spatial relationships may be indicated in other examples.

[0079] The control signals P1 to P3 may further indicate whether a +Y victim row address or a -Y victim row address should be calculated. Figure 7 In the example shown in , Y is an integer between 1 and 8. In some embodiments, control signals P1 to P3 can change with one or more pumps of a refresh operation, such as for a pump associated with a target refresh operation. Thus, P1 to P3 can indicate that +Y should be calculated in response to a pump, and -Y should be calculated in response to another pump. In some embodiments, when bit A0 is '0' (e.g., HitXADD is an even address), +Y can be calculated first, and when bit A1 is '1' (e.g., HitXADD is an odd address), -Y can be calculated first. In some embodiments, in addition to +Y or -Y, P1 to P3 can also change the value of Y between pumps. In some embodiments, signals other than the pumps can trigger changes in P1 to P3 during a refresh operation.

[0080] The conversion circuit 754 may provide a signal indicating whether a bit of the HitXADD address should be flipped (eg, changed from '1' to '0' or vice versa) to generate a flip signal for the victim row address indicated by the control signal. Figure 7In the example shown in FIG, three toggle signals M1 through M3 are provided, which in some embodiments may correspond to bits A1:A3. However, in other examples, more or fewer toggle signals may be provided. In some embodiments, the least significant bit A0 may not require a toggle signal to generate the target refresh address because it is known whether A0 is toggled based on the spatial relationship as previously discussed. The toggle signals may be provided to an address output circuit, such as address output circuit 656, which may toggle bits A1:A3 of HitXADD as indicated by the toggle signals M1 through M3 (e.g., by XORing the bits with the toggle signals) to generate the least significant bit of the target refresh address.

[0081] The conversion circuit 754 may provide a carry bit COUT that may indicate whether a high order bit is needed to generate the target refresh address for the victim row. The carry bit may be provided to one or more row hammer counters, such as row hammer counter circuits 448(0) to 448(7) and / or 548. The carry bit COUT may be used to generate the most significant bit of the target refresh address, as shown in FIG. Figure 4 and 5 described.

[0082] Portion 701 of conversion circuit 754 may receive address bits A0 through A3 and control signals P1 through P3 and provide various intermediate signals to other portions of conversion circuit 754. XOR circuit 702 may receive bits A0 and A2, and XOR circuit 704 may receive bit A3 and control signal P1. The outputs of XOR circuits 702 and 704 may be provided to XOR circuit 716, which may generate signal SCR1. Inverter circuit 720 may receive SCR1 and provide signal SCR1F.

[0083] XOR circuit 706 can receive bit A1 and bit A2. The output of XOR circuit 706 can be provided to inverter circuit 718. Inverter circuit 708 can control signal P2 and provide signal P2F. NAND circuit 722 can receive the output of inverter circuit 718 and signal P2F. The output of NAND circuit 722 can be received by inverter circuit 724, which can provide signal SCR2A1. NAND circuit 730 can also receive the output of inverter circuit 718 and control signal P3. The output of NAND circuit 730 can be provided to inverter circuit 734, which can provide signal SCR2A2.

[0084] NAND circuit 726 can receive the output of XOR circuit 706 and signal P2F. The output of NAND circuit 726 can be provided to inverter circuit 728, which can provide signal SCR2B1. NAND circuit 732 can receive the output of XOR circuit 706 and control signal P3. The output of NAND circuit 732 can be provided to inverter circuit 736, which can provide signal SCR2B2.

[0085] Inverter circuit 710 may receive control signal P3 and output signal P3F. NAND circuit 712 may receive control signals P2 and P3. The output of NAND circuit 712 may be provided to inverter circuit 714, which may provide signal SCR3.

[0086] The intermediate signals SCR1, SCR1F, SCR2A1, SCR2A2, SCR2B1, SCR2B2, SCR3, P2F, and P3F generated by portion 701 may be used by other portions of conversion circuit 754 to generate flip signals M1 through M3 and a carry bit COUT.

[0087] Portion 703 of conversion circuit 754 may receive the intermediate signals from portion 701 to generate flip signals M1 through M3. In some embodiments, flip signal M1 may indicate whether bit A1 of HitXADD should be flipped, flip signal M2 may indicate whether bit A2 should be flipped, and flip signal M3 may indicate whether bit A3 should be flipped. In some examples, when M1 through M3 are logic high ('1'), they indicate that the corresponding bits A1 through A3 should be flipped, and when M1 through M3 are logic low ('0'), they indicate that the corresponding bits A1 through A3 should not be flipped (e.g., remain the same).

[0088] XOR circuit 738 may receive signals SCR1 and P2F, and NOR circuit 740 may receive the output of XOR circuit 738 and signal SCR2B1. NOR circuit 744 may receive the output of NOR circuit 740 and signal SCR2B2. NOR circuit 756 may receive the output of NOR circuit 744 and signal SCR3. The output of NOR circuit 756 may be provided to inverter circuit 758, which may provide inverted signal M1.

[0089] NOR circuit 742 may receive signals SCR1 and SCR2A1. NOR circuit 746 may receive the output of NOR circuit 742 and signals SCR2A2 and SCR3. The output of NOR circuit 746 may be provided to inverter circuit 748, which may provide an inverting signal M2.

[0090] NOR circuit 743 may receive signals SCR1F and SCR2B1. NOR circuit 750 may receive the output of NOR circuit 743 and signals SCR2B2 and SCR3. The output of NOR circuit 743 may be provided to inverter 752, which may provide an inverting signal M3.

[0091] In some embodiments, the toggle signals M1 - M3 generated by portion 703 may be provided to an address output circuit, such as address output circuit 656 .

[0092] Portion 705 of conversion circuit 754 may receive address bits A1 and A2 and control signals P2 and P3, as well as an intermediate signal from portion 701 to generate a carry bit, COUT. NOR circuit 760 may receive bits A1 and A2, and NAND circuit 762 may receive signals P2F and P3F. The outputs of NOR circuit 760 and NAND circuit 762 may be provided to NOR circuit 774. Inverter circuit 764 may receive bit A2, and NAND circuit 766 may receive control signal P2 and signal P3F. The outputs of inverter circuit 764 and NAND circuit 766 may be provided to NOR circuit 776. NAND circuit 768 may receive bits A1 and A2, and NAND circuit 770 may receive signal P2F and control signal P3. The outputs of NAND circuit 768 and NAND circuit 770 may be received by NOR circuit 778.

[0093] NOR circuit 780 may receive the outputs of NOR circuit 774, NOR circuit 776, and NOR circuit 778. XOR circuit 772 may receive signal SCR1 and bit A2. NAND circuit 782 may receive the outputs of NOR circuit 780 and XOR circuit 772. The output of NAND circuit 782 may be provided to inverter circuit 784, which may provide a carry bit, COUT. In some embodiments, carry bit, COUT, may be provided to one or more row hammer counter circuits (e.g., row hammer counter circuits 448(0)-448(7) and / or 548) for use in generating more significant bits of the target refresh address.

[0094] Figure 8 is a table illustrating logic states of control signals for indicating a spatial relationship between an aggressor row and a victim row according to an embodiment of the present disclosure. In some embodiments, the states of P1 through P3 indicated in table 800 can be used to cause a conversion circuit, such as conversion circuit 754, to provide a signal indicating which bits, if any, of the aggressor row address should be flipped to generate a target refresh address corresponding to a victim row having the indicated spatial relationship with the aggressor row.

[0095] The top row of table 800 indicates the spatial relationship of the victim row to the aggressor row (e.g., + / - 1, + / - 2, + / - 3, etc.). The second row of table 800 indicates the calculated first victim row address or second victim row address. As mentioned, in some embodiments, if the aggressor row address is even, the +Y address is calculated first and the -Y address is calculated second, and if the aggressor row address is odd, the -Y address is calculated first and the +Y address is calculated second. Therefore, the "1st" and "2nd" columns of table 800 do not necessarily always correspond to +Y or -Y, or vice versa. The last three rows of table 800 indicate the logic states of control signals P1 to P3 to be provided to the conversion circuit to cause the conversion circuit to generate target refresh addresses for different spatial relationships.

[0096] Note that for the first calculated address, the states of P1 through P3 for + / -1 and + / -2 are the same as the states of P1 through P3 for + / -3. Similarly, the states of P1-3 for the second addresses calculated for + / -3 and + / -4 are the same, and the states of P1-3 for the first addresses calculated for + / -4 and + / -5 are the same. Table 800 also shows additional redundancies in the states of P1 through P3 (e.g., identical logic state combinations) for different address calculations for other spatial relationships. These redundancies are due to the fact that, as previously mentioned, P1 through P3 may only cause the generation of toggle signals corresponding to bits A1:A3 (e.g., toggle signals M1 through M3), but not A0. Therefore, for these pairs of spatial relationships, the only difference in the conversions of the two spatial relationships is the least significant bit A0 and / or the high-order bits (e.g., A4:A11).

[0097] Figure 9 Tables 900, 905, and 910 illustrate the logic states of toggle and carry signals used to generate a target refresh address from a matching address, according to an embodiment of the present disclosure. Tables 900, 905, and 910 may indicate the logic states of toggle signals M1, M2, and M3, respectively, to indicate whether the least significant bits of the aggressor row address should be toggled to generate a target refresh address for a victim row having a particular spatial relationship to the aggressor row associated with the aggressor row address. In some embodiments, toggle signals M1 through M3 may be provided by a conversion circuit, such as conversion circuit 754. Toggle signals M1 through M3 may be provided to an address output circuit, such as address output circuit 656, which may toggle bits of the aggressor row address to generate the least significant bits of the target refresh address as indicated by toggle signals M1 through M3.

[0098] Table 915 may indicate the logic state of a carry bit COUT that may be used to generate the high-order bits of the target refresh address. In some embodiments, the carry bit may be provided by a conversion circuit such as conversion circuit 754.

[0099] exist Figure 9In the example shown in FIG. 9 , the top row of tables 900 , 905 , 910 , and 915 indicates address bits A3:A0 of the aggressor row address (e.g., matching address HitXADD). In some embodiments, bits A3:A0 may be the least significant bits of the aggressor row address. As previously explained with reference to table 800 , the second row indicates the spatial relationship of the victim row corresponding to the target refresh address and the aggressor row corresponding to the aggressor row address. Also as explained above with reference to table 800 , the third row indicates whether the bit corresponds to the calculated first target refresh address or the second target refresh address. The first row (the fourth row) below rows 1 / 2 indicates the state of A3, as indicated by the label in the top row. The remaining rows indicate the state of toggle signals M1 through M3 (for tables 900 , 905 , and 910 ) or the state of carry bit COUT (for table 915).

[0100] As can be inferred from the states of the flip signals M1 to M3 shown in Tables 900, 905, and 910, certain logical relationships between the physical addresses and logical addresses of the word lines can be employed so that the same circuit can be used to generate victim row addresses for victim rows having a range of physical relationships with the aggressor row (e.g., + / - 1 to + / - 8 in the example shown). For example, as indicated by the flip signals M1 to M3, for the second target refresh address and both target refresh addresses for + / - 7, all bits A1:A3 are flipped, and for the first address of + / - 1, bits A1:A3 are not flipped. In another example, for certain spatial relationships and / or first or second addresses, the flip signals M1 and M3 are inversions of each other. In another example, for certain spatial relationships and / or first or second addresses, the flip signals M1 and M3 are inversions of M2. Additionally, it can be observed that the flip signals M1 to M3 themselves span various symmetries and / or inversions of the spatial relationships and / or first and second addresses, which can also be used to provide circuitry for generating target refresh addresses. Thus, while Figure 7 The conversion circuit shown in is one implementation, but other circuits may be used to implement the conversion circuit by using the various relationships between the row addresses shown in tables 900 , 905 , and / or 910 .

[0101] The apparatus and methods disclosed herein can calculate victim row addresses having various spatial relationships to an aggressor row based on one or more control signals. In some embodiments, the same circuit can be used to calculate different victim row addresses by changing the state of the control signals. The apparatus and methods disclosed herein can reduce or eliminate the need for descrambling circuits with latches and / or other complex circuits that may require more layout area. The apparatus and methods disclosed herein can reduce or eliminate the need for lookup tables and / or other descrambling operations that may require more computation time.

[0102] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with or separated from one or more other examples, embodiments, and / or processes and / or performed in a separate device or device portion according to the systems, devices, and methods of the present invention.

[0103] Finally, the above discussion is intended to be merely illustrative of the present invention system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present invention system has been described in detail with reference to exemplary embodiments, it should be understood that numerous modifications and alternative embodiments may be devised by those skilled in the art without departing from the broader and intended spirit and scope of the present invention system as set forth in the appended claims. The specification and drawings are, therefore, to be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A memory device comprising: a control signal generator circuit configured to provide a plurality of control signals; and a conversion circuit configured to receive a plurality of bits of the aggressor row address and the plurality of control signals and provide a plurality of flip signals, wherein the plurality of flip signals indicate whether to flip individual bits of the plurality of bits of the aggressor row address to generate a plurality of bits of the victim row address, The victim row address corresponds to a victim row having a spatial relationship with an aggressor row corresponding to the aggressor row address, the spatial relationship being indicated by the plurality of control signals.

2. The memory device of claim 1 , further comprising an address output circuit configured to flip the individual ones of the plurality of bits of the aggressor row address as indicated by the plurality of flip signals and provide the plurality of bits of the victim row address.

3. The memory device of claim 2 , further comprising: a scrambling circuit, wherein the scrambling circuit comprises the control signal generator circuit, the conversion circuit, and the address output circuit; and One or more row hammer counter circuits, Wherein the address output circuit provides the least significant bit of the victim row address, and the one or more row hammer counter circuits provide the one or more most significant bits of the victim row address.

4. The memory device of claim 3 , wherein the conversion circuit is further configured to provide a carry bit to the one or more row hammer counter circuits based at least in part on the aggressor row address, and the one or more most significant bits of the victim row address are based at least in part on the carry bit.

5. The memory device of claim 1, further comprising a refresh state control circuit configured to provide a row hammer refresh signal, and logic states of the plurality of control signals are based at least in part on the row hammer refresh signal.

6. The memory device of claim 1, wherein the plurality of bits of the aggressor row address and the plurality of bits of the victim row address are least significant bits. 7 . The memory device of claim 1 , wherein a number of the plurality of control signals is one less than a number of the plurality of bits of the aggressor row address.

8. A method for generating a refresh address, comprising: receiving a plurality of control signals, wherein logic states of the plurality of control signals indicate a spatial relationship between an aggressor row and a victim row; receiving a plurality of bits of an aggressor row address corresponding to the aggressor row; and A plurality of toggle signals are generated, wherein individual ones of the plurality of toggle signals correspond to individual ones of the plurality of bits of the aggressor row address, and states of the individual ones of the plurality of toggle signals indicate whether the individual ones of the plurality of bits of the aggressor row address should be toggled to generate a plurality of bits of a victim row address corresponding to the victim row having the spatial relationship indicated by the control signal.

9. The method of claim 8, further comprising flipping the individual ones of the plurality of bits of the aggressor row address as indicated by corresponding flip signals to generate the plurality of bits of the victim row address.

10. The method of claim 9, wherein flipping the individual ones of the plurality of bits of the aggressor row address comprises XORing the individual ones of the plurality of bits of the aggressor row address with the corresponding flip signal.

11. The method of claim 8, further comprising generating a carry bit, wherein a logic state of the carry bit is based at least in part on the plurality of control signals and the plurality of bits of the aggressor row address.

12. The method of claim 11, further comprising generating at least one additional bit of the victim row address based at least in part on the carry bit.

13. The method of claim 8, further comprising: Receive active hammer refresh signal; and The logic states of the plurality of control signals are set at least in part in response to the row hammer refresh signal.

14. The method of claim 13, further comprising setting the logic states of the plurality of control signals based at least in part on a logic state of a least significant bit of the plurality of bits of the aggressor row address.

15. The method of claim 13, further comprising: receiving a second-action hammer refresh signal; and The logic states of the plurality of control signals are changed in response to the second active row hammer refresh signal to generate a plurality of bits corresponding to a second victim row address of a second victim row.

16. The method of claim 15 , wherein the victim row is located on a first side of the aggressor row and the second victim row is located on a second side of the aggressor row, and wherein the victim row address is calculated before the second victim row address when a least significant bit of the plurality of bits of the aggressor row address is an even number, and the second victim row address is calculated before the victim row address when the least significant bit of the plurality of bits of the aggressor row address is an odd number.

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