Full bit line sensing to determine word line to memory hole shorts

Abstract

The present invention provides apparatus and techniques for detecting short circuits in memory devices and specifically detecting word line to channel short circuits and short circuits between bit line contacts at the top of a NAND string. The short circuit detection operation includes a channel pre-cleaning phase that discharges the channel of a non-shorted NAND string while boosting the bit line of the shorted NAND string, followed by a bit line pre-charge phase that boosts the bit line of the non-shorted NAND string, followed by a bit line discharge phase that discharges the bit line of the non-shorted NAND string, followed by a sensing phase that identifies the shorted NAND string as being in a programmed state or a non-conductive state.

Description

Background Art

[0001] The present technology relates to the operation of memory devices.

[0002] Semiconductor memory devices have become increasingly common in a variety of electronic devices. For example, nonvolatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0003] Charge storage materials (such as floating gates) or charge trapping materials can be used in such memory devices to store charge representing a data state. For example, the charge trapping materials can be arranged vertically in a three-dimensional (3D) stacked memory structure. An example of a 3D memory structure is a bit cost scalable (BiCS) architecture, which includes a stack of alternating conductive and dielectric layers.

[0004] Memory devices include memory cells that may be arranged in series into NAND strings, for example, where select gate transistors are provided at the ends of the NAND strings to selectively connect the channels of the NAND strings to source lines or bit lines. However, there are various challenges in operating such memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A is a block diagram of an example memory device.

[0006] Figure 1B yes Figure 1A 1 is a block diagram of an arrangement of a memory device 100 in which control circuitry 130 on a first die 130a communicates with a memory structure 126 on a separate second die 126b.

[0007] Figure 2 It is shown Figure 1A 0046] A block diagram of one embodiment of a sensing block 51 is shown.

[0008] Figure 3 Shows Figure 1A 0047] An exemplary implementation of a power control circuit 115 for providing voltage to a block of memory cells in a plane.

[0009] Figure 4 is a perspective view of an exemplary memory die 400 in which memory cell blocks are arranged in respective planes P0 and P1.

[0010] Figure 5 Shows Figure 1A 0046. Example transistor 520 in memory structure 126 of FIG.

[0011] Figure 6 Shows Figure 4FIG. 1 is an exemplary cross-sectional view of a portion of block B0-0 including NAND strings 700n and 710n.

[0012] Fig. 7A Shown with Figure 4 and Figure 6 An exemplary view of NAND strings in a consistent block B0-0.

[0013] Figure 7B Shows Fig. 7A An exemplary view of the NAND strings in block B0-0 of FIG.

[0014] Figure 7C Shown with Figure 7B An example of a consistent first failure mode, where in SB0, NAND string 700b has a word line to channel short path 801, and a NAND string cluster 800 including NAND strings 700b-700d are shorted to each other.

[0015] Fig.7D Shown with Figure 7B An example of a consistent second failure mode where in SB0, NAND string 700b has a word line to channel short path 801, and a NAND string cluster 810 including NAND strings 700b-700d in SB0 and NAND string 710a in SB1 are shorted to each other.

[0016] Fig. 7E Shown with Figure 4 and Figure 7B An example of a consistent third failure mode where in SB3 of B0-0, NAND string 730b has a word line to channel short path 831, and a NAND string cluster 819 including NAND strings 730b-730d in SB3 and NAND string 740 in SB0 of adjacent block B0-1 are shorted to each other.

[0017] Figure 7F Shown with Figure 7B An example of a consistent fourth failure mode where in SB0, NAND string 700a has a word line to channel short path 802, and a NAND string cluster 810 including NAND strings 700b-700d in SB0 and NAND string 710a in SB1 are shorted to each other.

[0018] Figure 7G Shown with Figure 7B An example of a consistent fifth failure mode, where in SB0, the NAND string 700a has a word line to channel short path 802, and no NAND strings are shorted to each other.

[0019] Figure 8A flow chart showing an exemplary process for performing a short circuit detection operation is shown. Figure 7C to Figure 7G The failure scenario is consistent.

[0020] Fig.9A A group of NAND strings and associated circuits are shown when there is a word line short circuit to a memory hole and a bit line contact short circuit to a bit line contact, which is configured similar to Figure 8 The same is true for the trench pre-cleaning phase of step 821 .

[0021] Fig. 9B A set of NAND strings and associated circuitry are shown, configured with Figure 8 The bit line precharge phase of step 822 is consistent with that of step 822, and follows Fig.9A Configuration.

[0022] Fig. 9C A set of NAND strings and associated circuitry are shown, configured with Figure 8 The bit line discharge phase of step 823 is consistent with that of step 824 and follows Fig. 9B Configuration.

[0023] Fig.9D A set of NAND strings and associated circuitry are shown, configured with Figure 8 The sensing phase of step 824 is consistent with that of step 824, and follows Fig. 9C Configuration.

[0024] Fig.9E A group of NAND strings and associated circuits are shown when there is a word line short circuit to a memory hole but there is no bit line contact short circuit to a bit line contact, which is configured similar to Figure 8 The same is true for the trench pre-cleaning phase of step 821 .

[0025] Fig.9F A set of NAND strings and associated circuitry are shown, configured with Figure 8 The bit line precharge phase of step 822 is consistent with that of step 822, and follows Fig.9E Configuration.

[0026] Figure 9G A set of NAND strings and associated circuitry are shown, configured with Figure 8 The bit line discharge phase of step 823 is consistent with that of step 824 and follows Fig.9F Configuration.

[0027] Figure 9H A set of NAND strings and associated circuitry are shown, configured with Figure 8 The sensing phase of step 824 is consistent with that of step 824, and follows Figure 9G Configuration. BLC and XXL transistors

[0028] Fig.10 Shown with Figure 8 and 9A to 9H Consistent voltage signal.

[0029] Fig.11A A first configuration of the block during manufacturing is shown, which results in Figure 6 and FIG. 7C to FIG. 7G A consistent short circuit where alternating layers are formed in the stack.

[0030] Fig. 11B A second configuration of a block during fabrication is shown, wherein non-uniform etching of the top dielectric layer 1105 results in over-etched dielectric regions 1105b and corner-etched dielectric regions 1105a having corners 1105a1 .

[0031] Fig. 11C A third configuration of the block in process is shown, wherein layer 1120 is deposited in memory holes 1110 - 1113 , filler 1121 is deposited, and mask layer 1122 is deposited.

[0032] Fig.11D A fourth configuration of the block during fabrication is shown, wherein the mask layer 1122 is patterned to form voids 1122v1 - 1122v4 .

[0033] Fig.11E A fifth configuration of the block in process is shown, in which a patterned mask layer 1122 is used to etch through the filler 1121 and portions of layer 1120 at the bottom of the memory hole.

[0034] Figure 11F1 A sixth configuration of the block in process is shown, wherein an additional polysilicon layer 1120a and dielectric material 1139 are deposited.

[0035] Fig.11F2 A seventh configuration of the block in process is shown, wherein the dielectric material is etched back to form dielectric cores 1140 - 1143 in the memory holes, followed by deposition of a doped silicon capping layer 1145 .

[0036] Fig.11G An eighth configuration of the block is shown during fabrication, wherein the doped silicon capping layer 1145 is etched to form bitline contacts 1145a1 , 1145a3 , 1145b , and 1145c .

[0037] Fig.11H A ninth configuration of the block in fabrication is shown, wherein vias 1151 - 1154 are formed over bitline contacts 1145a1 , 1145a3 , 1145b , and 1145c , respectively, and a bitline 1155 is formed over the via in insulating layer 1150 .

[0038] Fig. 12A The configuration of the blocks in another example of the manufacturing process is shown, which results in the same configuration as in FIG. 6 and FIG. FIG. 7C to FIG. 7G Consistent short circuit.

[0039] Fig. 12B Shows that following Fig. 12A A block configuration of a configuration in which a dielectric material 1250 and an additional polysilicon layer 1220a are deposited.

[0040] Fig. 12C Shows that following Fig. 12B A block configuration of a configuration in which the dielectric material is etched back. DETAILED DESCRIPTION

[0041] The present invention describes apparatus and techniques for detecting shorts in memory devices and in particular detecting word line to channel shorts and shorts between bit line contacts at the top of a NAND string.

[0042] In some memory devices, memory cells are joined to each other, such as in NAND strings in blocks or sub-blocks. Each NAND string includes: a plurality of memory cells connected in series between one or more drain-end select gate transistors (referred to as SGD transistors) located at the drain end of the NAND string connected to a bit line; and one or more source-end select gate transistors (referred to as SGS transistors) located at the source end of the NAND string or other memory strings or connected groups of memory cells connected to a source line. The select gate transistor is also referred to as a select gate. In addition, the memory cells can be arranged with a common control gate line (e.g., word line) that serves as a control gate. A set of word lines extends from the source side of the block to the drain side of the block. For example, see Fig. 7A The memory cells may be connected in other types of strings, and may be connected in other ways as well.

[0043] In a 3D memory structure, memory cells may be arranged in stacked vertical NAND strings in a substrate, where the stack includes alternating conductive and dielectric layers. Conductive layers containing, for example, tungsten serve as word lines connected to the memory cells. Each NAND string is formed by etching a memory hole in the stack and depositing various layers along the walls of the memory hole. For example, these layers may include Figure 6 The blocking oxide layer 663 (e.g., aluminum oxide), the charge trapping layer 664 (e.g., silicon nitride or other nitride), the tunnel layer 665 (e.g., gate oxide), and the channel layer 660 (e.g., comprising polysilicon) in the NAND string 700n in FIG. The materials provide a MANOS or metal (W)-aluminum oxide (Al2O3)-nitride (Si3N4)-oxide (SiO2)-silicon (Si) structure.

[0044] Each NAND string may have a pillar shape intersecting a word line to form a memory cell. A source terminal 700s of the NAND string is connected to the substrate 611, and a drain terminal 700d of the NAND string is connected to the bit line BL0.

[0045] Memory structures (including those described above) are widely used for storage and data transmission in, for example, consumer devices, enterprise systems, and industrial applications due to their non-volatile capabilities, affordability, high storage density, and access speed. However, due to process defects such as the presence of degassing and contamination particles of fluorine (F), various short circuit failure modes may occur. F degassing typically results in a short circuit between the bottom word line and the word line of the stack and the channel. NAND with a short circuit is referred to as a leaky NAND string.

[0046] In contrast, contamination particles typically cause a short circuit between the word line of the top word line of the stack and the channel (see, e.g. Figure 6 In particular, contamination particles can cause uneven deposition and etching of the top of the stack. This can cause etching particles to refract from irregular surfaces and damage a portion of the layer in the memory hole, such as during etching of the memory hole to open a path at the bottom of the memory hole. For example, see Fig.11E This results in a word line to channel short circuit path 1128, also referred to as a word line to memory hole short circuit path. In addition, the bottom of the memory hole can remain unopened (see Fig.11E The bottom of the memory holes 1130 and 1131 in the stack are not connected to the channel, so that the source line is not connected to the channel. The uneven etching of the top of the stack also causes shorts between the bit line contacts at the top of the NAND string (see Figure 6 A short circuit path 684 between the bit line contacts 680 and 681 in the doped silicon region 683 in the Fig.11G A short circuit path 1129 is formed between the bit line contacts 1145a1 and 1145a3 in the doped silicon region 1145a in the semiconductor device.

[0047] Shorts can interfere with program operations by pulling down the word line voltage, and in erase operations by pulling up the word line voltage. This can lead to block-level failures. Shorts typically occur in clusters of adjacent NAND strings (see Figure 7C NAND string cluster 800 in.

[0048] One method is to test the current in a NAND string that is expected to be in an erased (conductive) state. If the current is below a specified level, the NAND string is considered to be in a programmed (non-conductive) state. However, this method cannot distinguish between a word line short circuit with a channel and an unopened memory hole. For example, since a NAND string with an unopened memory hole does not affect other NAND strings, the NAND string can be adjusted based on the bit ignore setting during programming verification and reading. On the other hand, a NAND string with a word line short circuit with a channel affects other NAND strings because the word line voltage is affected. Therefore, when there is an adjustable unopened memory hole, a column or other NAND string group can be considered unavailable. This results in a yield loss.

[0049] Another method involves using voltage sensing. The bit line precharge voltage and the sensing voltage of the sensing circuit can be adjusted separately. When the sensing voltage is reduced, the NAND string with an open or unopened memory hole is sensed as being in an erased state (1 bit), while the NAND string with a word line shorted to the channel is sensed as being in a programmed state (0 bit). However, when sensing the bit line in the presence of a short circuit, the adjacent bit line is set to ground during the odd / even bit line sensing process. This method does not work when there is a NAND string cluster with a short circuit, in which case the voltage of the sensing bit line can be pulled down to the adjacent bit line by the short circuit. In this case, the sensing bit line / NAND string is sensed as being in an erased state.

[0050] The technology provided herein solves the above and other problems. In one aspect, a short circuit detection operation is performed on multiple NAND strings (such as a block or a portion of a block). The operation includes a channel pre-cleaning phase, followed by a bit line pre-charge phase, followed by a bit line discharge phase, followed by a sensing phase. See, e.g. Figure 8 Flowchart and Fig.10 The channel pre-cleaning phase discharges the channel of the non-short NAND string while boosting the bit line of the short NAND string. The bit line pre-charge phase boosts the bit line of the non-short NAND string while maintaining the boost on the bit line of the short NAND string. The bit line discharge phase discharges the bit line of the non-short NAND string while maintaining the boost on the bit line of the short NAND string. The sensing phase identifies the short NAND string as being in a programmed state or a non-conductive state based on its relatively low current, and identifies the non-short NAND string as being in an erased state or a conductive state based on its relatively high current. If the count of the short NAND string exceeds a threshold number, multiple NAND strings are considered to be excessively leaky and therefore unusable. If the count does not exceed a threshold number, multiple NAND strings are considered to be usable, and adjustments can be made to the leaking NAND strings.

[0051] The sensing phase may advantageously sense all bit lines and their corresponding NAND strings simultaneously in full bit line sensing. Full bit line sensing involves sensing a group of adjacent bit lines simultaneously. For example, this may be all or a portion of the bit lines of a block of memory cells.

[0052] This technique can be used to detect different types of shorting scenarios. In one scenario, the NAND string has a word line to channel short, but no bit line contact to bit line contact short. In another scenario, the NAND string has a word line to channel short and a bit line contact to bit line contact short.

[0053] These and other features are discussed further below.

[0054] Figure 1A 1 is a block diagram of an exemplary memory device. A memory device 100, such as a non-volatile memory system, may include one or more memory dies 108. The memory die 108 or chip includes a memory structure 126 of memory cells, such as an array of memory cells, a control circuit 110, and a read / write circuit 128. The memory structure 126 is addressable by word lines via a row decoder 124 and is addressable by bit lines via a column decoder 132. The read / write circuit 128 includes a plurality of sense blocks 51, 52, ..., 53 (sense circuits) and allows pages of memory cells to be read or programmed in parallel. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. The controller may be located on a die 127 separate from the memory die 108. Commands and data are transmitted between a host 140 and the controller 122 via a data bus 120, and between the controller and one or more memory dies 108 via a line 118.

[0055] The memory structure may be 3D. The memory structure may include one or more arrays of memory cells comprising a 3D array. The memory structure may include a monolithic 3D memory structure in which multiple memory levels are formed above (rather than in) a single substrate (such as a wafer) without an intermediate substrate. The memory structure may include any type of non-volatile memory formed monolithically in one or more physical levels of an array of memory cells having active areas disposed above a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0056] Control circuit 110 cooperates with read / write circuit 128 to perform memory operations on memory structure 126, and includes state machine 112, on-chip address decoder 114, and power control circuit 115. Storage area 113 may be provided, for example, for operating parameters and software / code. In one embodiment, state machine 112 can be programmed by software. In other embodiments, state machine 112 does not use software and is implemented entirely in hardware (e.g., circuit).

[0057] An on-chip address decoder 114 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. Power control circuitry 115 controls the power and voltages provided to the word lines, select gate lines, bit lines, and source lines during memory operations. The power control module may include drivers for the word lines, SGS and SGD transistors, and source lines. See also Figure 3 In one approach, the sense block may include a bit line driver.

[0058] In some implementations, some of the components may be combined. In various designs, one or more of the components other than the memory structure 126 (alone or in combination) may be considered to be at least one control circuit that is configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuit may include any one of the control circuit 110, the state machine 112, the decoders 114 and 132, the power control circuit 115, the sensing blocks 51, 52...53, the read / write circuit 128, the controller 122, etc., or a combination thereof. The state machine is a circuit that can control the operation of the control circuit 110. In some embodiments, the state machine is implemented or replaced by a microprocessor, a microcontroller, and / or a RISC processor.

[0059] The off-chip controller 122 (in one embodiment, a circuit) may include a processor 122e, a memory such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct many read errors. RAM 122b may be, for example, a DRAM that stores uncommitted data. During programming, a copy of the data to be programmed is stored in RAM 122b until programming is successfully completed. In response to successful completion, the data is erased from RAM 122b and committed or released to the memory cell block. RAM 122b may store data for one or more word lines.

[0060] A memory interface 122d may also be provided. A memory interface that communicates with the ROM, RAM, and processor is a circuit that provides an electrical interface between the controller and the memory die. For example, the memory interface may change the format or timing of a signal, provide a buffer, isolate surges, latch I / O, etc. The processor may issue commands to the control circuit 110 (or any other component of the memory die) via the memory interface 122d.

[0061] The memory in the controller 122, such as ROM 122a and RAM 122b, includes code such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein. Alternatively or in addition, the processor may access code from a subset 126a of the memory structure, such as a reserved area of ​​memory cells in one or more word lines.

[0062] For example, the controller can use code to access the memory structure, such as for programming operations, read operations and erase operations. The code may include boot code and control code (e.g., a set of instructions). The boot code is a software that initializes the controller and enables the controller to access the memory structure during the boot or startup process. The controller can use code to control one or more memory structures. When powered on, the processor 122e takes out the boot code from ROM 122a or subgroup 126a for execution, and the boot code initializes the system components and loads the control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes a driver that performs basic tasks, such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0063] A controller, such as RAM 122b and / or control circuit 110, may store parameters indicating the expected number of failed bits in a block. These parameters may include, for example, the number of bits per cell stored in the memory cell, the portion of the word lines programmed in a block or sub-block, the portion of the sub-block programmed in a block, the strength of the ECC process used to store and read data in the block, the duration of the pre-read voltage pulse (if used), and read accuracy, such as bit line or word line voltage stabilization time and number of sensing passes.

[0064] Generally speaking, the control code may include instructions for performing the functions described herein, including the steps of the flowcharts discussed further below, and provide voltage waveforms, including those discussed further below.The control circuitry may be configured to execute instructions for performing the functions described herein.

[0065] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smart phone, a tablet computer, a digital camera) that includes one or more processors, one or more processor-readable memory devices (RAM, ROM, flash memory, hard drive, solid-state memory), and the one or more processor-readable memory devices store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0066] In addition to NAND flash memory, other types of non-volatile memory may be used.

[0067] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (DRAM) or static random access memory (SRAM) devices, non-volatile memory devices, such as resistive random access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM) and magnetoresistive random access memory (MRAM), and other semiconductor elements capable of storing information. Each type of memory device can have a different configuration. For example, a flash memory device can be configured in a NAND configuration or a NOR configuration.

[0068] The memory device may be formed of passive components and / or active components in any combination. By way of non-limiting example, passive semiconductor memory components include ReRAM device components, which in some embodiments include resistivity switching storage elements, such as antifuses or phase change materials, and optional steering elements, such as diodes or transistors. In addition, by way of non-limiting example, active semiconductor memory components include EEPROM and flash memory device components, which in some embodiments include components containing charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0069] Multiple memory elements may be configured so that they are connected in series or so that each element may be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically includes memory elements connected in series. A NAND string is an example of a group of transistors connected in series that includes a memory cell and a SG transistor.

[0070] A NAND memory array can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements can be configured so that each element can be accessed individually, such as a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0071] Semiconductor memory elements located in and / or on a substrate may be arranged in three dimensions.

[0072] The memory elements may be arranged in a single memory device level in an ordered array, such as in multiple rows and / or columns. However, the memory elements may be arranged in an unconventional configuration or a non-orthogonal configuration. The memory elements may each have two or more electrodes or contact lines, such as a bit line and a word line.

[0073] The 3D memory array is arranged so that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in x, y and z directions, wherein the z direction is substantially perpendicular to the major surface of the substrate and the x and y directions are substantially parallel to the major surface of the substrate).

[0074] As a non-limiting example, a 3D memory array can be arranged as a plurality of vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y-direction), wherein each column has a plurality of memory elements. Other configurations of three-dimensional memory elements can also constitute a 3D memory array.

[0075] In a 3D NAND memory array, memory elements may be coupled together to form vertical NAND strings that span multiple horizontal memory device levels. Other 3D configurations are envisioned, with some NAND strings containing memory elements in a single memory level and other strings containing memory elements that span multiple memory levels. The 3D memory array may also be designed in a NOR configuration and in a ReRAM configuration.

[0076] Typically, in a monolithic 3D memory array, one or more memory device levels are formed above a single substrate. Optionally, a monolithic 3D memory array may also have one or more memory layers at least partially located within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic 3D array, the layers of each memory device level that constitutes the array are typically formed on the layers of the underlying memory device level of the array. However, the layers of adjacent memory device levels of a monolithic 3D memory array may be shared between memory device levels or have intermediate layers between memory device levels.

[0077] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to implement functions such as programming and reading. The associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0078] Figure 1B yes Figure 1A 1 is a block diagram of an arrangement of a memory device 100, wherein a control circuit 130 on a first die 130a communicates with a memory structure 126 on a separate second die 126b. The control circuit may communicate with the memory structure and die 126b via a memory interface 131 (e.g., similar to memory interface 122d). Examples of memory interfaces (I / Fs) include JEDEC's common flash memory interface. The control circuit may be configured to issue one or more commands via the memory interface to perform operations to distinguish shorted NAND strings from non-shorted NAND strings. These commands may involve executing steps of a flowchart discussed further below, and providing voltage waveforms discussed further below.

[0079] The techniques described herein may be implemented with a control die 130a coupled to one or more memory dies 126b, where the memory die includes a memory structure 126 and the control die includes control circuitry 130 representing all or a subset of the peripheral circuitry of the memory structure. The control circuitry may be located on the same die as the plurality of memory cells, or on a different die than the plurality of memory cells.

[0080] For example, the memory structure may include non-volatile memory cells. In some embodiments, the memory die and the control die are combined. The control circuit 130 may include a group of circuits that perform memory operations (e.g., write, read, erase, etc.) on the memory structure. The control circuit may include a state machine 112, a storage area 113, an on-chip address decoder 114, and a power control circuit 115. In another embodiment, a portion of the read / write circuit 128 is located on the control die 130a, and another portion of the read / write circuit is located on the memory die 126b. For example, the read / write circuit may include a sense amplifier. The sense amplifier may be located on the control die and / or the memory die.

[0081] The term "memory die" may refer to a semiconductor die that includes non-volatile memory cells for storing data. The term "control circuit die" may refer to a semiconductor die that includes control circuits for performing memory operations on the non-volatile memory cells on the memory die. Typically, many semiconductor dies are formed from a single semiconductor wafer.

[0082] Figure 2 It is shown Figure 1A 1 is a block diagram of one embodiment of a sense block 51 of FIG. A single sense block 51 is divided into one or more core portions called sense circuits SC0-SC3 or sense amplifiers and a common portion called management circuit 190. In one embodiment, each sense circuit is connected to a corresponding bit line and NAND string, and the common management circuit 190 is connected to a group of multiple (e.g., four or eight) sense circuits. Each sense circuit in the group communicates with an associated management circuit via a data bus 176. Thus, there are one or more management circuits that communicate with the sense circuits of a group of storage elements (memory cells).

[0083] SC0 can operate during a programming cycle to provide a precharge / program-inhibit voltage to an unselected bit line or a program-enable voltage to a selected bit line. The unselected bit lines are connected to unselected NAND strings and unselected memory cells therein. The unselected memory cells can be memory cells in an unselected NAND string, where the memory cells are connected to a selected or unselected word line. The unselected memory cells can also be memory cells in a selected NAND string, where the memory cells are connected to an unselected word line. The selected bit line is connected to a selected NAND string and a selected memory cell therein.

[0084] SC0 may also operate during a verify test in a programming loop to sense a memory cell to determine whether it has completed programming by reaching an assigned data state (e.g., as indicated by its Vth exceeding the verify voltage for the assigned data state). SC0 ​​may also operate during a read operation to determine the data state to which a memory cell has been programmed. SC0 ​​may also operate in an erase operation during a verify test to determine whether a plurality of memory cells have a Vth below the verify voltage. The sensing circuit may perform sensing by determining whether a conduction current in a connected bit line is above or below a predetermined threshold level. This indicates whether the Vth of the memory cell is below or above the word line voltage, respectively.

[0085] The sensing circuit may also be operated as described initially in a short circuit detection operation. In one approach, the sensing circuit determines the level of current in a NAND string in a selected sub-block of a block. In another approach, the sensing circuit determines the level of current flowing in common in a plurality of NAND strings (one NAND string in each sub-block of the block), where the NAND strings are connected to a common bit line. NAND strings having a current below a threshold are considered to be in a programmed state or a non-conductive state, and NAND strings having a current above a threshold are considered to be in an erased state or a conductive state. For example, as Fig.10As shown, the voltage Vsense of the sense node 171 may be monitored during the sense phase of operation to determine whether it drops below a threshold Vt at a sense time ts.

[0086] Each sensing circuit is connected to a corresponding bit line via a set of transistors. Each bit line is in turn connected to a NAND string in one or more blocks. In one approach, each NAND string is also connected to multiple NAND strings in a block, for example, one NAND string in each sub-block of a block. For example, SC0 is connected to BL0 via a set of transistors 250, and BL0 is connected to NAND string 700n. The set of transistors 250 can also be considered as part of the sensing circuit. The set of transistors includes XXL transistor 252, and assuming that BLC transistor 255 and BLS transistor 256 are also turned on, the XXL transistor is turned on (set to a conductive state) by providing a conductive path between bit line BL0 and sensing circuit SC0 to allow sensing. Power source node 251 receives a voltage, and assuming that BLC transistor 255 and BLS transistor 256 are also turned on, the voltage can be connected to the bit line via BLX transistor 253 to charge the bit line. NLO transistor 254 provides a ground connection. In some configurations, the BLC transistor is a bit line clamp transistor configured to clamp the voltage of the bit line. The BLS transistor is a sense transistor that is turned on throughout the short circuit detection operation as described herein and during other sensing operations. The transistor may be, for example, an nMOSFET.

[0087] In general, the BLC transistor 255 has a control gate 58, a drain 57, and a source 59, and can operate as a pass gate or a bit line clamp. When the voltage at the control gate is sufficiently higher than the voltage on the drain, the transistor operates as a pass gate to pass the voltage at the drain to the bit line at the source 59 of the transistor. When the voltage at the control gate is lower than the voltage on the drain, the BLC transistor operates as a source follower to set or clamp the bit line voltage at Vcg-Vth, where Vcg is the voltage on the control gate 58, and Vth (e.g., 1V) is the threshold voltage of the transistor. This assumes that the source line is at 0V.

[0088] When the XXL transistor is turned on, SC0 can be connected to the drain 57 of the BLC transistor. During sensing, the sense node 171 is charged up to an initial voltage, such as 3V. The sense node is then connected to the bit line via the XXL, BLC, and BLS transistors, and the attenuation amount of the sense node is used to determine whether the memory cell or NAND string is in a conductive state or a non-conductive state. Specifically, the comparison circuit 175 determines the attenuation amount by comparing the sense node voltage with the threshold Vt during sensing. See Fig.10174. An exemplary sensing time ts in FIG. 175. If the sense node voltage decays below Vt, the memory cell or NAND string is in a conductive state and its Vth is considered to be equal to or lower than the word line voltage. If the sense node voltage does not decay below Vt, the memory cell or NAND string is in a non-conductive state and its Vth is considered to be higher than the word line voltage. For example, the sense node latch 172 is set to 1 or 0 by the comparison circuit 175 based on whether the memory cell is in a conductive (erased) state or a non-conductive (programmed) state, respectively. The data in the sense node latch can be a bit that is read by the processor 192 and used to update the trip latch 174. Subsequently, for the next programming cycle, the processor can use the bits in the trip latch and the assigned data states in the latches 194-197 to determine whether the memory cell and NAND string are selected or not selected for programming in the programming cycle, thereby passing the appropriate enable or inhibit bit line voltage to the bit line, respectively. Latches 194-197 may be considered data latches or user data latches because they store the data to be programmed into the memory cells.

[0089] The management circuit 190 includes a processor 192, four exemplary sets of data latches 194-197 for sensing circuits SC0-SC3, respectively, and an I / O interface 196 coupled between the data latch sets and the data bus 120. A set of three data latches can be provided for each sensing circuit, for example, including separate latches LDL, MDL, and UDL. In some cases, a different number of data latches can be used. In a three-bit per cell embodiment, LDL stores bits for lower page data, MDL stores bits for middle page data, and UDL stores bits for upper page data.

[0090] The processor 192 performs calculations such as determining the data stored in the sensed memory cells and storing the determined data in the set of data latches. Each set of data latches 194-197 is used to store data bits determined by the processor 192 during a read operation and to store data bits imported from the data bus 120 during a programming operation, which represents the write data to be programmed into the memory. The I / O interface 196 provides an interface between the data latches 194-197 and the data bus 120.

[0091] During read, the operation of the system is under the control of the state machine 112, which controls the supply of different control gate voltages to the addressed memory cells. As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense circuit may trip at one of these voltages and the corresponding output will be provided from the sense circuit to the processor 192 via the data bus 176. At this point, the processor 192 determines the resulting memory state by taking into account the trip event of the sense circuit and the information about the control gate voltage applied via input line 193 from the state machine. It then calculates the binary encoding of the memory state and stores the resulting data bits into the data latches 194-197.

[0092] Some specific implementations may include multiple processors 192. In one embodiment, each processor 192 will include an output line (not shown) so that each output line is connected with a wired or connection. A wired or connection or line can be provided by connecting multiple lines together at a node, wherein each line carries a high or low input signal from a corresponding processor, and if any of the input signals is high, the output of the node is high. In some embodiments, the output line is reversed before being connected to the wired or line. This configuration enables to quickly determine when the programming process is completed during the programming verification test, because the state machine receiving the wired or can determine when all the programmed bits have reached the desired level. For example, when each bit reaches its desired level, the logic zero of the bit will be sent to the wired or line (or data one is reversed). When all bits output data 0 (or data one is reversed), the state machine knows to terminate the programming process. Because each processor communicates with eight sensing circuits, the state machine needs to read the wired or line eight times, or logic is added to the processor 192 to accumulate the results of the relevant bit lines so that the state machine only needs to read the wired or line once. Similarly, by properly choosing the logic levels, the global state machine can detect when the first bit changes its state and change the algorithm accordingly.

[0093] During a program or verify operation of a memory cell, the data to be programmed (write data) is stored in the data latch set 194-197 from the data bus 120. During reprogramming, a corresponding set of data latches of a memory cell may store data indicating when to enable reprogramming of the memory cell based on the programming pulse magnitude.

[0094] Under the control of the state machine, the programming operation applies a series of programming voltage pulses to the control gate of the addressed memory cell. The amplitude of each voltage pulse can be gradually increased by one step from the previous programming pulse in the process, which is called incremental step pulse programming. Each programming voltage is followed by a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, the processor 192 monitors the read-back memory state relative to the desired memory state. When the two are consistent, the processor 192 sets the bit line to a program inhibit mode, such as by updating its latch. This prohibits further programming of the memory cell coupled to the bit line even if additional programming pulses are applied to its control gate.

[0095] Each group of data latches 194-197 can be implemented as a stack of data latches for each sensing circuit. In one embodiment, each sensing circuit SC0 has three data latches. In some specific implementations, the data latches are implemented as shift registers so that the parallel data stored therein is converted into serial data of the data bus 120, and vice versa. All data latches corresponding to the read / write block of the memory cell can be connected together to form a block shift register, so that the data block can be input or output by serial transmission. Specifically, the read / write circuit module group is adjusted so that its data latch group shifts data into or out of the data bus in sequence, just as they are part of the shift register of the entire read / write block.

[0096] The data latch indicates when the associated memory cell reaches certain milestones of the programming operation. For example, the latch can identify that the Vth of the memory cell is below a specific verification voltage. The data latch indicates whether the memory cell is currently storing one or more bits from a page of data. For example, the LDL latch can be used to store the next page of data. When the next page bit is stored in the associated memory cell, the LDL latch is flipped (e.g., from 0 to 1). For three bits per cell, when the middle or upper page bit is stored in the associated memory cell, respectively, the MDL or UDL latch is flipped. This occurs when the associated memory cell completes programming.

[0097] Figure 3 Shows Figure 1A 1 is an exemplary implementation of a power control circuit 115 for providing voltage to a block of memory cells in a plane. In one approach, the circuit shown may be repeated for each plane of the die. In this example, the memory structure 126 includes a set of four related blocks B0-0 to B0-3, and another set of four related blocks B0-4 to B0-7. See also Figure 4 . Blocks can be in one or more planes. Figure 1AThe row decoder 124 provides voltage to the word line and the select gate control line of each block via the pass transistor 322. In one method, a separate row decoder is provided for each block. The row decoder provides a control signal to the pass transistor, which connects the block to the row decoder. In one method, the pass transistors of each group of blocks are controlled by a common control gate voltage. Therefore, the pass transistors of a group of blocks are all turned on or off at a given time. If the pass transistor is turned on, the voltage from the row decoder is provided to the corresponding control gate line or word line. If the pass transistor is turned off, the row decoder is disconnected from the corresponding control gate line or word line, so that the voltage floats on the corresponding control gate line or word line.

[0098] For example, control gate line 312 is connected to pass transistor groups 313-316, which in turn are connected to control gate lines B0-4 to B0-7, respectively. Control gate line 317 is connected to pass transistor groups 318-321, which in turn are connected to control gate lines B0-0 to B0-3, respectively.

[0099] Typically, a program or read operation is performed on a selected block at a time in a block. An erase operation can be performed on a selected block or sub-block. A row decoder can connect a global control line 302 to a local control line 303. The control line represents a conductive path. A voltage is provided on the global control line of many voltage drivers. Some voltage drivers can provide a voltage to a switch 350 connected to the global control line. A pass transistor 324 is controlled to pass the voltage from the voltage driver to the switch 350.

[0100] The voltage driver may include a selected data word line (WL) driver 347 that provides a voltage on a selected data word line during a programming or read operation. Driver 347 may provide a precharge voltage and a programming voltage on WLn during a programming cycle of a programming operation. Driver 348 may be used for unselected data word lines, and dummy word line drivers 349 and 349a may be used to provide a precharge voltage and a programming voltage on WLn, respectively. Figure 6 A voltage is provided on the dummy word lines WLDD and WLDS in .

[0101] The voltage driver may also include a separate SGD driver for each sub-block. Fig. 7A In the embodiment of the present invention, SGD drivers 346, 346a, 346b and 346c may be provided for SB0, SB1, SB2 and SB3, respectively. The SGD driver provides a voltage to a control line connected to the control gate of the SGD transistor (drain side select gate transistor). In one option, the SGS driver 345 is common to different sub-blocks in a block and provides a voltage to a control line connected to the control gate of the SGS transistor (source side select gate transistor).

[0102] The various components including the row decoder may receive commands from a controller, such as state machine 112 or controller 122, to perform the functions described herein.

[0103] The p-well voltage driver 330 provides a voltage Vp-well to the p+ contact 612b in the p-well region 611b, for example, via the conductive path 682. Figure 6 In one approach, the p-well region 611b is common to the block. Vp-well may be the same as Verase in FIG. 12. The blocks also share a set of bit lines 342. A source line (SL) voltage driver 331 provides a voltage Vsl to the n+ contact 612c in the p-well region 611b, for example, via a local interconnect 651.

[0104] The bit line voltage driver 340 includes a voltage source that provides a voltage to the bit line 342. The bit line voltage for sensing in an erase verification test may be, for example, 0.5V.

[0105] In such Figures 4 to 7B In the stacked memory device shown in , multiple groups of connected memory cells can be arranged in NAND strings that extend vertically upward from a substrate. In one approach, the bottom (or source terminal) of each NAND string contacts the substrate, such as a well region, and the top (or drain terminal) of each NAND string is connected to a corresponding bit line.

[0106] Figure 4 is with Figure 1A A perspective view of a consistent exemplary memory die 400 in which multiple memory cell blocks are arranged in corresponding planes P0 and P1. The memory die includes a substrate 611, a middle region 402 in which the memory cell blocks are formed, and an upper region 403 in which one or more upper metal layers are patterned to form bit lines. For example, a set of common bit lines BL0, BL1, ... extend over blocks B0-0 to B0-n-1 in plane P0. Another set of bit lines may extend over blocks B1-0 to B1-n-1 in plane P1. Planes P0 and P1 represent corresponding isolation regions formed in the substrate 611. In addition, a first block sequence 405 of n blocks (labeled B0-0 to B0-n-1) is formed in P0, and a second block sequence 415 of n blocks (labeled B1-0 to B1-n-1) is formed in P1. Each plane may have associated row and column control circuits, such as Figure 1A The row decoder 124, the read / write circuit 128 and the column decoder 132 are also shown.

[0107] In one approach, control circuitry 110, which may be located in a peripheral area of ​​the die, may be shared between planes. Each plane may have a separate set of bit lines.

[0108] By providing blocks of memory cells in multiple planes, parallel operations can be performed in the planes. For example, blocks in different planes can be erased simultaneously.

[0109] The substrate 611 may also carry the circuitry beneath the blocks, as well as one or more underlying metal layers that are patterned in conductive paths to carry the signals of the circuitry.

[0110] In this example, the memory cells are formed in vertical NAND strings in blocks. Each block includes a stacked area of ​​memory cells, where alternating layers of the stack represent word lines. In one possible approach, each block has opposing layered sides from which vertical contacts extend upward to the upper metal layer to form connections to the conductive paths. Although two planes are shown as an example, other examples may use four or more planes. One plane per die is also possible.

[0111] The plurality of blocks typically include user data blocks and one or more read-only memory (ROM) blocks, such as user ROM blocks. During the useful life of the memory device, the user data blocks may be used for repeated programming, reading, and erasing operations. These blocks typically store user data provided by a host. ROM blocks (also referred to as user ROM blocks) typically maintain the same data over the useful life of the memory device and do not change, as mentioned at the beginning. For example, the data in the user ROM blocks may include data identifying bad (defective) columns or bad blocks in the user data blocks. The data in the user ROM blocks may include parameters for configuring the memory device after power-on. One or more user ROM blocks are tested during manufacturing to ensure that they are free of defects.

[0112] When the memory is not powered, the bad column data is read in by the controller and used to provide a column replacement table used during read and write operations. In some cases, to improve reliability, ROM blocks use one bit per cell to store data. User data blocks can use two or more bits per cell to store data with higher density.

[0113] For example, B1-0 may be a user ROM block, and the remaining blocks B0-0 to B0-n-1 and B1-1 to B1-n-1 are user data blocks.

[0114] Figure 5 Shows Figure 1A1. An exemplary transistor 520 in the memory structure 126 of FIG. The transistor includes a control gate CG, a drain D, a source S, and a channel CH, and may represent, for example, a memory cell or a select gate transistor. The drain terminal of the transistor is optionally connected to a bit line BL via one or more other transistors in the NAND string, and the source terminal of the transistor is optionally connected to a source line SL via one or more other transistors in the NAND string. The transistor may represent, for example, a memory cell or a select gate transistor.

[0115] Figure 6 Shows Figure 4 0-0, including NAND strings 700n and 710n, which in this example are in a common sub-block. The block includes a stack 610 of alternating conductive layers (word line layers) and dielectric layers. These layers can be rectangular plates with a height in the z direction, a width in the y direction, and a length in the x direction.

[0116] The stack is shown as comprising one layer, but may optionally comprise multiple alternating conductive and dielectric layers, wherein the layers are separated by interfaces. The stack comprises a set of alternating conductive and dielectric layers, wherein memory holes are formed during the manufacturing process.

[0117] Conductive layers include SGS, WLDS, WL0-WL95, WLDD, and SGD(0). The conductive layer connected to the control gate of the memory cell is called a word line, and the conductive layer connected to the control gate of the source side selection gate transistor and the control gate of the drain side selection gate transistor is called a source side control line and a drain side control line, respectively. WLDS and WLDD are dummy word lines or conductive layers connected to dummy memory cells, which are not qualified to store user data. The dummy memory cell can have the same structure as the data memory cell, but the controller considers that the memory cell is not qualified to store any type of data including user data. One or more dummy memory cells can be provided at the drain end and / or source end of the NAND string of the memory cell to provide a gradual transition of the channel voltage gradient. The use of dummy memory cells is optional. WL0-WL95 are data word lines connected to the data memory cell, which are qualified to store user data. By way of example only, the stack includes ninety-six data word lines. DL is an exemplary dielectric layer.

[0118] A top 610t and bottom 610b of the stack are shown. WL95 is the topmost data word line or conductive layer, and WL0 is the bottommost data word line or conductive layer.

[0119] The NAND string is formed by etching a memory hole in the stack and then depositing multiple thin layers of material along the sidewalls of the memory hole. The memory cells are formed in the area where the word line intersects the multiple thin layers, and the select gate transistors are formed in the area where the SGS and SGD control lines intersect the multiple thin layers. For example, the drain side select gate transistor 716 is formed where the SGD control line intersects the multiple thin layers, and the source side select gate transistor 701 is formed where the SGS control line intersects the multiple thin layers. The topmost data memory cell 714 is formed where WL95 intersects the multiple thin layers, and the bottommost data memory cell 703 is formed where WL0 intersects the multiple thin layers.

[0120] Multiple thin layers may form an annular layer and may be deposited, for example, using atomic layer deposition. For example, these layers may include a blocking oxide layer 663, a charge trapping layer 664, a tunnel layer 665, and a channel layer 660. A dielectric core 666 (e.g., comprising silicon dioxide) may also be provided. The word line or control line may include a metal such as tungsten. In this example, all layers are disposed in the memory hole. In other methods, some of the layers may be disposed in the word line or control line layer. Multiple thin layers form a columnar active area (AA) of the NAND string.

[0121] The stack is formed on a substrate 611. In one approach, the substrate includes a p-well region 612 connected to the source terminal of the NAND string. The p-well region may include an epitaxial region 612a that extends upward adjacent to the source side select gate transistor. The p-well region may include an n+ contact 612c connected to a local interconnect 651 to receive a source line voltage and a p+ contact 612b connected to a conductive path 682 to receive a p-well voltage. The local interconnect 651 may include a conductive material 651b, such as a metal surrounded by an insulating material 651a, to prevent conduction with the metal of an adjacent word line. In one possible implementation, the p-well region is formed in an n-well 613, which in turn is formed in a p-type semiconductor region 614 of the substrate.

[0122] NAND string 700n has a source terminal 700s connected to the p-well at the bottom 610b of the stack 610. NAND string 700n also has a drain terminal 700d connected to bit line BL0 via a bit line contact 680 comprising n-type material at the top 610t of the stack. NAND strings 710n and 710n are connected to BL0 and BL1 via bit line contacts 680 and 681, respectively. A short circuit path 685 exists between WL95 and the channel layer 660. This is an example of a word line short to the channel. WL95 is an example of a leaky word line. A short circuit path 684 also exists between bit line contacts 680 and 681 in the doped silicon region 683 above the NAND string. This is a bit line contact to bit line contact short, or a bit line to bit line short. Additional examples of short circuits are shown in FIG. FIG. 7C to FIG. 7G Available in.

[0123] A NAND string can be considered to have a floating channel because the length of the channel is not formed on the substrate.

[0124] When programming a memory cell, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge trapping layer and travel through the tunnel layer. The Vth of the memory cell increases in proportion to the amount of charge stored. During an erase operation, the channel of the NAND string is charged, such as by applying a positive erase pulse to the substrate via the local interconnect 651, resulting in hole injection into the charge trapping layer.

[0125] Fig. 7A Shown with Figure 4 and Figure 6 0-0. The NAND strings are arranged in a 3D configuration in sub-blocks of the block. Each sub-block includes multiple NAND strings, with one example NAND string depicted. For example, SB0, SB1, SB2, and SB3 include example NAND strings 700n, 710n, 720n, and 730n, respectively. The NAND strings have Figure 6 Consistent data word lines, dummy word lines, and select gate lines. Each sub-block includes a group of NAND strings that extend in the x direction and have a common SGD line or control line layer. NAND strings 700n, 710n, 720n, and 730n are located in sub-blocks SB0, SB1, SB2, and SB3, respectively. Blocks can be programmed based on word line programming order. One option is to program memory cells in different word line portions in different sub-blocks, one sub-block at a time, before programming the memory cells of the next word line. For example, this can involve programming WL0 in SB0, SB1, SB2, and SB3, then programming WL1 in SB0, SB1, SB2, and SB3, and so on. For example, the word line programming order can start with WL0 (source end word line) and end at WL95 (drain end word line).

[0126] In an erase operation, typically an entire block is erased, but partial block erase is possible, such as by erasing selected sub-blocks of a block and / or by erasing memory cells connected to a subset of word lines that is less than all of the word lines.

[0127] Multiple memory cells of B0-0 are arranged in NAND strings, where each NAND string includes a continuous charge trapping layer along the length of the NAND string. NAND string 700n includes SGS transistor 701, dummy memory cell 702, data memory cells 703-714, dummy memory cell 715, and SGD transistor 716. NAND string 710n includes SGS transistor 721, dummy memory cell 722, data memory cells 723-734, dummy memory cell 735, and SGD transistor 736. NAND string 720n includes SGS transistor 741, dummy memory cell 742, data memory cells 743-754, dummy memory cell 755, and SGD transistor 756. NAND string 730n includes SGS transistor 761, dummy memory cell 762, data memory cells 763-774, dummy memory cell 775, and SGD transistor 776.

[0128] This example shows one SGD transistor at the drain terminal of each NAND string, and one SGS transistor at the source terminal of each NAND string. In one approach, the SGD transistors in SB0, SB1, SB2, and SB3 can be driven by separate control lines SGD(0), SGD(1), SGD(2), and SGD(3), respectively. In another approach, multiple SGD and / or SGS transistors can be provided in a NAND string.

[0129] Figure 7B Shows Fig. 7A 0. Each NAND string is represented by a column. In this simplified example, sub-blocks SB0-SB3 each include ten exemplary NAND strings connected to corresponding bit lines BL0-BL9. Black circles represent the connection points of the NAND strings to the bit lines. Fig. 7A NAND strings 700a, 710a, 720a, and 730a. Recall Figure 4 , the set of bit lines may extend over multiple blocks of memory cells.

[0130] Figure 7C Shown with Figure 7B An example of a consistent first failure mode, where in SB0, NAND string 700b has a word line to channel short circuit path 801, and a NAND string cluster 800 including NAND strings 700b-700d is shorted to each other. For simplicity, the NAND strings of SB1-SB3 are not shown. The cluster includes three NAND strings as an example, and these three NAND strings are connected to three different corresponding bit lines BL1-BL3. The cluster is contained in one sub-block.

[0131] exist FIG. 7C to FIG. 7FIn FIG. 5 , the shorted NAND strings are shown with a hatched pattern, while the remaining non-shorted NAND strings are unshaded. The short between NAND strings can be, for example, a bit line contact to a bit line contact short.

[0132] Fig.7D Shown with Figure 7B An example of a consistent second failure mode, where in SB0, NAND string 700b has a word line to channel short circuit path 801, and a NAND string cluster 810 including NAND strings 700b-700d in SB0 and NAND string 710a in SB1 is shorted to each other. For simplicity, the NAND strings of SB2 and SB3 are not shown. The cluster includes four NAND strings as an example, which are connected to four different corresponding bit lines BL0-BL3. The cluster extends across two adjacent sub-blocks of the block.

[0133] Fig. 7E Shown with Figure 4 and Figure 7B An example of a consistent third failure mode, where in SB3 of B0-0, NAND string 730b has a word line to channel short path 831, and a NAND string cluster 819 including NAND strings 730b-730d in SB3 and NAND string 740 in SB0 of adjacent block B0-1 are shorted to each other. For simplicity, the NAND strings of the remaining sub-blocks of the two blocks are not shown. The cluster includes four NAND strings as an example, and these four NAND strings are connected to four different corresponding bit lines BL0-BL3. The cluster extends across two adjacent sub-blocks of adjacent blocks B0-0 and B0-1, which is consistent with Figure 4 Consistent.

[0134] Figure 7F Shown with Figure 7B An example of a consistent fourth failure mode, where in SB0, NAND string 700a has a word line to channel short circuit path 802, and a NAND string cluster 810 including NAND strings 700b-700d in SB0 and NAND string 710a in SB1 are short circuited to each other. For simplicity, the NAND strings of SB2 and SB3 are not shown. The cluster includes four NAND strings as an example, and these four NAND strings are connected to four different corresponding bit lines BL0-BL3. The cluster extends across two adjacent sub-blocks of the block. In addition, the word line to channel short circuit path 802 is located in NAND string 700a, which is not short circuited to another NAND string, which is consistent with FIG. 7C to FIG. 7E The opposite of the example.

[0135] Figure 7G Shown with Figure 7BAn example of a consistent fifth failure mode, where in SB0, NAND string 700a has a word line to channel short path 802, and no NAND strings are shorted to each other. In this example, the short involves only NAND string 700a.

[0136] Figure 8 A flow chart showing an exemplary process for performing a short circuit detection operation is shown. Figure 7C to Figure 7G At step 820, a command is issued to start a short circuit detection operation for multiple NAND strings, such as in a block or sub-block. For example, Figure 1B The control circuit 130 may issue such commands via the interface 131. For example, the memory cell may be in an erased state.

[0137] Step 821 includes performing a channel pre-clean phase of operation. During this phase, the sensing circuit and associated transistor group may be Fig.9A 902. The presence of a word line short to the channel in NAND string 902 allows the positive voltage on WL95 to charge the channel of the NAND string. The charge on the channel is delivered to the bit line contact 912 and the bit line BL2. In addition, in this example, the presence of a short circuit path 906 between the bit line contacts 911-913 causes the voltage on BL1 and BL3 to increase. This process of charging the bit line is called reverse charging because the NAND string is the charging source, not the nodes 251-251d and the transistor groups 250-250d. Reverse charging is represented by an upward arrow. NAND strings 901-903 include clusters of shorted NAND strings.

[0138] NAND strings 900 and 904 do not have a short circuit and therefore are not charged during this phase. Instead, when the SGS transistor is turned on and the CELSRC line (source line) is grounded, the channels of these NAND strings are discharged. The discharge of CELSRC is represented by the downward arrows in NAND strings 900 and 904. Some discharge of CELSRC in NAND string 902 also occurs as shown by the corresponding downward arrow.

[0139] Step 822 includes performing the bit line precharge phase of the operation. In this phase, the sensing circuit and associated transistor group can be as follows Fig. 9B 2 is configured to provide a voltage to the bit line. Transistor groups 250-250d are configured to charge the bit line. This configuration of transistor groups 250 and 250d will result in charging BL0 and BL4, respectively, because they are connected to non-short-circuited NAND strings 900 and 904, respectively. However, bit lines BL1-BL3 continue to be reversely charged. The reverse charge is greater than the charge applied by transistor groups 250a-250c, so that the reverse charge is maintained.

[0140] Step 823 includes performing the bit line discharge phase of the operation. In this phase, the sensing circuit and associated transistor group can be as follows Fig. 9C The configuration shown is to stop supplying voltage to the bit lines. The bit lines BL1-BL3 continue to be reversely charged, while the voltages on BL0 and BL4 are discharged.

[0141] Step 824 includes performing a sensing phase of the operation to distinguish shorted NAND strings from non-shorted NAND strings. In this phase, the sensing circuit and associated transistor groups may be as follows: Fig.9D 1 is configured to sense a NAND string. The XXL, BLC, and BLS transistors are turned on to provide a path from the bit line to the corresponding sensing circuit. Each sensing circuit can detect the current and / or voltage in the corresponding NAND string based on the amount of voltage decay of the sensing node, for example, as discussed. See also Fig.10 The bit lines BL1-BL3 continue to charge reversely, while the voltages on BL0 and BL4 remain at a lower discharge level. Figure 2 As mentioned, the comparison circuit 175 can determine the decay amount of the sense node by comparing the sense node voltage to the threshold value Vt when sensing. If there is no reverse charging, as expected for non-short NAND strings (such as NAND strings 900 and 904), the sense node voltage will decay to below Vt. In this case, the NAND string has a relatively high current and is in a conductive state. If the bit line is reverse charged, as expected for shorted NAND strings (such as NAND strings 901-903), the sense node voltage will not decay below Vt. In this case, the NAND string has a relatively low current and is in a non-conductive state.

[0142] Step 825 includes setting data in the latches to identify shorted NAND strings and non-shorted NAND strings based on sensing. For example, or each bit line and NAND string, the corresponding sense node latch 172 can be set to 1 or 0, respectively, based on whether the memory cell is in a conductive state or a non-conductive state, for example, by the comparison circuit 175. This identifies each NAND string as shorted or non-shorted.

[0143] Step 826 includes obtaining a count of shorted NAND strings. For example, this may involve the control circuit reading latches to determine the number of latches that are set to 0, indicating a non-conductive NAND string.

[0144] Decision step 827 determines whether the count is greater than a threshold for the allowed number of shorted NAND strings in a block or other group. If the decision step is true (T), the block or other group of NAND strings is leaking at step 829 and may therefore be unusable. If the decision step is false (F), the block or other group of NAND strings is normal at step 828 and may therefore be used, for example, to store user data. Generally speaking, the control circuit is configured to count the number of NAND strings in a non-conductive state in a plurality of NAND strings based on sensing, and determine whether the number exceeds a threshold. In addition, the control circuit is configured to classify the plurality of NAND strings as unusable if the number exceeds a threshold.

[0145] In one approach, Figure 8 The testing process can occur at the manufacturing site before releasing the block to the end user. In another approach, the testing process occurs periodically, such as when the block reaches a specified program-erase cycle. This method can detect problems in a block that was initially normal but developed a short circuit due to the stress of the program-erase cycle.

[0146] Step 830 includes performing a recovery phase of operation after the sensing phase. The recovery phase returns the voltages of various control lines such as word lines, select gate lines, and bit lines to an initial level, such as 0V.

[0147] The short detection process can advantageously sense all bit lines / NAND strings simultaneously to effectively detect shorted clusters. This technique can distinguish between NAND strings that are not open at the bottom and NAND strings that have a word line shorted to the channel. These techniques are particularly suitable when clusters of NAND strings have their bit line contacts shorted to each other.

[0148] The pre-charge phase and the discharge phase help identify bit lines that can be discharged and therefore not subject to reverse charging from a short circuit.

[0149] 9A to 9H Each shows a group of NAND strings 900-904 connected to bit line contacts 910-914, respectively, which in turn are connected to bit lines BL0-BL4, respectively. The NAND strings include data memory cells connected to word lines WL0-WL95, dummy memory cells connected to word lines WLDS and WLDD, and source-end select gate transistors and drain-end select gate transistors connected to select gate lines SGS and SGD, respectively, which are similar to Figure 6 and Fig. 7A Consistent.

[0150] 9A to 9HAlso shown are sensing circuits and a set of transistors connected to each bit line. For example, sensing circuit SC0 and a set of transistors 250 are connected to BL0, sensing circuit SC1 and a set of transistors 250a are connected to BL1, sensing circuit SC2 and a set of transistors 250b are connected to BL2, sensing circuit SC3 and a set of transistors 250c are connected to BL3, and sensing circuit SC4 and a set of transistors 250d are connected to BL0. In this example, the transistors are nMOSFETs. Transistors with an "X" are non-conductive or turned off, while transistors without an "X" are conductive or turned on. Transistor groups 250-250d each include power source nodes 251-251d, respectively. Figure 8 The corresponding voltage signal during the short-circuit detection operation of Fig.10 .

[0151] 9A to 9D An example of a NAND string 902 having a word line shorted to a memory hole and a bit line contact shorted to a bit line contact is shown, which is similar to FIG. 7C to FIG. 7E Specifically, NAND string 902 has a word line to channel short circuit path 905 at WL95. In addition, there is a short circuit between bit line contacts 911 and 912 and between bit line contacts 912 and 913. These two short circuits form a continuous short circuit path 906 between bit line contacts 911-913. This is an example, as this type of short circuit can involve two or more bit line contacts that are generally adjacent to each other.

[0152] In with 9A to 9D In a specific embodiment, the control circuit is configured to be connected to a plurality of NAND strings (900-904), the plurality of NAND strings are connected to a plurality of word lines (WL0-WL95) and include a first short-circuited NAND string (902) short-circuited to a leakage word line (WL95) among the plurality of word lines, a second short-circuited NAND string (901 or 903) short-circuited to the first short-circuited NAND string, and a non-short-circuited NAND string (900 and 904) that is not short-circuited to another NAND string. Each NAND string is connected to a corresponding bit line among a plurality of bit lines (BL0-BL4).

[0153] In with 9A to 9D In another embodiment, the plurality of NAND strings include a shorted NAND string (902) and another shorted NAND string (901 or 903), wherein one of the shorted NAND strings includes a channel shorted to a word line (WL95) and a bit line contact (912) shorted to a bit line contact (911 or 913) of the other shorted NAND string. The bit line contact of the one shorted NAND string may extend from the bit line contact of the one shorted NAND string to the bit line contact of the other shorted NAND string via a doped silicon region (1145a, Fig.11H) is shorted to the bit line contact of another shorted NAND string.

[0154] exist 9A to 9D In the sensing phase 1003 ( Fig.10 ), the voltage of the bit lines connected to one short-circuited NAND string (BL2) and another short-circuited NAND string (BL1 or BL3) is higher than the voltage of the non-short-circuited NAND strings among the multiple NAND strings, and the non-short-circuited NAND strings (900 and 904) include NAND strings that are not short-circuited with another NAND string.

[0155] The voltage of the bit lines (BL0 and BL4) connected to the non-short-circuited NAND strings among the multiple NAND strings is boosted in the second bit line precharge phase and discharged in the third bit line discharge phase; the voltage of the bit lines connected to one short-circuited NAND string (BL2) and another short-circuited NAND string (BL1 and BL3) is higher than the voltage of the non-short-circuited NAND strings throughout the second phase and the third phase; and the non-short-circuited NAND strings include NAND strings that are not short-circuited with another NAND string.

[0156] Fig.9A A group of NAND strings and associated circuits are shown when there is a word line short circuit to a memory hole and a bit line contact short circuit to a bit line contact, which is configured similar to Figure 8 The transistors in the transistor group are turned off, except that BLS can be turned on to prepare for the subsequent stage of operation. The positive voltage on WL95 leaks into the channel of NAND string 902. The voltage is passed to bit line contact 912 and from there to BL2, as well as bit line contacts 911 and 913. The voltage on bit line contacts 911 and 913 is passed to BL1 and BL3 respectively. Therefore, in the channel pre-cleaning stage 1000, BL1-BL3 have the following Fig.10 For non-shorted NAND strings 900 and 904, the word line voltage does not leak into the channel. This allows their channels to be grounded at CELSRC when the SGS transistors are turned on. In the channel pre-cleaning phase 1000, BL0 and BL4 may be at 0V or other low levels, such as Fig.10 A portion of the voltage of the channel of NAND string 902 may also be passed to ground at CELSRC.

[0157] Fig. 9B A set of NAND strings and associated circuitry are shown, configured with Figure 8 The bit line precharge phase of step 822 is consistent with that of step 822, and follows Fig.9Aconfiguration. The BLX transistor is turned on to provide a positive voltage to the drain of the BLC transistor at the power source nodes 251 - 251d. The control gate voltage of the BLC transistor can be set to attempt to clamp the corresponding bit line voltage. The clamping of the NAND strings 900 and 904 is successful because their bit line voltages are low and allow a positive drain - to - source voltage at the corresponding BLC transistors. During the bit line pre - charge phase 1001, BL0 and BL4 can be clamped at V1 = 0.2V, for example, as shown for Vbl_good in Fig.10 However, the clamping of the NAND strings 901 - 903 is not successful because the bit line voltages of these NAND strings are high due to reverse charging from the short circuit. During the bit line pre - charge phase 1001, BL1 - BL3 remain at an elevated voltage, as shown for Vbl_sc in Fig.10

[0158] Fig. 9C shows a set of NAND strings and associated circuitry, whose configuration is consistent with the bit line discharge phase of step 823 of Figure 8 and follows the configuration of Fig. 9B The BLX and BLC transistors are turned off so that they do not provide a bias to the bit lines. Thus, during the bit line discharge phase 1002, the voltages of BL0 and BL4 discharge to a level V2 < V1, as shown for Vbl_good in Fig.10 During the bit line discharge phase 1002, BL1 - BL3 remain at an elevated voltage, as shown for Vbl_sc in Fig.10

[0159] Fig.9D shows a set of NAND strings and associated circuitry, whose configuration is consistent with the sensing phase of step 824 of Figure 8 and follows the configuration of Fig. 9C The BLC and XXL transistors are turned on to provide a conductive path from the sensing circuit to the corresponding bit lines. The voltage at the sensing node in the sensing circuit can be monitored to determine the conductive or non - conductive state of the NAND string, as discussed. For example, see Vsense in Fig.10 During the sensing phase 1003, the voltages of BL0 and BL4 remain at the discharged level V2, as shown for Vbl_good in Fig.10 During the sensing phase 1003, BL1 - BL3 remain at an elevated voltage, as shown for Vbl_sc in Fig.10 The voltages of BL1 - BL3 are significantly higher than the voltages of BL0 and BL4, such that the short - circuited NAND strings can be easily distinguished from the non - short - circuited NAND strings during the sensing phase.

[0160] FIG. 9E to FIG. 9H ​​An example of a word line shorted to a memory hole is shown, which does not have a bit line contact shorted to a bit line contact, which is consistent with Figure 7G Specifically, NAND string 902 has a word line to channel shorting path 905 at WL95. However, there is no shorting between the bit line contacts.

[0161] Fig.9E A group of NAND strings and associated circuits are shown when there is a word line short circuit to a memory hole but there is no bit line contact short circuit to a bit line contact, which is configured similar to Figure 8 The positive voltage on WL95 leaks into the channel of NAND string 902. The voltage is transferred to bit line contact 912 and from there to BL2. Therefore, in the channel pre-cleaning stage 1000, BL2 has Fig.10 For non-shorted NAND strings 900, 901, 903, and 904, the word line voltage does not leak into the channel. This allows their channels to be grounded at CELSRC when the SGS transistors are turned on. In the channel pre-cleaning phase 1000, BL0, BL1, BL3, and BL4 may be at 0V or other low levels, such as Fig.10 A portion of the voltage of the channel of NAND string 902 may also be passed to ground at CELSRC.

[0162] Fig.9F A set of NAND strings and associated circuitry are shown, configured with Figure 8 The bit line precharge phase of step 822 is consistent with that of step 822, and follows Fig.9E 1-251d. The control gate voltages of the BLC transistors may be set to attempt to clamp the corresponding bit line voltages. The clamping of NAND strings 900, 901, 903, and 904 is successful because their bit line voltages are low and allow for positive drain-to-source voltages at the corresponding BLC transistors. In the bit line precharge phase 1001, BL0, BL1, BL3, and BL4 may be clamped at V1=0.2V, for example, as Fig.10 However, the clamping of NAND string 902 is unsuccessful because the bit line voltage of this NAND string is higher due to the reverse charge from the short circuit. In the bit line precharge phase 1001, BL2 is maintained at an elevated voltage, as shown in FIG. Fig.10 As shown for Vbl_sc.

[0163] Figure 9G A set of NAND strings and associated circuitry are shown, configured with Figure 8is consistent with the bit line discharge phase of step 823 and follows Fig.9F 's configuration. The BLX and BLC transistors are turned off so that they do not provide a bias to the bit lines. Thus, during the bit line discharge phase 1002, the voltages of BL0, BL1, BL3, and BL4 discharge to a level V2 < V1, as Fig.10 shown for Vbl_good. During the bit line discharge phase 1002, BL2 remains at an elevated voltage, as Fig.10 shown for Vbl_sc.

[0164] Figure 9H shows a set of NAND strings and associated circuitry that is configured consistent with Figure 8 the sense phase of step 824 and follows Figure 9G 's configuration. The BLC and XXL transistors are turned on to provide a conduction path from the sense circuit to the respective bit lines. During the sense phase 1003, the voltages of BL0, BL1, BL3, and BL4 remain at the discharged level V2, as Fig.10 shown for Vbl_good. During the sense phase 1003, BL2 remains at an elevated voltage, as Fig.10 shown for Vbl_sc. The voltage of BL2 is significantly higher than the voltages of BL0, BL1, BL3, and BL4, such that the shorted NAND strings can be easily distinguished from the non-shorted NAND strings during the sense phase.

[0165] Fig.10 shows voltage signals consistent with Figure 8 and 9A to 9D . The voltage signals are on a common time axis that includes time points t0 - t5. The time points t0 - t1, t1 - t2, t2 - t3, t3 - t4, and t4 - t5 correspond to the channel pre-clean phase 1000, the BL pre-charge phase 1001, the BL discharge phase 1002, the sense phase 1003, and the recovery phase 1004, respectively.

[0166] Vbl_good is the voltage of a good bit line, e.g., a bit line not connected to a NAND string with a short, whether the short is a word line to channel short or a BL contact to BL contact short. During the short detection operation, a good bit line does not undergo reverse charging from a leaking (shorted) word line. During phase 1000, Vbl_good is at a low level, such as 0V. During phase 1001, the good bit line is pre-charged to a small voltage V1, e.g., 0.2V. During phase 1002, the good bit line is discharged to V2 which is less than V1. V2 can be approximately the same as the voltage during phase 1000.

[0167] Vbl_sc is the voltage of the bit line connected to the NAND string with a short circuit, whether the short circuit is a word line short circuit to the channel or a BL contact short circuit to the BL contact of another NAND string, which in turn has a word line short circuit to the channel. Such bit lines are referred to as affected bit lines. The leakage bit line is subjected to reverse charging from the leakage word line. The affected bit line is subjected to reverse charging from the leakage word line. As Vwl increases to Vdd, Vbl_sc increases to a first level L1 at t0a. Vsgd and Vsgs also increase to Vdd. Vdd is a power source voltage such as 2V-3V. When Vwl increases from Vdd to Vread, for example 8V, Vbl_sc further increases to a second level L2 at t0b. Vsgd and Vsgs also further increase from Vdd to Vsg, for example 6V. When the SGS transistor (curve 1013) is turned off, Vbl_sc further increases to a third level L3 at t1. Thus, during the precharge phase, the SGS transistor turns on, then turns off, while the SGD transistor turns on and remains on. L3 may be the peak level of Vbl_sc in operation. At t0-t0b, the voltage of the leakage bit line leaks into the channel and moves toward both the bit line and CELSRC because the SGD and SGS transistors are turned on, respectively. At t0b-t1, the SGS transistor turns off, causing the additional charge that leaked to CELSRC to leak to the bit line instead, thereby increasing its voltage from L2 to L3.

[0168] In one approach, Vwl remains at Vread until t4. Therefore, the bit line continues to be reverse charged by the leakage word line until t4. Although since the bit line is a long metal line, some parasitic effects will cause Vbl_sc to slowly decrease to level V3 during sensing.

[0169] Vbls is for example combined with Figure 2 and 9A to 9D The control gate voltage of the BLS transistor in question may be applied during the entire operation.

[0170] Vblc is the control gate voltage of the BLC transistor. A turn-on voltage V4 is applied in phase 1001, and a higher turn-on voltage V5 is applied in phase 1003. Note that during the sensing phase 1003, Vbl_sc is at V3>V5, so that for the affected bit line, reverse bit line charging continues. The BLC transistor does not clamp the affected bit line.

[0171] Vblx is the control gate voltage of the BLX transistor. During the bit line precharge phase 1001, this transistor is turned on using Von to provide a voltage to the drain of the BLC transistor.

[0172] Vnlo is the control gate voltage of the NLO transistor. This transistor is turned off (set to a non-conductive state) by setting Vnlo = Voff to avoid forming a ground path for the transistor group.

[0173] Vxxl is the control gate voltage of the XXL transistor. When BLC and BLS are also on, the transistor is turned on to connect the sensing circuit to the corresponding bit line. Vxxl=Von during the sensing phase 1003, and Vxxl=Voff in other phases.

[0174] Vsgd is the control gate voltage of the SGD transistor, and Vsgs is the control gate voltage of the SGS transistor. In one method, shown by curve 1010, these voltages are increased in two steps in phase 1000 at t0-t0b. These two steps represent the on-voltages Vdd and Vsg. In another method, shown by curve 1011, these voltages are increased in one step to Vsg. From t0b-t4, Vsgd remains at the on-level Vsg (curve 1012), while Vsgs decreases to a turn-off level of, for example, 0V (curve 1013). In one method, Vsgd is set as indicated for all sub-blocks of a block. In another method, Vsgd is set as indicated for a selected sub-block of a block.

[0175] Vwl is the control gate or word line voltage of the memory cell. Vwl is applicable to all memory cells. In one method shown by curve 1020, Vwl increases in two steps in phase 1000 at t0-t0b. The two steps represent Vdd and Vread. In another method shown by curve 1021, Vwl increases to Vread in one step. In one example, from t0b-t4, Vwl remains at Vread. This ensures that Vbl_sc remains high by reverse charging so that it can be distinguished from Vbl_good in the sensing phase.

[0176] Vsense is the voltage of the sense node in the sense circuit. During the sense phase, Vsense is set to an initial level at t3. During the sense process, when the XXL transistor is turned on, if the associated bit line is not reverse charged, Vsense will decay significantly below the threshold level Vt at the sensing time ts, as shown by curve 1031, indicating the absence of a word line short to the channel. If the associated bit line is reverse charged, Vsense will remain above Vt at ts, as shown by curve 1030, indicating the presence of a word line short to the channel.

[0177] The control circuit can be configured with commands and parameters for implementing the operation. For example, commands can be defined for initiating a short circuit operation and each of its phases. In addition, parameters can be set for various voltage levels and timings, as described below:

[0178] V4: BLC control gate voltage during the bit line precharge phase, where the bit line voltage of the normal non-short NAND string is clamped by this voltage;

[0179] V5: BLC control gate voltage during the sensing phase, used to set the bit line sensing voltage;

[0180] T1: defines the duration of the bit line precharge phase; and

[0181] T2: defines the duration of the bit line discharge phase.

[0182] In one exemplary implementation, the first phase includes simultaneously applying a positive voltage (Vread) to the word line, applying a turn-on voltage (Vdd or Vsg) to the source end select gate transistor and the drain end select gate transistor, and applying a turn-off voltage (0V) to the clamp transistor. The second phase includes continuing to apply a positive voltage to the word line, applying a turn-off voltage (0V) to the source end select gate transistor, continuing to apply a turn-on voltage (Vsg) to the drain end select gate transistor, and applying a first turn-on voltage (V4) to the clamp transistor. The third phase includes simultaneously continuing to apply a positive voltage to the word line, continuing to apply a turn-off voltage to the source end select gate transistor, continuing to apply a turn-on voltage to the drain end select gate transistor, and applying a turn-off voltage (0V) to the clamp transistor. The fourth phase includes simultaneously sensing multiple NAND strings, continuing to apply a positive voltage to the word line, continuing to apply a turn-off voltage to the source end select gate transistor, continuing to apply a turn-on voltage to the drain end select gate transistor, and applying a second turn-on voltage (V5) to the clamp transistor.

[0183] Generally speaking, during the bit line pre-charge phase, all bit line pre-charge voltages (V1) are set relatively low, and the bit lines are clamped by the BLC control gate voltage (V4). In one method, V1 = V4 - Vth of the BLC transistor. For a NAND string with an unopened memory hole, during the sensing phase, the bit line voltage will be V2 < V1 because there is no leakage path for reverse charging the bit line between the word line and the memory hole. In a voltage sensing operation, the bit line sensing voltage defined by V5 will be set higher than V2. In one method, V2 = V5 - Vth of the BLC transistor. The clamping of the bit line voltage is for good bit lines that are not reverse charged. Therefore, a NAND string with an unopened memory hole can be sensed as "1", indicating an erased state or a conductive state. The same is true for a good NAND string that does not have an unopened memory hole and does not have a short circuit. Therefore, this operation avoids differentiating between unopened memory holes and normal memory holes, but instead identifies a short circuit between the word line and the channel. Other operations can be performed to differentiate between unopened memory holes and normal memory holes.

[0184] For a NAND string with a short circuit between the word line and the channel, the bit line will be reverse charged to a high voltage V3 higher than V5. As mentioned, the reverse charging is caused by the word line voltage Vread reaching the bit line through the short circuit. Such NAND strings are sensed as "0", indicating a programmed state or a non-conductive state. Since the memory cells are in the erased state at the start of the operation, such NAND strings are identified as being problematic. The presence of a cluster of multiple NAND strings of this type may indicate a fault that can make the block unavailable.

[0185] In the full bit line voltage sensing mode, all bit lines are pre-charged to V1, rather than charging the odd bit lines to V1 and the even bit lines to 0V. Therefore, in terms of a cluster of shorted NAND strings, although one NAND string has a short circuit between the word line and the channel, the corresponding bit line and the adjacent bit lines in the cluster are simultaneously reverse charged to a high voltage (V3), which will be higher than V5 during sensing.

[0186] Note that the channel pre-cleaning phase makes it easier to differentiate NAND strings with a short circuit between the word line and the channel because it increases the amount of reverse charge on the affected bit lines. However, this phase can be omitted, such as to save time. In this case, the reverse charge on the affected bit lines starts during the bit line pre-charge phase.

[0187] FIG. 11A to FIG. 11H An exemplary configuration of a block during the manufacturing process is shown, showing how a defect during the process can lead to a short circuit. The drawings provide a general overview and do not necessarily include all steps. The etching process can include, for example, reactive ion etching.

[0188] Fig.11AA first configuration of the block during manufacturing is shown, which results in Figure 6 and Figure 7C to Figure 7G A consistent short circuit in which alternating layers are formed in a stack 1100. The layers are formed on a substrate 1101 and may include a dielectric such as a dense tetraethyl orthosilicate, for example Si(OC2H5)4 or dTEOS, and a sacrificial material such as SiN. The sacrificial material layers are shaded in the figure. Layers 1102 and 1105 are exemplary bottom and top dielectric layers, respectively, and layers 1103 and 1104 are exemplary bottom and top sacrificial layers, respectively.

[0189] Fig. 11B A second configuration of a block during fabrication is shown, wherein non-uniform etching of the top dielectric layer 1105 results in over-etched dielectric regions 1105b and corner-etched dielectric regions 1105a having corners 1105a1. The mask is deposited on Fig.11A 1106a-1106d. Due to the presence of particles or other process errors, the mask area is not patterned correctly. Therefore, when the memory holes 1110-1113 are etched in the stack via the mask area, the area 1105b of the dielectric layer is over-etched and has a lower height than the other areas 1105a, 1105c, 1105e, 1105f and 1105g of the dielectric layer. In addition, the corner 1105a1 is formed on the area 1105a of the dielectric layer. These are examples of various types of process errors that can cause short circuits as described herein.

[0190] After etching the memory holes, epitaxial regions 1101a-1101d may be grown from the substrate in the memory holes 1110-1113, respectively.

[0191] Dielectric walls 1105d may also be formed to divide the topmost sacrificial layer 1104 to form separate sub-blocks.

[0192] Additionally, at this point, the sacrificial material may be removed and replaced with a metal such as W to form conductive control gate lines and word lines. FIG. 11C to FIG. 11H The replacement can be done via gaps formed in the stack along its length. For example, a layer formed in the stack can be used. Figure 6 The gap of the local interconnector 651 of FIG. SiN in the control gate layer can be removed by wet etching in the gap, and then metal is deposited. Metal layer 1124 ( Fig. 11C ) is an example of a conductive word line.

[0193] Fig. 11CA third configuration of the block during manufacturing is shown, in which layer 1120 is deposited in the memory holes 1110-1113, filler 1121 is deposited, and mask layer 1122 is deposited. Layer 1120 may include a blocking oxide layer followed by a charge trapping layer, a tunnel layer, and a channel layer. These may include aluminum oxide (Al2O3)-nitride (Si3N4)-oxide (SiO2)-silicon (Si) layers, as previously discussed. In one approach, the channel layer is deposited as polysilicon. In another approach, the channel layer is deposited as undoped amorphous silicon (aSi) and is subsequently heated to form polysilicon. The channel layer is typically the last deposited layer in layer 1120 and is adjacent to a dielectric core subsequently formed in the memory hole. Filler 1121 may include a hard mask material, such as Advanced Patterning Film available from Applied Materials, Inc. TM The film can be easily stripped using chemical vapor deposition. A photoresist mask layer 1122 is then deposited. Due to the reduced height of the region 1105b of the dielectric layer, the photoresist mask layer includes a low region 1122a ( Fig. 11B ).

[0194] Fig.11D A fourth configuration of a block in the fabrication process is shown, wherein mask layer 1122 is patterned to form voids 1122v1-1122v4 and mask layer regions 1122b-1122f. Mask layer region 1122a remains.

[0195] Fig.11E A fifth configuration of a block in the manufacturing process is shown, in which a patterned mask layer 1122 is used to etch through portions of the filler 1121 and layer 1120 at the bottom of the memory holes. The purpose of this step is to use the mask area to guide the etchant in each memory hole and through the layer 1120 at the bottom of each memory hole to form an opening that allows the channel to contact the epitaxial region of the substrate. In this example, the low area 1122a hinders the etching of the first two memory holes on the left side of the figure. Specifically, the etching particles are refracted from the low area 1122a, as shown by arrows 1125 and 1126, and contact the area 1127 of the layer 1120. This contact can damage the area 1127 and form a word line to channel short 1128. In addition, the etchant does not properly reach the bottom 1130 and 1131 of the memory holes, so that it is not etched through the layer 1120. Therefore, these memory holes are not opened at the bottom.

[0196] In contrast, the etchant correctly reaches the bottoms 1132 and 1133 of the two memory holes on the right side of the figure, causing layer 1120 to be etched through.

[0197] Figure 11F1A sixth configuration of the block during fabrication is shown, in which an additional polysilicon layer 1120a and a dielectric material 1139 are deposited. The additional polysilicon layer 1120a ensures that for the two memory holes on the right side of the figure there is an electrical connection between the substrate and the polysilicon layer of layer 1120, in which the bottom portion of layer 1120 is etched through. The dielectric material may be, for example, SiO2. The dielectric material is used to form a dielectric core in each memory hole, such as Fig.11F2 The dielectric core is surrounded by a polysilicon channel layer represented by additional polysilicon layer 1120a and a portion of layer 1120.

[0198] Fig.11F2 A seventh configuration of the block during fabrication is shown, wherein the dielectric material is etched back to form dielectric cores 1140-1143 in the memory holes, followed by deposition of a doped silicon capping layer 1145. Figure 11F1 The excess dielectric material is removed, thereby leaving the dielectric cores 1140-1143 in the memory holes. See, e.g. Fig. 11B A capping layer 1145 comprising, for example, n+ doped amorphous silicon is then deposited over the stack.

[0199] Fig.11G An eighth configuration of a block in the manufacturing process is shown, in which the doped silicon capping layer 1145 is etched to form bit line contacts 1145a1, 1145a3, 1145b, and 1145c. The capping layer is etched back. Ideally, this results in a separate bit line contact for each NAND string 1180-1183. For example, separate bit line contacts 1145b and 1145c are successfully formed for NAND strings 1182 and 1183, respectively. However, the bit line contacts 1145a1 and 1145a3 of NAND strings 1180 and 1181 are connected in the continuous doped silicon region 1145a, respectively, and are shorted together through region 1145a2, thereby forming a short circuit path 1129. Portions of layers 1120 and 1120a located at the top of the stack are also etched away.

[0200] Fig.11H A ninth configuration of the block in fabrication is shown, wherein vias 1151-1154 are formed over bit line contacts 1145a1, 1145a3, 1145b, and 1145c, respectively, and a bit line 1155 is formed over the via in insulating layer 1150. A word line to channel shorting path 1128 is shown along with a BL contact to BL contact shorting path 1129.

[0201] FIG. 12A to FIG. 12C Another exemplary manufacturing process that results in a short circuit is shown.

[0202] Fig. 12AThe configuration of the blocks in another example of the manufacturing process is shown, which results in the Figure 6 and FIG. 7C to FIG. 7G consistent short circuit. This configuration is Fig.11E 1220 . In this case, there are contamination particles 1200, such as dust particles, that hinder the etching of the bottom of some memory holes. The particles are present after depositing a layer 1220 similar to layer 1120. As previously described, etching particles can refract from the irregular surface of the contamination particles and damage a portion of the layer in the memory hole, such as during etching the memory hole to open a path at the bottom of the memory hole. For example, see damaged area 1227. Specifically, etching particles refract from particles 1200, as shown by arrows 1225 and 1226. This results in a word line to channel short circuit path 1228. In addition, the bottom of the memory hole may remain unopened (see the bottom 1230 and 1231 of the memory hole). In contrast, the etchant correctly reaches the bottom 1232 and 1233 of the two memory holes on the right side of the figure, so that layer 1220 is etched through.

[0203] Fig. 12B Shows that following Fig. 12A 1200. The dielectric material 1250 and the additional polysilicon layer 1220a are deposited. The dielectric material 1250 is deposited to fill the memory holes and conform to the shape of the particle at the top of the stack. The additional polysilicon layer 1220a ensures that for the two memory holes on the right side of the figure, there is an electrical connection between the substrate and the polysilicon layer of layer 1220, wherein the bottom portion of layer 1220 is etched through. The additional polysilicon layer includes a portion 1220a1 located on the particle 1200. The dielectric material forms a dielectric core in each memory hole, such as Fig. 12C The dielectric core is surrounded by a polysilicon channel layer represented by additional layer 1220a and a portion of layer 1220.

[0204] Fig. 12C Shows that following Fig. 12B The block configuration of the configuration of the configuration in which the dielectric material is etched back. The etch back forms dielectric cores 1240-1243 in the memory holes. However, the presence of the particles results in over-etched dielectric regions 1255, similar to Fig. 11B Specifically, the particles form a region that is less resistant to the etchant, causing the region to be etched back at a higher rate than the surrounding region. Fig. 12B ) at the top of the stack is also etched away.

[0205] Subsequently, the doped silicon capping layer 1145 is Fig.11F2 Then, the doped silicon capping layer 1145 is deposited as shown. Fig.11GAs shown, it is etched back, resulting in the bit line contact and associated short circuit 1129.

[0206] Thus, it can be seen that in one specific implementation, an apparatus includes: a control circuit configured to be connected to a plurality of NAND strings via a plurality of word lines and a plurality of bit lines, each NAND string including a memory cell between a source end select gate transistor and a drain end select gate transistor, the memory cell being connected to the plurality of word lines, each bit line being connected to a clamp transistor configured to clamp a voltage of the bit line. The control circuit for performing the consecutive first, second, third and fourth stages of the short circuit detection operation is configured as follows: in the first stage, a positive voltage is applied to the word line at the same time, a turn-on voltage is applied to the drain end selection gate transistor, a turn-on voltage and then a turn-off voltage are applied to the source end selection gate transistor, and a turn-off voltage is applied to the clamp transistor; in the second stage, a positive voltage is continued to be applied to the word line at the same time, a turn-off voltage is applied to the source end selection gate transistor, a turn-on voltage is continued to be applied to the drain end selection gate transistor, and a first turn-on voltage is applied to the clamp transistor; in the third stage, a positive voltage is continued to be applied to the word line at the same time, a turn-off voltage is continued to be applied to the source end selection gate transistor, a turn-on voltage is continued to be applied to the drain end selection gate transistor, and a turn-off voltage is applied to the clamp transistor; and in the fourth stage, multiple NAND strings are sensed at the same time, a positive voltage is continued to be applied to the word line, a turn-off voltage is continued to be applied to the source end selection gate transistor, a turn-on voltage is continued to be applied to the drain end selection gate transistor, and a second turn-on voltage is applied to the clamp transistor.

[0207] In another specific implementation, a method includes: performing a bit line precharge phase of a short detection operation for a plurality of NAND strings, the plurality of NAND strings being connected to a plurality of word lines and including shorted NAND strings and non-shorted NAND strings, each NAND string being connected to a corresponding bit line of a plurality of bit lines, each bit line being connected to a clamping transistor, the clamping transistor being configured to clamp a voltage of the bit line, and performing the bit line precharge phase includes biasing the clamping transistor to charge the bit lines of the non-shorted NAND strings while applying a positive voltage to the plurality of word lines; performing a bit line discharge phase of a short detection operation, performing the bit line discharge phase includes turning off the clamping transistor to discharge the bit lines of the non-shorted NAND strings while continuing to apply a positive voltage to the plurality of word lines; and performing a sensing phase of a short detection operation, performing the sensing phase includes connecting a sensing circuit to the bit lines of the non-shorted NAND strings and the bit lines of the shorted NAND strings while continuing to apply a positive voltage to the plurality of word lines.

[0208] In another specific implementation, an apparatus includes: a control circuit configured to be connected to a plurality of NAND strings, the plurality of NAND strings being connected to a plurality of word lines and including a first shorted NAND string shorted to a leakage word line among the plurality of word lines, a second shorted NAND string shorted to the first shorted NAND string, and a non-shorted NAND string that is not shorted to another NAND string, each NAND string being connected to a corresponding bit line among a plurality of bit lines; and a memory interface connected to the circuit, the circuit configured to issue a command via the memory interface to perform an operation of distinguishing the first shorted NAND string and the second shorted NAND string from the non-shorted NAND string, the operation involving sensing the plurality of NAND strings after precharging and discharging the bit lines connected to the non-shorted NAND strings, while charging the bit lines connected to the first shorted NAND string by a voltage applied to the leakage word line, the leakage word line being electrically connected to the bit line of the first shorted NAND string via a channel of the first shorted NAND string.

[0209] The above specific embodiments of the present invention have been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. In view of the above teachings, many modifications and variations are possible. The described embodiments are selected to best explain the principles of the present invention and its practical application, so that other technical personnel in the field can best utilize the present invention in various embodiments and in various modifications suitable for the intended specific use. The scope of the present invention is intended to be limited by the appended claims.

Claims

1. A device comprising: A control circuit configured to be connected to a plurality of NAND strings via a plurality of word lines and a plurality of bit lines, each NAND string including a memory cell between a source-end select gate transistor and a drain-end select gate transistor, the memory cell being connected to the plurality of word lines, each bit line being connected to a clamp transistor, the clamp transistor being configured to clamp a voltage of the bit line, and the control circuit for performing consecutive first, second, third, and fourth stages of a short-circuit detection operation is configured to: In the first stage, a positive voltage is applied to the word line, a turn-on voltage is applied to the drain end select gate transistor, a turn-on voltage and then a turn-off voltage are applied to the source end select gate transistor, and a turn-off voltage is applied to the clamp transistor simultaneously; In the second phase, while continuing to apply the positive voltage to the word line, applying the off voltage to the source end select gate transistor, applying the on voltage to the drain end select gate transistor, and applying the first on voltage to the clamp transistor; In the third phase, while continuing to apply the positive voltage to the word line, applying the turn-off voltage to the source end select gate transistor, applying the turn-on voltage to the drain end select gate transistor, and applying the turn-off voltage to the clamp transistor; as well as In the fourth phase, the plurality of NAND strings are sensed simultaneously, the positive voltage continues to be applied to the word line, the off voltage is applied to the source end select gate transistor, the on voltage is applied to the drain end select gate transistor, and a second on voltage is applied to the clamp transistor.

2. The device according to claim 1, wherein: The second on-voltage is greater than the first on-voltage.

3. The device according to claim 1, wherein: The positive voltage comprises a read pass voltage.

4. The device according to claim 1, wherein: The control circuit is configured to count a number of NAND strings in a non-conductive state among the plurality of NAND strings based on the sensing, and determine whether the number exceeds a threshold.

5. The device according to claim 1, wherein: The sensing of the plurality of NAND strings is performed simultaneously via the plurality of bit lines using all bit line sensing.

6. The device according to claim 1, wherein: The plurality of NAND strings include a short-circuited NAND string having a channel short-circuited to a word line.

7. The device according to claim 1, wherein: The plurality of NAND strings include a shorted NAND string having a bit line contact shorted to a bit line contact of another NAND string.

8. The device according to claim 7, wherein: The bit line contact of the one shorted NAND string is shorted with the bit line contact of the other shorted NAND string via a doped silicon region extending from the bit line contact of the one shorted NAND string to the bit line contact of the other shorted NAND string.

9. The device according to claim 1, wherein: The plurality of NAND strings include a shorted NAND string; During the sensing, a voltage of a bit line connected to the short-circuited NAND string is higher than a voltage of a non-short-circuited NAND string among the plurality of NAND strings; and The non-shorted NAND string is not shorted to another NAND string and is not shorted to a word line.

10. The device according to claim 1, wherein: The plurality of NAND strings include a shorted NAND string; a voltage of a bit line connected to a non-short-circuited NAND string among the plurality of NAND strings is boosted in the second phase and discharged in the third phase; Throughout the second phase and the third phase, the voltage of the bit line connected to the shorted NAND string is higher than the voltage of the non-shorted NAND string; and The non-shorted NAND strings include NAND strings that are not shorted to another NAND string and are not shorted to a word line.

11. A method comprising: performing a bitline precharge phase of a short detection operation for a plurality of NAND strings, the plurality of NAND strings being connected to a plurality of word lines and including shorted NAND strings and non-shorted NAND strings, each NAND string being connected to a respective bit line of a plurality of bit lines, each bit line being connected to a clamp transistor configured to clamp a voltage of the bit line, and performing the bitline precharge phase includes biasing the clamp transistor to charge the bit lines of the non-shorted NAND strings while applying a positive voltage to the plurality of word lines; performing a bit line discharge phase of the short detection operation, the performing the bit line discharge phase comprising turning off the clamp transistor to discharge the bit line of the non-short NAND string while continuing to apply a positive voltage to the plurality of word lines; as well as A sensing phase of the short detection operation is performed, the performing the sensing phase comprising connecting a sensing circuit to the bit line of the non-shorted NAND string and the bit line of the shorted NAND string while continuing to apply the positive voltage to the plurality of word lines.

12. The method of claim 11, wherein the plurality of NAND strings are located in a block, the method further comprising: Based on the sensing, counting the number of shorted NAND strings; as well as If the number exceeds a threshold, the block is determined to be unavailable.

13. The method according to claim 11, further comprising: Based on the sensing, the shorted NAND strings are distinguished from the non-shorted NAND strings.

14. The method according to claim 11, wherein: The shorted NAND string is sensed to be in a non-conductive state, and the non-shorted NAND string is sensed to be in a conductive state.

15. The method of claim 11, wherein: The shorted NAND string is shorted to a word line of the plurality of word lines; and The positive voltage applied to the word line charges the bit line of the shorted NAND string during the bit line precharge phase, the bit line discharge phase, and the sensing phase.

16. The method according to claim 11, further comprising: A channel pre-cleaning phase of the short detection operation is performed before the bit line pre-charge phase is performed, and the performing of the channel pre-cleaning phase includes starting to apply the positive voltage to the plurality of word lines while turning off the clamp transistor, biasing the drain side select gate transistor with a turn-on voltage, and biasing the source side select gate transistor of each NAND string with a turn-on voltage and then with a turn-off voltage.

17. An apparatus comprising: a control circuit configured to be connected to a plurality of NAND strings connected to a plurality of word lines and including a first short-circuited NAND string short-circuited to a leaky word line among the plurality of word lines, a second short-circuited NAND string short-circuited to the first short-circuited NAND string, and a non-short-circuited NAND string that is not short-circuited to another NAND string and is not short-circuited to a word line, each NAND string being connected to a corresponding bit line among a plurality of bit lines; and a memory interface connected to the circuit, the circuit being configured to issue a command via the memory interface to perform an operation of distinguishing the first shorted NAND string and the second shorted NAND string from the non-shorted NAND string, the operation involving sensing the plurality of NAND strings after precharging and discharging the bit lines connected to the non-shorted NAND strings, while charging the bit lines connected to the first shorted NAND string by a voltage applied to the leakage word line, the leakage word line being electrically connected to the bit line of the first shorted NAND string via a channel of the first shorted NAND string.

18. The device according to claim 17, wherein: The leakage word line is electrically connected to the bit line of the second shorted NAND string via a shorting path between a bit line contact of the first shorted NAND string and a bit line contact of the second shorted NAND string.

19. The device according to claim 18, wherein: The short circuit path includes a doped silicon region between the bit line contact of the first shorted NAND string and the bit line contact of the second shorted NAND string.

20. The apparatus of claim 17, wherein: The first shorted NAND string and the second shorted NAND string are located in a shorted NAND string cluster.

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