Semiconductor structure and method of forming a semiconductor device

Abstract

Embodiments of the present application provide a semiconductor structure including an n-type epitaxial source / drain feature (NEPI) and a p-type epitaxial source / drain feature (PEPI) located above a substrate, wherein a top surface of the NEPI is lower than a top surface of the PEPI. The semiconductor structure further includes a metal compound feature disposed on the top surface of the NEPI and the top surface of the PEPI, a contact feature disposed on the metal compound feature and above both the NEPI and the PEPI, and a via structure disposed above the contact feature and above the NEPI, wherein the via structure is partially located in the contact feature. According to other embodiments of the present application, methods of forming a semiconductor device are also provided.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming semiconductor devices. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each having greater functionality and smaller feature sizes than the previous generation. In the course of IC development, functionality has generally increased, while geometry size has decreased, resulting in a trend toward smaller, more complex circuits for each successive generation. This scaling of the IC geometry size benefits from advances in IC processing and design. One area of development is in source / drain (S / D) components and conductive components that land on the S / D components. For example, how the S / D components are formed can reduce series resistance between the S / D components and the conductive components. SUMMARY

[0003] According to embodiments of the present application, a semiconductor structure is provided, comprising: an n-type epitaxial source / drain component (NEPI) and a p-type epitaxial source / drain component (PEPI) located above a substrate, wherein a top surface of the n-type epitaxial source / drain component (NEPI) is lower than a top surface of the p-type epitaxial source / drain component (PEPI); a metal compound component disposed on the top surface of the n-type epitaxial source / drain component (NEPI) and on the top surface of the p-type epitaxial source / drain component (PEPI); a contact component disposed on the metal compound component and above both the n-type epitaxial source / drain component (NEPI) and the p-type epitaxial source / drain component (PEPI); and a via structure disposed above the contact component and above the n-type epitaxial source / drain component (NEPI), wherein the via structure is partially located in the contact component.

[0004] According to another embodiment of the present application, a semiconductor structure is provided, comprising: a first fin structure and a second fin structure located above a substrate; an n-type epitaxial source / drain component (NEPI) grown on a recessed portion of the first fin structure, wherein a height of the n-type epitaxial source / drain component (NEPI) is at least 1.5 times greater than a critical dimension (CD) of the n-type epitaxial source / drain component (NEPI) measured at a widest portion of the n-type epitaxial source / drain component (NEPI); a p-type epitaxial source / drain component (PEPI) grown on a recessed portion of the second fin structure, wherein an uppermost surface of the p-type epitaxial source / drain component (PEPI) is higher than an uppermost surface of the n-type epitaxial source / drain component (NEPI); a dielectric fin located above the substrate and between the n-type epitaxial source / drain component (NEPI) and the p-type epitaxial source / drain component (PEPI), wherein a shortest horizontal distance between the n-type epitaxial source / drain component (NEPI) and the dielectric fin is greater than a shortest horizontal distance between the p-type epitaxial source / drain component (PEPI) and the dielectric fin; a metal compound component disposed above the n-type epitaxial source / drain component (NEPI), the p-type epitaxial source / drain component (PEPI), and the dielectric fin; a contact component disposed on the metal compound component; and a via structure disposed above the contact component and directly above the n-type epitaxial source / drain component (NEPI), wherein the via structure extends partially into the contact component.

[0005] According to yet another embodiment of the present application, there is provided a method of forming a semiconductor device, comprising: providing a structure having a substrate, an isolation structure located above the substrate, a first semiconductor fin and a second semiconductor fin extending from the substrate and protruding above the isolation structure, a dielectric fin extending from between the isolation structure and the first and second semiconductor fins, and a first dielectric spacer and a second dielectric spacer located on sidewalls of the first and second semiconductor fins, respectively; forming a first etch mask covering the second semiconductor fin and the second dielectric spacer, and exposing the first semiconductor fin and the first dielectric spacer; etching the first semiconductor fin and the first dielectric spacer through the first etch mask, obtaining a recessed portion of the first semiconductor fin, wherein a remaining portion of the first dielectric spacer has a first height; epitaxially growing an n-type source / drain component on the recessed portion of the first semiconductor fin, wherein an uppermost surface of the n-type source / drain component is higher than an uppermost surface of the first semiconductor fin by a first raised height; removing the first etch mask; forming a second etch mask covering the n-type source / drain component, the first semiconductor fin, and the remaining portion of the first dielectric spacer, and exposing the second semiconductor fin and the second dielectric spacer; etching the second semiconductor fin and the second dielectric spacer through the second etch mask, obtaining a recessed portion of the second semiconductor fin, wherein a remaining portion of the second dielectric spacer has a second height, the second height being greater than the first height; and epitaxially growing a p-type source / drain component on the recessed portion of the second semiconductor fin, wherein an uppermost surface of the p-type source / drain component is higher than an uppermost surface of the second semiconductor fin by a second raised height, the second raised height being greater than the first raised height.

[0006] According to embodiments of the present application, there is also provided a source / drain EPI structure for improving contact quality. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings in which: It should be noted that, in accordance with standard practice in the industry, the various elements are not drawn to scale. In fact, the dimensions of the various elements can be arbitrarily increased or decreased for the sake of clarity in the discussion.

[0008] Figure 1A A perspective view of a semiconductor device showing portions thereof in a manufacturing stage according to embodiments of the present application;

[0009] Figure 1B-1 、 Figure 1B-2 、 Figure 1B-3 、 and Figure 1B-4 A perspective view of a semiconductor device showing portions thereof in a manufacturing stage according to embodiments of the present application, located in S / D regions and along BB lines in Figure 1A Figure 1A ​a cross-sectional view of a semiconductor device of the present application;

[0010] Figure 1C and Figure 1D shows a portion of a semiconductor device in a manufacturing stage according to an embodiment of the present application; Figure 1A a cross-sectional view of a semiconductor device of the present application and along Figure 1A the C-C line and the D-D line in FIG. 1, respectively;

[0011] Figure 2A and Figure 2B shows a flowchart of a method of forming a semiconductor device according to an embodiment of the present application;

[0012] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , and Figure 21 are cross-sectional views of a portion of a semiconductor device of the present application along Figure 2A-Figure 2B the B-B line in FIG. 1 during various manufacturing stages of the method according to Figure 1A Figure 1A

[0013] Figure 22 and Figure 23 shows some process conditions for forming NEPI and PEPI, respectively, according to an embodiment of the present application. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, the formation of a first component over or on a second component can include embodiments where the first component and the second component are formed in direct contact, and where additional components can be formed between them such that the first component and the second component are not in direct contact. In addition, the present application can be repeated with variations and / or modifications in various examples. This repetition is for the purpose of simplicity and clarity and does not indicate a relationship between the various embodiments and / or structural arrangements discussed. ​​

[0015] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to readily describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. Furthermore, when describing numbers or ranges of numbers using terms such as “approximately” or “about,” based on the specific techniques disclosed herein and the knowledge of those skilled in the art, the term covers numbers within certain variations (e.g., + / - 10% or other variations) of the described numbers, unless otherwise stated. For example, the term “about 5 nm” may cover a size range from 4.5 nm to 5.5 nm, from 4.0 nm to 5.0 nm, etc.

[0016] This application relates to semiconductor manufacturing processes and structures, and more specifically to providing epitaxially grown source / drain (S / D) structures that maintain the integrity of the metal compound components (e.g., silicides) formed thereon during the formation processes of S / D contacts and vias. Epitaxially grown S / D structures are also known as EPI structures. In advanced technology nodes, some transistors are formed above a single fin (i.e., with a channel, source, and drain formed on a single semiconductor fin). These devices typically have an n-type source / drain EPI structure (NEPI) that is much higher than a p-type source / drain EPI structure (PEPI) and the original fin. Due to the height of the NEPI structure, the metal compound components (e.g., TiSi) formed directly above the NEPI are also higher than the corresponding metal compound components formed directly above the PEPI. When forming S / D contact vias (i.e., vias falling on the S / D contacts), the vias may be formed very close to the metal compound components on the NEPI. This can cause problems. For example, during the formation of the S / D contact via, some chemical elements, such as fluorine, may diffuse into the metal compound component, thereby adversely increasing the resistivity of the metal compound component. The object of this invention is to solve the above-mentioned problems and other issues associated with single-fin FinFET structures in advanced technology nodes. These and other aspects of the invention will be referenced to a description of the structure of a single-fin FinFET and its formation process. Figure 1A-Figure 21 Further discussion is required. Those skilled in the art should understand that the disclosed structures and methods can be applied to other types of devices, such as GAA (all-ring grommet) devices (e.g., GAA nanowires or GAA nanosheets).

[0017] Figure 1AA perspective view of a portion of a semiconductor device 100 during the manufacturing stage, according to an embodiment of the present invention, is shown. Figure 1B-1 , Figure 1B-2 , Figure 1B-3 ,and Figure 1B-4 The following is illustrated according to some embodiments. Figure 1A A cross-sectional view of the semiconductor device 100 with the BB line. Figure 1C and Figure 1D The diagram shows the respective paths along one embodiment. Figure 1A A cross-sectional view of the semiconductor device 100, including portions of the CC and DD lines. The semiconductor device 100 (or device 100) is provided for illustrative purposes and is not intended to limit embodiments of the invention to any number of devices, any number of regions, or any configuration of structures or regions. Additionally, device 100 may be an intermediate device or structure manufactured during the processing of an IC or a portion thereof, and may include: static random access memory (SRAM) and / or logic circuitry; passive components, such as resistors, capacitors, and inductors; and active components, such as p-type field-effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs such as FinFETs, GAA devices, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and combinations thereof.

[0018] Overall reference Figure 1A , Figure 1B-1 , Figure 1C ,and Figure 1DIn the depicted embodiment, device 100 includes a CMOS transistor having both an NMOSFET (e.g., an NMOS FinFET) and a PMOSFET (e.g., a PMOS FinFET). Device 100 includes a substrate 102 and various features formed therein or on it. Device 100 also includes a semiconductor fin (or simply a fin) 103 extending from the substrate 102. The lower portion of the fin 103 is separated by an isolation structure 105. Device 100 also includes a gate stack (or gate structure) 106 adjacent to the channel region of the fin 103, and S / D components 104 located above the recessed portion of the fin 103 and on both sides of the gate stack 106. The S / D component of the NMOSFET is designated 104n, and the S / D component of the PMOSFET is designated 104p. Device 100 also includes a gate spacer 108 located on the sidewall of the gate stack 106, and a fin sidewall (FSW) spacer 107 located on the sidewall of the fin 103. The FSW spacer 107 on the sidewall of the fin 103 for the NMOSFET is designated as 107n, while the FSW spacer 107 on the sidewall of the fin 103 for the PMOSFET is designated as 107p. In the depicted embodiment, the FSW spacers 107n and 107p are disposed on the top surface of the isolation structure 105, and the FSW spacer 107n is shorter than the FSW spacer 107p. The channel regions of the NMOSFET and PMOSFET, as well as the S / D components 104n and 104p, are separated by dielectric fins 111 that extend partially into the isolation structure 105. Device 100 also includes one or more dielectric layers, such as a contact etch stop layer (CESL) 110 located above the gate spacer 108 and the S / D component 104, a dielectric layer (or interlayer dielectric layer or ILD) 112 located above the CESL 110 and filling the gap between adjacent gate spacers 108, and other dielectric layers 134, 136, and 138 disposed on the ILD 112. For simplicity, dielectric layers 110, 112, 134, 136, and 138 are... Figure 1A The device 100 is generally shown as a dashed block. Figure 1A Other features not shown in the image. (See reference) Figure 1B-1 The device 100 also includes a metal compound component 128 formed over the S / D components 104n and 104p and the dielectric fin 111. In one embodiment, the metal compound component 128 comprises a silicide, such as titanium silicide. Above the metal compound component 128, the device 100 also includes barrier layers 127 and 129, an S / D contact 130, and an S / D contact via plug 140. Various features (or components) of the device 100 are further described below.

[0019] In this embodiment, substrate 102 is a silicon (Si) substrate. In alternative embodiments, substrate 102 may comprise other elemental semiconductors, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP); or alloy semiconductors, such as silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), and indium gallium phosphide (GaInP). In embodiments, substrate 102 may comprise a silicon-on-insulator (SOI) substrate, strained and / or stress-treated to improve performance, including epitaxial regions, doped regions, and / or other suitable features and layers.

[0020] Fin 103 comprises one or more layers of semiconductor material such as silicon or silicon-germanium. In some embodiments (e.g., embodiments for GAA transistors), fin 103 comprises multiple layers of semiconductor material, one stacked on top of the other, for example, multiple layers of silicon and multiple layers of silicon-germanium stacked alternately. In this embodiment, as... Figure 1A and Figure 1B-1As shown, each fin 103 includes a base 103a above a substrate 102 and an upper portion 103b above the base 103a. In one embodiment, the base 103a is directly connected to the substrate 102, while the upper portion 103b is directly connected to the base 103a. In one embodiment, the base 103a comprises the same material as the substrate 102, while the upper portion 103b comprises a different material than the base 103a. For example, the base 103a comprises silicon, while the upper portion 103b comprises silicon-germanium or phosphorus-doped silicon. In one embodiment, the bottom surface of the upper portion 103b is approximately flush with the top surface of the isolation structure 105. Each fin 103 has a height H1, for example, from about 40 nm to about 80 nm. The upper portion 103b in each source / drain region is recessed (this portion of the upper portion 103b is referred to as the recessed upper portion 103b) and is lower than the upper portion 103b in the channel region. S / D components 104n and 104p are disposed on a recessed upper portion 103b. The recessed upper portion 103b located below S / D component 104p is higher than the recessed upper portion 103b located below S / D component 104n. The fin 103 can be patterned by any suitable method. For example, the fin 103 can be patterned using one or more photolithography processes that include dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches compared to those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used as mask elements to pattern the fin 103. For example, a mask element can be used to etch a recess into or into a semiconductor layer on or within the substrate 102, leaving the fin 103 on the substrate 102.

[0021] S / D components 104 (104n and 104p) may include epitaxial semiconductor materials, for example, to apply appropriate stress and enhance the performance of device 100. In this embodiment, S / D component 104n includes epitaxially grown silicon doped with one or more n-type dopants, such as arsenic (As) or phosphorus (P); while S / D component 104p includes epitaxially grown silicon-germanium (SiGe) alloy doped with one or more p-type dopants, such as boron (B) or indium (In). In this embodiment, each of S / D components 104n and 104p is grown on a single fin 103. This is advantageous for small devices such as SRAM cells, which can further increase device density. In one embodiment, S / D components 104n and 104p are formed by recessing and etching into the fin 103 and epitaxially growing Si or SiGe thereon. Additionally, each of S / D components 104n and 104p may include multiple layers. S / D component 104n has a strip shape, wherein its height is greater than its critical dimension (CD, which is the width of the widest part of the S / D component). S / D component 104p has a rhombus shape.

[0022] refer to Figure 1B-2 , Figure 1B-3 ,and Figure 1C (For simplicity, not all features are shown in these figures.) The uppermost surface of the S / D component 104n is higher by a dimension H5 than the uppermost surface of the fin 103 (the non-recessed portion of the fin 103, or the portion of the fin 103 located below the gate 106). This dimension is referred to as the rise height (RH). Reference Figure 1B-2 , Figure 1B-4 ,and Figure 1D (For simplicity, not all features are shown in these figures.) The uppermost surface of the S / D component 104p is higher by a dimension H6 than the uppermost surface of the fin 103 (the unrecessed portion of the fin 103, or the portion of the fin 103 located below the gate 106). In other words, the S / D component 104p has a height H6. In this embodiment, H6 is greater than H5. In one embodiment, H6 is about 2 nm or more greater than H5. In another embodiment, H6 is about twice the height of H5. In one embodiment, the height H5 is in the range of about 0 nm to about 5 nm, for example, in the range of about 0 nm to about 2 nm, while the height H6 is in the range of about 2 nm to about 10 nm. The above-described differences in the heights H5 and H6 ensure that the portion of the metal compound 128 directly above the S / D component 104n is lower than the portion of the metal compound component 128 directly above the S / D component 104p (see [reference]). Figure 1B-1 Furthermore, it further ensures sufficient clearance between the S / D contact through-hole plug 140 and the S / D component 104n. Figure 1B-1The size H4 is chosen to ensure that the metal compound component 128 is not adversely affected by the formation of the via plug 140. In one embodiment, the size H4 is about 5 nm to about 35 nm, which is sufficient to protect the metal compound component 128 during the formation of the via plug 140. For example, one method of forming the via plug 140 involves chemical vapor deposition using WF6 or WCl5. In this case, chemical elements (e.g., fluorine or chlorine) released during the formation of the via plug 140 will not diffuse into the metal compound component 128, thus maintaining the quality of the metal compound component 128. If the size H4 is too small (e.g., less than 5 nm), chemical elements (e.g., fluorine) released during the formation of the via plug 140 may diffuse into the metal compound component 128 and adversely increase the resistivity of the metal compound component 128. If H4 is too large (greater than 35 nm), the thickness of the ILD 112 and the vertical dimension of the device 100 will be unnecessarily increased. This will also increase the thickness of the S / D contact 130, which may adversely increase its resistance. It is worth noting that in this embodiment, the uppermost surfaces of the fins 103 below the gates 106 for the NMOSFET and PMOSFET are substantially coplanar. Therefore, the difference in rise heights H5 and H6 is also the difference in the top surfaces of the S / D components 104n and 104p. In other words, the uppermost surface of the S / D component 104p is higher than the uppermost surface of the S / D component 104n by an amount of (H6-H5). Furthermore, in the case where the NMOSFET and PMOSFET are GAA transistors, the uppermost surface of the fin 103 is the uppermost surface of the channel layer in the corresponding GAA transistor. Therefore, the above discussion of the difference in rise heights H5 and H6 also applies to embodiments with GAA transistors.

[0023] refer to Figure 1B-2 In this embodiment, S / D component 104n has a larger EPI volume than S / D component 104p. In one embodiment, S / D component 104n has a strip shape, wherein its height H1 is approximately 1.5 to 2 times larger than its critical dimension (CD) W1. (110) The Si facet remains along the "x" direction. S / D component 104p has a rhomboid shape, which has a CD of W2. In this embodiment, W2 is greater than W1. Therefore, the shortest horizontal distance D1 between S / D component 104n and the nearest dielectric fin 111 is greater than the shortest horizontal distance D2 between S / D component 104p and the same dielectric fin 111 or another nearest dielectric fin 111 (see Figure 1B-1When measured 1 nm below the uppermost surface of fin 103, S / D component 104n has a width W3, and S / D component 104p has a width W4. The surfaces of S / D components 104n and 104p on this plane are also referred to as the corresponding pressure plates of S / D components 104n and 104p. Width W3 is also the width of the pressure plate of S / D component 104n, and width W4 is also the width of the pressure plate of S / D component 104p. In one embodiment, width W4 is smaller than width W3. The pressure plates of S / D components 104n and 104p are designed to be larger so that the landing area for S / D contact 130 can be larger (to reduce the series resistance of S / D contact 130). In addition, in this embodiment, width W4 is about 2 to 4 times smaller than width W2 (therefore it is rhomboid). For example, width W4 can be in the range of about 10 nm to about 20 nm, while width W2 can be in the range of about 30 nm to about 60 nm. In one embodiment, the S / D component 104p maintains a (111) crystal plane on top to increase the contact landing area and reduce the S / D contact resistance. FSW spacer 107n (see...) Figure 1B-1 It has a height of H7. The FSW spacer is 107p (see...). Figure 1B-1 The component 104n has a height of H8. In one embodiment, H8 is 4 to 8 times larger than H7. For example, H8 can be about 10 nm to about 30 nm, while H7 can be about 2 nm to about 5 nm. Heights H7 and H8 are some of the factors that determine the profiles (e.g., their volume and height) of the S / D components 104n and 104p.

[0024] refer to Figure 1B-3 The S / D component 104n comprises multiple layers. In the depicted embodiment, the S / D component 104n includes layers 104n-1, 104n-2, 104n-3, and 104n-4. Layer 104n-1 is a seed layer for the subsequent layer 104n-2. Layer 104n-1 may comprise a single layer or multiple layers and may comprise Si, Si:As, Si:P, or other suitable materials. For example, layer 104n-1 may comprise Si:As, wherein the As dopant concentration in the Si may be approximately 5E10. 20 atoms / cm 3 approximately 2E10 21 atoms / cm 3 The range. For another example, layer 104n-1 may comprise Si:P, where the P dopant concentration in Si can be in the range of approximately 1E10. 20 atoms / cm 3 approximately 8E10 20 atoms / cm 3 The range is specified. In this embodiment, layer 104n-2 comprises Si:P, wherein the concentration of P dopant in Si can be within approximately 1E10.21 atoms / cm 3 approximately 2E10 21 atoms / cm 3 The range, and layer 104n-3 comprises Si:P, wherein the concentration of P dopant in Si can be approximately 1E10. 21 atoms / cm 3 To approximately 5E10 21 atoms / cm 3 The range is defined. In this embodiment, layer 104n-4 comprises P-doped SiGe to protect the S / D component 104n from, for example, Ge outward diffusion. In one embodiment, layer 104n-4 comprises P-doped SiGe, wherein the Ge atom percentage in SiGe is about 1% to 5%, and the P dopant concentration in SiGe can be about 1E10. 21 atoms / cm 3 approximately 2E10 21 atoms / cm 3 The range is specified. In one embodiment, layer 104n-1 has a thickness of about 3 nm to about 10 nm, layer 104n-2 has a thickness of about 10 nm to about 30 nm, layer 104n-3 has a thickness of about 10 nm to about 20 nm, and layer 104n-4 has a thickness of about 3 nm to about 10 nm. The layer thicknesses, material compositions, and dopant concentrations discussed above are designed to improve the profile of the S / D component 104n (e.g., formed as a strip, having a larger volume, etc.) and improve the conductivity and performance of the S / D component 104n.

[0025] refer to Figure 1B-4 The S / D component 104p comprises multiple layers. In the depicted embodiment, the S / D component 104p includes layers 104p-1, 104p-2, 104p-3, and 104p-4. Layer 104p-1 is a seed layer for the subsequent layer 104p-2. Layer 104p-1 may comprise a single layer or multiple layers and may comprise Si, SiGe, boron-doped SiGe, or other suitable materials. For example, layer 104p-1 may comprise SiGe:B, wherein the percentage of Ge atoms in SiGe may range from about 20% to about 40%, and the concentration of B dopant in SiGe may be about 1E10. 20 To approximately 5E10 20 atoms / cm 3 The range is defined in this embodiment. Layer 104p-2 comprises a gradient SiGe doped with B, wherein the percentage of Ge atoms in SiGe gradually increases from about 30% to about 45% as the thickness of SiGe increases, and the concentration of B dopant in SiGe can be around 1E10. 20 atoms / cm 3 To approximately 1E1021 atoms / cm 3 The range is specified. In this embodiment, layer 104p-3 comprises a relatively constant SiGe doped with B, wherein the percentage of Ge atoms in SiGe ranges from about 35% to about 65% and remains substantially constant with increasing layer thickness, and wherein the concentration of B dopant in SiGe can be around 1E10. 21 atoms / cm 3 approximately 3E10 21 atoms / cm 3 The range is defined. In this embodiment, layer 104p-4 comprises B-doped SiGe to protect the S / D component 104p from, for example, Ge outward diffusion and to prevent B accumulation. In one embodiment, layer 104p-4 comprises B-doped SiGe, wherein the percentage of Ge atoms in SiGe gradually decreases from about 65% to 40% as the thickness of SiGe increases, and the concentration of B dopant in SiGe can be around 1E10. 21 atoms / cm 3 approximately 2E10 21 atoms / cm 3 The range is defined as follows. In one embodiment, layer 104p-1 has a thickness of about 5 nm to about 20 nm, layer 104p-2 has a thickness of about 10 nm to about 30 nm, layer 104p-3 has a thickness of about 5 nm to about 25 nm, and layer 104p-4 has a thickness of about 2 nm to about 10 nm. The layer thicknesses, material compositions, and dopant concentrations discussed above are designed to improve the profile of the S / D component 104p (e.g., formed as a rhombus, with a larger pressure plate, etc.) and to improve the conductivity and performance of the S / D component 104p.

[0026] refer to Figure 1A and Figure 1B-1 The isolation structure 105 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), low-k dielectric material, and / or other suitable insulating material. In one embodiment, the isolation structure 105 is formed by etching trenches in or on the substrate 102 (e.g., as part of the process for forming the fin 103), filling the trenches with an insulating material, and performing a chemical mechanical planarization (CMP) process and / or an etch-back process on the insulating material, leaving the remaining insulating material as the isolation structure 105. Other types of isolation structures may also be applicable, such as field oxide and LOCal oxide of silicon (LOCOS). The isolation structure 105 may include a multilayer structure, for example, having one or more pad layers on the surfaces of the substrate 102 and the fin 103, and a main isolation layer located above the one or more pad layers.

[0027] refer to Figure 1A , Figure 1C ,and Figure 1D The gate stack 106 includes a multilayer structure. For example, reference... Figure 1C The gate stack 106 may include a dielectric interface layer (not shown), a gate dielectric layer 106A (e.g., having SiO2) above the dielectric interface layer, and a gate electrode layer 106B above the gate dielectric layer 106A. In one embodiment, the gate stack 106 includes a so-called "high-k metal gate," which may include a high-k gate dielectric layer 106A, a work function metal layer (a portion of the gate electrode layer 106B) above the high-k gate dielectric layer, and a body metal layer (another portion of the gate electrode layer 106B) above the work function metal layer. The gate stack 106 may include additional layers such as capping layers and barrier layers. In various embodiments, the dielectric interface layer may include a dielectric material such as silicon oxide (SiO2) or silicon oxynitride (SiON) and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k gate dielectric layer may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), other suitable metal oxides, or combinations thereof; and may be formed by ALD and / or other suitable methods. The work function metal layer may include n-type or p-type work function elements. n-type work function metals may include metals with sufficiently low effective work function, such as titanium, aluminum, tantalum carbide, tantalum nitride carbon, tantalum nitride silicon, or combinations thereof. p-type work function metals may include metals with sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. The work function metal may be deposited by CVD, PVD, and / or other suitable processes. The gate electrode layer may include polysilicon or metals such as aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials; and may be deposited using plating, CVD, PVD, or other suitable processes. The gate stack 106 can be formed using any suitable process including a gate-before-gate process and a gate-after-gate process. In the gate-before-gate process, various material layers are deposited and patterned to form the gate stack 106 before forming the S / D component 104. In the gate-after-gate process (also known as the gate replacement process), a sacrificial (or temporary) gate structure is formed first. Then, after forming the S / D component 104, the sacrificial gate structure is removed and replaced by the gate stack 106. Figure 1A In the depicted embodiment, the NMOSFET and PMOSFET share a common gate stack 106. In an alternative embodiment, the NMOSFET and PMOSFET have their own gate stack 106 and do not share a common gate stack.

[0028] refer to Figure 1A and Figure 1B-1 Each of the fin sidewall spacers 107 and the gate spacers 108 can be a single-layer or multi-layer structure. In some embodiments, each of the spacers 107 and 108 includes a dielectric material, such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), other dielectric materials, or combinations thereof. In one example, the spacers 107 and 108 are formed by depositing a first dielectric layer (e.g., a SiO2 layer of substantially uniform thickness) as a pad layer over the device 100, which includes the gate stack 106 and the fin 103, and a second dielectric layer (e.g., a Si3N4 layer) as a primary D-shaped spacer over the first dielectric layer, followed by anisotropic etching to remove portions of the dielectric layer to form the spacers 107 and 108. Alternatively, the fin sidewall spacers 107 can be partially removed during the etching process that forms recesses into the fin 103 prior to the growth of the S / D component 104. In some embodiments, the fin sidewall spacer 107 can be completely removed by such an etching process.

[0029] In this embodiment, the dielectric fin 111 includes multiple layers of dielectric material, such as layers 111a, 111b, and 111c. For example, layer 111a may include silicon nitride. For example, layer 111b may include a low-k dielectric material, such as a dielectric material including Si, O, N, and C. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, degel, aerogel, amorphous fluorinated carbon, parylene, BCB, polyimide, or combinations thereof. Low-k dielectric materials generally refer to dielectric materials with a low dielectric constant, for example, whose dielectric constant is lower than that of silicon oxide (k≈3.9). For example, layer 111c may include silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from tetraethyl orthosilicate (TEOS), PSG, BPSG, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The dielectric fins 111 can be deposited using CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof.

[0030] CESL110 may include silicon nitride (Si3N4), silicon oxynitride (SiON), silicon nitride containing oxygen (O) or carbon (C), and / or other materials. CESL110 may be formed by plasma-enhanced CVD (PECVD) and / or other suitable deposition or oxidation processes. CESL110 covers the outer surfaces of S / D component 104 and dielectric fin 111, the sidewalls of spacers 107 and 108, and the top surface of isolation structure 105.

[0031] ILD 112 may comprise materials such as oxides formed from TEOS, undoped silicate glass, or doped silicon oxides such as borosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. Dielectric layer 112 may be deposited using a PECVD process, a flowable CVD (FCVD) process, or other suitable deposition techniques. In one embodiment, CESL 110 is deposited as a conformal layer over substrate 102, covering various structures thereon, and dielectric layer 112 is deposited over CESL 110 to fill trenches between gate stacks 106. In one embodiment, dielectric layers 134 and 138 may comprise the same material as ILD 112, while dielectric layer 136 may comprise a material different from that in layers 134 and 138. For example, layers 134 and 138 may comprise silicon oxide, while layer 136 may comprise silicon nitride.

[0032] The metal compound component 128 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum nickel silicide (NiPtGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), titanium germanium silicide (TiSiGe), nickel germanium silicide (NiSiGe), nickel platinum germanium silicide (NiPtSiGe), ytterbium germanium silicide (YbSiGe), platinum germanium silicide (PtSiGe), iridium germanium silicide (IrSiGe), erbium germanium silicide (ErSiGe), cobalt germanium silicide (CoSiGe), or other suitable compounds. In one embodiment, the conductive barrier layer 127 comprises titanium silicon nitride (TiSiN), and the conductive barrier layer 129 comprises titanium nitride (TiN). Alternatively, each of the conductive barrier layers 127 and 129 may comprise titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium silicate nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof. In an embodiment, the S / D contact 130 may comprise tungsten (W), cobalt (Co), copper (Cu), other metals, metal nitrides, or a combination thereof. In an embodiment, the through-hole plug 140 may comprise tungsten (W), tungsten carbide (WC), cobalt (Co), other metals, metal nitrides, or a combination thereof. In one embodiment, the thickness H2 of the S / D contact 130 is from about 20 nm to about 40 nm, and the through-hole plug 140 extends partially into the S / D contact 130 to a depth H3 of about 5 nm to about 15 nm. Additionally, the bottom of the through-hole plug 140 extending into the S / D contact 130 has a circular shape, thus giving the through-hole plug 140 an overall profile with an anchoring shape. The depth H3 and circular bottom profile of the through-hole plug 140 ensure that the through-hole plug 140 has a large contact surface with the S / D contact 130 to reduce resistance.

[0033] Figure 2A-Figure 2B A flowchart of a method 10 for forming a semiconductor device 100 according to various aspects of the present invention is shown. Method 10 is merely an example and is not intended to limit the scope of the invention beyond that expressly stated in the claims. Other operations may be provided before, during, and after method 10, and some of the described operations may be replaced, canceled, or repositioned for other embodiments of the method. Method 10 is described below in conjunction with... Figure 3-Figure 21 Describe, Figure 3-Figure 21 It is along Figure 1A Cross-sectional views of semiconductor device 100 at various stages of the manufacturing process of the BB line.

[0034] In operation 12, method 10 ( Figure 2A ) provides such as Figure 3 The structure of device 100 shown. (Refer to...) Figure 3 Device 100 includes a substrate 102 and various features formed in or on the substrate 102. Device 100 includes one or more semiconductor fins 103 separated by an isolation structure 105. Each fin 103 includes a base 103a and a top 103b. In one embodiment, for an NMOSFET, both the base 103a and the top 103b are silicon, while for a PMOSFET, the base 103a is silicon and the top 103b is silicon-germanium. Device 100 also includes fin sidewall (FSW) spacers 107 located on the sidewalls of the fins 103. Figure 3 In the depicted embodiment, the FSW spacer 107 includes multiple layers 107a and 107b. For example, layer 107a may include silicon nitride, while layer 107b may include silicon oxycarbonitride, silicon carbonitride, or silicon dioxide. Device 100 also includes dielectric fins 111. Each dielectric fin 111 includes multiple dielectric layers, such as dielectric layers 111a, 111b, and 111c. The materials of the dielectric fins 111 have been discussed previously. The dielectric fins 111 extend partially into the isolation structure 105 and are disposed between two adjacent fins 103. In one embodiment, the dielectric fins 111 are formed by a method including: forming a sacrificial layer covering the top surface and sidewalls of the fins 103; partially etching the isolation structure 105 between portions of the sacrificial layer on adjacent fins 103; depositing dielectric layers 111a, 111b, and 111c between portions of the sacrificial layer on adjacent fins 103; and removing the sacrificial layer. Dielectric layers 111a, 111b, and 111c can be deposited using ALD, CVD, PVD, or other suitable methods. Although in Figure 3 Not shown, but device 100 also includes a gate stack (or gate structure) 106 adjacent to the channel region of fin 103, and a gate spacer 108 located on the sidewall of the gate stack 106 (see [reference]). Figure 1A In one embodiment, the gate stack 106 is a sacrificial structure that will be replaced by a high-k metal gate stack in subsequent processes of this embodiment. The sacrificial gate stack 106 may include a sacrificial gate dielectric layer 106A (e.g., silicon oxide) and a sacrificial gate electrode layer 106b (e.g., polysilicon). Various components 102, 103, 105, 106, 107, 108, and 111 have been referenced. Figure 1A A discussion was held.

[0035] In operation 14, method 10 ( Figure 2A Fins 103 (especially the upper 103b) are etched in the NMOS region to form S / D trenches 150n, for example.Figure 4 As shown. This may involve multiple processes, including photolithography and etching. For example, operation 14 can form an etching mask 290 that covers the area for PMOS and exposes the area for NMOS, for example... Figure 4 As shown. Mask 290 comprises a material different from that of fin 103 and FSW spacer 107 to achieve etch selectivity during subsequent etching. For example, mask 290 may comprise a resist material (and thus may be referred to as a patterned resist layer and / or a patterned photoresist layer). In some embodiments, mask 290 has a multilayer structure, such as a resist layer disposed over an antireflective coating (ARC) layer. Other materials for mask 290 are contemplated by the present invention, as long as the aforementioned etch selectivity is achieved. In some embodiments, operation 14 comprises a photolithography process including: forming a resist layer over device 100 (e.g., by spin coating), performing a pre-exposure baking process, performing an exposure process using a photolithographic mask, performing a post-exposure baking process, and developing the exposed resist layer in a developer. After development, the patterned resist layer (e.g., patterned mask 290) comprises a resist pattern corresponding to the photolithographic mask. Alternatively, the exposure process can be implemented or replaced by other methods such as maskless lithography, electron beam writing, ion beam writing, or combinations thereof.

[0036] With the etching mask 290 in place, operation 14 etches the fin 103 in the NMOS S / D region to make it recessed (in Figure 4 The original, unrecessed fins are shown in dashed lines (this is also the fin below the gate stack 106). The upper recessed portion 103b of the fin 103 in the NMOS S / D region is referred to as 103b'. The etching process also partially recesses the FSW spacer 107. The recessed FSW spacer 107 in the NMOS region is referred to as 107n. The FSW spacer 107n is recessed to a height H7 (see...). Figure 1B-2The top surface of the FSW spacer 107n is higher than the bottom surface of the S / D trench 150n. In this embodiment, the bottom surface of the S / D trench 150n is located above the top surface of the isolation structure 105, therefore, the bottom surface and sidewall surfaces of the S / D trench 150n are located within the upper portion 103b of the semiconductor fin 103. In an alternative embodiment, the bottom surface of the S / D trench 150n may extend below the top surface of the isolation structure 105. Operation 14 may apply dry etching, wet etching, or a combination thereof. After the etching process is completed, operation 14 may perform a cleaning process on the S / D trench 150n to prepare it for subsequent epitaxial growth processes. For example, the cleaning process may use an inductively coupled plasma having argon, NF3, NH3, or a combination thereof. In one embodiment, the cleaning process is performed at a temperature T0 in the range of room temperature (e.g., 25°C) to about 250°C, and for a duration t0 to t1 of about 80 seconds to about 400 seconds. Figure 22 As shown.

[0037] In operation 16, method 10 ( Figure 2A The S / D component 104n is epitaxially grown in the trench 150n. This involves multiple steps to grow multiple layers (104n-1, 104n-2, 104n-3, and 104n-4) of the S / D component 104n, which will be referenced below. Figure 5-Figure 7 and Figure 22 Let's have a discussion. Figure 22 The duration and temperature of each step in the process of operating 16 are shown.

[0038] like Figure 5 As shown, layer 104n-1 is grown on the recessed upper portion 103b' of the fin 103 in the S / D trench 150n. In one embodiment, operation 16 includes depositing a seed layer as layer 104n-1 using a precursor such as dichlorosilane (DCS), AsH3, HCl, and / or other suitable gases, and at a pressure of about 100 to about 600 torr. Furthermore, the deposition is performed at a temperature T1 in the range of about 600°C to about 700°C, and for a duration t1 to t2 of about 100 seconds to about 400 seconds, as... Figure 22 As shown. Then, in operation 16, for example, HCl is used, and an etching process is performed on the deposited seed layer under a pressure of about 100 to about 500 torr. Furthermore, the etching is performed at a temperature T2 in the range of about 650°C to about 750°C, and the duration t2 to t3 is about 10 seconds to about 80 seconds, as shown. Figure 22 As shown. Through the above deposition and etching, layer 104n-1 is grown to a thickness of about 3 nm to about 10 nm. In one embodiment, layer 104n-1 comprises Si:As, wherein the concentration of As dopant in Si can be about 5E10. 20atoms / cm 3 approximately 2E10 21 atoms / cm 3 The range. In another embodiment, layer 104n-1 comprises Si:P, wherein the concentration of P dopant in Si can be in the range of approximately 1E10. 20 atoms / cm 3 approximately 8E10 20 atoms / cm 3 The range.

[0039] like Figure 6 As shown, layers 104n-2 and 104n-3 are grown on layer 104n-1. In one embodiment, operation 16 includes depositing layers 104n-2 and 104n-3 using precursors such as SiH4, PH3, HCl, and / or other suitable gases, and at a pressure of about 100 to about 600 torr. A combination of PH3 and SiH4 is used to increase P doping in layers 104n-2 and 104n-3 to enhance performance. Furthermore, the deposition is performed at a temperature T3 in the range of about 600°C to about 700°C, and for a duration of about 50 seconds to about 300 seconds from t3 to t4. Figure 22 As shown. Then, operation 16, for example using HCl, SiH4, and / or other suitable etchants, and under a pressure of about 100 to about 500 torr, etches the deposited layer. The etching is performed at a temperature T3 in the range of about 600°C to about 700°C, and for a duration t4 to t5 of about 10 seconds to about 80 seconds. Through the above deposition and etching, layer 104n-2 grows to a thickness of about 10 nm to about 30 nm, and layer 104n-3 grows to a thickness of about 10 nm to about 20 nm. In one embodiment, layer 104n-2 comprises Si:P, wherein the concentration of the P dopant in Si can be about 1E10. 21 atoms / cm 3 approximately 2E10 21 atoms / cm 3 The range, and layer 104n-3 comprises Si:P, wherein the concentration of P dopant in Si can be approximately 1E10. 21 To approximately 5E10 21 atoms / cm 3 The range.

[0040] like Figure 7As shown, layer 104n-4 is grown on layer 104n-3. In one embodiment, operation 16 includes depositing layer 104n-4 using a precursor such as DCS, PH3, HCl, and / or other suitable gases, and at a pressure of about 100 torr to about 600 torr. Furthermore, the deposition is performed at a temperature T4 in the range of about 650°C to about 750°C, and for a duration t5 to t6 of about 20 seconds to about 100 seconds, as... Figure 22 As shown. Then, operation 16, for example, using HCl, GeH4 and / or other suitable etchants, and at a pressure of about 5 to about 50 torr, performs an etching process on the deposited layer. Additionally, the etching is performed at a temperature T5 in the range of about 700°C to about 780°C, and the duration t6 to t7 is about 20 seconds to about 80 seconds, as shown. Figure 22 As shown. Through the above deposition and etching, layer 104n-4 is grown to a thickness of about 3 nm to about 10 nm. In one embodiment, layer 104n-4 comprises P-doped SiGe, wherein the Ge atom percentage in SiGe is about 1% to 5%, and the P dopant concentration in SiGe can be about 1E10. 21 atoms / cm 3 approximately 2E10 21 atoms / cm 3 The range. When layers 104n-1, 104n-2, 104n-3, and 104n-4 are formed during the various deposition and etching processes discussed above, operation 16 can use H2 or N2 gas as a carrier gas for the precursor and etchant. Additionally, in one embodiment, the various temperatures have the following relationship: T5 > T4 > T3, T3 < T1 ≤ T2, and T3 > T0.

[0041] In operation 18, method 10 ( Figure 2A In the PMOS region, fins 103 (particularly the upper 103b) are etched to form S / D trenches 150p. This may involve multiple processes, including photolithography and etching. For example, in operation 18, the etching mask 290 is removed from the PMOS region using, for example, resist stripping, ashing, or other suitable methods. Operation 18 then forms an etching mask 292 that covers the region for NMOS and exposes the region for PMOS, for example... Figure 8 As shown. The materials and forming process used for etching mask 292 can be the same as those used for etching mask 290. Then, with etching mask 292 in place, operation 18 etches fin 103 in the PMOS S / D region to make it recessed (in Figure 9The original, unrecessed fins are shown in dashed lines (this is also the fin below the gate stack 106). The upper recessed portion 103b of the fin 103 in the PMOS S / D region is referred to as 103b". In this embodiment, the upper recessed portion 103b" in the PMOS region is higher than the upper recessed portion 103b' in the NMOS region. The etching process also partially recesses the FSW spacer 107. The FSW spacer 107 recessed in the PMOS region is referred to as 107p. The FSW spacer 107p is recessed to a height H8 (see...). Figure 1B-2 The height H8 is greater than the height H7. The top surface of the FSW spacer 107p is higher than the bottom surface of the S / D trench 150p. In this embodiment, the bottom surface of the S / D trench 150p is located above the top surface of the isolation structure 105, therefore, the bottom surface and sidewall surface of the S / D trench 150p are located within the upper portion 103b of the semiconductor fin 103. Operation 18 can apply dry etching, wet etching, or a combination thereof. After the etching process is completed, operation 18 can perform a cleaning process on the S / D trench 150p to prepare it for subsequent epitaxial growth processes. For example, the cleaning process can use an inductively coupled plasma containing argon, NF3, NH3, or a combination thereof. In one embodiment, the cleaning process is performed at a temperature T6 in the range of room temperature (e.g., 25°C) to about 250°C for a duration of about 80 seconds to about 400 seconds from t8 to t9. Figure 23 As shown.

[0042] In operation 20, method 10 ( Figure 2A The S / D component 104p is epitaxially grown in the trench 150p. This involves multiple steps to grow multiple layers (104p-1, 104p-2, 104p-3, and 104p-4) of the S / D component 104p, which will be referenced below. Figure 10-Figure 13 and Figure 23 Let's have a discussion. Figure 23 The duration and temperature of each step of the process used in operation 20 are shown.

[0043] like Figure 10 As shown, layer 104p-1 is grown on the recessed portion 103b” of the fin 103 in the S / D trench 150p. In one embodiment, operation 20 includes depositing a seed layer as layer 104p-1 using a precursor such as DCS, GeH4, HCl, and / or other suitable gases. Furthermore, the deposition is performed at a temperature T7 in the range of about 600°C to about 650°C, and for a duration t9 to t10 of about 30 seconds to about 80 seconds. Figure 23As shown. Through the above deposition, layer 104p-1 is grown to a thickness of about 5 nm to about 20 nm. In one embodiment, layer 104p-1 comprises SiGe:B, wherein the percentage of Ge atoms in SiGe is in the range of about 20% to about 40%, and the concentration of B dopant in SiGe is about 1E10. 20 atoms / cm 3 To approximately 5E10 20 atoms / cm 3 The range.

[0044] like Figure 11 As shown, layer 104p-2 is grown on layer 104p-1. In one embodiment, operation 20 includes depositing layer 104p-2 using a precursor such as DCS, SiH4, GeH4, HCl, B2H6, and / or other suitable gases. Furthermore, the deposition is performed at a temperature T8 in the range of about 600°C to about 650°C, and for a duration t10 to t11 of about 30 seconds to about 80 seconds. Figure 23 As shown. Then, operation 20, for example using HCl, is used to perform an etching process on the deposited layer. Furthermore, the etching is performed at a temperature T8 in the range of approximately 600°C to approximately 650°C, and the duration t11 to t12 is approximately 5 seconds to approximately 20 seconds, as shown. Figure 23 As shown. Through the above deposition and etching, layer 104p-2 is grown to a thickness of about 10 nm to about 30 nm. In one embodiment, layer 104p-2 comprises a gradient SiGe doped with B, wherein the percentage of Ge atoms in SiGe gradually increases from about 30% to about 45% as the thickness of SiGe increases, and the concentration of B dopant in SiGe can be about 1E10. 20 atoms / cm 3 To approximately 1E10 21 atoms / cm 3 The range.

[0045] like Figure 12 As shown, layer 104p-3 is grown on layer 104p-2. In one embodiment, operation 20 includes depositing layer 104p-3 using a precursor such as DCS, GeH4, HCl, B2H6, and / or other suitable gases. Furthermore, the deposition is performed at a temperature T9 in the range of about 600°C to about 650°C, and for a duration t12 to t13 of about 50 seconds to about 300 seconds, as shown. Figure 23 As shown. Then, operation 20, for example using HCl, is used to perform an etching process on the deposited layer. Furthermore, the etching is performed at a temperature T10 in the range of approximately 600°C to approximately 650°C, and the duration t13 to t14 is approximately 10 seconds to approximately 80 seconds, as shown. Figure 23As shown. Through the above deposition and etching, layer 104p-3 is grown to a thickness of about 5 nm to about 25 nm. In one embodiment, layer 104p-3 comprises a relatively constant SiGe doped with B, wherein the percentage of Ge atoms in SiGe is in the range of about 35% to about 65% and remains substantially constant as the layer thickness increases, and wherein the concentration of B dopant in SiGe can be about 1E10. 21 atoms / cm 3 approximately 3E10 21 atoms / cm 3 The range.

[0046] like Figure 13 As shown, layer 104p-4 is grown on layer 104p-3. In one embodiment, operation 20 includes depositing layer 104p-4 using a precursor such as DCS, GeH4, HCl, B2H6, and / or other suitable gases. Furthermore, the deposition is performed at a temperature T11 in the range of about 600°C to about 650°C, and for a duration t14 to t15 of about 20 seconds to about 100 seconds, as shown. Figure 23 As shown. Then, operation 20 uses, for example, HCl, GeH4, and / or other suitable etchants to perform an etching process on the deposited layer. Furthermore, the etching is performed at a temperature T11 in the range of about 600°C to about 650°C, and the duration t15 to t16 is about 10 seconds to about 50 seconds, as shown. Figure 23 As shown.

[0047] In one embodiment, the deposition and etching process described above is repeated several times in a cyclic manner to form layer 104p-4. Through the deposition and etching process, layer 104p-4 grows to a thickness of approximately 2 nm to approximately 10 nm. In one embodiment, layer 104p-4 comprises boron-doped SiGe, wherein the percentage of Ge atoms in SiGe gradually decreases from approximately 65% ​​to 40% as the thickness of SiGe increases, and the boron dopant concentration in SiGe can be approximately 1E10. 21 atoms / cm 3 approximately 2E10 21 atoms / cm 3The range. When layers 104p-1, 104p-2, 104p-3, and 104p-4 are formed during the various deposition and etching processes discussed above, operation 20 may use H2 gas as a carrier gas, having a pressure in the range of about 10 torr to about 50 torr, for the precursor and etchant. Additionally, in one embodiment, the various temperatures have the following relationship: T9 > T8 > T7, T9 > T10 and T11, and T6 is lower than T7 to T11. After forming layer 104p-4, operation 20 removes the etch mask 292, for example, by resist stripping, ashing, or other suitable methods. The resulting structure of device 100 is shown in Figure 14 .

[0048] In the above embodiments, method 10 forms S / D component 104n before forming S / D component 104p. In alternative embodiments, method 10 may form S / D component 104p before forming S / D component 104n. In other words, operations 18 and 20 may be performed before operations 14 and 16.

[0049] In operation 22, method 10 ( Figure 2A Forming CESL110 and ILD layer 112, for example Figure 15 As shown. For example, CESL110 can be deposited above various surfaces of S / D components 104n and 104p, FSW spacer 107, gate spacer 108, and sacrificial gate stack 106. Then, ILD layer 112 is deposited over CESL110 and fills the spaces between the various structures. Operation 22 can implement a CMP process to planarize the top surface of ILD layer 112 and expose sacrificial gate stack 106 for gate replacement processes. CESL110 may include silicon nitride (Si3N4), silicon oxynitride (SiON), silicon nitride having oxygen (O) or carbon (C) elements, and / or other materials. CESL110 can be formed by plasma-enhanced CVD (PECVD) processes and / or other suitable deposition or oxidation processes. ILD 112 may comprise materials such as oxides formed from TEOS, undoped silicate glass, or doped silicon oxides such as borosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. ILD layer 112 may be deposited using PECVD, flowable CVD (FCVD), or other suitable deposition techniques.

[0050] In operation 24, method 10 ( Figure 2AThe sacrificial gate stack 106 is replaced with a functional gate stack 106. For example, operation 24 may perform one or more etching processes to remove the sacrificial gate stack 106, obtain a gate trench, and deposit the functional gate stack 106 into the gate trench.

[0051] In operation 26, in one embodiment, method 10 ( Figure 2B Etching S / D contact trenches 156 through ILD layers 112 and CESL 110 to expose S / D components 104n and / or 104p, for example... Figure 16 As shown. In one embodiment, an etching mask is formed over device 100, providing openings to expose various portions of device 100. These openings correspond to areas of device 100 for forming S / D contacts for S / D components 104n and 104p. Subsequently, device 100 is etched through the openings to remove exposed portions of ILD layers 112 and CESL 110, for example using a dry etching process, a wet etching process, a reactive ion etching process, other suitable etching processes, or combinations thereof. In one embodiment, layers 104n-4 and 104p-4 can be etched by an etching process. In one embodiment, the depth of trench 156 is in the range of about 20 nm to about 40 nm to provide a sufficiently large trench for the formation of S / D contacts.

[0052] In operation 28, method 10 ( Figure 2B Metal compound 128 is formed above S / D components 104n and 104p, for example... Figure 17As shown. In one embodiment, operation 28 includes depositing one or more metals into contact trench 156, annealing device 100 to react one or more metals with semiconductor materials in S / D components 104n and 104p to form metal compound components 128, and removing unreacted metal (some). In this embodiment, since the top surface of PEPI 104p is slightly higher than the top surface of NEPI 104n, the portion of metal compound 128 on PEPI 104p is slightly higher than the portion of metal compound 128 on NEPI 104n. In one embodiment, one or more metals also react with materials (e.g., Si) in ILD 112 and / or dielectric fins 111 to also form metal compound components 128 on ILD 112 and / or dielectric fins 111. For example, when titanium is deposited into contact trench 156, titanium nitride (TiN) can be formed on ILD 112, and titanium silicon nitride (TiSiN) can be formed on dielectric fins 111. It is worth noting that the metal compound component 128 may include different materials in different portions. For example, it may include silicides (e.g., TiSi or other metal semiconductor compounds) located above the S / D components 104n and 104p, and different compounds (e.g., TiN or TiSiN) located above the ILD 112 and dielectric fins 111. One or more metals may include titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or combinations thereof (e.g., alloys of two or more metals), and may be deposited using CVD, PVD, ALD, or other suitable methods. The metal compound component 128 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum nickel silicide (NiPtGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), titanium germanium silicide (TiSiGe), nickel germanium silicide (NiSiGe), nickel germanium silicide platinum silicide (NiPtSiGe), ytterbium germanium silicide (YbSiGe), platinum germanium silicide (PtSiGe), iridium germanium silicide (IrSiGe), erbium germanium silicide (ErSiGe), cobalt germanium silicide (CoSiGe), or other suitable compounds.

[0053] In operation 30, method 10 ( Figure 2B Barrier layers 127, 129 and S / D contacts 130 are formed above the metal compound component 128 and in the contact trench 156, for example... Figure 18As shown. For example, operation 30 can use ALD, CVD, PVD, plating, and / or other suitable processes to deposit barrier layers 127, 129 and S / D contact 130. A CMP process can be implemented to planarize the top surface of device 100 and remove excess portions of the metal material. In one embodiment, barrier layer 127 comprises titanium silicon nitride (TiSiN), and barrier layer 129 comprises titanium nitride (TiN). Alternatively, each of barrier layers 127 and 129 may comprise titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof. In an embodiment, S / D contact 130 may comprise tungsten (W), cobalt (Co), copper (Cu), other metals, metal nitrides, or combinations thereof.

[0054] In operation 32, method 10 ( Figure 2B Dielectric layers 134, 136, and 138 are deposited over the ILD layer 112 and the S / D contact 130, for example... Figure 19 As shown. Dielectric layers 134, 136, and 138 can be deposited using PECVD, flowable CVD (FCVD), or other suitable deposition techniques. In one embodiment, dielectric layers 134 and 138 may comprise TEOS-formed oxides, undoped silicate glass, or doped silicon oxides such as BPSG, FSG, PSG, BSG, and / or other suitable dielectric materials. Dielectric layer 136 comprises a material different from that in layers 134 and 138. For example, layers 134 and 138 may comprise silicon oxide, while layer 136 may comprise silicon nitride (Si3N4), silicon oxynitride (SiON), silicon nitride having oxygen (O) or carbon (C) elements, and / or other materials.

[0055] In operation 34, method 10 ( Figure 2B Etched via 139, which extends through dielectric layers 138, 136, and 134 and partially extends into S / D contact 130, for example... Figure 20As shown. In one embodiment, the via 139 extends partially into the S / D contact 130 to a depth H3 ranging from about 5 nm to about 15 nm, leaving a gap H4 between the bottom of the via 139 and the top surface of the NEPI104n and / or the metal compound component 128. The gap H4 is at least 5 nm for reasons previously discussed. Additionally, the bottom of the via 139 has a circular profile within the S / D contact 130 to increase the surface area of ​​the via 139. For example, operation 34 may perform anisotropic etching (e.g., anisotropic dry etching) to open dielectric layers 138, 136, and 134, followed by isotropic etching (e.g., isotropic wet etching) to etch the S / D contact 130 to form the via 139 with the depicted profile. Operation 34 may further perform O2 ashing and pre-cleaning of the via 139 to facilitate metal deposition in operation 36 on the surface of the via 139.

[0056] In operation 36, method 10 ( Figure 2B A through-hole plug 140 is formed in the through-hole 139, for example... Figure 21 As shown. In one embodiment, the via plug 140 is formed unobstructed. In other words, there is no obstruction layer between the via plug 140 and the S / D contact 130 (i.e., the via plug 140 directly contacts the S / D contact 130), which advantageously reduces the resistance between the via plug 140 and the S / D contact 130. Additionally, there is no obstruction layer between the via plug 140 and the dielectric layers 138, 136, 134. Operation 36 may deposit one or more metals or metal compounds into the via 139 and perform a CMP process on one or more metals or metal compounds. The remaining portion of the one or more metals or metal compounds forms the via plug 140. In one embodiment, operation 36 uses selective metal deposition techniques to deposit one or more metals or metal compounds. In another embodiment, operation 36 performs ion implantation (e.g., with Ge ions) to the sidewalls of the dielectric layers 138, 136, 134 surrounding the via plug 140. The injected sidewalls are used to seal the metallic elements of the through-hole plug 140 and prevent them from diffusing into the dielectric layers 138, 136, and 134. In embodiments, the through-hole plug 140 may include tungsten (W), tungsten carbide (WC), cobalt (Co), other metals, metal nitrides, or combinations thereof; and may be deposited using ALD, CVD, PVD, plating, and / or other suitable processes.

[0057] In operation 38, method 10 ( Figure 2B Other steps may be performed to complete the fabrication of device 100. For example, various processes may be implemented to form metal interconnects connecting transistors and other parts of device 100 to form a complete IC.

[0058] While not intended to be limiting, one or more embodiments of the present invention provide numerous benefits for semiconductor devices and their fabrication processes. For example, embodiments of the present invention form NEPI and PEPI structures such that the NEPI structure is larger but slightly lower than the PEPI. The NEPI and PEPI structures allow S / D contacts and S / D contact via plugs to be formed without damaging the metal compound components on the NEPI and PEPI, particularly when the S / D contact via plugs are partially embedded in the S / D contacts. Both NEPI and PEPI have large pressure plates to expand the contact landing area. Furthermore, the provided subject matter can be easily integrated into existing IC manufacturing processes and can be applied to many different process nodes.

[0059] In one example aspect, the present invention relates to a semiconductor structure comprising: an n-type epitaxial source / drain component (NEPI) and a p-type epitaxial source / drain component (PEPI) located above a substrate, wherein the top surface of the NEPI is lower than the top surface of the PEPI. The semiconductor structure further comprises: a metal compound component disposed on the top surfaces of the NEPI and the PEPI; a contact component disposed on the metal compound component and above both the NEPI and the PEPI; and a via structure disposed above the contact component and above the NEPI, wherein the via structure is partially located within the contact component.

[0060] In one embodiment of the semiconductor structure, the shortest distance between the via structure and the metal compound component is at least 5 nm. In another embodiment, the total volume of NEPI is greater than the total volume of PEPI.

[0061] In one embodiment, the semiconductor structure further includes: dielectric fins located above the substrate and between the NEPI and PEPI, wherein the shortest horizontal distance between the NEPI and the dielectric fins is greater than the shortest horizontal distance between the PEPI and the dielectric fins. In another embodiment, the semiconductor structure further includes: one or more dielectric layers surrounding the NEPI, PEPI, metal compound component, contact component, and via structure; and a barrier layer disposed between the contact component and one or more dielectric layers, wherein the via structure directly contacts the contact component and one or more dielectric layers. In one embodiment, the via structure extends into the contact component from about 5 nm to about 15 nm.

[0062] In one embodiment, the semiconductor structure further includes: a first fin structure and a second fin structure, located above a substrate, wherein NEPI is grown above a recessed portion of the first fin structure, and PEPI is grown above a recessed portion of the second fin structure; a first sidewall spacer disposed along a sidewall of the recessed portion of the first fin structure; and a second sidewall spacer disposed along a sidewall of the recessed portion of the second fin structure; wherein the second sidewall spacer is higher than the first sidewall spacer. In another embodiment, the second sidewall spacer is four to eight times higher than the first sidewall spacer.

[0063] In another embodiment, the top surface of the NEPI is higher than the uppermost surface of the first fin structure by a first elevation height, and the top surface of the PEPI is higher than the uppermost surface of the second fin structure by a second elevation height, wherein the second elevation height is greater than the first elevation height. In another embodiment, the second elevation height is at least 2 nm greater than the first elevation height. In another embodiment, the first width of the NEPI measured 1 nm below the uppermost surface of the first fin structure is greater than the second width of the PEPI measured 1 nm below the uppermost surface of the second fin structure.

[0064] In another example, the invention relates to a semiconductor structure comprising: a first fin structure and a second fin structure, located above a substrate; an n-type epitaxial source / drain component (NEPI) grown on a recessed portion of the first fin structure, wherein the height of the NEPI is at least 1.5 times larger than the critical dimension (CD) of the NEPI measured at its widest portion; and a p-type epitaxial source / drain component (PEPI) grown on a recessed portion of the second fin structure, wherein the uppermost surface of the PEPI is higher than the uppermost surface of the NEPI. The semiconductor structure further comprises: a dielectric fin, located above the substrate and between the NEPI and the PEPI, wherein the shortest horizontal distance between the NEPI and the dielectric fin is greater than the shortest horizontal distance between the PEPI and the dielectric fin. The semiconductor structure further comprises: a metal compound component disposed above the NEPI, the PEPI, and the dielectric fin; a contact component disposed on the metal compound component; and a via structure disposed above the contact component and directly above the NEPI, wherein the via structure extends partially into the contact component.

[0065] In one embodiment, the shortest distance between the through-hole structure and the metal compound component is at least 5 nm. In another embodiment, the first width of the NEPI measured 1 nm below the uppermost surface of the first fin structure is greater than the second width of the PEPI measured 1 nm below the uppermost surface of the second fin structure.

[0066] In one embodiment, the uppermost surface of the NEPI is higher than the uppermost surface of the first fin structure by a first elevation height, and the uppermost surface of the PEPI is higher than the uppermost surface of the second fin structure by a second elevation height, wherein the second elevation height is at least 2 nm greater than the first elevation height.

[0067] In one embodiment, the semiconductor structure further includes: a first sidewall spacer disposed along the sidewall of a recessed portion of the first fin structure; and a second sidewall spacer disposed along the sidewall of a recessed portion of the second fin structure, wherein the second sidewall spacer is higher than the first sidewall spacer.

[0068] In another example, the invention relates to a method comprising: providing a structure having a substrate, an isolation structure located above the substrate, a first semiconductor fin and a second semiconductor fin extending from the substrate and protruding above the isolation structure, a dielectric fin extending from the isolation structure and between the first semiconductor fin and the second semiconductor fin, and a first dielectric spacer and a second dielectric spacer respectively located on sidewalls of the first semiconductor fin and the second semiconductor fin. The method further comprises: forming a first etch mask that covers the second semiconductor fin and the second dielectric spacer and exposes the first semiconductor fin and the first dielectric spacer; etching the first semiconductor fin and the first dielectric spacer through the first etch mask to obtain a recessed portion of the first semiconductor fin, wherein the remaining portion of the first dielectric spacer has a first height. The method further comprises: epitaxially growing an n-type source / drain component on the recessed portion of the first semiconductor fin, wherein the uppermost surface of the n-type source / drain component is higher than the uppermost surface of the first semiconductor fin by a first height increase. The method further includes: removing a first etch mask; and forming a second etch mask that covers the remaining portions of the n-type source / drain component, the first semiconductor fin, and the first dielectric spacer, and exposes the second semiconductor fin and the second dielectric spacer; etching the second semiconductor fin and the second dielectric spacer through the second etch mask to obtain a recessed portion of the second semiconductor fin, wherein the remaining portion of the second dielectric spacer has a second height, which is greater than the first height. The method further includes: epitaxially growing a p-type source / drain component on the recessed portion of the second semiconductor fin, wherein the uppermost surface of the p-type source / drain component is higher than the uppermost surface of the second semiconductor fin by a second height increase, which is greater than the first height increase.

[0069] In one embodiment, the method further includes: forming one or more dielectric layers over the n-type source / drain component, the p-type source / drain component, and the dielectric fin; etching contact holes in the one or more dielectric layers to expose the uppermost surfaces of the n-type source / drain component and the p-type source / drain component; forming metal compound components on the uppermost surfaces of the n-type source / drain component and the p-type source / drain component; forming contact components over the metal compound components and in the contact holes; and forming via structures over the contact components and extending partially into the contact components. In another embodiment, forming the via structure includes: etching holes into the contact components, wherein the bottom surface of the holes is perpendicularly spaced from the metal compound components by at least 5 nm, and depositing via metal into the holes. In one embodiment, the metal compound components are also formed directly above the dielectric fin.

[0070] According to one embodiment of this application, a semiconductor structure is provided, comprising: an n-type epitaxial source / drain device (NEPI) and a p-type epitaxial source / drain device (PEPI) located above a substrate, wherein the top surface of the n-type epitaxial source / drain device (NEPI) is lower than the top surface of the p-type epitaxial source / drain device (PEPI); a metal compound device disposed on the top surfaces of the n-type epitaxial source / drain device (NEPI) and the p-type epitaxial source / drain device (PEPI); a contact device disposed on the metal compound device and above both the n-type epitaxial source / drain device (NEPI) and the p-type epitaxial source / drain device (PEPI); and a via structure disposed above the contact device and above the n-type epitaxial source / drain device (NEPI), wherein the via structure is partially located in the contact device. In some embodiments, the shortest distance between the via structure and the metal compound device is at least 5 nm. In some embodiments, the total volume of the n-type epitaxial source / drain device (NEPI) is greater than the total volume of the p-type epitaxial source / drain device (PEPI). In some embodiments, the semiconductor structure further includes: dielectric fins located above the substrate and between the n-type epitaxial source / drain device (NEPI) and the p-type epitaxial source / drain device (PEPI), wherein the shortest horizontal distance between the n-type epitaxial source / drain device (NEPI) and the dielectric fins is greater than the shortest horizontal distance between the p-type epitaxial source / drain device (PEPI) and the dielectric fins. In some embodiments, the semiconductor structure further includes: one or more dielectric layers surrounding the n-type epitaxial source / drain device (NEPI), the p-type epitaxial source / drain device (PEPI), the metal compound device, the contact device, and the via structure; and a barrier layer disposed between the contact device and one or more dielectric layers, wherein the via structure directly contacts the contact device and one or more dielectric layers. In some embodiments, the via structure extends into the contact device from about 5 nm to about 15 nm. In some embodiments, the semiconductor structure further includes: a first fin structure and a second fin structure, located above a substrate, wherein an n-type epitaxial source / drain component (NEPI) is grown above a recessed portion of the first fin structure, and a p-type epitaxial source / drain component (PEPI) is grown above a recessed portion of the second fin structure; a first sidewall spacer disposed along a sidewall of the recessed portion of the first fin structure; and a second sidewall spacer disposed along a sidewall of the recessed portion of the second fin structure; wherein the second sidewall spacer is higher than the first sidewall spacer. In some embodiments, the second sidewall spacer is four to eight times higher than the first sidewall spacer.In some embodiments, the top surface of the n-type epitaxial source / drain component (NEPI) is higher than the uppermost surface of the first fin structure by a first rise height, and the top surface of the p-type epitaxial source / drain component (PEPI) is higher than the uppermost surface of the second fin structure by a second rise height, wherein the second rise height is greater than the first rise height. In some embodiments, the second rise height is at least 2 nm greater than the first rise height. In some embodiments, the first width of the n-type epitaxial source / drain component (NEPI) measured 1 nm below the uppermost surface of the first fin structure is greater than the second width of the p-type epitaxial source / drain component (PEPI) measured 1 nm below the uppermost surface of the second fin structure.

[0071] According to another embodiment of this application, a semiconductor structure is provided, comprising: a first fin structure and a second fin structure, located above a substrate; an n-type epitaxial source / drain component (NEPI) grown on a recessed portion of the first fin structure, wherein the height of the n-type epitaxial source / drain component (NEPI) is at least 1.5 times larger than the critical dimension (CD) of the n-type epitaxial source / drain component (NEPI) measured at its widest portion; and a p-type epitaxial source / drain component (PEPI) grown on a recessed portion of the second fin structure, wherein the uppermost surface of the p-type epitaxial source / drain component (PEPI) is higher than the uppermost surface of the n-type epitaxial source / drain component (NEPI). The device comprises: a dielectric fin located above the substrate and between an n-type epitaxial source / drain component (NEPI) and a p-type epitaxial source / drain component (PEPI), wherein the shortest horizontal distance between the n-type epitaxial source / drain component (NEPI) and the dielectric fin is greater than the shortest horizontal distance between the p-type epitaxial source / drain component (PEPI) and the dielectric fin; a metal compound component disposed above the n-type epitaxial source / drain component (NEPI), the p-type epitaxial source / drain component (PEPI), and the dielectric fin; a contact component disposed on the metal compound component; and a via structure disposed above the contact component and directly above the n-type epitaxial source / drain component (NEPI), wherein the via structure partially extends into the contact component. In some embodiments, the shortest distance between the via structure and the metal compound component is at least 5 nm. In some embodiments, the first width of the n-type epitaxial source / drain component (NEPI), measured 1 nm below the uppermost surface of the first fin structure, is greater than the second width of the p-type epitaxial source / drain component (PEPI), measured 1 nm below the uppermost surface of the second fin structure. In some embodiments, the uppermost surface of the n-type epitaxial source / drain component (NEPI) is higher than the uppermost surface of the first fin structure by a first rise height, and the uppermost surface of the p-type epitaxial source / drain component (PEPI) is higher than the uppermost surface of the second fin structure by a second rise height, wherein the second rise height is at least 2 nm greater than the first rise height. In some embodiments, the semiconductor structure further includes: a first sidewall spacer disposed along the sidewall of a recessed portion of the first fin structure; and a second sidewall spacer disposed along the sidewall of a recessed portion of the second fin structure, wherein the second sidewall spacer is higher than the first sidewall spacer.

[0072] According to another embodiment of this application, a method for forming a semiconductor device is provided, comprising: providing a structure having a substrate, an isolation structure located above the substrate, a first semiconductor fin and a second semiconductor fin extending from the substrate and protruding above the isolation structure, a dielectric fin extending from the isolation structure and between the first semiconductor fin and the second semiconductor fin, and a first dielectric spacer and a second dielectric spacer respectively located on the sidewalls of the first semiconductor fin and the second semiconductor fin; forming a first etching mask, the first etching mask covering the second semiconductor fin and the second dielectric spacer, and exposing the first semiconductor fin and the first dielectric spacer; etching the first semiconductor fin and the first dielectric spacer through the first etching mask to obtain a recessed portion of the first semiconductor fin, wherein the remaining portion of the first dielectric spacer has a first height; and etching the recessed portion of the first semiconductor fin... An n-type source / drain component is epitaxially grown, wherein the uppermost surface of the n-type source / drain component is higher than the uppermost surface of the first semiconductor fin by a first rise height; a first etch mask is removed; a second etch mask is formed, the second etch mask covering the remaining portions of the n-type source / drain component, the first semiconductor fin, and the first dielectric spacer, and exposing the second semiconductor fin and the second dielectric spacer; the second semiconductor fin and the second dielectric spacer are etched through the second etch mask to obtain a recessed portion of the second semiconductor fin, wherein the remaining portion of the second dielectric spacer has a second height, the second height being greater than the first height; and a p-type source / drain component is epitaxially grown on the recessed portion of the second semiconductor fin, wherein the uppermost surface of the p-type source / drain component is higher than the uppermost surface of the second semiconductor fin by a second rise height, the second rise height being greater than the first rise height. In some embodiments, the method of forming a semiconductor device further includes: forming one or more dielectric layers over an n-type source / drain component, a p-type source / drain component, and dielectric fins; etching contact holes in the one or more dielectric layers to expose the uppermost surfaces of the n-type source / drain component and the p-type source / drain component; forming metal compound components on the uppermost surfaces of the n-type source / drain component and the p-type source / drain component; forming contact components over the metal compound components and in the contact holes; and forming via structures over the contact components and extending partially into the contact components. In some embodiments, forming the via structure includes: etching holes into the contact components, wherein the bottom surface of the holes is perpendicularly spaced from the metal compound components by at least 5 nm, and depositing via metal into the holes. In some embodiments, the metal compound components are also formed directly above the dielectric fins.

[0073] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: n-type epitaxial source / drain device (NEPI) and p-type epitaxial source / drain device (PEPI) are located above the substrate, wherein the top surface of the n-type epitaxial source / drain device (NEPI) is lower than the top surface of the p-type epitaxial source / drain device (PEPI). A metal compound component is disposed on the top surface of the n-type epitaxial source / drain component (NEPI) and the top surface of the p-type epitaxial source / drain component (PEPI); A contact component is disposed on the metal compound component and above both the n-type epitaxial source / drain component (NEPI) and the p-type epitaxial source / drain component (PEPI); and A via structure is disposed above the contact component and above the n-type epitaxial source / drain component (NEPI), wherein the via structure is partially located in the contact component.

2. The semiconductor structure according to claim 1, wherein, The shortest distance between the through-hole structure and the metal compound component is at least 5 nm.

3. The semiconductor structure according to claim 1, wherein, The total volume of the n-type epitaxial source / drain device (NEPI) is greater than the total volume of the p-type epitaxial source / drain device (PEPI).

4. The semiconductor structure according to claim 1, further comprising: A dielectric fin is located above the substrate and between the n-type epitaxial source / drain component (NEPI) and the p-type epitaxial source / drain component (PEPI), wherein the shortest horizontal distance between the n-type epitaxial source / drain component (NEPI) and the dielectric fin is greater than the shortest horizontal distance between the p-type epitaxial source / drain component (PEPI) and the dielectric fin.

5. The semiconductor structure according to claim 1, further comprising: One or more dielectric layers surround the n-type epitaxial source / drain component (NEPI), the p-type epitaxial source / drain component (PEPI), the metal compound component, the contact component, and the via structure; and A barrier layer is disposed between the contact component and the one or more dielectric layers, wherein the through-hole structure directly contacts the contact component and the one or more dielectric layers.

6. The semiconductor structure according to claim 1, wherein, The through-hole structure extends into the contact component from approximately 5 nm to approximately 15 nm.

7. The semiconductor structure according to claim 1, further comprising: The first fin structure and the second fin structure are located above the substrate, wherein the n-type epitaxial source / drain component (NEPI) is grown above the recessed portion of the first fin structure, and the p-type epitaxial source / drain component (PEPI) is grown above the recessed portion of the second fin structure. A first sidewall spacer is disposed along the sidewall of the recessed portion of the first fin structure; and A second sidewall spacer is disposed along the sidewall of the recessed portion of the second fin structure; wherein the second sidewall spacer is higher than the first sidewall spacer.

8. The semiconductor structure according to claim 7, wherein, The second sidewall spacer is four to eight times higher than the first sidewall spacer.

9. The semiconductor structure according to claim 7, wherein, The top surface of the n-type epitaxial source / drain component (NEPI) is higher than the uppermost surface of the first fin structure by a first elevation height, and the top surface of the p-type epitaxial source / drain component (PEPI) is higher than the uppermost surface of the second fin structure by a second elevation height, wherein the second elevation height is greater than the first elevation height.

10. The semiconductor structure according to claim 9, wherein, The second elevation height is at least 2 nm greater than the first elevation height.

11. The semiconductor structure according to claim 7, wherein, The first width of the n-type epitaxial source / drain component (NEPI), measured 1 nm below the uppermost surface of the first fin structure, is greater than the second width of the p-type epitaxial source / drain component (PEPI), measured 1 nm below the uppermost surface of the second fin structure.

12. A semiconductor structure, comprising: The first fin structure and the second fin structure are located above the substrate; An n-type epitaxial source / drain device (NEPI) is grown on a recessed portion of the first fin structure, wherein the height of the n-type epitaxial source / drain device (NEPI) is at least 1.5 times larger than the critical dimension (CD) of the n-type epitaxial source / drain device (NEPI) as measured at the widest portion of the n-type epitaxial source / drain device (NEPI); A p-type epitaxial source / drain component (PEPI) is grown on a recessed portion of the second fin structure, wherein the uppermost surface of the p-type epitaxial source / drain component (PEPI) is higher than the uppermost surface of the n-type epitaxial source / drain component (NEPI). A dielectric fin is located above the substrate and between the n-type epitaxial source / drain component (NEPI) and the p-type epitaxial source / drain component (PEPI), wherein the shortest horizontal distance between the n-type epitaxial source / drain component (NEPI) and the dielectric fin is greater than the shortest horizontal distance between the p-type epitaxial source / drain component (PEPI) and the dielectric fin. A metal compound component is disposed above the n-type epitaxial source / drain component (NEPI), the p-type epitaxial source / drain component (PEPI), and the dielectric fin. Contact components are disposed on the metal compound component; and A via structure is disposed above the contact component and directly above the n-type epitaxial source / drain component (NEPI), wherein the via structure extends partially into the contact component.

13. The semiconductor structure according to claim 12, wherein, The shortest distance between the through-hole structure and the metal compound component is at least 5 nm.

14. The semiconductor structure according to claim 12, wherein, The first width of the n-type epitaxial source / drain component (NEPI), measured 1 nm below the uppermost surface of the first fin structure, is greater than the second width of the p-type epitaxial source / drain component (PEPI), measured 1 nm below the uppermost surface of the second fin structure.

15. The semiconductor structure according to claim 12, wherein, The uppermost surface of the n-type epitaxial source / drain component (NEPI) is higher than the uppermost surface of the first fin structure by a first height increase, and the uppermost surface of the p-type epitaxial source / drain component (PEPI) is higher than the uppermost surface of the second fin structure by a second height increase, wherein the second height increase is at least 2 nm greater than the first height increase.

16. The semiconductor structure according to claim 12, further comprising: A first sidewall spacer is provided along the sidewall of the recessed portion of the first fin structure; as well as A second sidewall spacer is disposed along the sidewall of the recessed portion of the second fin structure, wherein the second sidewall spacer is higher than the first sidewall spacer.

17. A method of forming a semiconductor device, comprising: A structure having a substrate is provided, an isolation structure located above the substrate, a first semiconductor fin and a second semiconductor fin extending from the substrate and protruding above the isolation structure, a dielectric fin extending from the isolation structure and between the first semiconductor fin and the second semiconductor fin, and a first dielectric spacer and a second dielectric spacer respectively located on the sidewalls of the first semiconductor fin and the second semiconductor fin. A first etch mask is formed, which covers the second semiconductor fin and the second dielectric spacer, and exposes the first semiconductor fin and the first dielectric spacer. The first semiconductor fin and the first dielectric spacer are etched using the first etching mask to obtain a recessed portion of the first semiconductor fin, wherein the remaining portion of the first dielectric spacer has a first height; An n-type source / drain component is epitaxially grown on the recessed portion of the first semiconductor fin, wherein the uppermost surface of the n-type source / drain component is higher than the uppermost surface of the first semiconductor fin by a first elevation height; Remove the first etch mask; A second etch mask is formed, which covers the remaining portions of the n-type source / drain components, the first semiconductor fin, and the first dielectric spacer, and exposes the second semiconductor fin and the second dielectric spacer. The second semiconductor fin and the second dielectric spacer are etched using the second etching mask to obtain a recessed portion of the second semiconductor fin, wherein the remaining portion of the second dielectric spacer has a second height, the second height being greater than the first height; and A p-type source / drain component is epitaxially grown on the recessed portion of the second semiconductor fin, wherein the uppermost surface of the p-type source / drain component is higher than the uppermost surface of the second semiconductor fin by a second height, the second height being greater than the first height.

18. The method of forming a semiconductor device according to claim 17, further comprising: One or more dielectric layers are formed above the n-type source / drain component, the p-type source / drain component, and the dielectric fin; Contact holes are etched in one or more dielectric layers to expose the uppermost surface of the n-type source / drain component and the uppermost surface of the p-type source / drain component; Metal compound components are formed on the uppermost surface of the n-type source / drain component and the uppermost surface of the p-type source / drain component; A contact element is formed above the metal compound component and in the contact hole; as well as A through-hole structure is formed above the contact component and extends partially into the contact component.

19. The method of forming a semiconductor device according to claim 18, wherein, The formation of the through-hole structure includes: An etched hole is made into the contact component, wherein the bottom surface of the hole is perpendicularly spaced at least 5 nm from the metal compound component, and Deposit through-hole metal into the hole.

20. The method of forming a semiconductor device according to claim 18, wherein, The metal compound component is also formed directly above the dielectric fin.

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