Method for manufacturing semiconductor device, semiconductor device, and storage system

Abstract

The application provides a semiconductor device manufacturing method, a semiconductor device and a storage system. The manufacturing method comprises the following steps: forming a substrate, a stack structure and a plurality of channel holes, the stack structure is located on the surface of the substrate, the stack structure comprises insulating medium layers which are arranged at intervals in the direction away from the substrate, a groove is formed between two adjacent insulating medium layers, and each channel hole is arranged at intervals in the stack structure and penetrates to the substrate; forming a first medium layer on the exposed outer wall of each channel hole, the first medium layer is connected with at least three adjacent channel holes and forms a cavity between the at least three adjacent channel holes; and filling a metal material in each groove with the first medium layer to form a plurality of metal layers. In the method, the F ions in the metal material are blocked by the first medium layer, which alleviates the problem that the dielectric damage of CH caused by F diffusion is more likely to occur in the place with a larger CH size in the prior art, thereby affecting the electrical performance of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a method for manufacturing a semiconductor device, a semiconductor device, a three-dimensional memory, and a memory system. Background Technology

[0002] During the fabrication of 3D NAND devices, after the insulating dielectric layer is replaced with a metal layer, voids are formed between the channel holes (CH). These voids trap some reactive gases containing fluorine (F). In areas where the CH is large, the space between adjacent CHs is relatively small, such as at CH bowing points, making it easier for larger voids to form. This makes it more susceptible to dielectric damage to the CH caused by F diffusion, resulting in CH leakage and affecting the electrical performance of the device.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a method for fabricating a semiconductor device, a semiconductor device, a three-dimensional memory, and a memory system, in order to solve the problem in the prior art that dielectric damage to the CH caused by F diffusion is more likely to occur in areas with larger CH sizes, thereby affecting the electrical performance of the device.

[0005] To achieve the above objectives, according to one aspect of this application, a method for fabricating a semiconductor device is provided, comprising: forming a substrate, a stacked structure, and a plurality of channel holes, the stacked structure being located on the surface of the substrate, the stacked structure including insulating dielectric layers spaced apart along a direction away from the substrate, a groove being formed between two adjacent insulating dielectric layers, and each of the channel holes being spaced apart in the stacked structure and penetrating to the substrate; forming a first dielectric layer on the exposed outer wall of each of the channel holes, the first dielectric layer connecting at least three adjacent channel holes and forming a void between the at least three adjacent channel holes; and filling each groove in which the first dielectric layer is formed with a metal material to form a plurality of metal layers.

[0006] Optionally, after forming a first dielectric layer on the exposed outer wall of each of the channel holes, and before filling the grooves where the first dielectric layer is formed with metal material to form a plurality of metal layers, the method further includes: removing a portion of the first dielectric layer, exposing a portion of the outer wall of the channel hole, the remaining first dielectric layer forming a dielectric portion, the dielectric portion connecting at least three adjacent channel holes and forming the cavity between the at least three adjacent channel holes; and forming a second dielectric layer on the exposed outer wall of the channel hole and on the exposed surface of the dielectric portion.

[0007] Optionally, forming a first dielectric layer on the exposed outer wall of each of the channel holes includes: depositing a dielectric material of a predetermined thickness on the exposed outer wall of each of the channel holes using atomic layer deposition technology to connect at least three adjacent channel holes and form the void between at least three adjacent channel holes to obtain the first dielectric layer.

[0008] Optionally, removing a portion of the first dielectric layer includes: etching the first dielectric layer using a wet etching method or a gas etching method to remove the first dielectric layer of the predetermined thickness.

[0009] Optionally, forming a substrate, a stacked structure, and a plurality of vias includes: sequentially forming the substrate and a pre-stacked structure located on the substrate, the pre-stacked structure including an insulating dielectric layer and a sacrificial layer alternately stacked in a direction away from the substrate; removing a portion of the pre-stacked structure to form a plurality of pre-stacked vias penetrating to the substrate in the pre-stacked structure; removing each of the sacrificial layers to expose a portion of the outer wall of each of the pre-stacked vias, thereby obtaining a plurality of grooves; and forming a high-k dielectric layer on the exposed outer wall of each of the pre-stacked vias to obtain each of the vias.

[0010] Optionally, forming a high-k dielectric layer on the exposed outer wall of each of the prepared channel holes to obtain each of the channel holes includes: forming the high-k dielectric layer on the exposed outer wall of each of the prepared channel holes using atomic layer deposition technology to obtain each of the channel holes.

[0011] Optionally, removing each of the sacrificial layers to expose a portion of the outer wall of each of the pre-trench holes to obtain each of the grooves includes: removing a portion of the pre-stack structure, forming at least one gate line slit extending through the substrate in the pre-stack structure; and removing each of the sacrificial layers through the gate line slit to obtain each of the grooves.

[0012] Optionally, removing a portion of the pre-stacked structure and forming a plurality of pre-drilled channel holes extending through the substrate in the pre-stacked structure includes: removing a portion of the pre-stacked structure and forming a plurality of channel hole openings in the pre-stacked structure; sequentially filling each of the channel hole openings with a charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer to form each of the pre-drilled channel holes.

[0013] Optionally, the material of the metal layer includes tungsten.

[0014] According to another aspect of this application, a semiconductor device is provided, the semiconductor device including a substrate, a stacked structure, a plurality of vias, and a dielectric layer, wherein the stacked structure is located on the surface of the substrate, the stacked structure including an insulating dielectric layer and a metal layer alternately stacked in a direction away from the substrate; the plurality of vias are located in the stacked structure, and each of the vias penetrates to the substrate; the dielectric layer connects at least three adjacent vias, and forms a void between the at least three adjacent vias.

[0015] According to another aspect of this application, a three-dimensional memory is provided, comprising a semiconductor device fabricated by any of the methods described.

[0016] According to another aspect of this application, a storage system is provided, including a storage controller and the three-dimensional memory, the three-dimensional memory being configured to store data, and the storage controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0017] Applying the technical solution of this application, firstly, a substrate, a stacked structure located on the surface of the substrate, and a plurality of channel holes spaced apart in the stacked structure and respectively penetrating to each of the substrates are formed. The stacked structure includes insulating dielectric layers spaced apart along a direction away from the substrate, and a groove is formed between two adjacent insulating dielectric layers. Then, a first dielectric layer is formed on the exposed outer wall of the channel hole. The first dielectric layer connects at least three adjacent channel holes and forms a void between the at least three adjacent channel holes. Finally, metal material is filled into each of the grooves where the first dielectric layer is formed to form a plurality of metal layers. In this method, a first dielectric layer is formed on the exposed outer wall of each channel hole. This allows multiple channel holes with small gaps to be connected through the first dielectric layer, that is, at least three adjacent channel holes are connected, and a cavity is formed between these channel holes. After the metal material is filled, the F ions in the metal material are blocked by the first dielectric layer and cannot enter the cavity, thus avoiding damage to these channel holes by F ions. This alleviates the problem in the prior art where dielectric damage to CH caused by F diffusion is more likely to occur in areas with larger CH size, thereby affecting the electrical performance of the device. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 This illustration shows a schematic diagram of the structure of a semiconductor device after being cut along a direction perpendicular to the channel hole, according to a specific embodiment of this application.

[0020] Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application is shown;

[0021] Figure 3 A schematic diagram of the structure of a semiconductor device in a specific embodiment of this application is shown;

[0022] Figure 4 It shows in Figure 3 A schematic diagram of the structure after the dielectric layer is formed on the basis of the structure and then cut along the dashed line AA'.

[0023] Figure 5 It shows in Figure 4 A schematic diagram of the structure after removing part of the dielectric layer to form the dielectric part based on the original structure;

[0024] Figure 6 It shows in Figure 5 A schematic diagram of the structure after filling the groove with metal material in the medium section based on the structure;

[0025] Figure 7 This paper shows a schematic diagram of the substrate and the pre-stacked structure in one embodiment of the present application;

[0026] Figure 8 It shows the removal Figure 7 A schematic diagram of the structure after the middle part is stacked;

[0027] Figure 9 It shows in Figure 8 A schematic diagram of the structure after the gate line slit is formed on the top;

[0028] Figure 10 It shows the removal Figure 8 A schematic diagram of the structure behind the middle sacrificial layer.

[0029] The above figures include the following reference numerals:

[0030] 10. Substrate; 20. Stacked structure; 21. Preparatory stacked structure; 30. Channel via; 40. First dielectric layer; 50. Void; 60. Dielectric section; 70. Metal material; 80. Gate line slit; 90. Second dielectric layer; 201. Insulating dielectric layer; 202. Groove; 211. Sacrificial layer; 301. Preparatory channel via; 302. High-K dielectric layer. Detailed Implementation

[0031] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0032] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0033] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0034] In the process of manufacturing 3D NAND memory, such as Figure 1 As shown, after replacing the insulating dielectric layer in the stacked structure with a metal layer through the gate line slit, due to the limitations of the actual process, incomplete filling will occur, resulting in voids in the metal layer. These voids will trap some reactive gases containing F. Moreover, compared with voids in other places, the voids between multiple channel holes that are close together are larger and more prone to channel hole damage caused by F diffusion, resulting in channel hole leakage and thus affecting the electrical performance of the device.

[0035] To address the above problems, this application proposes a method for fabricating a semiconductor device, a semiconductor device, a three-dimensional memory, and a storage system.

[0036] In one typical embodiment of this application, a method for fabricating a semiconductor device is provided.

[0037] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. For example... Figure 2As shown, the method includes the following steps:

[0038] Step S101, as follows Figure 3 As shown, a substrate 10, a stacked structure 20, and a plurality of channel holes 30 are formed. The stacked structure 20 is located on the surface of the substrate 10. The stacked structure 20 includes insulating dielectric layers 201 spaced apart along a direction away from the substrate 10. A groove 202 is formed between two adjacent insulating dielectric layers 201. Each of the channel holes 30 is spaced apart in the stacked structure 20 and penetrates the substrate 10.

[0039] Step S102, as follows Figure 4 As shown, a first dielectric layer 40 is formed on the exposed outer wall of each of the above-mentioned channel holes 30, the first dielectric layer 40 connects at least three adjacent channel holes 30, and forms a cavity 50 between the at least three adjacent channel holes 30 connected.

[0040] Step S103, as follows Figure 6 As shown, metal material 70 is filled into each of the grooves 202 where the first dielectric layer 40 is formed, to form a plurality of metal layers.

[0041] In the above manufacturing method, firstly, a substrate, a stacked structure located on the surface of the substrate, and a plurality of channel holes spaced apart in the stacked structure and extending through each of the substrates are formed. The stacked structure includes insulating dielectric layers spaced apart along a direction away from the substrate, and a groove is formed between two adjacent insulating dielectric layers. Then, a first dielectric layer is formed on the exposed outer wall of the channel holes. The first dielectric layer connects at least three adjacent channel holes and forms a void between the at least three adjacent channel holes. Finally, metal material is filled into each of the grooves where the first dielectric layer is formed to form a plurality of metal layers. In this method, a first dielectric layer is formed on the exposed outer wall of each channel hole. This allows multiple channel holes with small gaps to be connected through the first dielectric layer, that is, at least three adjacent channel holes are connected, and a cavity is formed between these channel holes. After the metal material is filled, the F ions in the metal material are blocked by the first layer and cannot enter the cavity, thus avoiding damage to these channel holes by F ions. This alleviates the problem in the prior art where dielectric damage to CH caused by F diffusion is more likely to occur in areas with larger CH size, thereby affecting the electrical performance of the device.

[0042] In one specific embodiment, after forming a first dielectric layer on the exposed outer wall of each of the aforementioned channel holes, and before filling the aforementioned grooves where the first dielectric layer has been formed with metal material to form a plurality of metal layers, the method further includes: Figure 4 as well as Figure 5As shown, a portion of the first dielectric layer 40 is removed, exposing part of the outer wall of the channel via 30. The remaining first dielectric layer forms a dielectric portion 60, which connects at least three adjacent channel vias 30 and forms the void 50 between the connected at least three adjacent channel vias 30. A second dielectric layer 90 is formed on the exposed outer wall of the channel via 30 and the exposed surface of the dielectric portion 60. By removing a portion of the first dielectric layer and forming a second dielectric layer of suitable thickness, the existence of the void is ensured, and the resistance of the gate layer can be adjusted by adjusting the thickness of the second dielectric layer, further ensuring better overall semiconductor device performance.

[0043] In one embodiment of this application, a first dielectric layer is formed on the exposed outer wall of each of the aforementioned channel holes, including: Figure 4 As shown, an atomic layer deposition (ALD) technique is used to deposit a dielectric material of a predetermined thickness *d* on the exposed outer wall of each of the aforementioned channel holes to connect at least three adjacent channel holes, thus obtaining the aforementioned first dielectric layer. By forming a first dielectric layer of predetermined thickness on the exposed outer wall of each channel hole, multiple channel holes with small gaps are connected through the first dielectric layer, that is, at least three adjacent channel holes are connected. ACD technique ensures that the obtained first dielectric layer uniformly covers the outer wall of the channel holes, and the fabrication process is relatively simple.

[0044] Specifically, in one embodiment, such as Figure 4 As shown, during the process of forming the first dielectric layer of the predetermined thickness on the exposed outer wall of each of the above-mentioned channel holes, the first dielectric layer will grow on the outer wall of multiple channel holes that are far apart, that is, multiple channel holes with large gaps, and the first dielectric layers between the channel holes with large gaps will not contact each other; the first dielectric layers between multiple channel holes that are close together, that is, multiple channel holes with small gaps, will connect together, and a cavity 50 will be formed between these channel holes.

[0045] In another embodiment of this application, removing a portion of the first dielectric layer includes etching the first dielectric layer using a wet etching method or a gas etching method to remove the first dielectric layer of a predetermined thickness. By removing the first dielectric layer to a predetermined thickness, the first dielectric layer on the outer wall of the channel with larger gaps is completely removed, while the first dielectric layer between the multiple connected channel holes with smaller gaps remains. The remaining dielectric portion connects the multiple channel holes with smaller gaps, and the dielectric portion can prevent F ions in the filling metal material from diffusing into the voids, further alleviating the problem of dielectric damage to CH caused by F diffusion in areas with larger CH size.

[0046] In one specific embodiment of this application, such as Figure 3 as well as Figure 4 As shown, in order to connect at least three adjacent channel holes as described above and form a cavity therein, when forming a first dielectric layer with a predetermined thickness on the exposed outer walls of each of the above-mentioned channel holes, twice the above-mentioned predetermined thickness THK(d) is greater than or equal to the maximum distance between the outer walls of at least three adjacent channel holes. Specifically, the range of the predetermined thickness is generally set to CH1 - Δ < 2×THK(d) < CH2 - Δ, where CH1 represents the maximum distance between the outer walls of adjacent first channel holes, CH2 represents the distance between the outer walls of adjacent second channel holes, the outer wall of the first channel hole is the outer wall of the channel hole with a smaller gap that needs to form a cavity, the outer wall of the second channel hole is the outer wall of the channel hole with a larger gap that does not need to form a cavity, and Δ represents the process error. The range of CH2 is generally between 15 - 25 nm, and the range of CH1 is generally between 5 - 15 nm. The above-mentioned predetermined thickness is the thickness of the first dielectric layer in the horizontal direction, and the horizontal direction is perpendicular to the extending direction of the channel hole.

[0047] In another embodiment of the present application, forming a substrate, a stacked structure, and multiple channel holes includes: as Figure 7 shown, sequentially forming the above-mentioned substrate 10 and a preliminary stacked structure 21 located on the above-mentioned substrate 10, the above-mentioned preliminary stacked structure 21 includes the above-mentioned insulating dielectric layer 201 and the sacrificial layer 211 alternately stacked in a direction away from the above-mentioned substrate 10; as Figure 8 shown, removing a part of the above-mentioned preliminary stacked structure 21, and forming multiple preliminary channel holes 301 penetrating through the above-mentioned substrate 10 in the above-mentioned preliminary stacked structure 21; as Figure 10 shown, removing each of the above-mentioned sacrificial layers 211, so that part of the outer walls of each of the above-mentioned preliminary channel holes 301 are exposed, and obtaining multiple above-mentioned grooves 202; as Figure 3 shown, forming a high-K dielectric layer 302 on the exposed outer walls of each of the above-mentioned preliminary channel holes 301, and obtaining each of the above-mentioned channel holes 30.

[0048] In the above-mentioned embodiment, the above-mentioned high-K dielectric layer may not be provided, that is, the above-mentioned preliminary channel hole is the above-mentioned channel hole. It should be noted that in the case where the above-mentioned high-K dielectric layer exists, the outer wall of the above-mentioned channel hole is the outer wall of the above-mentioned high-K dielectric layer; in the case where the above-mentioned high-K dielectric layer does not exist, the outer wall of the above-mentioned channel hole is the outer wall of the above-mentioned preliminary channel hole.

[0049] Specifically, the above-mentioned sacrificial layer and the above-mentioned insulating dielectric layer may adopt conventional materials in the prior art. In another specific embodiment of the present application, the above-mentioned sacrificial layer is a silicon nitride layer, and the above-mentioned insulating dielectric layer is a silicon oxide layer.

[0050] In another embodiment of this application, a high-k dielectric layer is formed on the exposed outer wall of each of the aforementioned pre-prepared channel holes to obtain each of the aforementioned channel holes. This includes: forming the high-k dielectric layer on the exposed outer wall of each of the aforementioned pre-prepared channel holes using atomic layer deposition (ALD) technology to obtain each of the aforementioned channel holes. ALD technology ensures that the obtained high-k dielectric layer uniformly coats the outer wall of the channel hole, and the fabrication process is relatively simple.

[0051] Specifically, the high-k dielectric layer mentioned above includes alumina. In practical applications, the high-k dielectric layer can be alumina, or it can be other materials.

[0052] In another embodiment of this application, each of the aforementioned sacrificial layers is removed, exposing a portion of the outer wall of each of the aforementioned pre-prepared channel holes, resulting in each of the aforementioned grooves, including: Figure 8 As shown, the above-mentioned pre-stacked structure 21 with the portion removed, as... Figure 9 As shown, at least one gate line slit 80 extending through the substrate is formed in the pre-stacked structure 21; each of the sacrificial layers 211 is removed through the gate line slit 80 to obtain the following: Figure 10 The aforementioned grooves 202 are shown. By forming the aforementioned gate line slits, the aforementioned sacrificial layer can be replaced with the aforementioned metal layer.

[0053] In another embodiment of this application, a portion of the above-mentioned pre-stacked structure is removed, and a plurality of pre-reserved channel holes extending through the substrate are formed in the pre-stacked structure, including: removing a portion of the above-mentioned pre-stacked structure, forming a plurality of channel hole openings in the pre-stacked structure; and sequentially filling each of the above-mentioned channel hole openings with a charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer to form each of the above-mentioned pre-reserved channel holes.

[0054] Specifically, the aforementioned channel layer, tunneling layer, electron trapping layer, and charge blocking layer constitute a PONO stacked structure, namely a polysilicon-oxide-silicon nitride-oxide stacked structure.

[0055] In another embodiment of this application, the material of the first dielectric layer includes titanium nitride, and the material of the second dielectric layer includes titanium nitride. More specifically, the material of both the first and second dielectric layers is titanium nitride. Of course, the materials of the first and second dielectric layers are not limited to titanium nitride, and may include any other feasible materials. In some specific embodiments, the materials of the first and second dielectric layers may be different.

[0056] According to another specific embodiment of this application, such as Figure 6 As shown, the materials of the aforementioned metal layer include, but are not limited to, tungsten.

[0057] Specifically, the material of the aforementioned metal layer is tungsten.

[0058] In another typical embodiment of this application, a semiconductor device is provided, which is manufactured using any of the methods described above.

[0059] The aforementioned semiconductor device is fabricated using the aforementioned method. This fabrication method involves forming a first dielectric layer on the exposed outer wall of each channel hole. This allows multiple channel holes with small gaps to be connected through the first dielectric layer, that is, connecting at least three adjacent channel holes and forming a cavity between these channel holes. After filling with metal material, F ions in the metal material are blocked by the first layer and cannot enter the cavity, thus avoiding damage to these channel holes by F ions. This alleviates the problem in the prior art where F diffusion easily occurs in areas with larger CH size, causing dielectric damage to CH and thus affecting the electrical performance of the device, resulting in better performance of the semiconductor device.

[0060] In another typical embodiment of this application, a semiconductor device is provided, the semiconductor device including a substrate, a stacked structure, a plurality of channel holes and a dielectric layer, wherein the stacked structure is located on the surface of the substrate, the stacked structure including an insulating dielectric layer and a metal layer alternately stacked along a direction away from the substrate; the plurality of channel holes are located in the stacked structure, and each of the channel holes penetrates to the substrate; the dielectric layer connects at least three adjacent channel holes and forms a void between the at least three adjacent channel holes.

[0061] The aforementioned semiconductor device includes a substrate, a stacked structure on the substrate, a plurality of channel vias in the stacked structure, and a dielectric layer connecting at least three adjacent channel vias. The dielectric layer connects at least three adjacent channel vias and forms voids between them, allowing F ions in the metal layer to be blocked by the dielectric layer. This prevents F ions from damaging the channel vias, thus mitigating the problem in the prior art where F diffusion easily occurs in areas with larger CH sizes, causing dielectric damage to CH and affecting the electrical performance of the device. This results in better performance for the semiconductor device.

[0062] In one specific embodiment, the aforementioned dielectric layer may be a first dielectric layer. Alternatively, the dielectric layer may also include a dielectric portion and a second dielectric layer. The dielectric portion connects to at least three adjacent outer walls of the first channel holes. The outer walls of the first channel holes have small gaps and require the formation of voids, with voids formed between the outer walls of the first channel holes. The second dielectric layer is located on the outer walls of the second channel holes and on the surface of the dielectric portion away from the outer walls of the first channel holes. The outer walls of the second channel holes have larger gaps and do not require the formation of voids.

[0063] In another typical embodiment of this application, a three-dimensional memory is provided, comprising a semiconductor device fabricated by any of the methods described above.

[0064] The three-dimensional memory includes the aforementioned semiconductor device, which is connected to at least three adjacent channel holes through a dielectric layer, and forms a void between these channel holes. This allows F ions in the metal layer to be blocked by the dielectric layer, avoiding damage to the channel holes by F ions. This alleviates the problem in the prior art where F diffusion easily occurs in areas with larger CH sizes, causing dielectric damage to CH and thus affecting the electrical performance of the device. As a result, the semiconductor device has better performance, thereby optimizing the performance of the three-dimensional memory.

[0065] In another typical embodiment of this application, a storage system is provided, including a storage controller and the aforementioned three-dimensional memory, wherein the three-dimensional memory is configured to store data, and the storage controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0066] The aforementioned storage system includes the aforementioned three-dimensional memory. The dielectric layer of the aforementioned three-dimensional memory connects at least three adjacent channel holes and forms voids between these channel holes, so that F ions in the metal layer can be blocked by the dielectric layer, avoiding damage to the channel holes by F ions. This alleviates the problem in the prior art where F diffusion easily occurs in areas with larger CH sizes, causing dielectric damage to CH and thus affecting the electrical performance of the device, resulting in better performance of the entire storage system.

[0067] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0068] 1) In the method for fabricating a semiconductor device according to this application, firstly, a substrate, a stacked structure located on the surface of the substrate, and a plurality of channel holes spaced apart in the stacked structure and respectively penetrating to each of the substrates are formed. The stacked structure includes insulating dielectric layers spaced apart along a direction away from the substrate, and a groove is formed between two adjacent insulating dielectric layers. Then, a first dielectric layer is formed on the exposed outer wall of the channel hole. The first dielectric layer connects at least three adjacent channel holes and forms a void between the at least three adjacent channel holes. Finally, metal material is filled into each of the grooves where the first dielectric layer is formed to form a plurality of metal layers. In this method, a first dielectric layer is formed on the exposed outer wall of each channel hole. This allows multiple channel holes with small gaps to be connected through the first dielectric layer, that is, at least three adjacent channel holes are connected, and a cavity is formed between these channel holes. After the metal material is filled, the F ions in the metal material are blocked by the first layer and cannot enter the cavity, thus avoiding damage to these channel holes by F ions. This alleviates the problem in the prior art where dielectric damage to CH caused by F diffusion is more likely to occur in areas with larger CH size, thereby affecting the electrical performance of the device.

[0069] 2) The semiconductor device of this application is fabricated using the above method. The above fabrication method forms a first dielectric layer on the exposed outer wall of each channel hole. In this way, multiple channel holes with small gaps are connected through the first dielectric layer, that is, at least three adjacent channel holes are connected, and a cavity is formed between these channel holes. After the metal material is filled, the F ions in the metal material are blocked by the first layer and cannot enter the cavity, thus avoiding damage to these channel holes by F ions. This alleviates the problem in the prior art that the dielectric damage of CH caused by F diffusion is more likely to occur in areas with larger CH size, thereby affecting the electrical performance of the device, resulting in better performance of the semiconductor device.

[0070] 3) The semiconductor device of this application includes a substrate, a stacked structure on the substrate, a plurality of channel holes in the stacked structure, and a dielectric layer connecting at least three adjacent channel holes. The dielectric layer connects at least three adjacent channel holes and forms voids between them, allowing F ions in the metal layer to be blocked by the dielectric layer, thus preventing damage to the channel holes by F ions. This alleviates the problem in the prior art where F diffusion easily occurs in areas with larger CH sizes, causing dielectric damage to CH and affecting the electrical performance of the device, resulting in better performance of the semiconductor device.

[0071] 4) The three-dimensional memory of this application includes the above-mentioned semiconductor device. The semiconductor device is connected to at least three adjacent channel holes through a dielectric layer, and a cavity is formed between these channel holes. This allows F ions in the metal layer to be blocked by the dielectric layer, avoiding damage to the channel holes by F ions. This alleviates the problem in the prior art where F diffusion easily occurs in areas with larger CH size, causing dielectric damage to CH and thus affecting the electrical performance of the device. This results in better performance of the semiconductor device, thereby achieving performance optimization of the three-dimensional memory.

[0072] 5) The storage system of this application includes the above-mentioned three-dimensional memory. The dielectric layer of the three-dimensional memory is connected to at least three adjacent channel holes and forms a cavity between these channel holes, so that F ions in the metal layer can be blocked by the dielectric layer, avoiding damage to the channel holes by F ions. This alleviates the problem in the prior art that F diffusion is more likely to occur in areas with larger CH size, causing dielectric damage to CH and thus affecting the electrical performance of the device, resulting in better performance of the entire storage system.

[0073] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: forming a substrate, a stack structure and a plurality of channel holes, the stack structure is located on a surface of the substrate, the stack structure comprises insulating medium layers which are arranged in a direction away from the substrate, a groove is formed between two adjacent insulating medium layers, each channel hole is arranged in the stack structure and penetrates the substrate; forming a first medium layer on an exposed outer wall of each channel hole, the first medium layer connects at least three adjacent channel holes and forms a hollow between the at least three adjacent channel holes, the hollow is closed in a circumferential direction; filling a metal material in each groove formed with the first medium layer to form a plurality of metal layers.

2. The method of claim 1, wherein, After forming the first medium layer on the exposed outer wall of each channel hole, before filling the metal material in each groove formed with the first medium layer to form a plurality of metal layers, the method further comprises: removing part of the first medium layer so that part of the outer wall of the channel hole is exposed, and the remaining first medium layer forms a medium part which connects at least three adjacent channel holes and forms the hollow between the at least three adjacent channel holes; forming a second medium layer on the exposed outer wall of the channel hole and the exposed surface of the medium part.

3. The method of claim 1, wherein, forming a first medium layer on the exposed outer wall of each channel hole comprises: depositing a medium material with a predetermined thickness on the exposed outer wall of each channel hole by using an atomic layer deposition technology to connect at least three adjacent channel holes and form the hollow between the at least three adjacent channel holes, so as to obtain the first medium layer.

4. The method of claim 3, wherein, removing part of the first medium layer comprises: etching the first medium layer by using a wet etching method or a gas etching method to remove the first medium layer with the predetermined thickness.

5. The method of claim 1, wherein, forming a substrate, a stack structure and a plurality of channel holes comprises: sequentially forming the substrate and a preliminary stack structure located on the substrate, the preliminary stack structure comprises the insulating medium layers and the sacrificial layers which are alternately arranged in a direction away from the substrate; removing part of the preliminary stack structure to form a plurality of preliminary channel holes which penetrate the substrate in the preliminary stack structure; removing each sacrificial layer so that part of the outer wall of each preliminary channel hole is exposed to obtain a plurality of grooves; forming a high-K medium layer on the exposed outer wall of each preliminary channel hole to obtain each channel hole.

6. The method of claim 5, wherein, forming a high-K medium layer on the exposed outer wall of each preliminary channel hole to obtain each channel hole comprises: forming the high-K medium layer on the exposed outer wall of each preliminary channel hole by using an atomic layer deposition technology to obtain each channel hole.

7. The method of claim 5, wherein, removing each sacrificial layer so that part of the outer wall of each preliminary channel hole is exposed to obtain each groove comprises: removing part of the preliminary stack structure to form at least one gate line slit which penetrates the substrate in the preliminary stack structure; removing each sacrificial layer through the gate line slit to obtain each groove.

8. The method of claim 5, wherein, Removing part of the preliminary stack structure to form a plurality of preliminary via holes penetrating to the substrate in the preliminary stack structure, comprising: Removing part of the preliminary stack structure to form a plurality of via hole openings in the preliminary stack structure; Filling a charge blocking layer, an electron trapping layer, a tunneling layer and a channel layer in sequence in each of the via hole openings to form each of the preliminary via holes.

9. The method according to any one of claims 1 to 8, characterized in that, The material of the metal layer comprises tungsten.

10. A semiconductor device, characterized by comprising: Comprising: a substrate; a stack structure on a surface of the substrate, the stack structure comprising insulating dielectric layers and metal layers alternately stacked away from the substrate; a plurality of via holes in the stack structure, and each of the via holes penetrating to the substrate; a dielectric layer connecting at least three adjacent via holes, and forming a hollow between the connected at least three adjacent via holes, the hollow being closed in a circumferential direction.

11. A three-dimensional memory, comprising: The semiconductor device of claim 10 or a semiconductor device made by the method of any one of claims 1 to 9.

12. A storage system, characterized by A three-dimensional memory as claimed in claim 11, and a storage controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.

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