A multi-objective coordinated N3S_CBPWM modulation algorithm for a neutral-point-clamped three-level inverter

Abstract

The application relates to a multi-target coordinated N3S_CBPWM modulation algorithm of a neutral point clamped three-level inverter, which comprehensively considers multiple targets of neutral point voltage balance, reduction of switching loss and reduction of common mode voltage, one phase is clamped in one switching cycle, one phase has one switching action, and the other phase has two switching actions. In addition, a method for reducing common mode voltage is provided, modulation wave constraint conditions of the N3S_CBPWM modulation algorithm based on reduction of common mode voltage are given, active neutral point voltage control based on the N3S_CBPWM modulation algorithm is provided for effectively controlling the neutral point voltage. The modulation method provided by the application can not only effectively control the balance of the neutral point voltage, reduce the switching loss of the system, but also reduce the injected common mode voltage, improve the operation efficiency of the inverter, and realize the optimal control of the three-level inverter.

Description

Technical Field

[0001] This invention belongs to the field of inverter modulation technology, and particularly relates to a multi-objective coordinated N3S_CBPWM modulation algorithm for a midpoint clamped three-level inverter. Background Technology

[0002] With the development of power electronics and power devices, midpoint-clamped three-level inverters have been widely used in many applications, such as wind turbine drives, photovoltaic systems, and electric vehicles, due to their better harmonic characteristics and lower switching transistor withstand voltage. However, this has also brought new challenges. The increased number of power transistors leads to more complex control algorithms, accompanied by issues such as switching losses, midpoint voltage deviation, and common-mode voltage effects. Midpoint voltage balance is a crucial indicator for ensuring the safe and reliable operation of the inverter. Midpoint voltage deviation and fluctuations not only reduce the quality of the inverter's output voltage and current but can even cause the DC-side capacitor to over-voltage, potentially leading to an explosion. Since the current generated by common-mode voltage consumes power when flowing through the load, it is detrimental to the load and increases system maintenance costs, affecting long-term safe operation and making it unsuitable for some special applications. Therefore, common-mode voltage needs to be limited to a certain range. Switching losses are one of the important indicators for measuring the efficient operation of an inverter. Reducing switching losses can effectively extend the lifespan of power devices.

[0003] In a three-level inverter, the neutral point voltage imbalance includes DC offset and AC ripple, which can lead to overvoltage phenomena that damage switching equipment and cause output current distortion. Therefore, to ensure the safe and reliable operation of a three-level inverter, a method that achieves neutral point voltage balance is necessary. Switching losses are also a crucial indicator of inverter efficiency. Increased switching losses inevitably reduce the performance of power devices.

[0004] Currently, most methods maintain midpoint voltage balance by employing different pulse width modulation (PWM) strategies. These strategies are mainly divided into carrier-based PWM (CBPWM) and space vector PWM (SVPWM). Injecting a specific zero-sequence voltage into the modulated wave and comparing it with the carrier wave can achieve the same effect as SVPWM, thus realizing the equivalence of CBPWM and SVPWM. However, classic CBPWM, SVPWM, and DPWM cannot achieve unconditional midpoint potential balance, requiring a new method to address this issue. A novel method based on Virtual Space Vector PWM (VSVPWM) employs a carrier-based implementation. This new method constructs a virtual vector that can maintain zero midpoint current across the entire range, unconditionally achieving midpoint potential balance. However, it adds one switching action per cycle, thus increasing switching losses.

[0005] Meanwhile, excessively high common-mode voltage will generate shaft current, increasing mechanical wear between bearings, causing electromagnetic interference, and affecting the normal operation of other electrical equipment.

[0006] Therefore, there is a need for a modulation method for a three-level inverter that can simultaneously reduce system switching losses, control midpoint voltage balance, and reduce common-mode voltage. Summary of the Invention

[0007] The purpose of this invention is to provide a multi-objective coordinated N3S_CBPWM modulation algorithm for a midpoint-clamped three-level inverter in order to solve the above-mentioned problems.

[0008] The present invention achieves the above objectives through the following technical solutions:

[0009] A multi-objective coordinated N3S_CBPWM modulation algorithm for a midpoint-clamped three-level inverter includes the following steps:

[0010] S1: Collect the voltage u of the upper capacitor on the DC side of the three-level inverter. C1 Lower capacitor voltage u C2 Three-phase output phase current i A i B i C Three-phase output phase voltage u A u B u C The data is then sorted by size to obtain the processed data.

[0011] S2: Calculate the midpoint voltage balance modulation wave constraint condition and the common-mode voltage modulation wave reduction constraint condition in the 1+1+1 mode and the 2+1+0 mode, respectively, based on the processed data.

[0012] S3: Based on the midpoint voltage balance modulation wave constraint condition and the common-mode voltage reduction modulation wave constraint condition, the multi-objective coordinated control modulation algorithm of the midpoint clamped three-level inverter is obtained.

[0013] As a further optimization of the present invention, the processed data in step S1 includes: maximum voltage u L =max(u A u B u C Minimum voltage u S =min(u A u B u C and intermediate voltage u M =mid(u A u B u C ), maximum current i L =max(iA i B i C Minimum voltage i S =min(i A i B i C ) and intermediate voltage i M =mid(i A i B i C ).

[0014] As a further optimization of the present invention, the specific steps in step S2 for calculating the common-mode voltage modulation wave constraint conditions in 1+1+1 mode and 2+1+0 mode based on the processed data are as follows:

[0015] S201: Set the common-mode voltage of N3S_CBPWM to:

[0016]

[0017] In the formula L k_2 and L k_1 These are the instantaneous levels generated by comparing the dual-modulated wave of the k-th phase with the carrier wave, and their values ​​are {0,1}.

[0018] S202: According to equation (1), the common-mode voltage is set to be limited to ±1 / 6U. dc The conditions are:

[0019]

[0020] S203: The common-mode voltage modulation wave reduction constraint conditions in the 1+1+1 mode and the 2+1+0 mode are calculated according to Equation (2). The 1+1+1 mode and the 2+1+0 mode can be further divided into eight modes according to the number of switching operations per phase and the polarity of the phase of one switching operation. The results are shown in the table below:

[0021]

[0022]

[0023] As a further optimization of the present invention, the specific process of calculating the common-mode voltage modulation wave constraint condition in step S203 in the 1+1+1 mode is as follows:

[0024] When u M When >0, equation (2) can be simplified to:

[0025] 0≤L L_1 +L M_1 +L S_2 ≤2 (3);

[0026] Both the maximum voltage phase and the intermediate voltage phase are compared with the concave carrier wave; in the middle stage of a switching cycle, there will be an interval where the maximum voltage phase and the intermediate voltage phase simultaneously output a 2-level signal, and d L,2 >d M,2 , where d L,2 and d M,2 These represent the duty cycles of L-phase 2-level and M-phase 2-level, respectively; when L M_1 When = 1, L L_1 To satisfy the condition of equation (3), let L be 1. M_1 When = 1, L S_2 =0, thus obtaining the duty cycle constraint d S,0 >d M,2 ; This is converted into a constraint condition for reducing the common-mode voltage modulation wave, i.e.:

[0027] u S_2 +u M_1 ≤1;

[0028] When comparing the voltage intermediate phase with the convex carrier, set L M_1 When = 1, L L_1 =0, the duty cycle must satisfy d M,2 <d L,1 ; This is converted into a constraint condition for reducing common-mode voltage modulation, i.e.:

[0029] u L_1 +u M_1 ≤1;

[0030] When u M When <0, both the intermediate voltage phase and the minimum voltage phase are compared with the concave carrier. In the middle of a switching cycle, there will be a range where the intermediate voltage phase and the minimum voltage phase both output a 0 level, and d S,0 >d M,0 , where d S,0 and d M,0 These represent the duty cycles of phase S (0 level) and phase M (0 level), respectively; when L M_2 When = 0, L S_2 To satisfy the condition of equation (3), let L be 0. M_2 When = 0, L L_1 =1, thus obtaining the constraint condition for reducing common-mode voltage modulation waves, namely:

[0031] u M_2 +u L_1 ≥1;

[0032] When comparing the voltage intermediate phase with the convex carrier, set L S_2 When = 0, L M_2 =1, reducing the common-mode voltage modulation wave constraint condition, that is:

[0033] u M_2 +u S_2 ≥1.

[0034] As a further optimization of the present invention, in step S203, L_PB / M_2S(u) is calculated in the 2+1+0 mode. M -u S <1) The specific process of reducing the common-mode voltage modulation wave constraint condition in the mode is as follows:

[0035] L_PB / M_2S(u M -u S In mode <1), L_PB indicates that the maximum phase is clamped to the positive bus, and M_2S indicates that the intermediate phase of the voltage has two switching operations. In this mode, due to u L Clamped to level 2, the voltage minimum phase has only one switching action. Therefore, equation (2) can be simplified to:

[0036] 0≤L M_1 +L M_2 +L S_2 ≤2 (4);

[0037] Set the duty cycle constraint to d s,0 ≥d M,2 To meet the common-mode voltage constraint condition;

[0038] The constraint on the duty cycle is transformed into a constraint on reducing the common-mode voltage modulation wave, that is:

[0039] u M_1 +u S_2 ≤1.

[0040] As a further optimization of the present invention, the step S2 of calculating the midpoint voltage balance modulation wave constraint conditions in the 1+1+1 mode and the 2+1+0 mode based on the processed data includes the following steps:

[0041] Step S301: Define the direction of flow from the midpoint as the positive direction of the midpoint current, and introduce the midpoint current. To achieve active control of the midpoint voltage, where T s This represents one switching cycle;

[0042] Step S302: Calculate the midpoint voltage balance modulation wave constraint conditions for the 1+1+1 mode and the 2+1+0 mode respectively:

[0043] In the 1+1+1 mode, active neutral point voltage balance control is achieved by injecting zero-sequence voltage into the three-phase modulation wave. The formula for calculating the injected zero-sequence voltage is as follows:

[0044]

[0045] In the 2+1+0 mode, active neutral point voltage balance control is achieved by injecting differential mode voltage into the secondary switching phase. The formula for calculating the injected differential mode voltage is as follows:

[0046]

[0047] In the formula i x This is the current corresponding to the phase of the secondary switch operation.

[0048] The beneficial effects of this invention are as follows:

[0049] 1) The method proposed in this invention can achieve the same midpoint voltage balancing effect as VSVPWM across the entire range, with lower switching losses than VSVPWM, and can reduce the common-mode voltage to ±1 / 6U in most ranges. dc ;

[0050] 2) The N3S_CBPWM modulation method proposed in this invention comprehensively considers multiple objectives such as midpoint voltage balance, reducing switching losses and lowering common-mode voltage, thus optimizing the entire three-level inverter system;

[0051] 3) This invention requires no additional peripherals, has low system cost, and the control method is simple and easy to implement. Attached Figure Description

[0052] Figure 1 This is a flowchart of the multi-objective coordinated control of the three-level inverter of the present invention;

[0053] Figure 2 a represents the common-mode voltage u in the 1+1+1 mode under different conditions. M >0 when u M A diagram using a concave carrier wave;

[0054] Figure 2 b represents the common-mode voltage u in the 1+1+1 mode under different conditions. M >0 when u M A diagram illustrating the use of a convex carrier wave;

[0055] Figure 2 c represents the common-mode voltage u in the 1+1+1 mode under different conditions. M <0 time u M A diagram illustrating the use of a convex carrier wave;

[0056] Figure 2 d represents the common-mode voltage u in the 1+1+1 mode under different conditions. M <0 time u M A diagram using a concave carrier wave;

[0057] Figure 3 For L_PB / M_2S(u L-u S >1) A diagram of the common-mode voltage in mode 1;

[0058] Figure 4 a is a diagram illustrating the duty cycle adjustment of the midpoint active control in the 1+1+1 mode of the N3S_CBPWM method;

[0059] Figure 4 b is a diagram illustrating the duty cycle adjustment of the midpoint active control in the N3S_CBPWM method under the 2+1+0 mode;

[0060] Figure 5 a is a comparison graph of switching losses between VSVPWM and CBPWM;

[0061] Figure 5 b is a comparison graph of the switching losses of N3S_CBPWM and CBPWM;

[0062] Figure 5 c is a comparison graph of the switching losses of N3S_CBPWM and VSVPWM;

[0063] Figure 6 a is the steady-state experimental waveform of CBPWM when m = 0.3 and φ = π / 12;

[0064] Figure 6 b is the steady-state experimental waveform of CBPWM when m = 0.3 and φ = 5π / 12;

[0065] Figure 6 c is the steady-state experimental waveform of CBPWM when m = 0.9 and φ = π / 12;

[0066] Figure 6 d is the steady-state experimental waveform of CBPWM when m = 0.9 and φ = 5π / 12;

[0067] Figure 7 a is the steady-state experimental waveform of VSVPWM when m = 0.3 and φ = π / 12;

[0068] Figure 7 b is the steady-state experimental waveform of VSVPWM when m = 0.3 and φ = 5π / 12;

[0069] Figure 7 c is the steady-state experimental waveform of VSVPWM when m = 0.9 and φ = π / 12;

[0070] Figure 7 d is the steady-state experimental waveform of VSVPWM when m = 0.9 and φ = 5π / 12;

[0071] Figure 8a is the steady-state experimental waveform of N3S_CBPWM when m = 0.3 and φ = π / 12;

[0072] Figure 8 b is the steady-state experimental waveform of N3S_CBPWM when m = 0.3 and φ = 5π / 12;

[0073] Figure 8 c is the steady-state experimental waveform of N3S_CBPWM when m = 0.9 and φ = π / 12;

[0074] Figure 8 d is the steady-state experimental waveform of N3S_CBPWM when m = 0.9 and φ = 5π / 12;

[0075] Figure 9 a is the experimental diagram of midpoint voltage recovery of N3S_CBPWM when m=0.3 and φ=π / 12;

[0076] Figure 9 b is the experimental diagram of midpoint voltage recovery of N3S_CBPWM when m=0.3, φ=5π / 12;

[0077] Figure 9 c is the experimental diagram of midpoint voltage recovery of N3S_CBPWM when m=0.9 and φ=π / 12;

[0078] Figure 9 d is the experimental diagram of midpoint voltage recovery of N3S_CBPWM when m=0.9 and φ=5π / 12;

[0079] Figure 10 a is the experimental diagram of midpoint voltage recovery of CBPWM when m = 0.9 and φ = 5π / 12;

[0080] Figure 10 b is the experimental diagram of midpoint voltage recovery of VSVPWM when m = 0.9 and φ = 5π / 12. Detailed Implementation

[0081] The present application will now be described in further detail with reference to the accompanying drawings. It should be noted that the following specific embodiments are only used to further illustrate the present application and should not be construed as limiting the scope of protection of the present application. Those skilled in the art can make some non-essential improvements and adjustments to the present application based on the above application content.

[0082] Example 1

[0083] This embodiment provides a novel midpoint potential clamping three-level inverter modulation method for achieving multi-objective coordinated control. The invention will be described in detail below with reference to the accompanying drawings:

[0084] Table 2. System Parameters

[0085]

[0086] Compared with the modulation method of traditional three-level inverters, this invention provides a modulation method with multi-objective coordinated control that features midpoint potential balance, reduced switching losses, and reduced common-mode voltage, comprising the following steps:

[0087] Step S1: Use a voltage sensor to acquire the voltage u of the upper capacitor on the DC side of the three-level inverter. C1 Lower capacitor voltage u C2 Three-phase output phase current i A i B i C Three-phase output phase voltage u A u B u C ;

[0088] Step S2: Introduce a modulation method that achieves multiple objectives such as midpoint voltage balance, reducing switching losses and lowering common-mode voltage, and derive eight modes of N3S_CBPWM based on switching characteristics;

[0089] Step S3: Based on the condition of reducing common-mode voltage, calculate the duty cycle of the eight modes of N3S_CBPWM and give the corresponding modulation wave constraint conditions.

[0090] Step S4: Select the optimal mode based on the principle of minimizing switching losses, and use the active midpoint voltage balancing algorithm under N3S_CBPWM for active midpoint control.

[0091] Step S2 comprehensively considers multiple objectives, including midpoint voltage balance, reducing switching losses, and lowering common-mode voltage, and includes the following steps:

[0092] Step S201: Use a voltage sensor to acquire the voltage u of the upper capacitor on the DC side of the three-level inverter. C1 Lower capacitor voltage u C2 Three-phase output phase current i A i B i C Three-phase output phase voltage u A u B u C Determine the magnitude of the three-phase output phase current and the three-phase output phase voltage, and the maximum voltage u. L =max(u A u B u C Minimum voltage u S =min(u A u B u Cand intermediate voltage u M =mid(u A u B u C ), maximum current i L =max(i A i B i C Minimum voltage i S =min(i A i B i C ) and intermediate voltage i M =mid(i A i B i C );

[0093] Step S202: Based on the number of switches per phase and the polarity of the phase in a single switching action, the N3S_CBPWM method can be divided into eight modes, as follows:

[0094] Within one switching cycle, if each phase is allowed to output levels 0, 1, and 2, based on the volt-second balance principle, the line voltage of a three-phase three-level inverter can be represented by a matrix as follows:

[0095] Gd=H (1)

[0096] here:

[0097]

[0098] d = [d L,2 ,d L,1 ,d L,0 ,d M,2 ,d M,1 ,d M,0 ,d S,2 ,d S,1 ,d S,0 ] T

[0099] H = [u L -u M ,u M -u S ,1,1,1] T

[0100] Considering the feasibility of duty cycle implementation in practical applications, the following constraints must be met:

[0101] 0 < d k,n <1 (2)

[0102] Where d k,n , represents the duty cycle of the k (k=L,M,S) phase n (n=0,1,2) level.

[0103] Taking the L_PB / M_2S mode as an example, L_PB indicates that the largest phase is clamped to the positive bus (S_NB indicates that the smallest phase is clamped to the negative bus), and M_2S indicates that the intermediate phase of the voltage has two switching operations, and the duty cycle at this time satisfies d L_1 =d L_0 =d S_2 =0, and the duty cycle in this mode can be calculated according to equations (1) and (2) and the duty cycle constraints mentioned above:

[0104]

[0105] Each mode can be further divided into two cases based on the polarity of a single switching action, resulting in a total of eight cases. However, L_PB / M_2S(u L The <0) mode can only be implemented when the modulation index m < 0.577. It can be replaced by the classic CBPWM. Similarly, S_PB / M_2S(u L The <0) mode can also be replaced by CBPWM.

[0106] Similar to the method described above, the duty cycle of the eight modes of N3S_CBPWM can be obtained.

[0107] In step S3, the method for reducing the common-mode voltage in N3S_CBPWM mode includes the following steps:

[0108] Classical CBPWM incurs switching losses once per phase, resulting in three-phase switching operations; this is referred to as the 1+1+1 mode below, while the mode proposed in this paper is called the 2+1+0 mode. N3S_CBPWM consists of 1+1+1 and 2+1+0 modes, and the eight modes of N3S_CBPWM are shown in the table below:

[0109]

[0110] The common-mode voltage of N3S_CBPWM based on dual modulation waves and a single carrier can be written as:

[0111]

[0112] In the formula L k_2 and L k_1 These are the instantaneous levels generated by comparing the dual-modulation wave of phase k with the carrier wave, with values ​​{0, 1}. To limit the common-mode voltage to ±1 / 6U... dc Then the following expression should be satisfied:

[0113]

[0114] Step S301: The method for reducing the common-mode voltage in 1+1+1 mode is as follows:

[0115] To reduce common-mode voltage, in 1+1+1 mode, the maximum phase voltage (u) is required. L ) and minimum voltage phase (u S A reverse carrier must be used. Let's define u... L Compared with concave carrier, u S Compared to a convex carrier. Compared to u M The carrier form being compared needs to be discussed separately for different situations. The methods for reducing common-mode voltage are as follows: Figure 3 As shown.

[0116] When u M When the voltage is greater than 0, the output levels of the voltage maximum phase and the voltage intermediate phase are both composed of 2 and 1, while the output level of the voltage minimum phase is composed of 1 and 0. Equation (4) can be simplified to:

[0117] 0≤L L_1 +L M_1 +L S_2 ≤2 (5)

[0118] like Figure 3 As shown in (a), both the maximum voltage phase and the intermediate voltage phase are compared with the concave carrier. In the middle of a switching cycle, there will be a period where the maximum voltage phase and the intermediate voltage phase simultaneously output a 2-level signal, and d... L,2 >d M,2 When L M_1 When = 1, L L_1 It must be 1. To satisfy the condition of equation (5), L must be 1. M_1 When = 1, L must be made S_2 =0, thus obtaining the duty cycle constraint d S,0 >d M,2 This is converted into a constrained u of a dual-modulated wave. S_2 +u M_1 ≤1.

[0119] Similarly, when comparing the voltage intermediate phase with the convex carrier phase, such as... Figure 3 As shown in (b). Requirement L M_1 When = 1, L must be made L_1 =0, the duty cycle must satisfy d M,2 <d L,1 This is converted into a constrained u of a dual-modulated wave. L_1 +u M_1 ≤1.

[0120] When u MWhen <0, both the intermediate voltage phase and the minimum voltage phase are compared with the concave carrier. In the middle of a switching cycle, there will be a range where the intermediate voltage phase and the minimum voltage phase both output a 0 level, and d S,0 >d M,0 , where d S,0 and d M,0 These represent the duty cycles of phase S (0 level) and phase M (0 level), respectively; when L M_2 When = 0, L S_2 To satisfy the condition of equation (3), let L be 0. M_2 When = 0, L L_1 =1, thus obtaining the constraint condition for reducing common-mode voltage modulation waves, namely:

[0121] u M_2 +u L_1 ≥1;

[0122] When comparing the voltage intermediate phase with the convex carrier, set L S_2 When = 0, L M_2 =1, reducing the common-mode voltage modulation wave constraint condition, that is:

[0123] u M_2 +u S_2 ≥1.

[0124] Step S302: The reduction of common-mode voltage in 2+1+0 mode is as follows:

[0125] In the 2+1+0 mode, one phase is always clamped. To reduce the common-mode voltage, the carrier waves of the second-phase switching operation and the first-phase switching operation must be reversed. Let's define that the second-phase switching operation is compared with the concave carrier wave, and the first-phase switching operation is compared with the convex carrier wave.

[0126] L_PB / M_2S(u L -u S >1) Taking mode as an example, in this mode, due to u L Clamped to level 2, the voltage minimum phase has only one switching action, and equation (4) simplifies to:

[0127] 0≤L M_1 +L M_2 +L S_2 ≤2 (6)

[0128] Voltage intermediate phase u M There are two switching actions, outputting three levels: 2, 1, and 0. To satisfy the common-mode voltage constraint, the duty cycle constraint is d. s,0 ≥d M,2 In this mode, the common-mode voltage is as follows: Figure 4 As shown.

[0129] In L_PB / M_2S(uL -u S In the >1) mode, the constraint on the duty cycle is transformed into a constraint on the dual-modulation wave, i.e., u M_1 +u S_2 ≤1.

[0130] The same method was used to analyze L_PB / S_2S(u L -u M <1) mode, where L M_2 =L L _=1L L =1, so equation (4) can be simplified to:

[0131] -1≤L M_1 +L S_1 +L S_2 ≤1 (7)

[0132] In this mode, the phase with the highest voltage has two switching actions, L S_1 +L S_2 ={0, 1, 2}, when L S_1 +L S_2 When the common-mode voltage is 2, it is impossible to satisfy (7) under any circumstances. The common-mode voltage can only be reduced to ±2 / 3, i.e., equation (8):

[0133] -2≤L M_1 +L S_1 +L S_2 ≤2 (8)

[0134] To prevent the common-mode voltage from reaching ±1, when L S_1 +L S_2 =2,L M_1 It cannot be 1, therefore its duty cycle must satisfy d. M1 ≥d S2 Its dual-modulation wave constraint is u S_1 +u M_1 ≤1.

[0135] This situation will also occur in S_NB / L_2S(u M -u S The common-mode voltage modulation wave constraint conditions for the eight modes of N3S_CBPWM can be deduced based on the above analysis method, which occurs in mode <1).

[0136] In step S4, the active midpoint voltage control method based on the N3S_CBPWM method includes the following steps:

[0137] Step S401: Define the direction of flow from the midpoint as the positive direction of the midpoint current. Active control of the midpoint voltage is achieved by introducing the midpoint current. Where T sThis represents one switching cycle.

[0138] Step S402: Active control of the neutral point voltage is also divided into two modes: 1+1+1 and 2+1+0. In the 1+1+1 mode, active neutral point voltage balance control can be achieved by injecting zero-sequence voltage into the three-phase modulation wave. The formula for calculating the magnitude of the injected zero-sequence voltage is:

[0139]

[0140] In the 2+1+0 mode, since one voltage is always clamped, zero-sequence voltage cannot be injected into the modulation voltage. Therefore, active neutral-point voltage balance control can only be achieved by injecting differential-mode voltage into the secondary switching phase. The formula for injecting differential-mode voltage is as follows: In the formula i x This is the current corresponding to the phase of the secondary switch operation.

[0141] exist Figure 5 The switching losses of CBPWM, VSVPWM, and N3S_CBPWM were compared. Figure 5 (a) compares the switching losses of VSVPWM and CBPWM. Across the full modulation and full power factor ranges, the switching losses of VSVPWM are greater than those of CBPWM. Figure 5 (b) compares the switching losses of N3S_CBPWM and CBPWM. At low modulation, the switching losses of N3S_CBPWM and CBPWM are the same; at high modulation, the switching loss of N3S_CBPWM is greater than that of CBPWM. When at high modulation and high power factor, the switching loss of N3S_CBPWM is slightly less than that of CBPWM. Figure 5 (c) The switching losses of N3S_CBPWM and VSVPWM were compared. N3S_CBPWM exhibited lower switching losses than VSVPWM across the entire range, with the ratio falling between 0.75 and 0.85.

[0142] This invention compares three modulation methods: classic CBPWM, VSVPWM, and N3S_CBPWM. Figure 6 This is the steady-state experimental waveform of CBPWM. Figure 7 and Figure 8 These are the steady-state experimental waveforms for VSVPWM and N3S_CBPWM. Under both modulation strategies, the midpoint voltage shows no fluctuation across the full modulation and power factor range. Comparing the phase voltages of the three modulation strategies, the common-mode voltage using N3S_CBPWM remains within ±1 / 6U under all conditions. dc The following values ​​are much smaller than CBPWM and VSVPWM.

[0143] Figure 9The experiment demonstrates the midpoint voltage recovery under different modulation and power factors of the N3S_CBPWM. It can be seen that the active midpoint voltage control method of this invention can rapidly restore the midpoint voltage to a balanced state. Figure 10 The experiment demonstrates the midpoint voltage recovery of CBPWM and VSVPWM under m = 0.9 and φ = 5π / 12. Although CBPWM can eliminate DC offset, it exhibits a third-harmonic ripple in the midpoint voltage. VSVPWM, on the other hand, shows better midpoint voltage balancing capability.

[0144] To achieve unconditional midpoint voltage balance within a single switching cycle, while simultaneously reducing switching losses and common-mode voltage, this invention proposes N3S_CBPWM. N3S_CBPWM possesses the same midpoint voltage balancing capability as VSVPWM, while exhibiting lower switching losses. Furthermore, compared to CBPWM and VSVPWM, N3S_CBPWM demonstrates a significant advantage in reducing common-mode voltage. Example results show that N3S_CBPWM exhibits superior performance.

[0145] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A multi-objective coordinated N3S_CBPWM modulation algorithm for a midpoint-clamped three-level inverter, characterized in that, Includes the following steps: S1: Collect the voltage u of the upper capacitor on the DC side of the three-level inverter. C1 Lower capacitor voltage u C2 Three-phase output phase current i A i B i C Three-phase output phase voltage u A u B u C The data is then sorted by size to obtain the processed data. Maximum voltage u L = max(u A ,u B ,u C ), minimum voltage u S = min(u A ,u B ,u C ) and intermediate voltage u M = mid(u A ,u B ,u C ); maximum current i L = max(i A ,i B ,i C ), minimum voltage i S = min(i A ,i B ,i C ) and intermediate voltage i M = mid(i A ,i B ,i C ); S2: Calculate the midpoint voltage balance modulation wave constraint condition and the common-mode voltage modulation wave reduction constraint condition in the 1+1+1 mode and the 2+1+0 mode, respectively, based on the processed data. The specific steps for reducing the common-mode voltage modulation wave constraint conditions in the 1+1+1 and 2+1+0 modes are as follows: S201: Set the common-mode voltage of the N3S_CBPWM modulation algorithm as follows: （1）； In the formula and These are the instantaneous levels generated by comparing the dual-modulated wave of the k-th phase with the carrier wave, and their values ​​are {0,1}. S202: According to equation (1), the common-mode voltage is set to be limited to ±1 / 6U. dc The conditions are: （2）； S203: The common-mode voltage modulation wave reduction constraint conditions in the 1+1+1 mode and the 2+1+0 mode are calculated according to Equation (2). The 1+1+1 mode and the 2+1+0 mode can be further divided into eight modes according to the number of switching operations per phase and the polarity of the phase of one switching operation. The results are shown in the table below: ； Among them, u M_1 u M_2 The voltages at levels M-phase 1 and M-phase 2; u L_1 u L_2 The voltages at L-phase 1 level and L-phase 2 level; u S_1 u S_2 The voltages are S-phase 1 level and S-phase 2 level; The midpoint voltage balance modulation wave constraint conditions in 1+1+1 mode and 2+1+0 mode include the following steps: Step S301: Define the direction of flow from the midpoint as the positive direction of the midpoint current, and introduce the midpoint current. To achieve active control of the midpoint voltage, where T s This represents one switching cycle; Step S302: Calculate the midpoint voltage balance modulation wave constraint conditions for the 1+1+1 mode and the 2+1+0 mode respectively: In the 1+1+1 mode, active neutral point voltage balance control is achieved by injecting zero-sequence voltage into the three-phase modulation wave. The formula for calculating the injected zero-sequence voltage is as follows: ； In the 2+1+0 mode, active neutral point voltage balance control is achieved by injecting differential mode voltage into the secondary switching phase. The formula for calculating the injected differential mode voltage is as follows: ； In the formula This is the current corresponding to the phase of the secondary switch operation; S3: Based on the midpoint voltage balance modulation wave constraint condition and the common-mode voltage reduction modulation wave constraint condition, the multi-objective coordinated control modulation algorithm of the midpoint clamped three-level inverter is obtained.

2. The multi-objective coordinated N3S_CBPWM modulation algorithm for a midpoint-clamped three-level inverter according to claim 1, characterized in that, The specific process for calculating the common-mode voltage modulation wave constraint condition in step S203 under the 1+1+1 mode is as follows: when Then, equation (2) can be simplified to: （3）； Both the maximum voltage phase and the intermediate voltage phase are compared with the concave carrier wave; in the middle of a switching cycle, there will be a range where the maximum voltage phase and the intermediate voltage phase simultaneously output a 2-level signal, and , where d L,2 and d M,2 These represent the duty cycles of L-phase 2-level and M-phase 2-level, respectively; when When =1, To satisfy the condition of equation (3), we set it to 1. When =1, =0, thus obtaining the duty cycle constraint. , where d S,2 This indicates the duty cycle of the S-phase 2 level; This is converted into a constraint condition for reducing the common-mode voltage modulation wave, namely: ； When comparing the voltage intermediate phase with the convex carrier, the setting is... When =1, =0, duty cycle must satisfy , where d L,1 This indicates the duty cycle of phase 1 (L-phase). This is converted into a constraint condition for reducing common-mode voltage modulation, i.e.: ； when At that time, both the intermediate voltage phase and the minimum voltage phase are compared with the concave carrier wave. In the middle of a switching cycle, there will be a period where the intermediate voltage phase and the minimum voltage phase simultaneously output a 0 level. , where d S,0 and d M,0 These represent the duty cycles of phase S (0 level) and phase M (0 level), respectively. when When =0, To satisfy the condition of equation (3), we set the value to 0. When =0, =1, thus obtaining the constraint condition for reducing common-mode voltage modulation waves, namely: ； When comparing the voltage intermediate phase with the convex carrier, the setting is... When =0, =1, reducing the common-mode voltage modulation wave constraint condition, that is: 。 3. The multi-objective coordinated N3S_CBPWM modulation algorithm for a midpoint-clamped three-level inverter according to claim 2, characterized in that, In step S203, L_PB / M_2S(u) is calculated under the 2+1+0 mode. M -u S <1) The specific process of reducing the common-mode voltage modulation wave constraint condition is as follows: L_PB / M_2S In this mode, L_PB indicates that the maximum phase is clamped to the positive bus, and M_2S indicates that the intermediate phase of the voltage has two switching operations. In this mode, because... Clamped to level 2, the voltage minimum phase has only one switching action. Therefore, equation (2) can be simplified to: （4） ； Set the duty cycle constraint as To meet the common-mode voltage constraint condition; The constraint on the duty cycle is transformed into a constraint on reducing the common-mode voltage modulation wave, that is: .

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