A 2×2 array receiving integrated chip for terahertz radar, detection and imaging

Abstract

The present invention discloses a 2×2 array receiving integrated chip for terahertz radar and detection imaging. The chip is based on GaAs technology and adopts a 1μm planar GaAs Schottky diode air bridge structure as a process layout for 2×2 array receiving integration for terahertz radar and detection imaging; the chip specifically includes 4 single-channel heterodyne receiver units integrated in a 2×2 array arrangement in a central symmetric manner; the frequency multiplier part of each single-channel heterodyne receiver unit is located outside the chip, and the mixer part is located inside the chip; each single-channel heterodyne receiver unit has 5 ports, namely a W-band local oscillator signal port, an RF radio frequency signal port, a DC bias port, an intermediate frequency signal output port, and a ground port. The present invention can realize the frequency conversion of 4-channel terahertz frequency band signals, improve the integration level, and reduce the system complexity and cost.

Description

Technical Field

[0001] The invention belongs to the technical field of detection imaging, and in particular relates to a 2×2 array receiving integrated chip for terahertz radar and detection imaging. Background Art

[0002] Miniaturization, high real-time performance, high resolution and large scene imaging are the future development trends of radar and detection imaging systems. Terahertz waves refer to electromagnetic waves with a frequency range of 0.1 to 10 THz, which is between the microwave frequency band and infrared. It has the advantages of both and is one of the frontiers and hot areas of information science and technology research.

[0003] Terahertz waves are shorter, have higher carrier frequencies, are easier to transmit large-bandwidth signals, and have extremely high resolution. Their application in radar and detection imaging will provide unique advantages for modern detection technology.

[0004] However, in array imaging systems, the number of array elements required to meet the imaging resolution requirement is large, the size is large, and the cost is high. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a 2×2 array receiving integrated chip for terahertz radar and detection imaging in view of the above-mentioned deficiencies in the prior art, which can improve chip integration and reduce system complexity and hardware cost.

[0006] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0007] A 2×2 array receiving integrated chip for terahertz radar, detection and imaging, the chip is based on GaAs technology, and uses a 1μm planar GaAs Schottky diode air bridge structure as a process layout for 2×2 array receiving integration for terahertz radar, detection and imaging;

[0008] The chip specifically includes four single-channel heterodyne receiver units integrated in a centrally symmetrical 2×2 array;

[0009] The frequency multiplier part of each single-channel heterodyne receiver unit is located outside the chip, and the mixer part is located inside the chip;

[0010] Each single-channel heterodyne receiver unit has 5 ports, namely, a W-band local oscillator signal port, an RF signal port, a DC bias port, an intermediate frequency signal output port and a ground port. The chip has 4 W-band local oscillator signal ports, 4 RF signal ports, 4 intermediate frequency signal output ports, 4 DC bias ports and 4 ground ports.

[0011] To optimize the above technical solutions, the specific measures taken also include:

[0012] The DC bias port mentioned above is a GaAs Schottky diode port. One end of the GaAs Schottky diode is connected to high voltage, and the other end is connected to a ground port through a square pad designed in the center.

[0013] In each of the above-mentioned single-channel heterodyne receiver units, the W-band local oscillator LO signal is fed into the W-band local oscillator signal port through a waveguide, and is multiplied into a terahertz band local oscillator signal through a frequency multiplier in a biased state. The detected terahertz band RF radio frequency signal is fed into the RF radio frequency signal port through a waveguide, and the frequency-converted intermediate frequency signal under the mixer is connected to the SMA output through four intermediate frequency signal output ports.

[0014] The W-band local oscillator signal ports are located on the left and right sides of the chip;

[0015] The RF radio frequency signal port is located in the upper and lower directions of the chip and faces the center;

[0016] The intermediate frequency signal output port is located on the upper and lower sides of the chip and outputs outward;

[0017] The DC bias port is arranged inside the single-channel heterodyne receiver unit and is used for DC biasing of the mixer and the frequency multiplier.

[0018] The W-band local oscillator signal port is an E-plane probe, which is fed through a waveguide cavity.

[0019] The above-mentioned RF radio frequency signal port is fed through a waveguide cavity perpendicular to the chip surface.

[0020] The above-mentioned intermediate frequency signal output port is connected through an SMA connector.

[0021] The above four RF radio frequency signal ports form a 400um×1300um matrix.

[0022] The voltage range of the above-mentioned DC bias port is -2V to 2V, which is used for signal frequency multiplication and modulation.

[0023] The present invention has the following beneficial effects:

[0024] The present invention is based on a 2×2 array monolithic integrated receiving chip of an advanced 1 μm planar GaAs Schottky diode process, has a high degree of integration, and can achieve reception within the 850 GHz range working in the terahertz frequency band.

[0025] The chip of the present invention adopts 4 single-channel heterodyne receiver units to be integrated in a 2×2 array arrangement, and a port on one side of a GaAs Schottky diode that realizes the mixing and frequency multiplication functions is connected to the designed central pad GND for grounding, and the upper and lower ends of the chip are applied, and the DC bias terminal voltage range of the other side port of the GaAs Schottky diode is -2V to 2V, the W-band local oscillator signal port is located on the left and right outside of the chip, the RF radio frequency signal port is located in the upper and lower directions of the chip and faces the center, and the intermediate frequency signal output port is located on the upper and lower sides of the chip for outward output. The 2×2 array chip of the present invention is integrated on a single chip, which can realize the frequency conversion of 4-channel terahertz frequency band signals, improve the integration level, and reduce the system complexity and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is the overall architecture diagram of the chip of the present invention;

[0027] Figure 2 This is an example diagram of the signal port of the chip of the present invention;

[0028] Figure 3 It is a schematic diagram of the chip structure layout of the present invention. DETAILED DESCRIPTION

[0029] The embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0030] See also Figure 1-3 The present invention discloses a 2×2 array receiving integrated chip for terahertz radar and detection imaging. The chip is based on GaAs technology and uses a 1μm planar GaAs Schottky diode air bridge structure as a process layout for 2×2 array receiving integration for terahertz radar and detection imaging. The specific introduction is as follows:

[0031] The chip of the present invention is based on GaAs Schottky diode devices and is designed based on 1μm GaAs process parameters. The overall integrated chip solution architecture is as follows: Figure 1 As shown, the frequency multiplication part is located on the outside, and the frequency mixing part is located on the inside. The chip specifically includes four single-channel heterodyne receiver units integrated in a centrally symmetrical 2×2 array;

[0032] Chip signal ports and structures such as Figure 2 , Figure 3 As shown, the frequency multiplier part of each single-channel heterodyne receiver unit is located outside the chip, and the mixer part is located inside the chip, and they are arranged in a centrally symmetrical manner.

[0033] Each single-channel heterodyne receiver unit has 5 ports, namely, a W-band local oscillator signal port, an RF signal port, a DC bias port, an intermediate frequency signal output port and a ground port. The chip has 4 W-band local oscillator signal (LO) ports, 4 RF signal ports, 4 intermediate frequency signal (IF) output ports, 4 DC bias (DC) ports and 4 ground ports.

[0034] For details, see Figure 1 In each single-channel heterodyne receiver unit, the W-band local oscillator LO signal is fed into the W-band local oscillator signal port through a waveguide, and is multiplied into a terahertz band local oscillator signal through a frequency multiplier in a biased state. The detected terahertz band RF signal is fed into the RF signal port through a waveguide, and the frequency-converted intermediate frequency signal (4-8GHZ) under the mixer is connected to the SMA output through four intermediate frequency signal output ports.

[0035] The W-band local oscillator signal port is located on the left and right outside of the chip;

[0036] The RF radio frequency signal port is located in the upper and lower directions of the chip and faces the center;

[0037] See also Figure 2 , 4 RF signal ports form a 400um×1300um matrix;

[0038] The intermediate frequency signal (IF) output port is located on the upper and lower sides of the chip and outputs outward;

[0039] The DC bias port is arranged inside the single-channel heterodyne receiver unit and is used for DC biasing of the mixer and the frequency multiplier.

[0040] Furthermore, the W-band local oscillator signal port is an E-plane probe, which is fed through a waveguide cavity.

[0041] The RF radio frequency signal port is fed through a waveguide cavity perpendicular to the chip surface.

[0042] The intermediate frequency signal output port is connected through an SMA connector.

[0043] The DC bias port is a GaAs Schottky diode port, which is applied through the centrally designed square pad to achieve the mixing and frequency doubling functions of the GaAs Schottky diode port connected to the central pad GND designed to apply the DC bias voltage.

[0044] In the embodiment, the voltage range of the DC bias port is -2V to 2V, which is used for frequency multiplication and modulation of the signal.

[0045] The terahertz high-frequency 2×2 array chip designed by the present invention is based on GaAs technology and adopts a 1μm planar GaAs Schottky diode air bridge structure as the process version. Figure 1 The integrated design becomes a monolithic integrated chip, the specific structure is as follows Figure 3 As shown. A superheterodyne circuit structure is adopted, including mixing and frequency multiplication devices, which are composed of 4 single-channel heterodyne receiving structures (single-channel heterodyne receiver units). The 4 single-channel heterodyne receiving structures are arranged in a central symmetric manner. The GaAs Schottky diode port for realizing the mixing and frequency multiplication functions is connected to the designed center pad GND to apply a DC bias voltage. The DC (DC bias) terminal voltage range is -2V to 2V, so that the frequency multiplication function and modulation frequency conversion function can be realized. The W-band local oscillator signal port is located on the left and right outside of the chip, the RF radio frequency signal port is located in the upper and lower directions of the chip and faces the center, and the intermediate frequency signal output port is located on the upper and lower sides of the chip and outputs outward. The W-band local oscillator LO signal is fed through a waveguide, and is multiplied to a terahertz frequency band local oscillator signal through a GaAs frequency multiplication device in a biased state. The detected terahertz frequency band RF signal is fed into the RF signal port through a waveguide, and the IF intermediate frequency signal (4 to 8GHZ) is down-converted by the mixer and connected to the SMA output through 4 ports.

[0046] The present invention can realize the frequency conversion of 4-channel terahertz frequency band signals, improve the integration level, and reduce the system complexity and cost.

[0047] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A 2×2 array receiving integrated chip for terahertz radar, detection and imaging, characterized in that: The chip is based on GaAs technology and uses a 1μm planar GaAs Schottky diode air bridge structure as a process layout for 2×2 array reception integration for terahertz radar and detection imaging; The chip specifically includes four single-channel heterodyne receiver units integrated in a centrally symmetrical 2×2 array; The frequency multiplier part of each single-channel heterodyne receiver unit is located outside the chip, and the mixer part is located inside the chip; Each single-channel heterodyne receiver unit has 5 ports, namely, a W-band local oscillator signal port, an RF radio frequency signal port, a DC bias port, an intermediate frequency signal output port and a ground port. The chip has 4 W-band local oscillator signal ports, 4 RF radio frequency signal ports, 4 intermediate frequency signal output ports, 4 DC bias ports and 4 ground ports.

2. A 2×2 array receiving integrated chip for terahertz radar, detection and imaging according to claim 1, characterized in that: The DC bias port is a GaAs Schottky diode port, one end of the GaAs Schottky diode is connected to a high voltage, and the other end is connected to a ground port through a square pad designed in the center.

3. The 2×2 array receiving integrated chip for terahertz radar, detection and imaging according to claim 2, characterized in that: In each single-channel heterodyne receiver unit, the W-band local oscillator LO signal is fed into the W-band local oscillator signal port through a waveguide, and is multiplied into a terahertz band local oscillator signal by a frequency multiplier in a biased state. The detected terahertz band RF signal is fed into the RF signal port through a waveguide, and four intermediate frequency signals are obtained through a mixer and connected to the SMA output through four intermediate frequency signal output ports.

4. A 2×2 array receiving integrated chip for terahertz radar, detection and imaging according to any one of claims 1 to 3, characterized in that: The W-band local oscillator signal port is located on the left and right outside of the chip; The RF radio frequency signal port is located in the upper and lower directions of the chip and faces the center; The intermediate frequency signal output port is located on the upper and lower sides of the chip and outputs outward; The DC bias port is arranged inside the single-channel heterodyne receiver unit and is used for DC biasing of the mixer and the frequency multiplier.

5. The 2×2 array receiving integrated chip for terahertz radar, detection and imaging according to claim 4, characterized in that: The W-band local oscillator signal port is an E-plane probe, which is fed through a waveguide cavity.

6. A 2×2 array receiving integrated chip for terahertz radar, detection and imaging according to claim 5, characterized in that: The RF radio frequency signal port is fed through a waveguide cavity perpendicular to the chip surface.

7. A 2×2 array receiving integrated chip for terahertz radar, detection and imaging according to claim 6, characterized in that: The intermediate frequency signal output port is connected through an SMA connector.

8. The 2×2 array receiving integrated chip for terahertz radar, detection and imaging according to claim 4, characterized in that: The four RF signal ports form a 400um×1300um matrix.

9. The 2×2 array receiving integrated chip for terahertz radar, detection and imaging according to claim 3, characterized in that: The voltage range of the DC bias port is -2V to 2V, and is used for frequency multiplication and modulation of signals.

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