Test apparatus, method, computer device, storage medium and program product

Abstract

The application relates to a test device, a method, a computer device, a storage medium and a program product. The test device comprises a test mainboard and a short-circuit board. The test mainboard is connected with a to-be-tested adapter card, and the to-be-tested adapter card is connected with the short-circuit board. The test mainboard outputs a test signal to the to-be-tested adapter card, so that the test signal reaches the short-circuit board through the to-be-tested adapter card; the short-circuit board outputs a backflow signal according to the output signal of the to-be-tested adapter card, so that the backflow signal reaches the test mainboard after passing through the to-be-tested adapter card; and the test mainboard performs signal analysis according to the backflow signal output by the short-circuit board, and obtains a performance test result of the to-be-tested adapter card. In the scheme, a signal loop is formed through the short-circuit board in the test device, the test mainboard in the test device can locate whether a problem exists in a channel of the to-be-tested adapter card according to the backflow signal, the synchronous test of multiple to-be-tested adapter cards can be realized through the short-circuit board, the loss of a server mainboard slot is reduced, and the service life of the server mainboard is prolonged.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a testing device, method, computer equipment, storage medium and program product. BACKGROUND

[0002] With the gradual improvement of server application and performance, it is often necessary to introduce a function expansion card or a riser card (PCI-E Riser card) plugged into the PCI-E interface to expand or switch the mainboard PCI-E interface. When the pass of the PCI-E Riser card in the server is broken, the performance of the server in actual operation may be affected, and even the system hardware of the server may be seriously damaged. Therefore, the pass connectivity detection of the PCIe Riser card is very important.

[0003] The current detection method for the PCI-E Riser card includes installing the PCIe Riser card on the server for on-board debugging, that is, installing the PCI-E Riser card into the matching server mainboard, inserting the corresponding card on the PCI-E Riser card, and verifying the performance of the card plugged on the PCI-E Riser card through function verification and script testing under the server operating system, so as to judge the performance of the PCI-E Riser card.

[0004] The above method of judging the performance of the PCI-E Riser card will cause great consumption of the slot of the server mainboard in the scene of detecting the performance of multiple PCI-E Riser cards, and affect the service life of the slot of the server mainboard. SUMMARY

[0005] Therefore, it is necessary to provide a testing device, method, computer equipment, storage medium and program product capable of improving the accuracy of the detection result of the performance of the PCI-E Riser card in view of the above technical problems.

[0006] In a first aspect, the present application provides a testing device, comprising: a test mainboard and a short circuit board; the test mainboard is connected with a to-be-tested riser card, and the to-be-tested riser card is connected with the short circuit board;

[0007] The test mainboard is configured to output a test signal to the to-be-tested riser card, so that the test signal reaches the short circuit board through the to-be-tested riser card;

[0008] The short circuit board is configured to output a backflow signal according to the output signal of the to-be-tested riser card, so that the backflow signal reaches the test mainboard after passing through the to-be-tested riser card;

[0009] The test mainboard is also used for signal analysis according to the backflow signal output by the short circuit board, so as to obtain the performance test result of the to-be-tested adapter card.

[0010] In the scheme, the signal loop is formed through the short circuit board in the test device, and the test mainboard in the test device can locate whether there is a problem in the path of the to-be-tested adapter card according to the backflow signal, and does not depend on the server and the test tag card for indirectly testing the to-be-tested adapter card. The direct testing can be realized through the short circuit board and the test mainboard, and the synchronous performance testing of multiple to-be-tested adapter cards can be realized through the short circuit board, so that the performance of the to-be-tested adapter card does not need to be tested by plugging the server mainboard multiple times, the mechanical complexity of the tooling is reduced, the wear of the slot of the server mainboard is reduced, the service life of the server mainboard is prolonged, and the cost consumption is reduced.

[0011] In one of the optional embodiments, the test mainboard comprises a first processor;

[0012] The first processor is configured to output a first test signal so that the first test signal passes through the to-be-tested adapter card and reaches the short circuit board;

[0013] The short circuit board is configured to output a first backflow signal according to the first output signal of the to-be-tested adapter card, so that the first backflow signal passes through the to-be-tested adapter card and reaches the test mainboard;

[0014] The first processor is further configured to perform signal analysis according to the first backflow signal, so as to obtain the performance test result of the path between the transmitting end and the receiving end of the to-be-tested adapter card.

[0015] In the embodiment, the short circuit loop of the path between the transmitting end and the receiving end of the to-be-tested adapter card is formed through the short circuit board, so that the addition of cables and other test tools can be effectively avoided, and the simultaneous detection of multiple to-be-tested adapter cards can be realized, thereby improving the performance detection efficiency of the multiple to-be-tested adapter cards.

[0016] In one of the optional embodiments, the output end of the first processor is connected with the transmitting end of the to-be-tested adapter card, and the receiving end of the to-be-tested adapter card is connected with the input end of the first processor;

[0017] The transmitting end of the short circuit board is connected with the transmitting end of the to-be-tested adapter card, and the receiving end of the short circuit board is connected with the receiving end of the to-be-tested adapter card.

[0018] In the embodiment, the short circuit loop of the path between the transmitting end and the receiving end of the to-be-tested adapter card is formed through the short circuit board, so that the addition of cables and other test tools can be effectively avoided, and the simultaneous detection of multiple to-be-tested adapter cards can be realized, thereby improving the performance detection efficiency of the multiple to-be-tested adapter cards.

[0019] In one of the optional embodiments, the test mainboard further comprises a second processor;

[0020] The second processor is configured to output a second test signal so that the second test signal passes through the to-be-tested adapter card to the short circuit board.

[0021] The short circuit board is configured to output a second backflow signal according to the second output signal of the to-be-tested adapter card, so that the second backflow signal passes through the to-be-tested adapter card to the first processor.

[0022] The first processor is further configured to perform signal analysis on the second backflow signal to obtain a performance test result of the IIC channel of the to-be-tested adapter card.

[0023] In the embodiment, the short circuit loop of the IIC channel in the to-be-tested adapter card is formed by the short circuit board, so that the test tool such as a cable is effectively avoided, and the positioning detection of the IIC channel of the to-be-tested adapter card is accurately and conveniently realized.

[0024] In one of the optional embodiments, the output end of the second processor is connected with the IIC pin of the to-be-tested adapter card; the hundred-meg signal pin of the to-be-tested adapter card is connected with the input end of the first processor, and the IIC pin and the hundred-meg signal pin of the to-be-tested adapter card are connected with the short circuit board; the IIC pin of the short circuit board is connected with the IIC pin of the to-be-tested adapter card, and the hundred-meg signal pin of the short circuit board is connected with the hundred-meg signal pin of the to-be-tested adapter card.

[0025] In the embodiment, the short circuit loop of the IIC channel in the to-be-tested adapter card is formed by the short circuit board, so that the test tool such as a cable is effectively avoided, and the positioning detection of the IIC channel of the to-be-tested adapter card is accurately and conveniently realized.

[0026] In one of the optional embodiments, the test mainboard further comprises an IIC expansion component; the input end of the IIC expansion component is connected with the output end of the second processor, and the output end of the IIC expansion component is connected with the IIC pin of the to-be-tested adapter card.

[0027] The second processor is configured to output a second test signal so that the second test signal passes through the IIC expansion component and the IIC pin of the to-be-tested adapter card to the short circuit board.

[0028] In the embodiment, by adding the IIC expansion component, the IIC address conflict is avoided as much as possible in the scene of simultaneous detection of multiple PCI-E Riser cards.

[0029] In one of the optional embodiments, the test mainboard further comprises a power supply.

[0030] The power supply is configured to output a third test signal so that the third test signal passes through the voltage pin of the to-be-tested adapter card to the short circuit board.

[0031] The short circuit board is used for outputting a third backflow signal according to a third output signal of a voltage pin of the to-be-tested adapter card, so that the third backflow signal reaches the second processor through a wake-up pin of the to-be-tested adapter card.

[0032] The second processor is further configured to output the third backflow signal to the first processor.

[0033] The first processor is further configured to perform signal analysis on the third backflow signal to obtain a performance test result of a power supply path of the to-be-tested adapter card.

[0034] In the embodiment, the voltage pin and the wake-up pin of the PCI-E Riser card are short-circuited to form a loop, and the third test signal output by the power supply of the test mainboard is completely backflowed to the CPLD of the test mainboard, which can effectively avoid adding test tools such as cables, and can locate whether the power supply path of the PCI-E Riser card is abnormal.

[0035] In one of the optional embodiments, the short circuit board comprises a voltage pin and a wake-up pin; the short-circuited voltage pin is connected with the voltage pin of the to-be-tested adapter card; and the wake-up pin of the short circuit board is connected with the wake-up pin of the to-be-tested adapter card.

[0036] In the embodiment, the voltage pin and the wake-up pin of the PCI-E Riser card are short-circuited to form a loop, and the third test signal output by the power supply of the test mainboard is completely backflowed to the CPLD of the test mainboard, which can effectively avoid adding test tools such as cables, and can locate whether the power supply path of the PCI-E Riser card is abnormal.

[0037] In one of the optional embodiments, the test mainboard further comprises at least one of a buzzer, a nixie tube and an LED connected with the first processor.

[0038] The first processor is further configured to output performance abnormality information through at least one of the buzzer, the nixie tube and the LED in a case where it is determined that the performance of the to-be-tested adapter card is abnormal.

[0039] In the embodiment, the path information of the abnormal PCI-E Riser card can be output through the buzzer, the nixie tube and the LED, and the abnormal path can be effectively located, and the detection efficiency of the PCI-E Riser card is improved.

[0040] In a second aspect, a test method is provided, which is applied to the test device provided in any one of the first aspect, and the method comprises:

[0041] The test mainboard of the test device outputs a test signal to the to-be-tested adapter card, so that the test signal reaches the short circuit board of the test device through the to-be-tested adapter card.

[0042] The short circuit board outputs a return flow signal according to an output signal of the adapter card to be tested, so that the return flow signal reaches the test mainboard after passing through the adapter card to be tested;

[0043] The test mainboard analyzes the return flow signal output by the short circuit board to obtain a performance test result of the adapter card to be tested.

[0044] In this embodiment, the signal loop is formed by the short circuit board in the test device, and the test mainboard in the test device can locate whether there is a problem in the channel of the adapter card to be tested according to the return flow signal. Moreover, the direct test can be realized through the short circuit board and the test mainboard, the method of direct test improves the accuracy of the channel test result of the adapter card to be tested, reduces the mechanical complexity of the tooling, reduces the damage to the server mainboard, and reduces the cost consumption.

[0045] In a third aspect, a computer device is provided. The computer device includes a memory and a processor. The memory stores a computer program. The processor implements the method of the second aspect when executing the computer program.

[0046] In a fourth aspect, a computer readable storage medium is provided. The computer readable storage medium stores a computer program. The computer program is executed by a processor to implement the method of the second aspect.

[0047] In a fifth aspect, a computer program product is provided. The computer program product includes a computer program. The computer program is executed by a processor to implement the method of the second aspect.

[0048] The test device, the method, the computer device, the storage medium, and the program product. The test device includes a test mainboard and a short circuit. The test mainboard is connected with an adapter card to be tested, and the adapter card to be tested is connected with the short circuit board. The test mainboard outputs a test signal to the adapter card to be tested, so that the test signal reaches the short circuit board after passing through the adapter card to be tested. The short circuit board outputs a return flow signal according to an output signal of the adapter card to be tested, so that the return flow signal reaches the test mainboard after passing through the adapter card to be tested. The test mainboard analyzes the return flow signal output by the short circuit board to obtain a performance test result of the adapter card to be tested. In this solution, the signal loop is formed by the short circuit board in the test device, and the test mainboard in the test device can locate whether there is a problem in the channel of the adapter card to be tested according to the return flow signal. Moreover, the synchronous performance test of multiple adapter cards to be tested can be realized through the short circuit board, the performance of the adapter card to be tested does not need to be tested by plugging the server mainboard for multiple times, the mechanical complexity of the tooling is reduced, the damage to the slot of the server mainboard is reduced, the service life of the server mainboard is prolonged, and the cost consumption is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 An environment diagram for testing a Riser card in one embodiment of the prior art;

[0050] Figure 2 A block diagram of the structure of a testing device in one embodiment;

[0051] Figure 3 A block diagram of the structure of a testing device including a first processor in another embodiment;

[0052] Figure 4 A block diagram of the structure of a testing device including a first processor in another embodiment;

[0053] Figure 5 A block diagram of the structure of a testing device including a clock buffer in another embodiment;

[0054] Figure 6 A block diagram of the structure of a testing device including a gate module in another embodiment;

[0055] Figure 7 A block diagram of the structure of a testing device including a second processor in another embodiment;

[0056] Figure 8 A block diagram of the structure of a testing device including a second processor in another embodiment;

[0057] Figure 9 A block diagram of the structure of a testing device including an IIC expansion module in another embodiment;

[0058] Figure 10 A block diagram of the structure of a testing device including a sensor in another embodiment;

[0059] Figure 11 A block diagram of the structure of a testing device including a power supply in another embodiment;

[0060] Figure 12 A block diagram of the structure of a testing device including a power supply in another embodiment;

[0061] Figure 13 A block diagram of the structure of a testing device including an LED in a power supply in another embodiment;

[0062] Figure 14 A block diagram of the structure of a testing device including a buzzer, an LED, a number tube in another embodiment;

[0063] Figure 15 A flow diagram of a testing method in one embodiment;

[0064] Figure 16 Figure 1 is a diagram of an internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0065] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0066] With the gradual improvement of server application and performance, it is often necessary to introduce a PCI-E Riser card to expand or connect the PCI-E interface of the motherboard. Usually, each server has multiple PCI-E Riser cards to achieve the expansion of functions or the improvement of performance.

[0067] At present, these PCI-E Riser cards lack corresponding detection methods, and it is difficult to determine the path connectivity of the PCI-E Riser card before actual installation. When part of the paths of the server installation application PCI-E Riser card is in the open circuit condition, the performance of the server in the actual running process may be reduced, and even the system hardware may be seriously damaged.

[0068] At present, the hardware path detection scheme for the PCI-E Riser card is to install the PCI-E Riser card on the server device for on-board debugging, that is, to install the PCI-E Riser card on the matching server motherboard, and to insert the corresponding test card on the PCI-E Riser card. The performance of the test card inserted on the PCI-E Riser card is verified by methods such as function verification and script testing under the system, so as to indirectly judge the advantages and disadvantages of the PCI-E Riser card. As shown in Figure 1 , the connection relationship among the PCI-E Riser card, the test card and the server motherboard is included. Figure 1

[0069] However, the above scheme is relatively cumbersome to operate, and requires matching test equipment and cables for testing, or builds a server whole machine for testing. When verifying, the test card device inserted on the PCI-E Riser card needs to be checked under the system, or the performance of the test card is verified by test scripts and other methods, so as to indirectly judge whether the path of the PCI-E Riser card is normal. Not only is time wasted, but also part of the IO function may be missed. When a large number of PCI-E Riser cards are verified and tested, repeated plugging and unplugging will be performed on the server PCI-E gold finger, which will reduce the service life of the corresponding server PCI-E slot and affect the quality of the server.

[0070] ​The application provides a test device, as shown in the drawings, which comprises a test mainboard and a short-circuit board; wherein the test mainboard is connected with a to-be-tested adapter card, and the to-be-tested adapter card is connected with the short-circuit board. Figure 2

[0071] The test mainboard is used for outputting a test signal to the to-be-tested adapter card, so that the test signal reaches the short-circuit board through the to-be-tested adapter card.

[0072] The short-circuit board is used for outputting a backflow signal according to the output signal of the to-be-tested adapter card, so that the backflow signal reaches the test mainboard after passing through the to-be-tested adapter card.

[0073] The test mainboard is further used for performing signal analysis according to the backflow signal output by the short-circuit board, so as to obtain a performance test result of the to-be-tested adapter card.

[0074] Optionally, the test mainboard can be a substrate comprising a processor and a power supply, and the processor can be one or more processors such as a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a Complex Programmable Logic Device (CPLD), a Microcontroller Unit (MCU) and the like.

[0075] Optionally, the adapter card can be a PCI-E interface adapter card in a server, for example, a PCI-E Riser card; or an adapter card of other signal interfaces in a server.

[0076] Optionally, the short-circuit board is used for being connected with the to-be-tested adapter card and the test mainboard, so as to form a short-circuit signal path, and the short-circuit board can be set in accordance with the to-be-tested adapter card based on the characteristics of the short-circuit board.

[0077] In this embodiment, the short-circuit board is connected to the to-be-tested adapter card, the to-be-tested adapter card is inserted into a card slot slot of the test mainboard, the test mainboard is powered on, and after a period of time, the test of the to-be-tested adapter card is started. The period of time can be 10 seconds, 20 seconds, etc.

[0078] ​Exemplarily, the test mainboard in the test device outputs a test signal to the to-be-tested adapter card. Here, the test signal can be determined according to the channel to be tested by the to-be-tested adapter card. Exemplarily, if the power supply channel of the to-be-tested adapter card is to be tested, the test signal output by the test mainboard can be understood as a voltage value; if the IIC channel of the to-be-tested adapter card is to be tested, the test signal output by the test mainboard can be IIC address information; if other channels of the to-be-tested adapter card are to be tested, the test mainboard can output a pulse modulation signal. In this embodiment, the signal output by the test mainboard is determined based on the channels included in the to-be-tested adapter card.

[0079] The test signal is output by the test mainboard, and is output to the short circuit board through the to-be-tested adapter card. The short circuit board outputs a return signal according to the signal output by the to-be-tested adapter card. It should be noted that, in the case that the channel of the to-be-tested adapter card is normal, the output signal of the to-be-tested adapter card is the test signal; if the channel of the to-be-tested adapter card fails, the output signal of the to-be-tested adapter card can be other signals. The short circuit board outputs a return signal to the to-be-tested adapter card according to the output signal of the to-be-tested adapter card. The return signal passes through the to-be-tested adapter card, and the test mainboard acquires the return signal for signal analysis. Similarly, the return signal passes through the to-be-tested adapter card. In the case that the channel of the to-be-tested adapter card is normal, the return signal received by the test mainboard through the to-be-tested adapter card is the return signal; if the channel of the to-be-tested adapter card fails, the return signal received by the test mainboard through the to-be-tested adapter card can be other signals.

[0080] Optionally, the test mainboard performs signal analysis according to the received return signal. Optionally, the test mainboard can analyze the waveform of the return signal, the signal parameter of the return signal, or other parameters indicated by the return signal, such as a voltage value, to determine whether the channel corresponding to the return signal has a fault, and obtain the performance detection result of the to-be-tested adapter card. Optionally, in the case that the to-be-tested adapter card includes multiple channels, that is, in the case that the test mainboard receives return signals corresponding to multiple channels, the test mainboard performs signal analysis on the return signals corresponding to all channels. If the return signal corresponding to at least one channel is abnormal, that is, if at least one channel has a fault, the channel is located and prompt information of the fault of the channel is output, and it is determined that the performance of the to-be-tested adapter card is abnormal. If the return signals corresponding to all channels are normal, that is, if all channels are normal, it is determined that the performance of the to-be-tested adapter card is normal.

[0081] The test device includes a test mainboard and a short circuit. The test mainboard is connected with the to-be-tested adapter card, and the to-be-tested adapter card is connected with the short circuit board. The test mainboard outputs a test signal to the to-be-tested adapter card, so that the test signal reaches the short circuit board through the to-be-tested adapter card; the short circuit board outputs a backflow signal according to the output signal of the to-be-tested adapter card, so that the backflow signal reaches the test mainboard after passing through the to-be-tested adapter card; and the test mainboard performs signal analysis according to the backflow signal output by the short circuit board, to obtain a performance test result of the to-be-tested adapter card. In this solution, a signal loop is formed through the short circuit board in the test device, and the test mainboard in the test device can locate whether a path of the to-be-tested adapter card has a problem according to the backflow signal. In addition, the short circuit board can also be used to perform synchronous performance tests on multiple to-be-tested adapter cards, without the need to plug in the server mainboard multiple times to test the performance of the to-be-tested adapter card, thereby reducing the mechanical complexity of the tooling, reducing the loss of the slot of the server mainboard, prolonging the service life of the server mainboard, and reducing the cost consumption.

[0082] In one of the optional embodiments, as shown in Figure 3 the test mainboard includes a first processor.

[0083] The first processor is configured to output a first test signal, so that the first test signal reaches the short circuit board through the to-be-tested adapter card.

[0084] The short circuit board is configured to output a first backflow signal according to the first output signal of the to-be-tested adapter card, so that the first backflow signal reaches the test mainboard through the to-be-tested adapter card.

[0085] The first processor is further configured to perform signal analysis according to the first backflow signal, to obtain a performance test result of a path between a transmitting end and a receiving end of the to-be-tested adapter card.

[0086] Optionally, the first processor can be any one of an FPGA, a PLD, a CPLD, and an MCU. Optionally, the first test signal output by the first processor can be a pulse width modulation (PWM).

[0087] In the case that the first processor is a CPLD and the to-be-tested adapter card is a PCI-E Riser card, the following can be referred to for illustration: Figure 3The CPLD outputs a first test signal for testing the connectivity of the path between the transmitting end and the receiving end of the PCI-E Riser card. For example, the first test signal can be a PWM signal, which passes through the PCI-E Riser card to the short circuit board, the short circuit board forms a return signal of the PWM signal according to the signal output by the PCI-E Riser card, and the return signal of the PWM signal passes through the PCI-E Riser card to the CPLD, the CPLD analyzes the signal according to the return signal of the PWM signal, and determines the connectivity of the path between the transmitting end and the receiving end in the PCI-E Riser card. For example, if the CPLD determines that the signal state of the return signal of the PWM signal is abnormal, it is determined that there is a fault in the path between the transmitting end and the receiving end in the PCI-E Riser card.

[0088] Optionally, as shown in Figure 4 The output end of the first processor is connected with the transmitting end of the adapter card to be tested, and the receiving end of the adapter card to be tested is connected with the input end of the first processor; the transmitting end of the short circuit board is connected with the transmitting end of the adapter card to be tested, and the receiving end of the short circuit board is connected with the receiving end of the adapter card to be tested.

[0089] The adapter card to be tested includes a transmitting port and a receiving port, and the short circuit board forms a short circuit loop with the transmitting end and the receiving end, and the short circuit board also includes a transmitting end and a receiving end. The test mainboard can detect the connectivity of the path between the transmitting end and the receiving end by outputting a first test signal.

[0090] For example, taking the first processor as a CPLD and the adapter card to be tested as a PCI-E Riser card as an example, it can be referred to Figure 4 The PCI-E Riser card includes a transmitting port TXDP and TXDN and a receiving port RXDP and RXDN. The transmitting port TXDP and TXDN of the PCI-E Riser card are connected with the transmitting port TXDP and TXDN of the short circuit board, and the receiving port RXDP and RXDN of the short circuit board are connected with the receiving port RXDP and RXDN of the PCI-E Riser card. The transmitting port TXDP and TXDN of the PCI-E Riser card are connected with the output end of the CPLD; the receiving port RXDP and RXDN of the PCI-E Riser card are connected with the input end of the CPLD.

[0091] Exemplarily, the first test signal can be a PWM signal. The PWM signal output by the CPLD passes through the transmitting ports TXDP and TXDN of the PCI-E Riser card and reaches the transmitting ports TXDP and TXDN of the short circuit board. The short circuit board forms a return signal of the PWM signal according to the signal output by the PCI-E Riser card, and outputs the return signal to the receiving ports RXDP and RXDN of the PCI-E Riser card through the receiving ports RXDP and RXDN of the short circuit board, and the receiving ports RXDP and RXDN of the PCI-E Riser card output the return signal to the CPLD. The CPLD analyzes the signal according to the return signal of the PWM signal, and determines the connectivity of the path between the transmitting end TXDP and TXDN and the receiving end RXDP and RXDN in the PCI-E Riser card. Exemplarily, if the CPLD determines that the signal state of the return signal of the PWM signal is abnormal, it is determined that there is a fault in the path between the transmitting end TXDP and TXDN and the receiving end RXDP and RXDN in the PCI-E Riser card.

[0092] Optionally, in order to realize the expansion of the first test signal, a clock buffer Buffer can also be added in the test mainboard. Exemplarily, taking the first processor as the CPLD and the to-be-tested adapter card as the PCI-E Riser card as an example, it can be referred to Figure 5 As shown in the figure, the input end of the clock buffer Buffer is connected with the output end of the CPLD, and the output end of the clock buffer Buffer is connected with the transmitting ports TXDP and TXDN of the PCI-E Riser card respectively, so as to realize the expansion of the first test signal output by the CPLD.

[0093] Optionally, in order to improve the utilization rate of the pins of the CPLD, a gate circuit can also be arranged in the test mainboard. Exemplarily, taking the first processor as the CPLD and the to-be-tested adapter card as the PCI-E Riser card as an example, it can be referred to Figure 6 As shown in the figure, the input end of the gate circuit is connected with the receiving ends RXDP and RXDN of the PCI-E Riser card, and the output end of the gate circuit is connected with the input end of the CPLD, so as to realize the integration and collection of the multiple signals output by the receiving end of the PCI-E Riser card. Exemplarily, if the state of the return signal output by at least one port of the receiving end of the PCI-E Riser card is abnormal, the state of the return signal output by the gate circuit is abnormal, and it is determined that there is a fault in the path between the transmitting end TXDP and TXDN and the receiving end RXDP and RXDN in the PCI-E Riser card; if the states of the return signals output by all the ports of the receiving end of the PCI-E Riser card are normal, the state of the return signal output by the gate circuit is normal, and it is determined that the path between the transmitting end TXDP and TXDN and the receiving end RXDP and RXDN in the PCI-E Riser card is normal.

[0094] In the embodiment, the short circuit board is used to form a short circuit loop of the transmitting end and the receiving end of the to-be-tested adapter card, so that the test tool such as a cable can be effectively avoided. In addition, the clock buffer and the gate circuit are used to branch and integrate the test signals, so that the utilization efficiency of the pins or ports of the first processor (CPLD) is improved, and the logic resource consumption of the first processor (CPLD) is reduced, thereby the simultaneous detection of multiple to-be-tested adapter cards can be realized, and the performance detection efficiency of the multiple to-be-tested adapter cards is improved.

[0095] In order to further detect other paths of the to-be-tested adapter card, in one of the optional embodiments, as shown in Figure 7 The test mainboard further includes a second processor.

[0096] The second processor is configured to output a second test signal, so that the second test signal passes through the to-be-tested adapter card and reaches the short circuit board.

[0097] The short circuit board is configured to output a second backflow signal according to the second output signal of the to-be-tested adapter card, so that the second backflow signal passes through the to-be-tested adapter card and reaches the first processor.

[0098] The first processor is further configured to perform signal analysis on the second backflow signal to obtain a performance test result of an IIC path of the to-be-tested adapter card.

[0099] Optionally, the second processor can be an MCU or any other processor. Optionally, the second test signal output by the second processor can be used to directly or indirectly indicate IIC address information.

[0100] Taking the first processor as a CPLD, the to-be-tested adapter card as a PCI-E Riser card, and the second processor as an MCU as an example, refer to Figure 7 The MCU can be used as a master device of the IIC, the CPLD can be used as a slave device of the IIC, the MCU can send different IIC address information to the PCI-E Riser card, and the IIC path of the PCI-E Riser card can be tested. For example, the different IIC address information passes through the PCI-E Riser card and reaches the short circuit board, the short circuit board forms corresponding backflow information according to the IIC address information output by the PCI-E Riser card, the backflow information passes through the PCI-E Riser card and reaches the CPLD, and the CPLD analyzes the backflow information of the IIC address information to determine the connectivity of the IIC path of the PCI-E Riser card. For example, if the CPLD determines that the backflow information of the IIC address information is incorrect, it is determined that the IIC path of the PCI-E Riser card has a fault.

[0101] Optionally, as shown in Figure 8As shown, the output end of the second processor is connected with the IIC pin of the to-be-tested adapter card; the hundred-megabit signal pin of the to-be-tested adapter card is connected with the input end of the first processor, and the IIC pin and the hundred-megabit signal pin of the to-be-tested adapter card are connected with the short circuit board; the IIC pin of the short circuit board is connected with the IIC pin of the to-be-tested adapter card, and the hundred-megabit signal pin of the short circuit board is connected with the hundred-megabit signal pin of the to-be-tested adapter card.

[0102] The to-be-tested adapter card includes the IIC pin and the hundred-megabit signal pin, and correspondingly, the short circuit board also includes the IIC pin and the hundred-megabit signal pin, so that the short circuit board forms a short circuit loop with the test mainboard and the to-be-tested adapter card, and the connectivity of the IIC channel in the to-be-tested adapter card is detected through the output of the second test signal.

[0103] Exemplarily, the first processor is a CPLD, the to-be-tested adapter card is a PCI-E Riser card, and the second processor is an MCU, which can be referred to as Figure 8 As shown. The MCU can be a master device of IIC, the CPLD can be a slave device of IIC, the MCU sends different IIC address information to the PCI-E Riser card for testing the connectivity of the IIC channel of the PCI-E Riser card. Exemplarily, the different IIC address information reaches the short circuit board through the IIC pin of the PCI-E Riser card, the short circuit board forms corresponding backflow information according to the IIC address information output by the IIC pin of the PCI-E Riser card, and outputs the backflow information to the hundred-megabit signal pin and the RESERVE pin of the PCI-E Riser card through the hundred-megabit signal pin of the short circuit board, so that the CPLD receives the IIC address information output by the hundred-megabit signal pin and the RESERVE pin of the PCI-E Riser card, and the MCU waits for the CPLD to respond according to the received IIC address information, and if the CPLD does not respond, it is determined that the IIC channel in the PCI-E Riser card has a fault.

[0104] Optionally, in order to further expand the IIC address information, as shown in Figure 9 The test mainboard further includes an IIC expansion component; the input end of the IIC expansion component is connected with the output end of the second processor, and the output end of the IIC expansion component is connected with the IIC pin of the to-be-tested adapter card.

[0105] The second processor is configured to output a second test signal, so that the second test signal reaches the short circuit board through the IIC expansion component and the IIC pin of the to-be-tested adapter card.

[0106] Exemplarily, the first processor is a CPLD, the to-be-tested adapter card is a PCI-E Riser card, the second processor is an MCU, and the IIC expansion component is an IIC switch, which can be referred to as Figure 9As shown, the MCU can serve as the master of the IIC, and the CPLD can serve as the slave of the IIC. The MCU outputs the IIC address information to the IIC switch. The IIC switch includes 16 address channels and can output different IIC address information after expansion. The IIC address information output by the IIC pins of the PCI-E Riser card reaches the short circuit board. The short circuit board forms corresponding reflow information according to the IIC address information output by the IIC pins of the PCI-E Riser card. The reflow information is output to the 100 Mbps signal pins and the RESERVE pins of the PCI-E Riser card through the 100 Mbps signal pins of the short circuit board. Thus, the CPLD receives the IIC address information output by the 100 Mbps signal pins and the RESERVE pins of the PCI-E Riser card. The MCU waits for the CPLD to respond according to the received IIC address information. If the CPLD does not respond, it is determined that the IIC channel in the PCI-E Riser card is faulty. After obtaining the judgment result of the IIC channel, the MCU can send the judgment result to the CPLD through the UART. Thus, the CPLD can summarize the judgment results of the channels to obtain the detection result of the PCI-E Riser card.

[0107] Optionally, at least one temperature sensor sensor can be arranged in the PCI-E Riser card. Figure 10 As shown, in this case, the MCU can also directly read the temperature value of the sensor in the PCI-E Riser card through the IIC interface of the gold finger. According to the temperature value and the preset temperature threshold, it is determined whether the sensor in the PCI-E Riser card is in a normal working state. Thus, the judgment result is sent to the CPLD through the UART. Thus, the CPLD can summarize the judgment results of the channels to obtain the detection result of the PCI-E Riser card.

[0108] In this embodiment, the short circuit loop of the IIC channel in the to-be-tested adapter card is formed through the short circuit board, which can effectively avoid adding a cable or other test tools. By adding the IIC expansion component, the IIC address conflict can be avoided as much as possible in the scenario of simultaneous detection of multiple PCI-E Riser cards.

[0109] In one of the optional embodiments, as shown in Figure 11 The test mainboard further includes a power supply.

[0110] The power supply is configured to output a third test signal, so that the third test signal reaches the short circuit board through the voltage pins of the to-be-tested adapter card.

[0111] The short circuit board is configured to output a third backflow signal according to a third output signal of a voltage pin of the to-be-tested riser card, so that the third backflow signal reaches the second processor through a wake pin of the to-be-tested riser card.

[0112] The second processor is further configured to output the third backflow signal to the first processor.

[0113] The first processor is further configured to perform signal analysis on the third backflow signal to obtain a performance test result of a power supply path of the to-be-tested riser card.

[0114] In the embodiment, the power supply is configured to supply power to the test mainboard and to detect the power supply path of the to-be-tested riser card.

[0115] With the first processor being a CPLD, the to-be-tested riser card being a PCI-E Riser card, and the second processor being an MCU, refer to FIG. 1. Figure 11 The power supply outputs a voltage signal, which reaches a detection voltage channel of the short circuit board through a voltage pin of the PCI-E Riser card. The detection voltage channel of the short circuit board obtains a backflow voltage according to an output voltage of the voltage pin of the PCI-E Riser card, and outputs the backflow voltage to the MCU through a wake pin of the PCI-E Riser card. The MCU detects whether the backflow voltage of the PCI-E Riser card is normal through an ADC function, and then determines whether the power supply path of the PCI-E Riser card is normal, so as to output a detection result to the CPLD through a UART pin.

[0116] Optionally, the power supply of the test mainboard can supply power of 5V, 3V3, and 12V, that is, the voltage pin includes pins corresponding to 5V, 3V3, and 12V respectively; and the wake pin includes at least one of a WAKE pin and a RESET pin.

[0117] Optionally, as shown in FIG. 2, the short circuit board includes voltage pins and a wake pin. The shorted voltage pins are connected to voltage pins of the to-be-tested riser card, and the wake pin of the short circuit board is connected to a wake pin of the to-be-tested riser card. Figure 12 Correspondingly, the short circuit board also includes voltage pins and a wake pin, so that the short circuit board forms a short circuit loop with the test mainboard and the to-be-tested riser card, and detects the connectivity of the power supply path in the to-be-tested riser card by outputting a third test signal.

[0118] With the first processor being a CPLD, the to-be-tested riser card being a PCI-E Riser card, and the second processor being an MCU, refer to FIG. 1.

[0119] Figure 12 ​The power supply outputs a 5V and / or 3V3 voltage signal to the PCI-E Riser card, so that the internal sensors and other devices of the PCI-E Riser card work normally. The voltage signal is output to the voltage pins of the short circuit board through the voltage pins of the PCI-E Riser card. The short circuit board obtains a backflow voltage according to the output voltage of the voltage pins of the PCI-E Riser card, and outputs the backflow voltage to the MCU through the wake-up pins of the short circuit board. The MCU detects whether the backflow voltage of the PCI-E Riser card is normal through the ADC function, and then judges whether the power supply path of the PCI-E Riser card is normal, so as to output the detection result to the CPLD through the UART pin.

[0120] Optionally, the short circuit board can also be provided with an LED to detect whether it is powered, to exclude the failure condition that the short circuit board is not powered. For reference can be made to Figure 13 as shown.

[0121] In this embodiment, the 3V3 and 3V3_AUX of the PCI-E Riser card are respectively short-circuited with the WAKE and RESET signals to form a loop. The third test signal output by the power supply of the test mainboard is all reflowed to the CPLD of the test mainboard, which can effectively avoid adding test tools such as cables, and can locate whether the power supply path of the PCI-E Riser card is abnormal.

[0122] In the case that at least one path of the to-be-tested adapter card is abnormal, in one of the optional embodiments, as shown in Figure 14 The test mainboard further comprises at least one of a buzzer, a digital tube, and an LED connected with the first processor.

[0123] The first processor is further configured to output performance abnormal information through at least one of the buzzer, the digital tube, and the LED when it is determined that the performance of the to-be-tested adapter card is abnormal.

[0124] In this embodiment, the test mainboard is provided with a digital tube, a buzzer, an LED and other devices for alarm function, the first processor is a CPLD, the to-be-tested adapter card is a PCI-E Riser card, and the second processor is an MCU. For reference can be made to Figure 14 When the CPLD detects that a certain path of the PCI-E Riser card is abnormal, it can output the information of the abnormal PCI-E Riser card through the buzzer ringing and the LED flashing, and at the same time, the port number corresponding to the abnormal path of the PCI-E Riser card can be displayed through the digital tube. Optionally, the device for outputting abnormal information can also be a display screen, a liquid crystal screen, a diode, etc. This embodiment does not limit this.

[0125] In the embodiment, the abnormal channel information of the PCI-E Riser card can be output by the buzzer, the nixie tube, the LED and the like, the abnormal channel can be effectively located, and the detection efficiency of the PCI-E Riser card is improved.

[0126] The test method provided by the embodiment can be applied to the test device as shown in Figure 1 In one embodiment, as shown in Figure 15 A test method is provided, which is applied to the test device as shown in Figure 1 for example, and includes the following steps:

[0127] In step 201, a test signal is output to the to-be-tested adapter card through a test mainboard of the test device, so that the test signal reaches a short-circuit board of the test device through the to-be-tested adapter card.

[0128] In the embodiment, after the test device is powered on, the test signal is output to the to-be-tested adapter card through the test mainboard in the test device. For example, if the power supply channel of the to-be-tested adapter card is detected, the test signal output by the test mainboard can be understood as a voltage value; if the IIC channel of the to-be-tested adapter card is detected, the test signal output by the test mainboard can be IIC address information; if other channels of the to-be-tested adapter card are detected, the test mainboard can output a pulse modulation signal. The signal output by the test mainboard in the embodiment is determined based on the channels included in the to-be-tested adapter card.

[0129] In step 202, a backflow signal is output by the short-circuit board according to the output signal of the to-be-tested adapter card, so that the backflow signal reaches the test mainboard through the to-be-tested adapter card.

[0130] In the embodiment, the short-circuit board outputs the backflow signal according to the received output signal of the to-be-tested adapter card, so that the backflow signal reaches the test mainboard through the to-be-tested adapter card. For example, if the to-be-tested adapter card outputs a voltage value, the short-circuit board outputs a backflow voltage corresponding to the voltage value, the backflow voltage is output to the test mainboard through the to-be-tested adapter card; if the to-be-tested adapter card outputs IIC address information, the short-circuit board outputs backflow IIC address information corresponding to the IIC address information, the backflow IIC address information is output to the test mainboard through the to-be-tested adapter card; if the to-be-tested adapter card outputs other signals, such as a PWM signal, the short-circuit board outputs backflow PWM signals corresponding to the PWM signal, the backflow PWM signals are output to the test mainboard through the to-be-tested adapter card.

[0131] In step 203, signal analysis is performed by the test mainboard according to the backflow signal output by the short-circuit board, and a performance test result of the to-be-tested adapter card is obtained.

[0132] In the embodiment, the test mainboard performs signal analysis according to the received backflow signal. Optionally, the test mainboard can analyze the waveform of the backflow signal, the signal parameter of the backflow signal, or other parameters indicated by the backflow signal, such as a voltage value, to determine whether the channel corresponding to the backflow signal has a fault, and obtain the performance detection result of the to-be-tested adapter card. Optionally, in the case where the to-be-tested adapter card includes multiple channels, that is, in the case where the test mainboard receives backflow signals corresponding to multiple channels, the test mainboard performs signal analysis on the backflow signals corresponding to all channels. If the backflow signal corresponding to at least one channel is abnormal, that is, at least one channel has a fault, the channel is located and prompt information that the channel has a fault is output, and it is determined that the performance of the to-be-tested adapter card is abnormal. If the backflow signals corresponding to all channels are normal, that is, all channels are normal, it is determined that the performance of the to-be-tested adapter card is normal.

[0133] In the above test method, the test mainboard of the test device outputs a test signal to the to-be-tested adapter card, so that the test signal passes through the to-be-tested adapter card to reach the short-circuit board of the test device; the short-circuit board outputs a backflow signal according to the output signal of the to-be-tested adapter card, so that the backflow signal reaches the test mainboard after passing through the to-be-tested adapter card; and the test mainboard performs signal analysis according to the backflow signal output by the short-circuit board to obtain the performance test result of the to-be-tested adapter card. In the scheme, the signal loop is formed by the short-circuit board in the test device, and the test mainboard in the test device can locate whether the channel of the to-be-tested adapter card has a problem according to the backflow signal. In addition, the short-circuit board can also realize synchronous performance testing of multiple to-be-tested adapter cards, without the need to plug in the server mainboard multiple times to test the performance of the to-be-tested adapter card, thereby reducing the mechanical complexity of the tooling, reducing the loss of the slot of the server mainboard, prolonging the service life of the server mainboard, and reducing the cost consumption.

[0134] It should be understood that, although each step in the flowchart involved in each of the above-described embodiments is shown in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart involved in each of the above-described embodiments can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or stages in other steps.

[0135] In one embodiment, a computer device, which can be a server, is provided, and an internal structure diagram of the computer device can be as shown in Figure 16The computer device includes a processor, a memory and a network interface connected through a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The database of the computer device is configured to store test data. The network interface of the computer device is configured to communicate with an external terminal through a network connection. The computer program is executed by the processor to implement a test method.

[0136] Those skilled in the art can understand that Figure 16 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0137] In one embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the following steps:

[0138] The test mainboard of the test device outputs a test signal to the to-be-tested adapter card, so that the test signal passes through the to-be-tested adapter card and reaches the short-circuit board of the test device;

[0139] The short-circuit board outputs a backflow signal according to the output signal of the to-be-tested adapter card, so that the backflow signal passes through the to-be-tested adapter card and reaches the test mainboard;

[0140] The test mainboard analyzes the backflow signal output by the short-circuit board to obtain a performance test result of the to-be-tested adapter card.

[0141] The computer device provided in the above embodiments has similar implementation principles and technical effects to the above method embodiments, and thus will not be described here.

[0142] In one embodiment, a computer readable storage medium is provided, storing a computer program, and the computer program is executed by a processor to implement the following steps:

[0143] The test mainboard of the test device outputs a test signal to the to-be-tested adapter card, so that the test signal passes through the to-be-tested adapter card and reaches the short-circuit board of the test device;

[0144] The short-circuit board outputs a backflow signal according to the output signal of the to-be-tested adapter card, so that the backflow signal passes through the to-be-tested adapter card and reaches the test mainboard;

[0145] The performance test result of the to-be-tested adapter card is obtained by the test mainboard performing signal analysis according to the backflow signal output by the short circuit board.

[0146] The computer readable storage medium provided in the above embodiment has similar implementation principles and technical effects to the above method embodiments, and details are not described herein.

[0147] In one embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the following steps:

[0148] The test mainboard of the testing device outputs a test signal to the to-be-tested adapter card, so that the test signal passes through the to-be-tested adapter card and reaches the short circuit board of the testing device;

[0149] The short circuit board outputs a backflow signal according to the output signal of the to-be-tested adapter card, so that the backflow signal reaches the test mainboard after passing through the to-be-tested adapter card;

[0150] The performance test result of the to-be-tested adapter card is obtained by the test mainboard performing signal analysis according to the backflow signal output by the short circuit board.

[0151] The computer program product provided in the above embodiment has similar implementation principles and technical effects to the above method embodiments, and details are not described herein.

[0152] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties.

[0153] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric memory (Ferroelectric Random Access Memory, FRAM), phase change memory (Phase Change Memory, PCM), graphene memory, etc. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0154] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0155] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A testing device, characterized in that, The testing device includes: a test motherboard and a shorting board; the test motherboard is connected to the adapter card under test, and the adapter card under test is connected to the shorting board; the test motherboard includes a first processor and a second processor; The test motherboard is used to output a test signal to the adapter card under test, so that the test signal reaches the shorting board through the adapter card under test; the test signal includes at least one of voltage value, IIC address information and pulse modulation signal; wherein, the second processor is used to output a second test signal, so that the second test signal reaches the shorting board through the adapter card under test; The shorting board is used to output a second return signal according to the second output signal of the adapter card under test, so that the second return signal reaches the first processor through the adapter card under test; The first processor is further configured to perform signal analysis on the second return signal to obtain the performance test results of the IIC path of the adapter card under test; The test motherboard also includes an IIC expansion component, the input of which is connected to the output of the second processor, and the output of which is connected to the IIC pin of the adapter card under test. The second processor is configured to output the second test signal so that the second test signal passes through the IIC expansion component and the IIC pin of the adapter card under test to reach the shorting board; The shorting board is used to output a return signal according to the output signal of the adapter card under test, so that the return signal reaches the test motherboard after passing through the adapter card under test; The test motherboard is also used to perform signal analysis based on the return current signal output by the short-circuit board to obtain the performance test results of the adapter card under test. The test motherboard also includes gate circuits. The return signal passes through the adapter card under test and then reaches the gate circuits, and finally reaches the test motherboard.

2. The apparatus according to claim 1, characterized in that, The first processor is configured to output a first test signal so that the first test signal passes through the adapter card under test and reaches the shorting board; The shorting board is used to output a first return signal according to the first output signal of the adapter card under test, so that the first return signal passes through the adapter card under test and reaches the test motherboard. The first processor is further configured to perform signal analysis based on the first return signal to obtain the performance test results of the path between the transmitter and receiver of the adapter card under test.

3. The apparatus according to claim 2, characterized in that, The output terminal of the first processor is connected to the transmitter terminal of the adapter card under test, and the receiver terminal of the adapter card under test is connected to the input terminal of the first processor. The transmitting end of the shorting board is connected to the transmitting end of the adapter card under test, and the receiving end of the shorting board is connected to the receiving end of the adapter card under test.

4. The apparatus according to claim 3, characterized in that, The test motherboard also includes a clock buffer, the input of which is connected to the output of the first processor, and the output of which is connected to the transmitter of the adapter card under test.

5. The apparatus according to claim 1, characterized in that, The output of the second processor is connected to the IIC pin of the adapter card under test; the 100Mbps signal pin of the adapter card under test is connected to the input of the first processor; and both the IIC pin and the 100Mbps signal pin of the adapter card under test are connected to the shorting board. The IIC pin of the shorting board is connected to the IIC pin of the adapter card under test, and the 100Mbps signal pin of the shorting board is connected to the 100Mbps signal pin of the adapter card under test.

6. The apparatus according to claim 1, characterized in that, The test motherboard also includes a power supply; The power supply is used to output a third test signal so that the third test signal reaches the shorting board through the voltage pin of the adapter card under test; The shorting board is used to output a third return signal according to the third output signal of the voltage pin of the adapter card under test, so that the third return signal reaches the second processor through the wake-up pin of the adapter card under test; The second processor is further configured to output the third return signal to the first processor; The first processor is also used to perform signal analysis on the third return signal to obtain the performance test results of the power supply path of the adapter card under test.

7. The apparatus according to claim 6, characterized in that, The shorting board includes a voltage pin and a wake-up pin; the shorted voltage pin is connected to the voltage pin of the adapter card under test; the wake-up pin of the shorting board is connected to the wake-up pin of the adapter card under test.

8. A testing method, characterized in that, Applied in the testing apparatus as described in any one of claims 1-7, the method comprises: The test motherboard of the test device outputs a test signal to the adapter card under test, so that the test signal passes through the adapter card under test and reaches the shorting board of the test device; the test signal includes at least one of voltage value, IIC address information and pulse modulation signal; The shorting board outputs a return signal based on the output signal of the adapter card under test, so that the return signal passes through the adapter card under test and reaches the test motherboard. The test motherboard performs signal analysis based on the return current signal output by the short-circuit board to obtain the performance test results of the adapter card under test. The test motherboard also includes gate circuits. The return signal passes through the adapter card under test and then reaches the gate circuits, and finally reaches the test motherboard. The second test signal is output by the second processor of the test motherboard, so that the second test signal reaches the shorting board through the adapter card under test; The shorting board outputs a second return signal based on the second output signal of the adapter card under test, so that the second return signal passes through the adapter card under test and reaches the first processor of the test motherboard. The first processor performs signal analysis on the second return signal to obtain the performance test results of the IIC path of the adapter card under test. The second test signal is output by the second processor so that the second test signal passes through the IIC expansion component of the test motherboard and the IIC pin of the adapter card under test to reach the shorting board. The input terminal of the IIC expansion component is connected to the output terminal of the second processor, and the output terminal of the IIC expansion component is connected to the IIC pin of the adapter card under test.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method of claim 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method of claim 8.

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