Aging test interface expansion module and aging test system

Abstract

The invention discloses an aging test interface expansion module and an aging test system, including an SPI bus, an IIC bus, an IO expansion chip, a decoder and a first buffer register; the SPI bus and the IIC bus are used to connect to the aging test device, the IO expansion chip is connected to the IIC bus, the decoder is connected to the IO expansion chip, the first buffer register is connected to the decoder and the CS port of the SPI bus, and is used to connect to the CS port of the slave device; wherein the IIC bus controls the IO expansion chip and the decoder to generate an enable signal for switching the slave device, and the enable signal controls the selection of the slave device; the SPI bus communicates with the selected slave device. The circuit principle of the aging test interface expansion module of the invention is simple, easy to implement, and has low hardware cost; only one SPI and one IIC control bus are needed, the driving capability is strong, and high-efficiency and stable operation can be maintained after multiple channels are loaded, and hundreds of slave devices can be easily mounted on the SPI bus, and the number of expansion interfaces is large; it has strong scalability.

Description

Technical Field

[0001] The present invention relates to the technical field of aging test, and in particular to an aging test interface expansion module and an aging test system. Background Art

[0002] With the development of the optical communication industry, there is an increasing demand for power-on aging testing or aging screening of optical chips and optical devices. Since aging takes a long time and there are many devices being aged at the same time, it is necessary to continuously monitor the voltage and current values ​​of the devices during the aging process. With the increase in the number of devices for aging monitoring, hundreds of voltage and current channels need to be monitored in real time on a set of aging system boards, and the number of ADC and DAC chips required will reach dozens or even hundreds. This requires considering how to simply and quickly expand the number of devices mounted on the SPI bus.

[0003] The current solution to expand the number of devices mounted on the SPI bus is: the SCLK and MOSI signals of the SPI bus are directly connected to multiple slave devices at the same time, and the MISO and CS signals of the SPI bus itself are not used. Other IO ports are selected by software to simulate the MISO and CS signals, so that each slave device is assigned a CS chip select signal output port and SPI_MISO signal receiving port simulated by the IO port. However, the number of devices that can be directly driven by such an SPI bus port is limited, generally not more than ten slave devices. The expansion requires a large number of IO ports to be simulated, and the chip select signal simulated by the software requires frequent switching control during the communication process, which is easy to operate and greatly reduces the acquisition rate. If more separate SPI buses are used, the demand for bus master devices will increase greatly, which will greatly increase the cost of the aging system, and IO resources will also be consumed in large quantities. The software workload will also increase further. Summary of the invention

[0004] The purpose of the present invention is to provide an aging test interface expansion module and an aging test system, which are simple and easy to implement, have low hardware cost, strong scalability and a large number of expansion interfaces.

[0005] The invention discloses an aging test interface expansion module, comprising an SPI bus, an IIC bus, an IO expansion chip, a decoder and a first buffer register; the SPI bus and the IIC bus are used to connect with an aging test device, the IO expansion chip is connected with the IIC bus, the decoder is connected with the IO expansion chip, the first buffer register is connected with the decoder and the CS port of the SPI bus, and is used to connect with the CS port of a slave device;

[0006] Among them, the IIC bus controls the IO expansion chip and the decoder to generate an enable signal for switching the slave device, and the enable signal controls the selection of the slave device; the SPI bus communicates with the selected slave device.

[0007] Optionally, the first buffer register includes a first input port, multiple first enable ports and multiple first output ports; the first input port is connected to the CS port of the SPI bus; the first enable port is connected to the decoder to receive an enable signal of the decoder; and the first output port is used to connect to the CS port of the slave device.

[0008] Optionally, the expansion module further includes a third buffer register; the first input port of the first buffer register is connected to the CS port of the SPI bus through the third buffer register.

[0009] Optionally, the expansion module further includes a second buffer register; the second buffer register is connected to the decoder and the MISO port of the SPI bus, and is used to connect to the SDO port of the slave device.

[0010] Optionally, the second buffer register includes a second input port, multiple second enable ports and multiple second output ports; the second input port is connected to the MISO port of the SPI bus; the second enable port is connected to the decoder to receive an enable signal of the decoder; and the second output port is used to connect to the SDO port of the slave device.

[0011] Optionally, the expansion module further includes a third buffer register; the second input port of the second buffer register is connected to the MISO port of the SPI bus through the third buffer register.

[0012] Optionally, the expansion module further includes a third buffer register; the SCLK port of the SPI bus is used to connect to the SCK port of the device through the third buffer register.

[0013] Optionally, the MOSI port of the SPI bus is used to connect to the SDI port of the slave device respectively through the third buffer register.

[0014] Optionally, there is one first input port, and there are four first enable ports and four first output ports.

[0015] The invention also discloses an aging test system, which is characterized by comprising an aging test device and the above aging test interface expansion module; the aging test device is connected with an SPI bus and an IIC bus.

[0016] The circuit principle of the aging test interface expansion module of the present invention is simple, easy to implement, and has low hardware cost; it only needs one SPI and one IIC control bus, has strong driving capability, can maintain efficient and stable operation after multiple loads, can easily realize hundreds of slave devices mounted on the SPI bus, and has a large number of expansion interfaces; it has strong scalability and can simply realize continued expansion; and has simple software control logic. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The included drawings are used to provide a further understanding of the embodiments of the present invention, which constitute a part of the specification, are used to illustrate the implementation of the present invention, and together with the text description, explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0018] Figure 1 is a schematic block diagram of an aging test interface expansion module according to an embodiment of the present invention;

[0019] Figure 2 It is a specific circuit diagram of the aging test interface expansion module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative, but the present invention can be implemented in many alternative forms and should not be construed as being limited to only the embodiments described herein.

[0021] The present invention is described in detail below with reference to the accompanying drawings and optional embodiments.

[0022] like Figure 1 and Figure 2 As shown, as an embodiment of the present invention, an aging test interface expansion module is disclosed, including an SPI bus, an IIC bus, an IO expansion chip, a decoder and a first buffer register; the SPI bus and the IIC bus are used to connect to the aging test device, the IO expansion chip is connected to the IIC bus, the decoder is connected to the IO expansion chip, the first buffer register is connected to the decoder and the CS port of the SPI bus, and is used to connect to the CS port of the slave device; wherein the IIC bus controls the IO expansion chip and the decoder to generate an enable signal for switching the slave device, and the enable signal controls the selection of the slave device; the SPI bus communicates with the selected slave device.

[0023] The aging test interface expansion module of the present invention controls the IO expansion chip through the IIC bus, which can expand a part of the available IO ports. With the decoding function of the decoder, the number of available ports can be increased geometrically (increased by 2 nports, n is the number of IO ports before decoding). These ports are used to control the selection of slave devices (such as ADC chips) that need to be collected. When all channels of a slave device chip are collected and communicated, the IIC bus selects the next slave device for selection. Specifically, when a certain SPI slave device (such as ADC, DAC chip, etc.) is selected, the SPI bus starts to communicate. During the communication process, according to the SPI communication protocol, the CS signal will be set low or high for each frame of data transmission. Since the SPI_CS signal of the SPI bus itself is used, all channel data collection communications in the same slave device (such as ADC, DAC chip, etc.) can be completed efficiently. At the same time, due to the enhanced driving effect of the first buffer register, the scalability can also be greatly improved.

[0024] The circuit principle of the aging test interface expansion module of the present invention is simple, easy to implement, and has low hardware cost; it only needs one SPI and one IIC control bus, has strong driving capability, can maintain efficient and stable operation after multiple loads, can easily realize hundreds of slave devices mounted on the SPI bus, and has a large number of expansion interfaces; it has strong scalability and can simply realize continued expansion; and has simple software control logic.

[0025] Specifically, the first buffer register includes a first input port, multiple first enable ports and multiple first output ports; the first input port is connected to the CS port of the SPI bus; the first enable port is connected to the decoder to receive the enable signal of the decoder; the first output port is used to connect to the CS port of the slave device.

[0026] Specifically, the expansion module further includes a third buffer register; the first input port of the first buffer register is connected to the CS port of the SPI bus through the third buffer register. The third buffer register can further enhance the driving effect and greatly improve the scalability.

[0027] Specifically, the expansion module further includes a second buffer register; the second buffer register is connected to the decoder and the MISO port of the SPI bus, and is used to connect to the SDO port of the slave device. The second buffer register can further enhance the driving effect and greatly improve the scalability.

[0028] Specifically, the second buffer register includes a second input port, multiple second enable ports and multiple second output ports; the second input port is connected to the MISO port of the SPI bus; the second enable port is connected to the decoder to receive the enable signal of the decoder; the second output port is used to connect to the SDO port of the slave device.

[0029] Specifically, the expansion module further includes a third buffer register; the second input port of the second buffer register is connected to the MISO port of the SPI bus through the third buffer register.

[0030] Specifically, the expansion module also includes a third buffer register; the SCLK port of the SPI bus is used to connect to the SCK port of the device through the third buffer register.

[0031] Specifically, the MOSI ports of the SPI bus are used to be connected to the SDI ports of the slave devices respectively through the third buffer register.

[0032] Specifically, there is one first input port, and there are four first enable ports and four first output ports.

[0033] More specifically, Figure 1 FIG. 1 is a circuit connection block diagram of an embodiment of the present invention, as shown in FIG. Figure 1 As shown, 010 is the IIC control bus of the input system, 020 is the SPI control bus of the input system, 030 is the IO expansion chip controlled by IIC and the further expanded decoder, 040 is the data buffer (Buffer) for enhanced driving of the SPI bus signal, and 050 is the SPI bus slave device, such as an ADC chip (analog-to-digital converter) or a DAC chip (digital-to-analog converter).

[0034] The IIC bus can expand several IO ports by controlling the IO expansion chip, and further decode more slave device chip enable signals CS_ENx through the decoder. This signal is only used for slave device selection switching. After the switching is completed, the four communication lines of the SPI bus itself can be used for rapid control and acquisition. After all channels of the slave device have completed the required SPI communication operations, the IIC bus is used again to control the switch to the enable signal of the next slave device. A complete round of operations is completed until all mounted slave devices have completed communication, and the next round of cycles can be carried out.

[0035] Figure 2 FIG. 2 is a specific circuit connection diagram of an embodiment of the present invention. Figure 1As shown, SPI_SCLK is the clock signal of the SPI bus, SPI_MOSI is the master device data output signal of the SPI bus, SPI_MISO is the master device data input signal of the SPI bus, SPI_CS is the chip select and frame synchronization signal of the SPI bus itself, and CS_ENx is the slave device enable signal after IIC expansion and decoding. The A end of the first buffer register is the signal input end, the Y end is the signal output end, and the OE end is the channel enable control pin. For example: when the signal received by 1OE is 0, port 1A will be connected to port 1Y; when the signal received by 1OE is 1, port 1A will be disconnected from port 1Y. That is, when CS_EN1 is 0 and other CS_ENs are 1, the CS port of Device#1 is connected to SPI_CS, the SDO pin is connected to SPI_MISO, and communication can proceed normally; on the contrary, when CS_EN1 is 1, the communication between Device#1 and SPI is disconnected.

[0036] As another embodiment of the present invention, an aging test system is disclosed, specifically, comprising an aging test device and the aging test interface expansion module as described above; the aging test device is connected to the SPI bus and the IIC bus.

[0037] The above contents are further detailed descriptions of the present invention in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. An aging test interface expansion module, characterized in that: It includes an SPI bus, an IIC bus, an IO expansion chip, a decoder and a first buffer register; the SPI bus and the IIC bus are used to connect to an aging test device, the IO expansion chip is connected to the IIC bus, the decoder is connected to the IO expansion chip, the first buffer register is connected to the decoder and the CS port of the SPI bus, and is used to connect to the CS port of a slave device; Wherein, the IIC bus controls the IO expansion chip and the decoder to generate an enable signal for switching the slave device, and the enable signal controls the selection of the slave device; the SPI bus communicates with the selected slave device; The first buffer register includes a first input port, multiple first enable ports and multiple first output ports; the first input port is connected to the CS port of the SPI bus; the first enable port is connected to the decoder to receive an enable signal of the decoder; the first output port is used to connect to the CS port of the slave device.

2. The aging test interface expansion module according to claim 1, characterized in that: The expansion module also includes a third buffer register; the first input port of the first buffer register is connected to the CS port of the SPI bus through the third buffer register.

3. The aging test interface expansion module according to claim 1, characterized in that: The expansion module also includes a second buffer register; the second buffer register is connected to the decoder and the MISO port of the SPI bus, and is used to connect to the SDO port of the slave device.

4. The aging test interface expansion module according to claim 3, characterized in that: The second buffer register includes a second input port, multiple second enable ports and multiple second output ports; the second input port is connected to the MISO port of the SPI bus; the second enable port is connected to the decoder to receive the enable signal of the decoder; the second output port is used to connect to the SDO port of the slave device.

5. The aging test interface expansion module according to claim 4, characterized in that: The expansion module also includes a third buffer register; the second input port of the second buffer register is connected to the MISO port of the SPI bus through the third buffer register.

6. The aging test interface expansion module according to claim 1, characterized in that: The expansion module also includes a third buffer register; the SCLK port of the SPI bus is used to connect to the SCK port of the device through the third buffer register.

7. The aging test interface expansion module according to claim 6, characterized in that: The MOSI port of the SPI bus is used to connect to the SDI port of the slave device through the third buffer register.

8. The aging test interface expansion module according to claim 1, characterized in that: The first input port has one, and the first enable port and the first output port have four.

9. An aging test system, characterized in that: The invention comprises an aging test device and an aging test interface expansion module as claimed in any one of claims 1 to 8; the aging test device is connected to the SPI bus and the IIC bus.

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