Chip test system based on local sharing expected data comparator

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a chip test system based on a local sharing expected data comparator, the system divides a memory of a chip into a plurality of memory groups, the memories in a single memory group share one shared comparator, and compared with a corresponding comparator configured for each memory, the chip test efficiency is improved. The total number of comparators is effectively reduced, the area overhead of a chip is reduced, compared with the same comparator on the shared controller side of all memories, the shared comparators are arranged on the memory bank side, the data paths of the memories and the corresponding shared comparators are short, the difficulty in system time sequence convergence is avoided, the wiring density near the controller is reduced, and the system reliability is improved. And the layout and wiring blockage is avoided.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a chip testing system based on a locally shared expected data comparator. Background Technology

[0002] In the modern integrated circuit industry, the demand for on-chip memory is increasing, and its proportion is also rising, especially in artificial intelligence chips, where the proportion of on-chip memory far exceeds that of other logic components. Therefore, testing on-chip memory is indispensable. Typically, functional testing of on-chip memory is time-consuming and has low coverage. Therefore, a common practice in current technology is to use built-in self-test circuits to perform structural testing on-chip memory.

[0003] Built-in self-test (WPT) circuits typically consist of a controller module, an interface interaction module, and a desired data comparator. In a typical WPT circuit, the controller can be shared and is usually located far from the memory under test (MDT). The interface interaction logic, on the other hand, needs to be matched with the MDT, is located closer to the MDT, and is usually numerous and cannot be shared.

[0004] In existing technologies, expected data comparators are typically arranged in two ways. The first is to place them together with the interface interaction module, with each memory independently setting up its own expected data comparator. This arrangement makes timing convergence easier and does not cause placement and routing blockage, but the chip area overhead is large. The second is to share the expected data comparator among all memories. This shared comparator is set up in the controller. The chip area overhead is small, but the data path between the memory and the comparator is long, requiring a large number of buffers, which can cause timing convergence difficulties and placement and routing blockage near the controller.

[0005] Currently, built-in test circuits with expected data comparators have certain drawbacks. Therefore, we propose a test circuit scheme that uses a locally shared expected data comparator, placed as close as possible to the memory under test. This solves the problem of saving area while also considering the physical location of the memory under test.

[0006] Therefore, how to save space while avoiding wiring blockage and timing convergence difficulties has become an urgent problem to be solved. Summary of the Invention

[0007] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows: A chip testing system based on a locally shared expected data comparator, the system includes a chip, the chip includes a controller, M memory groups, shared comparators corresponding to the M memory groups, and an interface interaction module corresponding to each memory, the memory groups including several memories with the same clock source.

[0008] The interface interaction module is used to send test data to the corresponding memory.

[0009] The memory is used to perform memory tests based on the received test data and output the actual test results corresponding to the test data to the corresponding interface interaction module.

[0010] The interface interaction module is also used to receive the actual test results corresponding to the test data, and send the actual test results corresponding to the test data and the expected test results corresponding to the test data to the shared comparator corresponding to the memory group to which the corresponding memory belongs.

[0011] The shared comparator is used to determine the data comparison result based on the actual test result and the expected test result corresponding to the test data, and send the data comparison result to the controller.

[0012] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the chip testing system based on a locally shared expected data comparator provided by the present invention achieves considerable technological progress and practicality, and has broad industrial application value. It has at least the following advantages: This invention divides the chip's memory into multiple memory groups, with each memory group sharing a shared comparator. Compared to configuring a corresponding comparator for each memory, this effectively reduces the total number of comparators and lowers the chip's area overhead. Compared to all memories sharing the same comparator on the controller side, the shared comparator is located on the memory group side, resulting in a shorter data path between the memory and the corresponding shared comparator. This avoids difficulties in system timing convergence and reduces the density of wiring near the controller, preventing layout and wiring blockage. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of a chip testing system based on a locally shared expected data comparator, provided as an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] This embodiment provides a chip testing system based on a locally shared expected data comparator. The system includes a chip, which includes a controller, M memory groups, shared comparators corresponding to the M memory groups, and an interface interaction module corresponding to each memory. The memory groups include several memories with the same clock source. The interface interaction module is used to send test data to the corresponding memory; The memory is used to perform memory testing based on the received test data and output the actual test results corresponding to the test data to the corresponding interface interaction module. The interface interaction module is also used to receive the actual test results corresponding to the test data, and send the actual test results corresponding to the test data and the expected test results corresponding to the test data to the shared comparator of the memory group to which the corresponding memory belongs. The shared comparator is used to determine the data comparison result based on the actual test result and the expected test result corresponding to the test data, and send the data comparison result to the controller.

[0017] In the prior art, there are usually two ways to lay out memory in a chip: one is boundary arrangement and the other is center arrangement. This embodiment is applied to the scenario where memory is laid out in the chip in the boundary arrangement manner.

[0018] The controller is used to generate test data and coordinate the entire test process. A memory group can refer to a collection of several memories that use the same clock source. Multiple memories in a single memory group share the same shared comparator. Compared to configuring comparators independently for each memory, this effectively reduces the number of comparators and lowers chip area overhead.

[0019] Test data can be in various formats such as all 0s, all 1s, checkerboard, or walking positions.

[0020] See Figure 1This is a schematic diagram of a chip testing system based on a locally shared expected data comparator provided in an embodiment of the present invention. The schematic diagram takes four memory groups, each containing three memories, as an example. Implementers should know that the number of memory groups and the number of memories contained in each memory group can be flexibly adjusted according to the actual situation, and the number of memories contained in different memory groups can be different.

[0021] Specifically, the transmission and control logic between multiple memories and a shared comparator within a single memory group can reuse the transmission and control logic of the same comparator shared by all memories in the prior art. The transmission and control logic between multiple shared comparators and the controller can reuse the transmission and control logic between the independent comparator and the controller of each memory in the prior art. This effectively reduces design complexity, directly reuses mature interface logic, ensures design reliability and compatibility with existing architectures, and facilitates design debugging and maintenance.

[0022] In one specific implementation, the memory includes a plurality of storage units, and the controller includes a data generator, an address generator, a memory control signal generator, and an algorithm controller. The algorithm controller is used to determine the current test step, the address generator is used to generate the access address of the storage unit in the memory corresponding to the current test step, the data generator is used to generate test data corresponding to the current test step, the memory control signal generator is used to generate an enable signal and send it to the memory corresponding to the current test step, the enable signal including a write enable signal and a read enable signal, and the controller is used to send the test data, access address, and enable signal corresponding to the current test step to the interface interaction module. Accordingly, sending test data to the corresponding memory includes: Send the test data, access address, and enable signal corresponding to the current test step to the corresponding memory; The step of performing memory testing based on the received test data and outputting the actual test results corresponding to the test data to the corresponding interface interaction module includes: According to the write enable signal, the test data is written to the storage unit corresponding to the access address; Based on the read enable signal, the data in the storage unit corresponding to the access address is read out as the actual test result corresponding to the test data and sent to the interface interaction module corresponding to the memory.

[0023] The algorithm controller is used to manage the execution steps and state transitions of the test algorithm, which can refer to algorithms such as the March algorithm.

[0024] Access addresses can be generated using incrementing, decrementing, or skipping methods. Access addresses can be used to determine the corresponding memory cell within the memory.

[0025] Specifically, in the testing process, the read enable signal is usually generated after the write enable signal, in order to read the test data written to the memory cell under the control of the write enable signal.

[0026] In one specific implementation, the interface interaction module includes interface interaction sending logic and interface interaction receiving logic corresponding to the memory; The interface interaction sending logic is used to send test data to the corresponding memory; The interface interaction receiving logic is used to receive the actual test results corresponding to the test data.

[0027] The interface interaction sending logic can also be used to send access addresses and enable signals to the corresponding memory.

[0028] The interface interaction receiving logic can also be used to pass the actual test results corresponding to the received test data to the shared comparator.

[0029] In one specific implementation, the physical distance between the individual memories in a single memory group within the chip is less than a preset first distance threshold.

[0030] The first distance threshold is used to constrain the physical location of multiple memories within the same memory group to be close together, so that when the same memory group uses a shared comparator, the data paths are shorter, thereby reducing data transmission latency, improving timing convergence, and reducing wiring complexity.

[0031] Specifically, implementers can divide memory groups based on the physical locations of all memory units using a density-based clustering algorithm. However, it is necessary to ensure that multiple memory units within a divided memory group share the same clock source. The density-based clustering algorithm can be the DBSCAN clustering algorithm.

[0032] In one specific implementation, the physical distance between the center location of a single memory group in the chip and the physical location of the shared comparator corresponding to the memory group in the chip is less than a preset second distance threshold.

[0033] The second distance threshold is used to constrain the physical location of the memory group and its corresponding shared comparator to be close together, so as to shorten the data path from the actual test result and the expected result to the shared comparator, reduce the signal transmission delay from the memory to the shared comparator, and improve the comparison speed.

[0034] In one specific implementation, the chip corresponds to several test time periods, and only one memory is tested within a single test time period.

[0035] In this system, each memory uses time-division multiplexing to share comparator resources, in order to avoid conflicts caused by multiple memories accessing the shared comparator at the same time, thereby simplifying the control logic and reducing peak power consumption.

[0036] In one specific implementation, the shared comparator includes a gated switch; The gate switch is used to control the enable state of the shared comparator.

[0037] Specifically, by using a gating switch, the shared comparator corresponding to a memory group is turned off when it is not being tested, and the shared comparator corresponding to a memory group is turned on before it is being tested, thereby supporting dynamic power consumption management of the shared comparator and improving system energy efficiency.

[0038] In one specific implementation, the controller is further configured to send a desired data mask to the shared comparator. When the desired data mask is a first preset value, the gating switch of the shared comparator controls the enabled state of the shared comparator to be enabled. When the desired data mask is a second preset value, the gating switch of the shared comparator controls the enabled state of the shared comparator to be disabled.

[0039] The first preset value can be 1, and the second preset value can be 0. The controller sends the desired data mask to the shared comparator to control the gate switch corresponding to the shared comparator, thereby controlling the enable state of the shared comparator.

[0040] In this embodiment, the chip's memory is divided into multiple memory groups, and the memories in a single memory group share a shared comparator. Compared to configuring a corresponding comparator for each memory, this effectively reduces the total number of comparators and lowers the chip's area overhead. Compared to all memories sharing the same comparator on the controller side, the shared comparator is located on the memory group side, resulting in a shorter data path between the memory and the corresponding shared comparator. This avoids difficulties in system timing convergence and reduces the density of wiring near the controller, preventing layout and wiring blockage.

[0041] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A chip testing system based on a locally shared expected data comparator, characterized in that, The system includes a chip, which includes a controller, M memory groups, a shared comparator corresponding to each of the M memory groups, and an interface interaction module corresponding to each memory. The memory groups include several memories with the same clock source. The interface interaction module is used to send test data to the corresponding memory; The memory is used to perform memory testing based on the received test data and output the actual test results corresponding to the test data to the corresponding interface interaction module. The interface interaction module is also used to receive the actual test results corresponding to the test data, and send the actual test results corresponding to the test data and the expected test results corresponding to the test data to the shared comparator of the memory group to which the corresponding memory belongs. The shared comparator is used to determine the data comparison result based on the actual test result and the expected test result corresponding to the test data, and send the data comparison result to the controller.

2. The chip testing system based on a locally shared expected data comparator according to claim 1, characterized in that, The memory includes several storage units, and the controller includes a data generator, an address generator, a memory control signal generator, and an algorithm controller. The algorithm controller is used to determine the current test step, the address generator is used to generate the access address of the storage unit in the memory corresponding to the current test step, the data generator is used to generate the test data corresponding to the current test step, the memory control signal generator is used to generate an enable signal and send it to the memory corresponding to the current test step, the enable signal includes a write enable signal and a read enable signal, and the controller is used to send the test data, access address, and enable signal corresponding to the current test step to the interface interaction module. Accordingly, sending test data to the corresponding memory includes: Send the test data, access address, and enable signal corresponding to the current test step to the corresponding memory; The step of performing memory testing based on the received test data and outputting the actual test results corresponding to the test data to the corresponding interface interaction module includes: According to the write enable signal, the test data is written to the storage unit corresponding to the access address; Based on the read enable signal, the data in the storage unit corresponding to the access address is read out as the actual test result corresponding to the test data and sent to the interface interaction module corresponding to the memory.

3. The chip testing system based on a locally shared expected data comparator according to claim 1, characterized in that, The interface interaction module includes interface interaction sending logic and interface interaction receiving logic for the corresponding memory. The interface interaction sending logic is used to send test data to the corresponding memory; The interface interaction receiving logic is used to receive the actual test results corresponding to the test data.

4. The chip testing system based on a locally shared expected data comparator according to claim 1, characterized in that, The physical distance between each memory in a single memory group within the chip is less than a preset first distance threshold.

5. The chip testing system based on a locally shared expected data comparator according to claim 1, characterized in that, The physical distance between the center location of a single memory group in the chip and the physical location of the shared comparator corresponding to the memory group in the chip is less than a preset second distance threshold.

6. The chip testing system based on a locally shared expected data comparator according to claim 1, characterized in that, The chip corresponds to several test time periods, and only one memory is tested within a single test time period.

7. The chip testing system based on a locally shared expected data comparator according to claim 1, characterized in that, The shared comparator includes a gated switch; The gate switch is used to control the enable state of the shared comparator.

8. The chip testing system based on a locally shared expected data comparator according to claim 7, characterized in that, The controller is also configured to send a desired data mask to the shared comparator. When the desired data mask is a first preset value, the gating switch of the shared comparator controls the enabled state of the shared comparator to be enabled. When the desired data mask is a second preset value, the gating switch of the shared comparator controls the enabled state of the shared comparator to be disabled.

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