Data store usage associated with abnormal closures

Abstract

The present disclosure generally relates to efficient block usage after an unexpected graceful shutdown (UGSD) event. After a UGSD event, a data storage device alerts a host device that a QLC block that the host device was using prior to the UGSD event is experiencing ongoing block recovery and that the block is also not available to accept new data. The block is then checked to determine whether the block can continue to be used for programming that was in progress at the time of the UGSD event. Once determined, the data storage device notifies the host device so that normal operations can continue. Additionally, the number of free blocks available for programming is monitored during the UGSD event so that the host device can be alerted in the event that a power loss stoppage is triggered.

Description

BACKGROUND

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 106,544, filed October 28, 2020, which is incorporated by reference herein. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate generally to efficient block usage after ungraceful shutdown (UGSD) events.

[0004] Description of the Related Art

[0005] Power loss is a problem for data storage devices such as solid state drives (SSDs) where incompletely programmed blocks can pose a threat to data integrity and device reliability. Consecutive power loss events are especially troublesome because as the data storage device runs out of blocks for data storage, the available storage blocks can run out, which will cause the data storage device to be unable to accept new data and be placed in an undesirable read-only mode.

[0006] Advanced technology data storage devices have used capacitors to handle power loss scenarios. Capacitors hold enough power to help handle power loss protection (PLP). Capacitors can run out. Even with some power reserve from the host device or capacitors or advanced power loss flagging, consecutive power loss can still result in the depletion of available blocks for the data storage device to operate normally.

[0007] At power recovery, the data storage device can select a new block to write data to while discarding the original block because it will not be processed in time due to the ready time limit. Thus, when the next power loss comes around, the data storage device will select another block for data routing until enough power loss results in the complete depletion of block count.

[0008] Thus, there is a need in the art for a sufficient and proper data storage device to host device communications during UGSD / PLP recovery. SUMMARY

[0009] The present disclosure generally relates to efficient block usage after an unexpected graceful shutdown (UGSD) event. After a UGSD event, the data storage device alerts the host device that a QLC block that the host device was using prior to the UGSD event is experiencing ongoing block recovery and that the block is also not available to accept new data. The block is then checked to determine if the block can continue to be used for programming that was in progress at the time of the UGSD event. Once determined, the data storage device notifies the host device so that normal operations can continue. Additionally, the number of free blocks available for programming is monitored during the UGSD event so that the host device can be alerted in the event that a power loss stoppage is triggered.

[0010] In one embodiment, a data storage device includes a non-volatile memory device; and a controller coupled to the non-volatile memory device, wherein the controller is configured to: detect a power loss event during a block programming operation; issue a block busy alert to a host device upon power up after the power loss event; determine whether the block can still be programmed continuously; and issue a block ready alert to the host device.

[0011] In another embodiment, a data storage device includes a non-volatile memory device; and a controller coupled to the non-volatile memory device, wherein the controller is configured to: determine power up after a power loss event; check a remaining count of free blocks available for subsequent power loss processing; determine whether the remaining amount of free blocks is above or below a threshold; and either: continue processing power loss data integrity checks and usage; or issue a logical block address (LBA) alert for any incoming data from a host device.

[0012] In another embodiment, a data storage device includes a non-volatile memory device; means for determining whether a block can be programmed continuously after a power loss event; and means for issuing a block busy alert to a host device after a power loss event. BRIEF DESCRIPTION OF DRAWINGS

[0013] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, can be had by reference to embodiments thereof which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure can admit to other equally effective embodiments.

[0014] Figure 1 is a schematic block diagram illustrating a storage system in accordance with one embodiment, in which a data storage device can be used as a storage device for a host device.

[0015] Figure 2is a schematic diagram of fuzzy-fine programming according to one embodiment.

[0016] Figure 3 is a method flow diagram illustrating data storage device power loss handling according to one embodiment.

[0017] Figure 4 is a method flow diagram illustrating checking for block depletion due to power loss according to one embodiment.

[0018] To facilitate an understanding of this description, like reference characters are used to identify like elements throughout the service figures. It is contemplated that elements disclosed in one embodiment can be advantageous ly used in other embodiments without specific recitation. DETAILED DESCRIPTION

[0019] In the following, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the particularly described embodiments. On the contrary, any combination of the following features and elements, whether related to different embodiments or not, can be utilized to realize and practice the present disclosure. In addition, although embodiments of the present disclosure can achieve advantages over other possible solutions and / or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not a limitation of the present disclosure. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims, unless specifically recited therein. Likewise, reference to "the present disclosure" should not be interpreted as a generalization of any inventive subject matter disclosed herein and should not be considered an element or limitation of the appended claims, unless specifically recited in such a claim.

[0020] The present disclosure generally relates to efficient block usage after an unexpected graceful shutdown (UGSD) event. After a UGSD event, the data storage device alerts the host device that a QLC block that was being used by the host device prior to the UGSD event is experiencing sustained block recovery and that the block is also not available to accept new data. The block is then checked to determine if the block can continue to be used for programming that was in progress at the time of the UGSD event. Once determined, the data storage device notifies the host device so that normal operations can continue. Additionally, the number of free blocks available for programming is monitored during the UGSD event so that the host device can be alerted in the event that a power loss stop is triggered.

[0021] Figure 1is a schematic block diagram illustrating a storage system 100 in accordance with one embodiment, in which a data storage device 106 can be used as a storage device for a host device 104. For example, the host device 104 can utilize a non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes a host DRAM 138, in which a portion of the host DRAM 138 is allocated as a host memory buffer (HMB) 140. The HMB 140 can be used by the data storage device 106 as an additional working area or additional storage area for the data storage device 106. In some examples, the HMB 140 can not be accessible to the host device. In some examples, the storage system 100 can include multiple storage devices, such as the data storage device 106, which can work as a storage array. For example, the storage system 100 can include multiple data storage devices 106 configured to collectively work as a redundant array of inexpensive / independent disks (RAID) for a large-capacity storage device for the host device 104.

[0022] The host device 104 can store data to and / or retrieve data from one or more storage devices, such as the data storage device 106. As shown, the host device 104 can communicate with the data storage device 106 via an interface 114. The host device 104 can include any of a variety of devices, including a computer server, a network-attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone handset such as a so-called “smart” phone, a so-called “smart” tablet, a television, a camera, a display device, a digital media player, a video gaming console, a video streaming device, or other device capable of sending or receiving data from the data storage device. Figure 1

[0023] The data storage device 106 includes a controller 108, an NVM 110, a power supply 111, a volatile memory 112, an interface 114, and a write buffer 116. In some examples, for clarity, the data storage device 106 can include only those components that are relevant to the present disclosure. Figure 1 ​additional components not shown. For example, the data storage device 106 can include a printed circuit board (PCB) to which components of the data storage device 106 are mechanically attached, and which includes conductive traces that electrically interconnect the components of the data storage device 106, etc. In some examples, the physical size and connector configuration of the data storage device 106 can conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5” data storage devices (e.g., HDDs or SSDs), 2.5” data storage devices, 1.8” data storage devices, peripheral component interconnect (PCI), PCI extended (PCI-X), PCI Express (PCIe) (e.g., PCIe xl, x4, x8, x16, PCIe Mini card, MiniPCI, etc.). In some examples, the data storage device 106 can be directly coupled (e.g., directly soldered) to a motherboard of the host device 104.

[0024] The interface 114 of the data storage device 106 can include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 can operate according to any suitable protocol. For example, the interface 114 can operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. Electrical connections of the interface 114 (e.g., data bus, control bus, or both) are electrically connected to the controller 108, providing electrical connections between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connections of the interface 114 can also allow the data storage device 106 to receive power from the host device 104. For example, as shown, the power supply 111 can receive power from the host device 104 via the interface 114. Figure 1

[0025] ​The NVM 110 can include a plurality of storage devices or storage units. The NVM 110 can be configured to store and / or retrieve data. For example, a storage unit of the NVM 110 can receive data and receive a message from the controller 108 instructing the storage unit to store the data. Similarly, a storage unit of the NVM 110 can receive a message from the controller 108 instructing the storage unit to retrieve data. In some examples, each of the storage units can be referred to as a die. In some examples, a single physical chip can include multiple dies (i.e., multiple storage units). In some examples, each storage unit can be configured to store a relatively large amount of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

[0026] In some examples, each storage unit of the NVM 110 can include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0027] The NVM 110 can include a plurality of flash memory devices or storage units. The NVM flash memory devices can include NAND or NOR based flash memory devices and can store data based on charge contained in a floating gate of a transistor for each flash memory unit. In NVM flash memory devices, a flash memory device can be divided into a plurality of dies, where each die of the plurality of dies includes a plurality of blocks, which can be further divided into a plurality of pages. Each block of the plurality of blocks within a particular memory device can include a plurality of NVM cells. A row of NVM cells can be electrically connected using a word line to define a page of the plurality of pages. Respective cells in each page of the plurality of pages can be electrically connected to a respective bit line. Further, the NVM flash memory devices can be 2D or 3D devices and can be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controller 108 can write data to and read data from the NVM flash memory devices at a page level and erase data from the NVM flash memory devices at a block level.

[0028] The data storage device 106 includes a power source 111, which can provide power to one or more components of the data storage device 106. When operating in a standard mode, the power source 111 can use power provided by an external device, such as the host device 104, to power the one or more components. For example, the power source 111 can use power received from the host device 104 via the interface 114 to power the one or more components.

[0029] In some examples, the power source 111 can include one or more power storage components configured to power the one or more components when operating in an off mode, such as in the event that power is stopped being received from an external device. In this way, the power source 111 can act as an on-board backup power source. Some examples of the one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like.

[0030] In some examples, the amount of power that can be stored by the one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by the one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0031] The data storage device 106 also includes a volatile memory 112, which can be used by the controller 108 to store information. The volatile memory 112 can include one or more volatile memory devices. In some examples, the controller 108 can use the volatile memory 112 as a cache. For example, the controller 108 can store cached information in the volatile memory 112 until the cached information is written to the non-volatile memory 110. As Figure 1 shown, the volatile memory 112 can consume power received from the power source 111. Examples of the volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.).

[0032] The data storage device 106 includes a controller 108, which can manage one or more operations of the data storage device 106. For example, the controller 108 can manage reading data from and / or writing data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 can initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command. The controller 108 can determine at least one operational characteristic of the storage system 100 and store the at least one operational characteristic to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores data associated with the write command in an internal memory or write buffer 116 prior to sending the data to the NVM 110. In some other embodiments, the HMB 140 can be utilized.

[0033] Figure 2 is a schematic diagram illustrating fuzzy-fine programming, according to one embodiment. When programmed to the NVM 110, data is initially programmed to SLC memory. After programming to SLC memory, the data is then programmed to QLC memory. The first programming to QLC memory is fuzzy programming. Fuzzy programming is providing a voltage pulse to cause the current state to enter a state that is further resolved but not fully resolved. After fuzzy programming to QLC memory, the data is then fine programmed to QLC memory. Fine programming is performed at a point in time after fuzzy programming to write the data again in a fully resolved state. The listed memory is not intended to be limiting, but to provide an example of a possible embodiment.

[0034] With respect to Figure 2 Fuzzy-fine programming is implemented on a QLC storage block 200 of an NVM, such as the NVM 110 of Figure 2 The QLC storage block 200 includes a plurality of word lines WLN, WLN-1, and WLN-2. The QLC storage block 200 also includes a plurality of strings St0, St1, St2, and St3, such that each of the plurality of word lines includes a plurality of strings. For example, WLN includes St0, St1, St2, and St3. Further, WLN, St0 can represent a storage block of the QLC storage block 200, where data is stored to and read from the storage block.

[0035] When programming to a storage block, the programming can cause the voltage distribution to shift or disturb the voltage of a storage block of an adjacent word line, where the storage block of the adjacent word line was previously programmed, which can cause bit error accumulation or bit flips to occur. For example, programming of WLN St0 can disturb the voltage of a storage block of an adjacent word line WLN-1 St0. Thus, when fuzzy-fine programming is performed on a QLC storage block 200, the fuzzy-fine programming can alternate between adjacent word lines. For example, in Figure 2 , fuzzy programming is performed on WLN St0, followed by fine programming of WLN-1 St0, where WLN-1 St0 was previously fuzzy programmed. Unlike fuzzy programming, when a storage block is fine programmed, the adjacent storage blocks indicated by the diagonal pattern that were previously fine programmed can not be affected by the programming of the storage block. After fine programming of WLN-1 St0, fuzzy programming is performed on WLN St1.

[0036] During programming to a QLC storage block 200, a power loss event can occur. Examples of a power loss event can include a power surge, a power outage, a circuit breaker tripping, a short circuit, and the like. When a power loss event occurs, a data storage device, such as Figure 1 , can include sufficient capacitors to program data from volatile memory to non-volatile memory. However, in some cases, the amount of power that the capacitors can store can not be sufficient to fully program all of the data from the volatile memory to the non-volatile memory. When a power loss event occurs during an NVM programming operation, a controller, such as Figure 1 , determines the location where the current programming is occurring in the storage block. For example, in a QLC storage block 200, the controller can detect a power loss event during fine programming, such as fine programming of WLN-1 St2 storage block, or during fuzzy programming, such as fuzzy programming of WLN St3 storage block, where the controller determines the location where the current programming is occurring.

[0037] Figure 3 is a method 300 flow diagram illustrating a data storage device power loss process, according to one embodiment. At block 302, programming of a QLC storage block, such as Figure 2 , QLC storage block 200, occurs by first programming host data to SLC memory and then transferring the host data from the SLC memory to QLC memory SLC to QLC folding. At block 304, a power loss event, such as UGSD, occurs, where a controller, such as Figure 1 , controller 108, detects the power loss event. At block 306, the QLC programming is terminated. The QLC programming can be metablocks across multiple dies or zoned namespace (ZNS) blocks in a single die.

[0038] At block 308, if the data storage device has sufficient power in the power reserve (i.e., capacitor or external power unit), the controller continues SLC programming within the allowed power loss protection time limit, such as about 30 ms. The allowed power loss protection time limit can be a percentage of time of the total time that the capacitor can provide power to the data storage device. Further, at block 308, control data including the last QLC programming location is uploaded to the NVM. The control data can include SLC block information and terminated QLC block information. The terminated QLC block information can include word line information and programming stage, such as whether the terminated programming is fine programming or fuzzy programming. At block 310, the data storage device resumes power.

[0039] At block 312, the controller identifies the QLC programming location when the power loss event occurred. For example, the location can be Figure 2 WLN-1St2. At block 314, the controller issues a block busy alert to the host device, such as Figure 1 The block busy alert is a notification that the block recovery operation is in progress and the block associated with the block recovery operation is not ready to accept new data. The block busy alert can also notify the host device that the host device should not modify data belonging to the block associated with the block recovery operation and data stored in the SLC block associated with the block. In other words, the host device should not alter data of the block associated with the block recovery operation located anywhere in the data storage device during the block recovery operation. At block 316, the host device is able to perform functions on the data storage device, except for the block associated with the block busy alert.

[0040] At block 318, the controller determines whether the identified location at block 312 is a fuzzy programming location. The controller checks the QLC programming status on the last programming location. The controller can check a plurality of word lines of the storage block in sequence to find the last programmed word line and determine which word line is the last fuzzy word line and the last fine word line. Further, the last programming location can also be stored in the SLC memory as part of the control data of block 308. If the location is a fuzzy programming location at block 318, then the fuzzy location can be continuously fine programmed at block 320 if data is saved in the SLC memory.

[0041] However, if at block 318, the controller determines that the identified location at block 312 is not a fuzzy programming location, then data is being fine programmed to the QLC storage block location at block 322 when the power loss event occurs at block 322. At block 324, the controller reads the last fine programmed word line with an error correction code (ECC) engine and checks the bit error rate (BER) of the last fine programmed word line.

[0042] At block 326, the controller determines whether the BER is greater than or less than a predetermined threshold. The predetermined threshold can be a value set at the time of data storage device startup or a configurable value adjusted during the lifetime and operation of the data storage device, where the configurable value can be specific to individual storage units of the NVM. Further, if the BER is greater than the predetermined threshold, the controller can flag the block as an unprogrammable location.

[0043] If the BER is less than the predetermined threshold at block 326, then at block 328, the controller is able to continue using the QLC storage block for subsequent programming. However, if the BER is greater than the predetermined value at block 326, then at block 330, the SLC data of the fine programmed QLC storage block location is copied to another SLC backup location. The SLC data is copied for the word lines associated with a BER greater than the predetermined threshold. When the BER is greater than the predetermined threshold, the BER can be considered an unacceptable BER (UBER).

[0044] At block 332, the QLC storage block is flagged in a power loss table as losing good data at the QLC storage block location. The power loss table can include the number of blocks that have been affected by power loss and the backup data of the affected word lines stored at the SLC backup location. Further, the losing good data is stored at the SLC backup location, where the SLC backup location is programmed at block 308. The QLC block can be continuously used for QLC read and write operations, except for the word lines associated with the UBER. At block 334, the controller issues a block ready prompt to the host device, where the block ready prompt indicates that the QLC storage block is accessible again.

[0045] It should be appreciated that the data storage device can allow the host device to continue sending read and write commands to other blocks of the data storage device located between block 312 and block 332.

[0046] Figure 4 is a flow diagram illustrating a method 400 of checking for power loss induced block exhaustion according to one embodiment. At block 402, after a power loss event occurs, the data storage device resumes operation after power recovery. At block 404, the controller checks a remaining count of free blocks available for subsequent power loss processing. The number of free blocks can be the number of blocks that are unprogrammed or blocks that were not affected by the power loss event. At block 406, the controller keeps track of SLC backup blocks. At block 408, the controller determines whether the number of free blocks is too low. In determining whether the number of free blocks is too low, the controller can compare the number of free blocks to a predetermined free block count threshold.

[0047] If the number of free blocks is not too low at block 408, then at block 410, the controller continues to check power loss data integrity and usage. The check of power loss data integrity and usage can be the previously describedFigure 3 However, if the number of free blocks is too low at block 408, then at block 412, the controller determines that the NVM can not have enough storage space to handle power loss. The determination can be a comparison of the current storage space to a pre-determined free block count threshold. At block 414, when the number of free block counts is less than the pre-determined threshold of free blocks (i.e., the number of free blocks available is less than the number of free blocks required), the controller is configured to clean up SLC backup blocks in order to free up storage to store additional data to the SLC backup block area.

[0048] At block 416, the controller determines whether the number of free blocks after the clean-up operation is still too low. If the number of free blocks is greater than the pre-determined threshold at block 416, then the controller continues to check power loss data integrity and usage, where the check of power loss data integrity and usage can be a comparison of the current storage space to a pre-determined free block count threshold. If the number of free blocks is less than the pre-determined threshold of free blocks at block 416, then the controller triggers a power loss stop at block 418. The power loss stop can include issuing a logical block address (LBA) warning for any incoming data from the host device. The LBA warning can include a “unable to program due to low capacity” message. In addition, when the power loss stop is issued, the controller records the event for host messaging. Figure 3

[0049] By alerting the host device that the QLC blocks being used by the host device prior to the UGSD event are experiencing sustained block recovery, and monitoring the number of free blocks available, efficient use of the data storage device is achieved.

[0050] In one embodiment, a data storage device includes a non-volatile memory device; and a controller coupled to the non-volatile memory device, where the controller is configured to detect a power loss event during a block programming operation; issue a block busy alert to a host device upon power up after the power loss event; determine whether the block can still be programmed continuously; and issue a block ready alert to the host device. The controller is further configured to identify a programming location of the block at the time of the power loss event. The controller is further configured to determine whether the location is a fuzzy programming location or a fine programming location. The controller is further configured to read a word line at the location and check a bit error rate of the word line. The controller is further configured to determine whether the bit error rate of the block is above or below a threshold. The controller is further configured to mark the block as losing good data at a particular location in a power loss table. The good data lost at the particular location is stored in an SLC backup location. The controller is further configured to copy data from one SLC location to another SLC location upon determining that the bit error rate is too high for the location being programmed in the block at the time of the power loss event. While the determination is ongoing, the data storage device allows the host device to continue using other blocks of the data storage device.​

[0051] In another embodiment, a data storage device includes a non-volatile memory device and a controller coupled to the non-volatile memory device, where the controller is configured to determine a power loss event after, check a remaining count of free blocks available for subsequent power loss handling, determine whether the remaining amount of free blocks is above or below a threshold, and either: continue processing power loss data integrity checks and usage, or issue a logical block address (LBA) warning for any incoming data from a host device. The controller is further configured to keep track of a plurality of SLC backup blocks. The controller is further configured to continue processing the power loss data integrity checks and usage upon determining that the remaining amount of free blocks is above the threshold. The controller is further configured to clean up SLC backup blocks upon determining that the remaining amount of free blocks is below the threshold. The controller is configured to determine again whether the remaining amount of free blocks is above or below the threshold after cleaning up SLC backup blocks. The controller is configured to issue the LBA warning upon determining that the remaining amount of free blocks is again below the threshold. Continuing processing the power loss data integrity checks and usage includes issuing a block busy indication to the host device. The controller is also configured to determine whether a location in a block being programmed at the time of the power loss event can be programmed continuously or needs to be marked as lost good data in a power loss table. The controller is further configured to issue a block ready indication to the host device upon determining that the block can be programmed.

[0052] In another embodiment, a data storage device includes a non-volatile memory device, means for determining whether a block can be programmed continuously after a power loss event, and means for issuing a block busy indication to a host device after a power loss event. The data storage device also includes means for tracking available free blocks after a power loss event.

[0053] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure can be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the claims that follow.

Claims

1. A data storage device, the data storage device comprising: a non-volatile memory device; and a controller coupled to the non-volatile memory device, wherein the controller is configured to: detect a power loss event during a program operation on a block; issue a block busy indication to a host device upon power up after the power loss event, wherein the block busy indication indicates to the host device that a block associated with the block busy indication will not be modified; determine whether the block can still be programmed continuously; and issue a block ready indication to the host device.

2. The data storage device of claim 1, wherein the controller is further configured to identify a program location of the block at the time of the power loss event.

3. The data storage device of claim 2, wherein the controller is further configured to determine whether the location is a fuzzy program location or a fine program location.

4. The data storage device of claim 3, wherein the controller is further configured to read a word line at the location and check a bit error rate of the word line.

5. The data storage device of claim 1, wherein the controller is further configured to determine whether a bit error rate of the block is above or below a threshold.

6. The data storage device of claim 1, wherein the controller is further configured to mark the block as losing good data at a particular location in a power loss table.

7. The data storage device of claim 6, wherein the losing good data at the particular location is stored in an SLC backup location.

8. The data storage device of claim 1, wherein the controller is further configured to copy data from one SLC location to another SLC location upon determining that a bit error rate is too high for a location being programmed in the block at the time of the power loss event.

9. The data storage device of claim 1, wherein the data storage device allows the host device to continue using other blocks of the data storage device while determining.

10. A data storage device, the data storage device comprising: a non-volatile memory device; and a controller coupled to the non-volatile memory device, wherein the controller is configured to: determine power up after a power loss event; check a remaining count of free blocks available for subsequent power loss processing; determine whether the remaining amount of free blocks is above or below a threshold; and either: continue processing a power loss data integrity check and use, wherein processing the power loss data integrity check and use includes issuing a block busy indication to a host device, and wherein the block busy indication indicates to the host device that a block associated with the block busy indication will not be modified; or issue a logical block address (LBA) warning to the host device for any incoming data from the host device, wherein the LBA warning is a low capacity message.

11. The data storage device of claim 10, wherein the controller is further configured to keep track of a plurality of SLC backup blocks.

12. The data storage device of claim 10, wherein the controller is further configured to continue processing the power loss data integrity check and use upon determining that the remaining amount of free blocks is above the threshold.

13. The data storage device of claim 10, wherein the controller is further configured to clean SLC backup blocks upon determining that the remaining amount of free blocks is below the threshold.

14. The data storage device of claim 13, wherein the controller is configured to determine whether the remaining amount of free blocks is above or below a threshold again after cleaning the SLC backup blocks.

15. The data storage device of claim 14, wherein the controller is configured to issue the LBA warning upon determining that the remaining amount of free blocks is below the threshold again.

16. The data storage device of claim 10, wherein continuing to process the power loss data integrity check and use includes issuing a block busy hint to the host device.

17. The data storage device of claim 16, wherein the controller is further configured to determine whether a location in the block that was being programmed at the time of the power loss event is able to be programmed continuously or needs to be marked as missing good data in a power loss table.

18. The data storage device of claim 17, wherein the controller is further configured to issue a block ready hint to the host device upon determining that the block is able to be programmed.

19. A data storage device, the data storage device comprising: a memory device; a controller coupled to the memory device, the controller configured to: determine whether a block is able to be programmed continuously after a power loss event; and issue a block busy hint to a host device after the power loss event, wherein the block busy hint indicates to the host device that a block associated with the block busy hint will not be modified.

20. The data storage device of claim 19, wherein the controller is further configured to track available free blocks after the power loss event. ​

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