Method and system for realizing large-point FFT or DFT based on small-point algorithm core

Abstract

The present invention discloses a method for realizing large-scale FFT or DFT based on small-scale FFT or DFT algorithm core. Large-scale FFT / DFT operation can be realized by using existing small-scale FFT / DFT algorithm core and specific peripheral operation; the method only includes one-dimensional FFT / DFT processing, without matrix transposition operation, simple structure, strong flexibility, and reduces the purchase and R&D cost of the algorithm core.

Description

Technical Field

[0001] The present invention relates to the technical field of signal test and measurement, and in particular to a method for realizing a large-number FFT / DFT based on a small-number FFT / DFT algorithm core. Background Art

[0002] In signal test and measurement systems, some application scenarios require high-precision analysis of the frequency domain characteristics of data. Therefore, not only is it necessary to perform FFT / DFT operations on the data to complete the transformation from time domain to frequency domain, but a larger number of FFT / DFT points is also required to meet higher frequency domain resolution requirements.

[0003] The FFT / DFT operation of data is usually completed using the FFT / DFT core of the FPGA / DSP / software algorithm package. However, the existing FFT / DFT cores usually have a maximum number of FFT / DFT points they support. The number of FFT / DFT points required for some frequency domain high-resolution application scenarios may exceed the maximum number of points supported by the existing FFT / DFT cores. In this case, directly using the existing algorithm cores cannot meet the requirements.

[0004] How to apply the existing FFT / DFT core to achieve FFT / DFT functions exceeding its maximum supported points without directly redeveloping the large-point FFT / DFT algorithm core, and to achieve the equivalent of directly making the large-point FFT / DFT function, is a problem that needs to be solved in the high-precision frequency domain analysis of the current signal test and measurement system.

[0005] In the existing methods for implementing large-point FFT, it is also split into multiple small-point FFTs. The Winograd algorithm requires multiple matrix transpositions, which introduces additional operations. Patent CN103106181A optimizes the operations of multiple transpositions, but in the two-dimensional FFT operation, there is a requirement that the two dimensions of the data split must be integer powers of 2, which imposes certain restrictions on the number of FFT points. Summary of the invention

[0006] In view of this, the present invention provides a method for realizing large-point FFT / DFT based on small-point FFT / DFT algorithm core, which only includes one-dimensional FFT / DFT processing and no matrix transposition operation, has a simpler structure and more flexible FFT / DFT point support.

[0007] The theoretical derivation process is as follows: For the FFT result X(p) of N-point data x(n),

[0008]

[0009] Where p = 0, 1, 2, ..., N-1, n = 0, 1, 2, ..., N-1, "exp(·)" is an exponential function with the natural constant e as the base, and "j" is an imaginary unit;

[0010]

[0011] For each i1, x(i2*M+i1) is equivalent to performing M-way serial-to-parallel conversion on x(n) with i1 as the starting point and M points as the period. Where N=M*K, M is the number of serial-to-parallel conversions for x(n), and K is the number of points in the small-point FFT / DFT algorithm core.

[0012]

[0013]

[0014]

[0015]

[0016] The term is equivalent to performing a K-point FFT / DFT on x(i2*M+i1) and performing M-1 cycles of repeated expansion to N points; then for each i1's N-point expanded FFT / DFT data, use Perform weighted complex multiplication, sum the weighted results of the p-th point complex multiplication corresponding to all i1, and obtain X(p). Here, "%" is the remainder operation.

[0017] Based on the above derivation, the specific steps for calculating an FFT / DFT with N points are as follows:

[0018] S00, perform M-channel data serial-to-parallel conversion: extract the single-channel input discrete signal sequence x(n), n = 0, 1, 2, ..., with M as the cycle period, in sequence to 1 to M parallel data output ports, and the m-th channel output data is represented as x m (k), m = 1, 2, .., M, then x m (k) satisfies the relationship with x(n): x m (k) = x(M*k+m-1); x(n) and x m (k) are both real data or complex data;

[0019] S01, data x of the mth channel m (k) is used as the input of this path, and a small number of points FFT / DFT core is used to complete the FFT / DFT operation in sequence using K points. The complex data output by the mth FFT / DFT core operation is recorded as X m(i), i=0, 1, 2, ... (K-1); for each data output in parallel in step S00, call the FFT / DFT core to perform K-point FFT / DFT operation;

[0020] S02, the mth operation outputs the data X of point K m (i) Repeat the expansion M-1 times with K points as the period, and expand to M*K points of data. The data after the m-th period expansion is X' m (p), p=0,1,2,…(M*K-1), then X' m (p) and X m (i) Satisfy the relationship: X' m (p) = X m (p%K), where "%" is a remainder operation; each K-point data output from the step S01 is expanded to M*K point data.

[0021] S03, generate and each road X' m (p) The complex weighting factor sequence w corresponding to each data point m (p), Where "exp(·)" is an exponential function with the natural constant e as the base, and "j" is an imaginary unit. When the number of points K configured for each FFT / DFT core and the number of serial-to-parallel conversion paths M are determined, the complex weighting factor sequence w corresponding to the m-th path of data m (p) is determined and will not change according to the change of input data. Therefore, the process of generating the weighting factor sequence in this step can be performed independently of other steps in advance or synchronously with other steps.

[0022] S04, expand each point M*K complex data X' after the m-th path generated in step S02 m (p) and step S03 to generate the complex weighting factor sequence w of this path m (p), perform point-to-point complex multiplication to obtain M*K point complex data X' m (p)*w m (p); perform point-to-point complex multiplication on each path of expanded data and the complex weighting factor sequence of that path to obtain M paths of M*K point complex data.

[0023] S05, all the M-way M*K-point complex data X' generated in step S04 m (p)*w m (p), add the corresponding data of each point to get the final M*K point FFT / DFT operation result X(p), that is,

[0024] So far, through the above steps, the function of realizing M*K point FFT / DFT calculation based on K point FFT / DFT core has been completed.

[0025] Beneficial effects:

[0026] The present invention utilizes the existing small-point FFT / DFT algorithm core, does not need additional direct algorithm development, and only includes one-dimensional FFT / DFT processing; there is no matrix transposition operation, and large-point FFT / DFT can be achieved through specific peripheral operations; the present invention has strong scalability and flexibility, a simpler implementation structure, and supports more flexible FFT / DFT points; the present invention expands the scope of use of existing algorithm resources, reduces the rigid requirements for algorithm core specifications, and thus reduces chip or algorithm package procurement costs and R&D costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a principle block diagram of the present invention.

[0028] Figure 2 It is a principle block diagram of an embodiment.

[0029] Figure 3 It is a comparison chart of the results of the FFT method of the present invention in the embodiment and the results of directly performing FFT. DETAILED DESCRIPTION

[0030] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0031] Using FPGA-based, 65536-point FFT algorithm IP core to implement 65536*2-point FFT frequency domain analysis system Figure 2 As shown, the system includes: an ADC chip with serial and parallel acquisition outputs, an FPGA chip, a DDR chip and a host computer.

[0032] In this system, the ADC chip first collects the input single-channel analog voltage signal into discrete digital signals, converts the serial-to-parallel signal into two-channel signals and outputs them to the FPGA port; the FPGA calls the 65536-point FFT IP core and instantiates it into two parallel FFT modules; the DDR opens up a 65536*2-depth storage space for each signal, and each digital signal input from the FPGA port is sequentially and cyclically stored in the corresponding DDR storage space;

[0033] For the DDR storage space corresponding to each data channel, every time 65536 points of data are stored, the FPGA reads the 65536-point segmented data into the FFT module corresponding to the channel, and the FFT module uses these data to complete the 65536-point FFT operation;

[0034] The weighting factors of each channel described in step S03 are generated by two DDS IP cores instantiated by FPGA. For the i-th complex data X output by the m-th (m=1,2) FFT core, m(i), i = 0, 1, 2, ..., 65535; corresponding to method S02, X m (i) The period is extended to M*K points of complex data X' m (p),X' m (p) = X m (p%K), in this embodiment, p = 0, 1, 2, ... (65536*2-1), K = 65536, M = 2, each output point X m (i) In fact, X′ has been obtained m (i) and X′ m (i+65536), so X m (i) The complex weighting factors w generated by the two DDSs are m (i) and w m (i+65536)) performs complex multiplication to generate a 2-point complex result X′ m (i)*w m (i) and X′ m (i+65536)*w m (i+65536); each complex data output by the algorithm core is divided into two data paths: real part and imaginary part;

[0035] Add the weighted multiplication results of the two data paths together to get X′ 1 (i)*w 1 (i)+X′ 2 (i)*w 2 (i) and X′ 1 (i+65536)*w 1 (i+65536))+X′ 2 (i+65536)*w 2 (i+65536); FPGA transmits 2 points X' each time through the PCIe interface 1 (i)*w 1 (i)+X′ 2 (i)*w 2 (i) and X 1 ′(i+65536)*w 1 (i+65536))+X′ 2 (i+65536)*w 2 The complex result of (i+65536) is sent to the host computer as the final FFT result of the i-th point and the i+65536-th point. When the total number of sample points read by the host computer is 65536*2, a 65536*2 point FFT calculation is completed and can be used for frequency domain analysis.

[0036] The method described in the present invention is implemented in a frequency domain analysis system using an FPGA 65536-point FFT algorithm IP core to implement 65536*2-point FFT as follows:

[0037] S00, ADC chip collects the input single-channel analog voltage signal x(t) in series and parallel as two-channel discrete digital signal sequence x 1 (n) and x 2 (n);

[0038] S01, x 1 (n) and x 2 (n) Read in through the FPGA port and convert x 1 (n) Store the data in sequence in a loop into the 65536*2 depth storage space SPACE1 allocated for it in DDR. 2 (n) Store in sequence and in a loop into the storage space SPACE2 with a depth of 65536*2 allocated for it in DDR;

[0039] S02. After DDR SPACE1 is full of 65536 points of data, the data is read into the 65536-point FFT module FFT1 instantiated by FPGA. After DDR SPACE2 is full of 65536 points of data, the data is read into the 65536-point FFT module FFT2 instantiated by FPGA.

[0040] S03, FFT1 and FFT2 complete 65536-point FFT operations respectively;

[0041] S04, and the i-th point complex data X output by FFT1 1 (i) Correspondingly, the two DDSs of the first data channel, DDS11 and DDS12, generate complex weighting factors w 1 (i) and w 1 (i+65536); and the i-th point data X output by FFT2 2 (i) Correspondingly, the two DDSs of the second data channel, DDS21 and DDS22, respectively generate complex weighting factors w 2 (i) and w 2 (i+65536), where wm(i)=exp(-j*2*π*i / 2 / 65536*(m-1)), m=1,2, where "exp(·)" is an exponential function with the natural constant e as the base, and "j" is an imaginary unit;

[0042] S05, the i-th point complex data X output by FFT1 1 (i) X′ after periodic expansion 1 (i) and X′ 1 (i+65536) and the complex weighting factor w1 (i) and w 1 (i+65536) complex multiplication to obtain the weighted complex signal X′ 1 (i)*w 1 (i) and X′ 1 (i+65536)*w 1 (i+65536), the complex data of the i-th point output by FFT2 after period expansion X′ 2 (i) and X′ 2 (i+65536) and the complex weighting factor w 2 (i) and w 2 (i+65536) complex multiplication to obtain the weighted complex signal X′ 2 (i)*w 2 (i) and X′ 2 (i+65536)*w 2 (i+65536);

[0043] S06. Calculate X′ 1 (i)*w 1 (i)+X′ 2 (i)*w 2 (i), X′ 1 (i+65536)*w 1 (i+65536)+X′ 2 (i+65536)*w 2 (i+65536);

[0044] S07, X' in step S06 1 (i)*w 1 (i)+X′ 2 (i)*w 2 (i), X′ 1 (i+65536)*w 1 (i+65536)+X′ 2 (i+65536)*w 2 The complex result of (i+65536) is sent to the host computer through the PCIe bus between the FPGA and the host computer, and is used as the two points X(i) and X(i+65536) in the final 65536*2 point FFT result;

[0045] S08, the host computer reads 65536 times in total, each time reading the results of the i-th and i+65536-th points, and obtains the final 65536*2-point result. Each time the host computer reads 65536*2 points of complex data, it obtains a 65536*2-point FFT result and uses it for frequency domain analysis.

[0046] The results of using the 65536-point FFT algorithm core to implement a 65536*2-point FFT are compared with the results of directly performing a 65536*2-point FFT. Figure 3 As shown, it can be seen that they are completely equivalent.

[0047] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for implementing a large-point FFT or DFT based on a small-point algorithm core, characterized in that: The method is implemented by the following system: The system includes: ADC chip and FPGA chip, where: The ADC chip collects a single-channel analog signal into a discrete digital signal and converts it serially and parallelly into M-channel signals; The FPGA chip includes M FFT / DFT modules, M DDS modules, complex multiplication modules, and complex addition modules; Among them, M FFT / DFT modules receive M signals output by the ADC chip respectively, and perform FFT / DFT operations, and repeat and expand M times with K points as a period; The M DDS modules respectively calculate complex weighting factors of M signals; The complex multiplication module performs point-to-point complex multiplication of the M*K point data calculated and expanded by the FFT / DFT module and the complex weighting factors of the M DDS modules on the corresponding paths; The complex addition module performs point-to-point addition on the M-way complex multiplication results; The method comprises: S00, perform M-channel data serial-to-parallel conversion: extract a single-channel discrete signal sequence x(n) with N points in sequence, with M as the cycle period, to form 1 to M channels of parallel data, where N = M*K, and the m-th channel output x m (k) = x(M*k+m-1), m = 1, 2, .., M; K is the number of points in the small-point FFT / DFT algorithm kernel; S01, for x m (k), using the FFT / DFT kernel, we use K points in sequence to complete the operation and get X m (i), i = 0, 1, 2, ... (K-1); S02, X m (i) Repeat the expansion M times with K points as the cycle, and expand to M*K points of data X' m (p), p = 0, 1, 2, ... (M * k-1), that is: X' m (p) = X m (p%K), where "%" is the remainder operation; S03, X' m (p) and the complex weighting factor sequence w of the mth path m (p) Perform point-to-point complex multiplication to obtain M*K point complex data X' m (p)*w m (p); where Among them, "exp(·)" is the exponential function with the natural constant e as the base, and "j" is the imaginary unit; S04, perform the operations of S01 to S03 on all M parallel data, and then complete all M parallel data X' m (p)*w m (p) Perform point-to-point addition to obtain M*K point FFT / DFT calculation results 2. A method for implementing a large-point FFT or DFT based on a small-point algorithm core as claimed in claim 1, characterized in that: S00 performs serial-to-parallel conversion, x(n) and x m (k) is real number data or complex number data.

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