Random access memory device and method of manufacturing the same

Abstract

Embodiments of the invention provide a random access memory device including a memory bank comprising M main word lines and R replacement word lines, a row / column decoder, and an array of redundant fuse elements. A sorted list of main failed bit counts is generated in descending order of per word line bit failure count. A sorted list of replacement failed bit counts is generated in ascending order of per word line bit failure count. The main word lines are replaced from top to bottom of the list with the replacement word lines until the main failed bit count equals the replacement failed bit count or until all replacement word lines are exhausted. Optionally, the sorted list of main failed bit counts can be reordered in ascending or descending order of word line address prior to the replacement process. Embodiments of the invention also provide a method of manufacturing a random access memory device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention generally relate to the field of semiconductor, and more particularly, to a random access memory device and a manufacturing method thereof. BACKGROUND

[0002] Despite best efforts, many memory dies have defective memory cells at the time of manufacture. Such memory dies can be "fixed" to be operable memory dies by utilizing redundant cells. For example, a word line connected to at least one defective memory cell can be logically replaced with a redundant word line connected to a row of redundant memory cells. A memory die that includes defective memory cells distributed over more word lines than the total number of redundant word lines can not be fixable and thus can have to be discarded. SUMMARY

[0003] One aspect of the present invention provides a method of manufacturing a random access memory device, comprising: providing a semiconductor device including a memory bank comprising M number of main word lines and R number of replacement word lines, a row / column decoder, and an array of redundant fuse elements; generating a sorted main failed bit count list tabulating addresses in the M number of main word lines and a per word line bit failed count in descending order of the per word line bit failed count; generating a sorted replacement failed bit count list tabulating addresses of the R number of replacement word lines and the per word line bit failed count in ascending order of the per word line bit failed count; and performing a redundant fuse programming process in which a first redundant fuse element within the array of redundant fuse elements is programmed to logically replace a main word line on the sorted main failed bit count list with a corresponding word line having a same list order number in the sorted replacement failed bit count list until a main failed bit count is equal to a replacement failed bit count or until all of the R number of replacement word lines are used to replace R number of topmost main word lines on the sorted main failed bit count list.

[0004] Another aspect of the present invention provides a method of manufacturing a random access memory device, comprising: providing a semiconductor device including a memory bank including M number of main word lines and R number of replacement word lines, a row / column decoder, and an array of redundant fuse elements; generating a sorted primary failed bit count list tabulating addresses in the M number of main word lines and a per word line bit failed count in descending order of the per word line bit failed count; generating a sorted replacement failed bit count list tabulating addresses of the R number of replacement word lines and a per word line bit failed count in ascending order of the per word line bit failed count; determining a total replacement count number equal to a minimum of an equal failed count row number and R, the equal failed count row number being a list order number in the sorted primary failed bit count list when a primary failed bit count in the sorted primary failed bit count list is equal to a replacement failed bit count in the sorted replacement failed bit count list; generating a reordered primary failed bit count list modified from the sorted primary failed bit count list by reordering a highest subset of the total replacement count number of lists including the main word lines in ascending address or descending address order; and performing a redundant fuse programming process in which first redundant fuse elements within the array of redundant fuse elements are programmed to logically replace main word lines on the sorted primary failed bit count list with corresponding word lines having a same list order number in the sorted replacement failed bit count list until the total replacement count number of lists in the reordered primary failed bit count list are replaced.

[0005] Yet another aspect of the present invention provides a random access memory device, comprising: a memory bank including a main memory array region and a redundant memory array region, wherein the main array region includes M x N number of main memory cells connected to M number of main word lines and N number of bit lines, and the redundant memory array region includes R x N number of redundant memory cells connected to R number of redundant word lines and the N number of bit lines; and a first redundant fuse element configured to logically replace each main word line having more failed memory bits than a threshold number of per word line bit failed counts in the main array region with a corresponding one of the redundant word lines having a corresponding failed count number not greater than the threshold number of per word line bit failed counts, wherein the threshold number of per word line bit failed counts is a positive integer, wherein the random access memory device includes at least one feature selected from: a first feature in which each redundant word line not replacing any main word line includes a corresponding failed bit count number equal to or greater than the threshold number of per word line bit failed counts; and a second feature in which at least one main word line has a corresponding non-zero failed bit count number and is not replaced by any of the redundant word lines, the non-zero failed bit count number being equal to or less than the threshold number of per word line bit failed counts. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the present application can be best understood with reference to the following detailed description when considered in connection with the accompanying drawings. It should be noted that, for the purpose of clarity, not all components are drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the figure in question for visual clarity.

[0007] Figure 1 is an assembly diagram of an example random access memory die according to embodiments of the present disclosure.

[0008] Figure 2 is a process flow diagram illustrating a first example sequence of processing steps for fabricating a random access memory die according to embodiments of the present disclosure. Figure 1 is a zoomed-in view of a memory bank within the example random access memory die of

[0009] Figure 3 is a process flow diagram illustrating a second example sequence of processing steps for fabricating a random access memory die according to embodiments of the present disclosure.

[0010] Figure 4 is a process flow diagram illustrating a second example sequence of processing steps for fabricating a random access memory die according to embodiments of the present disclosure.

[0011] Figure 5 is a process flow diagram illustrating a second example sequence of processing steps for fabricating a random access memory die according to embodiments of the present disclosure.

[0012] Figure 6 is a zoomed-in view of a memory bank within the example random access memory die of Figure 1 is a zoomed-in view of a memory bank within the example random access memory die of

[0013] Figure 7 is a zoomed-in view of a memory bank within the example random access memory die of Figure 1 is a zoomed-in view of a memory bank within the example random access memory die of

[0014] Figure 8 is a process flow diagram illustrating a second example sequence of processing steps for fabricating a random access memory die according to embodiments of the present disclosure.

[0015] Figure 9 is a table tabulating various fault bit count tables that can be generated and employed during use of the methods of embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] The present disclosure provides many different embodiments or examples of implementing various features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the present disclosure in any way. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and second component form in direct contact, and where additional components can form between the first component and second component such that the first component and second component can not be in direct contact. Furthermore, the present disclosure can be repeated with reference numeral and / or character in various examples. The repetition is for the purpose of simplicity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's or portion's relationship to another element, component or portion as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0018] Referring to Figure 1 , an assembly diagram of an example random access memory die is shown in accordance with embodiments of the present disclosure. The random access memory die includes a plurality of random access memory cells, i.e., memory cells that can be accessed randomly upon a specified set of logical addresses, such as a combination of a word line address and a bit line address. For example, the random access memory die can include an array of dynamic random access memory cells that include respective series connections of access transistors and capacitors. One node of the capacitor can be connected to a source region of the access transistor, a gate electrode of the access transistor can be a portion of a word line that can be activated by a word line control transistor. A drain region of the access transistor can be connected to a respective bit line through a drain connection structure, such as a drain contact via structure. Generally, each random access memory cell can be provided in an array environment within a respective memory bank.

[0019] An example random access memory die includes eight memory banks, labeled "Memory Bank_i," where integer i ranges from 0 to 7. Generally, a random access memory die according to embodiments of the present disclosure includes at least one memory bank. Each memory bank includes a two-dimensional array of memory cells that are accessible by a respective set of word lines and a respective set of bit lines. Each word line includes a gate electrode for a row of access transistors that can be laterally spaced apart along a first horizontal direction, and each bit line can be connected to a respective set of drain regions located within a respective column of access transistors arranged along a second horizontal direction. The second horizontal direction can be perpendicular to the first horizontal direction. While embodiments of the present disclosure are described with a random access memory die that includes eight memory banks, embodiments in which a different number of memory banks are present within a random access memory die are expressly contemplated herein.

[0020] A random access memory die can include row / column decoder circuitry that decodes word line addresses and bit line addresses during operation of the random access memory die. The row / column decoder circuitry can activate a word line corresponding to a decoded word line address, and the row / column decoder circuitry can activate a set of bit lines in a memory bank that includes a selected bit line address. Generally, the row / column decoder circuitry activates at least one word line and a set of bit lines associated with a selected address or a selected range of addresses during operation of the random access memory die.

[0021] A random access memory die can include control circuitry that controls various operations within the random access memory die. The various operations include program operations (i.e., write operations), erase operations, and read operations.

[0022] A random access memory die can include at least one input / output circuit that controls the flow of data into and out of the random access memory die. Latches and data buffers can be provided within the at least one input / output circuit.

[0023] A random access memory die can include power supply circuitry that is configured to provide supply voltages to the memory banks and various other circuitry within the random access memory die. Other various peripheral circuitry (not shown) can be provided within the random access memory die as needed, such as clock circuitry, signal buffers, and signal amplifiers.

[0024] According to an aspect of the present disclosure, a random access memory die can include at least one redundancy fuse region including redundancy fuse elements, which can include first redundancy fuse elements and second redundancy fuse elements. The first redundancy fuse elements can include programmable read-only memory (PROM) elements, such as electrically programmable fuses. The first redundancy fuse elements can be configured to reconfigure electrical connections between row-column decoder circuitry and word lines within a memory bank. For example, if a set of defective main word lines in a memory bank are logically replaced by a set of replacement word lines, the first redundancy fuse elements are configured to activate a corresponding one of the replacement word lines when a word line address corresponding to a defective word line is decoded by the row / column decoder circuitry. In one embodiment, each first redundancy fuse element can be applied to logically replace a defective main word line with a corresponding one of the replacement word lines.

[0025] According to an aspect of the present disclosure, replacement storage cells can be provided in a memory bank, which can be used to logically replace individual storage bits that can remain in any memory bank after a defective main word line is replaced with a replacement word line. In one embodiment, each second redundancy fuse element can be applied to logically replace a defective storage cell with a corresponding one of the replacement storage cells, i.e., with a single replacement storage cell configured to store a single bit of data.

[0026] Figure 2 is a zoomed-in view of a memory bank within an exemplary random access memory die according to embodiments of the present disclosure. Figure 1 is a zoomed-in view of a memory bank within an exemplary random access memory die according to embodiments of the present disclosure. Figure 2 The illustrated memory bank can be any one of the memory banks in Figure 1 According to embodiments of the present disclosure, a memory bank can include a main memory array region and a redundant memory array region. In one embodiment, the main array region includes M x N main storage cells connected to M main word lines and N bit lines, and the redundant memory array region includes R x N redundant storage cells connected to R replacement word lines and N bit lines. In one embodiment, the integer M can be a number that is an integer power of 2, i.e., 2 k where k can be in a range from 8 to 20. The integer N can or can not be a number that is an integer power of 2, i.e., 2 l where l can be in a range from 8 to 20. The integer R is typically less than M, and can be in a range from 0.1% to 10% of the number M, e.g., 0.2% to 5%.

[0027] The MxN main memory cells can be located within a main memory array region. The R x N redundant memory cells can be located within a redundant memory array region that can be laterally offset from the main memory array region along the direction of the bit lines. The main word lines can be numbered in numerical order from one side to the other, with the numerical index increasing by 1 with each shift from one main word line to another. For example, the main word lines can be numbered numerically such that the (i+1)th main word line is labeled as PWL_i, where the integer i varies from 0 to (M-1). The replacement word lines can be numbered in numerical order from one side to the other, with the numerical index increasing by 1 with each shift from one replacement word line to another. For example, the replacement word lines can be numbered numerically such that the (j+1)th replacement word line is labeled as RWL_j, where the integer j varies from 0 to (R-1). The bit lines can be perpendicular to the main word lines and the replacement word lines. The bit lines can be sequentially labeled with numbers from one side to the other, such that the (k+1)th bit line is labeled as BL_k, where the integer k varies from 0 to (N-1).

[0028] Generally, a series of semiconductor fabrication process steps can be employed to fabricate each memory bank. Testing of each random access memory die can be performed during a test step, which can be performed prior to dicing the random access memory dies within a wafer into a plurality of discrete random access memory dies. During the test step, functional failures of each memory cell can be identified in each memory bank. A failure bit map of the MxN main memory cell array and a failure bit map of the R x N redundant memory cell array can be generated during the test step. Failures of a memory cell can include any defect in providing functionality of the memory cell, and can include a program failure, an erase failure, or a read failure. Generally, any failure to randomly write a “1” or a “0” and / or to randomly read a correct value of a “1” or a “0” can be considered a functional failure of a memory cell.

[0029] Figure 3The process of determining a per-wordline failure bit count for each primary wordline PWL_i in the memory bank is illustratively shown according to embodiments of the present disclosure. The per-wordline failure bit count for any given primary wordline PWL_i can be determined by counting the total number of failed memory cells addressed by the primary wordline PWL_i. For example, the total number of failed memory cells addressed by the first primary wordline PWL_0 is the first primary failure bit count PFBC(0) for the first primary wordline PWL_0. For each integer i between 0 and M (i.e., for each integer i in the range from 1 to (M-1)), the total number of failed memory cells addressed by the (i+1)th primary wordline PWL_i is the (i+1)th primary failure bit count PFBC(i) for the (i+1)th primary wordline PWL_i. In general, the per-wordline failure bit count for each primary wordline PWL_i in the memory bank can be generated by counting the total number of failed memory cells (as identified in the testing step) addressed by the respective primary wordline PWL_i.

[0030] Figure 4 The process of determining a per-wordline failure bit count for each redundant wordline RWL_j in the memory bank is illustratively shown according to embodiments of the present disclosure. For any given redundant wordline RWL_j, the per-wordline failure bit count is determined by counting the total number of failed memory cells addressed by the redundant wordline RWL_j. For example, the total number of failed memory cells addressed by the first redundant wordline RWL_0 is the first redundant failure bit count RFBC(0) for the first redundant wordline RWL_0. For each integer j between 0 and R (i.e., for each integer j in the range from 1 to (R-1)), the total number of failed memory cells addressed by the (j+1)th redundant wordline RWL_j is the (j+1)th redundant failure bit count PFBC(j) for the (j+1)th redundant wordline RWL_j. In general, the per-wordline failure bit count for each redundant wordline RWL_j in the memory bank can be generated by counting the total number of failed memory cells (as identified in the testing step) addressed by the respective redundant wordline RWL_j.

[0031] Figure 5 is a first flowchart showing a sequence of processing steps for fabricating a first example of a random access memory die of the present disclosure. Figure 9 is a table tabulating various failure bit count lists that can be generated and employed during use of the methods of embodiments of the present disclosure. Reference is made to Figures 1-4 and Figure 5 Step 510 of

[0032] Reference is made to Figure 5 Step 520 ofFigure 9 A sorted primary failed bit count list can be generated for each memory bank, e.g., by an automated program running on the tester or on a computing device in communication with the tester. The sorted primary failed bit count list tabulates the addresses of the M primary wordlines and the per-wordline bit failed count in descending order of per-wordline bit failed count. Thus, the wordline addresses of the primary wordlines having the highest per-wordline bit failed count are arranged at the top of the sorted primary failed bit count list, and the wordline addresses of the primary wordlines having the lowest per-wordline bit failed count (typically zero, as a majority (i.e., more than 50%) of the primary wordlines are fully functional) are arranged at the bottom of the sorted primary failed bit count list. The total number of wordline addresses associated with non-zero primary failed bit counts can or can not be greater than the total number of replacement wordlines R in the memory bank.

[0033] In an illustrative example, the sorted primary failed bit count list can be generated by performing at least one write operation in which at least one test data pattern can be written into the primary memory array region of the memory bank. At least one read operation can be performed in which at least one test data pattern is read from the primary memory array region. The number of storage bit failures for each primary wordline can be determined based on changes in the at least one test data pattern between the at least one read operation and the at least one write operation. The addresses of the primary wordlines can be sorted such that the associated number of storage bit failures for each primary wordline is arranged in descending order.

[0034] Referring to Figure 5 Step 530 and Figure 9 A sorted replacement failed bit count list can be generated for each memory bank, e.g., by an automated program running on the tester or on a computing device in communication with the tester. The sorted replacement failed bit count list tabulates the addresses of the R replacement wordlines and the per-wordline bit failed count in ascending order of per-wordline bit failed count. Thus, the wordline addresses of the replacement wordlines having the lowest per-wordline bit failed count (typically zero, as a majority (i.e., more than 50%) of the replacement wordlines are fully functional) are arranged at the top of the sorted replacement failed bit count list, and the wordline addresses of the wordlines having the highest per-wordline bit failed count are arranged at the bottom of the sorted replacement failed bit count list.

[0035] In an illustrative example, a ranked replacement faulty bit count list can be generated by performing at least one write operation in which at least one test data sample is written to a replacement memory array in a memory bank. At least one read operation can be performed in which the at least one test data sample is read from the replacement array. A number of storage bit faults per replacement wordline can be determined based on a change in the at least one test data sample between the at least one read operation and the at least one write operation. Addresses of the replacement wordlines can be ranked such that the associated storage bit fault numbers per replacement wordline are in ascending order.

[0036] Referring to Figure 5 At step 540, a redundant fuse programming process can be performed. The redundant fuse programming process can be part of a testing step in which functional defects of a storage die under test are repaired by activation of replacement wordlines and by activation of replacement storage cells in a replacement storage cell region.

[0037] In particular, a first redundant fuse element within an array of redundant fuse elements can be programmed to logically replace a main wordline on a ranked main faulty bit count list with a corresponding wordline having a same list order number on a ranked replacement faulty bit count list. The process starts from a topmost row (i.e., line) of the ranked main faulty bit count list and the ranked replacement faulty bit count list. In one embodiment, a row number (i.e., list order number) of each replacement wordline logically replacing a defective main wordline in the ranked replacement faulty bit count list can be the same as a row number (i.e., list order number) of the defective main wordline replaced by the corresponding replacement wordline in the ranked main faulty bit count list. The process can continue until the main faulty bit count equals the replacement faulty bit count or until all R replacement wordlines are used to replace R topmost main wordlines on the ranked main faulty bit count list. In the case where the main faulty bit count equals the replacement faulty bit count, this number is referred to as a threshold number of bit faults per wordline.

[0038] For example, if a total number of fully functional replacement wordlines (i.e., having no faulty storage bits addressed by a corresponding main wordline) is R' (not greater than R), and if a total number of main wordlines having a non-zero faulty bit count is not greater than R', a first redundant fuse element can be applied to logically replace each main wordline having a non-zero faulty bit count with a corresponding fully functional replacement wordline.

[0039] If the total number of fully functional replacement word lines (i.e., that do not have any failed storage bits addressed by a corresponding main word line) is R' (not greater than R), and if the total number of main word lines having a non-zero failed bit count is greater than R', first redundancy fuse elements can be applied, R' main word lines having a non-zero failed bit count are each logically replaced by a corresponding one of R' fully functional replacement word lines. In addition, even if an extra replacement word line has a non-zero failed bit count that is in the same order as the number (i.e., row number) of the list order in the sorted main failed bit count list, the extra main word line having a non-zero failed bit count can be each logically replaced by a corresponding one of the extra replacement word lines until all R replacement word lines are used to replace R topmost main word lines on the sorted main failed bit count list, or until the main failed bit count equals the replacement failed bit count for the same list order number (i.e., for the same row number), i.e., until the threshold number of bit failure counts per word line is reached.

[0040] In one embodiment, the failed bit count of the Rth main word line on the sorted main failed bit count list can be greater than the failed bit count of the Rth replacement word line on the sorted replacement failed bit count list. In this embodiment, all R replacement word lines can be employed to replace the topmost R main word lines on the sorted main failed bit count list.

[0041] In another embodiment, the failed bit count of the Rth main word line on the sorted main failed bit count list can be equal to or less than the failed bit count of the Rth replacement word line on the sorted replacement failed bit count list. In this embodiment, the logical replacement process can terminate when the list order number (i.e., row number) of the failed bit count of the corresponding main word line on the sorted main failed bit count list equals the failed bit count of the corresponding replacement word line on the sorted replacement failed bit count list is reached. In this embodiment, one or more replacement word lines are not used to replace any main word line.

[0042] According to embodiments of the present disclosure, main word lines on the sorted main failed bit count list are replaced in order from top to bottom by corresponding word lines on the sorted replacement failed bit count list having the same list order number (i.e., same row number).

[0043] According to an embodiment of the disclosure, at least one un-repaired defective memory cell can exist in the memory bank after the respective word lines having the same list order number on the ordered replacement faulty bit count list logically replace the subset of the primary word lines on the ordered primary faulty bit count list. In this embodiment, each of the R number of redundant word lines is used to replace a respective one of the defective primary word lines (i.e., the primary word lines connected to the at least one faulty memory cell), or has the same number of defective memory cells as any remaining un-replaced defective primary word line, or has a greater number of defective memory cells than any remaining un-replaced defective primary word line.

[0044] According to one aspect of the disclosure and with reference to Figure 1 and Figure 6 , a random access memory device can include replacement memory cells located in at least one replacement memory cell region. Each set of replacement memory cells can be located within a replacement memory bit array configured to be individually accessed by a respective pair of access lines (e.g., a pair consisting of a replacement word line and a replacement bit line). In this embodiment, a second redundant fuse element within the array of redundant fuse elements (located within the redundant fuse region) can be programmed such that the programmed second redundant fuse element logically replaces each faulty memory bit in the replacement memory cells with a respective one of the replacement memory cells, the faulty memory bits being located within the primary memory array region and connected to a respective primary word line that is not logically replaced by a respective replacement word line. In one embodiment, the replacement memory cells can be arranged in a periodic array, such as a P x Q rectangular array.

[0045] Accordingly, each faulty bit within the M x N array of memory cells within the memory array region can be repaired with a memory bit connected to a respective one of the replacement word lines or with a memory bit located within a replacement memory cell. In one embodiment, a set of N memory cells attached to each replacement word line is accessed simultaneously, and each replacement memory cell replacing a faulty memory bit within the M x N array of memory cells is individually addressed. The combination of row / column decoder circuitry and groups of redundant fuse elements within the redundant fuse region rewire address select signals from the controller to the redundant word lines and replacement memory cells.

[0046] In one embodiment, each pair of access lines used to access a replacement memory cell can be configured to only access a single replacement memory cell within the replacement memory cell, and can be electrically isolated from all other replacement memory cells. In one embodiment, the replacement memory cells can include an array of static random access memory cells including a respective set of at least six field effect transistors.

[0047] In one embodiment, the second redundant fuse element can be programmed such that the control circuit (connected to the second redundant fuse element and controlling data flow based on the configuration of the second redundant fuse element) reroutes data for each faulty storage location that is to be replaced by a respective one of the replacement storage locations to the respective one of the replacement storage locations during a program operation. In addition, the second redundant fuse element can be programmed such that the control circuit (connected to the second redundant fuse element and controlling data flow based on the configuration of the second redundant fuse element) reroutes an erase signal for each faulty storage location that is to be replaced by a respective one of the replacement storage locations to the respective one of the replacement storage locations during an erase operation. The control circuit can overwrite data for each faulty storage location that is to be replaced by a respective one of the replacement storage locations with data read from the respective one of the replacement storage locations during a read operation. Thus, read operations from the memory array region and the redundant cell region can be performed concurrently with read operations from the respective groups of at least one replacement storage location, and thereafter a rewrite operation can be performed in which data from the at least one replacement storage location overwrites data from defective storage locations within the memory array region (comprising the MxN array of storage locations) that are replaced by the respective replacement storage locations.

[0048] Figure 7 is a magnified view of an alternative configuration of memory banks within an exemplary random access memory die according to embodiments of the present disclosure. Figure 1 is a magnified view of an alternative configuration of memory banks within an exemplary random access memory die according to embodiments of the present disclosure.

[0049] In one embodiment, the random access memory device comprises a dynamic random access memory device in which each storage location within a memory bank comprises a respective series connection of a capacitor structure configured to store an electric charge therein and an access transistor configured to control the flow of electric charge into and out of the capacitor.

[0050] Generally, the main word lines can be formed within a single memory array containing the MxN array of storage locations, or can be formed within at least two memory arrays containing respective M t xN arrays of storage locations such that all M tThe total of all values of Rs for index s in the range of 0 to T is equal to R. The total number of redundant memory cell regions can be in the range of 1 to 128, although larger numbers can be used. In embodiments of multiple memory array regions and / or multiple redundant memory cell regions, such multiple memory array regions and / or multiple redundant memory cell regions can be laterally spaced apart from one another along the bit line direction, and can be interleaved with one another along the bit line direction. In other words, instances of memory array regions and / or instances of redundant memory cell regions can alternate along the bit line direction. Bit lines can extend continuously through each of the memory array regions and the redundant memory cell regions. For example, in one embodiment, a single memory array containing an MxN array of memory cells or can be formed with a single redundant memory cell region. In another embodiment, a single memory array containing an MxN array of memory cells or can be formed with at least two redundant memory cell regions, where each redundant memory cell region contains a corresponding RsxN array of replacement memory cells such that the total of all values of Rs for index s in the range of 0 to T is equal to R. In such embodiments, the at least two redundant memory cell regions can be formed before and after the single memory array. In another embodiment, at least two memory arrays contain corresponding MtxN arrays of memory cells such that the total of all Mt is equal to M, while at least two redundant memory cell regions contain corresponding RsxN arrays of replacement memory cells such that the total of all values of Rs for index s in the range of 0 to T is equal to R. In such embodiments, the at least two redundant memory cell regions can be formed after each of the at least two memory arrays. In another embodiment, at least two memory arrays contain corresponding MtxN arrays of memory cells such that the total of all Mt is equal to M, while at least two redundant memory cell regions contain corresponding RsxN arrays of replacement memory cells such that the total of all values of Rs for index s in the range of 0 to T is equal to R. In such embodiments, the at least two redundant memory cell regions can be formed before and after each of the at least two memory arrays.

[0051] Figure 8 is a second flow diagram illustrating a first example sequence of processing steps for fabricating a random access memory die of the present disclosure.

[0052] Referring collectively to Figures 1-4 , Figure 6 and Figure 7 and Figure 8At step 810 of the method of manufacturing a random access memory device, the method can include a step of providing a semiconductor device including a memory bank including M number of main word lines and R number of replacement word lines, a row / column decoder, and an array of redundant fuse elements.

[0053] Referring collectively to Figures 1-4 , Figure 6 and Figure 7 and Figure 8 steps 820 and Figure 9 , the method can include a step of generating a sorted main failed bit count list tabulating addresses of the M number of main word lines and a per word line bit failed count in descending order of the per word line bit failed count. The same processing steps as in step 520 of Figure 5 may be employed.

[0054] Referring collectively to Figures 1-4 , Figure 6 and Figure 7 and Figure 8 steps 830 and Figure 9 , the method can include a step of generating a sorted replacement failed bit count list tabulating addresses of the R number of replacement word lines and a per word line bit failed count in ascending order of the per word line bit failed count. The same processing steps as in step 530 of Figure 5 may be employed.

[0055] Referring collectively to Figures 1-4 , Figure 6 and Figure 7 and Figure 8 steps 840, the method can include a step of determining a total replacement count number equal to a minimum of the equal failed count row number and R. The replacement count number is the list order number (i.e., row number) up to which the replacement process in the main failed bit count list is subsequently performed. In other words, the subsequent replacement operation for a failed main word line in the top of the sorted main failed bit count list terminates at the list order number equal to the replacement count number.

[0056] The equal failed count row number is the list order number in the sorted main failed bit count list where the main failed bit count is equal to the replacement failed bit count in the sorted replacement failed bit count list, i.e., the list order number (or row number in the table) equal to the threshold number of per word line bit failed counts. In this embodiment, any failed main word line having a list order number (i.e., row number in the list) equal to or greater than the equal failed count row number is futilely replaced by the corresponding replacement word line having the equal list order number because the corresponding replacement word line has the same number of failed storage bits or has a greater number of failed storage bits.

[0057] Referring collectively to Figures 1-4 , Figure 6 andFigure 7 and Figure 8 the step 850 of Figure 9 The method can include a step of generating a reordered primary failed bit count list by reordering a highest subset of total replacement count numbers of the list containing the primary word lines in ascending address order or descending address order, such that the primary failed bit count list is modified to yield the reordered primary failed bit count list. In other words, only the primary word line addresses of the defective primary word lines that are subsequently logically replaced by replacement word lines are ordered in ascending address order or descending address order.

[0058] According to an aspect of the disclosure, the reordering algorithm can select between ascending address order and descending address order such that, after the defective primary word lines are replaced with replacement word lines logic, the physical wiring distance (i.e., the physical distance of the metal interconnect structures used to transmit electrical signals) can be minimized.

[0059] In one embodiment, a reordered replacement failed bit count list can be generated by reordering a highest subset of total replacement count numbers of the list containing the replacement word lines in ascending address order or descending address order, such that the replacement failed bit count list is modified to yield the reordered replacement failed bit count list. In other words, only the replacement word line addresses of the replacement word lines that subsequently logically replace the defective primary word lines are ordered in ascending address order or descending address order. If the reordered primary failed bit count list is ordered in ascending word line address order, then the reordered replacement failed bit count list is ordered in ascending word line address order. If the reordered primary failed bit count list is ordered in descending word line address order, then the reordered replacement failed bit count list is ordered in descending word line address order.

[0060] Referring collectively to Figures 1-4 , Figure 6 and Figure 7 and Figure 8 The method can include a step of performing a redundant fuse programming process in which first redundant fuse elements within the array of redundant fuse elements are programmed to logically replace primary word lines on the reordered primary failed bit count list with corresponding word lines having the same listing order number on the ordered replacement failed bit count list until the total replacement count number of listings in the reordered primary failed bit count list is replaced. Figure 5 The method employed by the step 540 of Figure 8 The step 860 of

[0061] In one embodiment, the primary word lines on the reordered primary failed bit count list are sequentially replaced from top to bottom with corresponding word lines having the same listing order number on the ordered replacement failed bit count list.

[0062] In one embodiment, the random access memory device includes replacement storage cells located within a replacement storage bit array configured to be individually accessed by respective pairs of access lines. A second redundant fuse element within the array of redundant fuse elements can be programmed such that the programmed second redundant fuse element logically replaces each faulty storage bit with a respective one of the replacement storage cells, each faulty storage bit located within the main memory array region and connected to a respective main word line that is not logically replaced by a respective replacement word line.

[0063] In one embodiment, addresses of the set of all replacement word lines for a respective one of the replacement main word lines strictly increase or strictly decrease from one side to the other side of the R replacement word lines.

[0064] Referring to all of the drawings, there is provided, in accordance with various embodiments of the present disclosure, a random access memory device including a memory bank including a main memory array region and a redundant memory array region, wherein the main array region includes M x N main storage cells connected to M main word lines and N bit lines, and the redundant memory array region includes R x N redundant storage cells connected to R replacement word lines and N bit lines; and a first redundant fuse element configured to logically replace each main word line within the main array region having more faulty storage bits than a threshold number of faulty bits per word line with a respective one of the redundant word lines having a respective number of faulty counts not greater than the threshold number of faulty bits per word line, wherein the threshold number of faulty bits per word line is a positive integer. The random access memory device includes at least one feature selected from the following: a first feature, each redundant word line that does not replace any main word line includes a respective number of faulty counts equal to or greater than the threshold number of faulty bits per word line; and a second feature, at least one main word line has a respective non-zero number of faulty counts and is not replaced by any one of the redundant word lines, the non-zero number of faulty counts being equal to or less than the threshold number of faulty bits per word line.

[0065] In one embodiment, the random access memory device includes replacement storage cells located within a replacement storage bit array configured to be individually accessed by respective pairs of access lines; and a second redundant fuse element configured to logically replace each faulty storage bit located within the main memory array region and connected to a respective main word line that is not logically replaced by a respective replacement word line with a respective one of the replacement storage cells.

[0066] In one embodiment, each pair of access lines is configured to access only a single one of the replacement storage cells and is electrically isolated from all other replacement storage cells. In one embodiment, the replacement storage cells include an array of static random access memory cells including a respective set of at least six field effect transistors.

[0067] In one embodiment, the random access memory device includes a control circuit configured to: rewire data of each failed storage bit that is replaced by a respective one of the replacement storage units to the respective one of the replacement storage units during a program operation; and rewrite data of each failed storage bit that is replaced by the respective one of the replacement storage units with data read from the respective one of the replacement storage units during a read operation.

[0068] In one embodiment, the random access memory device includes at least one feature selected from: a first feature that a set address of all replacement word lines that replace a respective one of the main word lines strictly increases or strictly decreases from one side to another side within the R x N redundant storage units; and a second feature that the R x N redundant storage units include at least two redundant storage unit regions that are laterally spaced apart from each other or are laterally spaced apart from each other by at least a subset of the M x N main storage units. According to various embodiments of the present disclosure, a method of manufacturing a random access memory device is provided, including: providing a semiconductor device including a memory bank including M main word lines and R replacement word lines, a row / column decoder, and a redundant fuse element array; generating a sorted main failed bit count list tabulating addresses in the M main word lines and an each word line bit failure count in descending order of the each word line bit failure count; generating a sorted replacement failed bit count list tabulating addresses of the R replacement word lines and the each word line bit failure count in ascending order of the each word line bit failure count; and performing a redundant fuse programming process in which a first redundant fuse element within the redundant fuse element array is programmed to logically replace a main word line on the sorted main failed bit count list with a respective word line having a same list order number in the sorted replacement failed bit count list until a main failed bit count is equal to a replacement failed bit count or until all of the R replacement word lines are used to replace R topmost main word lines on the sorted main failed bit count list.

[0069] In some embodiments, the main word lines on the sorted main failed bit count list are replaced in order from top down to respective word lines having a same list order number on the sorted replacement failed bit count list.

[0070] In some embodiments, generating the sorted list of primary fault bit counts includes: performing at least one write operation, in which at least one test data sample is written to a main memory array region; performing at least one read operation, in which the at least one read operation is read from the main memory array region; determining the number of faults per main word line based on the change of the at least one test data sample between the at least one read operation and the at least one write operation; and sorting the addresses of the main word lines such that the associated number of faults per main word line is arranged in descending order.

[0071] In some embodiments, generating the sorted list of replacement fault bit counts includes: performing at least one write operation, in which at least one test data sample is written to a replacement memory array; performing at least one read operation, in which the at least one read operation is read from the replacement memory array; determining the number of faults per replacement word line based on the change of the at least one test data sample between the at least one read operation and the at least one write operation; and sorting the addresses of the replacement word lines such that the associated number of faults per replacement word line is arranged in ascending order.

[0072] In some embodiments, the random access memory device includes alternative memory cells located within an alternative memory bit array configured to be accessed individually by corresponding access line pairs; and the method includes programming a second redundant fuse element within the redundant fuse element array such that the programmed second redundant fuse element replaces each faulty memory bit located within the main memory array region and connected to a corresponding main word line that has not been replaced by the corresponding alternative word line logic with a corresponding logic of the alternative memory cell.

[0073] In some embodiments, each pair of access lines is configured to access only a single alternative memory cell among the alternative memory cells and is electrically isolated from all other alternative memory cells.

[0074] In some embodiments, the alternative memory cell includes an array of static random access memory cells, each comprising a corresponding group of at least six field-effect transistors.

[0075] In some embodiments, the second redundant fuse element is programmed such that a control circuit connected to the second redundant fuse element re-routes data of each failed storage bit that is replaced by a respective one of the replacement storage units to the respective one of the replacement storage units during a program operation; and the control circuit overwrites data of each failed storage bit that is replaced by the respective one of the replacement storage units with data read from the respective one of the replacement storage units during a read operation.

[0076] In some embodiments, the R number of replacement word lines are located in at least two redundant storage unit regions that are laterally spaced apart from each other or are laterally spaced apart from each other by at least a subset of the M number of main word lines.

[0077] In some embodiments, the random access memory device comprises a dynamic random access memory device, each storage bit within the memory bank in the dynamic random access memory device comprises a respective series connection of a capacitor structure and an access transistor, the capacitor structure is configured to store a charge of each storage bit, the access transistor is configured to control a flow of the charge into and out of the capacitor structure.

[0078] According to embodiments of the present disclosure, there is provided a method of manufacturing a random access memory device, comprising: providing a semiconductor device comprising a memory bank comprising M number of main word lines and R number of replacement word lines, a row / column decoder, and an array of redundant fuse elements; generating a sorted primary failed bit count list tabulating addresses in the M number of main word lines and a per word line bit failed count in descending order of the per word line bit failed count; generating a sorted replacement failed bit count list tabulating addresses of the R number of replacement word lines and a per word line bit failed count in ascending order of the per word line bit failed count; determining a total replacement count number equal to a minimum of an equal failed count row number and R, the equal failed count row number being a list order number in the sorted primary failed bit count list when a primary failed bit count in the sorted primary failed bit count list is equal to a replacement failed bit count in the sorted replacement failed bit count list; generating a reordered primary failed bit count list modified from the sorted primary failed bit count list by reordering a highest subset of the total replacement count number of lists containing the main word lines in ascending address or descending address order; and performing a redundant fuse programming process in which a first redundant fuse element within the array of redundant fuse elements is programmed to logically replace a main word line on the sorted primary failed bit count list with a respective word line having a same list order number in the sorted replacement failed bit count list until the total replacement count number of lists in the reordered primary failed bit count list are replaced.

[0079] In some embodiments, the main word lines on the reordered main failed bit count list are replaced in top-to-bottom order with the corresponding word lines on the reordered replacement failed bit count list having the same list order number.

[0080] In some embodiments, the random access memory device includes replacement storage cells located within a replacement storage bit array, the replacement storage bit array configured for individual access by a corresponding access line; and the method includes programming a second redundant fuse element within the array of redundant fuse elements such that the programmed second redundant fuse element logically replaces each failed storage bit located within the main storage array region and connected to a corresponding main word line that is not logically replaced by a corresponding replacement word line.

[0081] In some embodiments, the addresses of the set of all replacement word lines that replace a corresponding one of the main word lines increase strictly or decrease strictly from one side of the R replacement word lines to the other. Various embodiments of the present disclosure can be used to repair random access memory dies having a high bit error rate (BER), i.e., a probability of functional failure for any given memory cell configured to store a single bit. In an illustrative comparative example repair scheme, if a memory array region includes 1024 main word lines and 4096 bit lines, if a redundant cell region includes 64 replacement word lines and the same number of bit lines, and if the bit error rate is 100 parts per million (i.e., 0.0001), a replacement scheme that uses only fully functional replacement word lines (i.e., only replacement word lines that are not connected to any failed storage bit) provides an effective bit error rate of approximately 82 parts per million after a redundancy repair process using approximately 60% of all replacement word lines. In contrast, in an example repair scheme that employs embodiments of the present disclosure, if a memory array region includes 1024 main word lines and 4096 bit lines, if a redundant cell region includes 64 replacement word lines and the same number of bit lines, and if the bit error rate is 100 parts per million (i.e., 0.0001), a replacement scheme according to embodiments of the present disclosure can provide an effective bit error rate of approximately 78 parts per million after a redundancy repair process using approximately 90% of all replacement word lines. According to embodiments of the present disclosure, near 100% yield (depending on the total number of replacement storage cells) can be achieved when using replacement storage cells.

[0082] In another illustrative repair scheme, if the memory array region includes 1024 main word lines and 4096 bit lines, if the redundancy cell region includes 64 replacement word lines and the same number of bit lines, and if the error rate is 1000 parts per million (i.e., 0.001), a replacement scheme that employs only fully functional replacement word lines (i.e., replacement word lines that are not connected to any faulty memory bit) provides an effective error rate of approximately 995 parts per million after approximately 5% of the redundancy repair process using all replacement word lines. The high error rate significantly reduces the number of fully functional replacement word lines, thus rendering the repair ineffective. In contrast, in an illustrative repair scheme that employs embodiments of the present disclosure, if the memory array region includes 1024 main word lines and 4096 bit lines, if the redundancy cell region includes 64 replacement word lines and the same number of bit lines, and if the error rate is 1000 parts per million (i.e., 0.001), a replacement scheme according to embodiments of the present disclosure can provide an effective error rate of approximately 940 parts per million after approximately 90% of the redundancy repair process using all replacement word lines. Using replacement memory cells, according to embodiments of the present disclosure, a much higher yield can be obtained (depending on the total number of replacement memory cells) relative to the comparative illustrative repair scheme. Thus, embodiments of the present disclosure can provide a higher die yield after redundancy repair.

[0083] The foregoing summarizes features of several embodiments so that those skilled in the art will better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily apply the present disclosure as a basis for the design or modification of other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of manufacturing a random access memory device, comprising: providing a semiconductor device including a memory bank comprising M number of main word lines and R number of replacement word lines, a row / column decoder, and an array of redundancy fuse elements; generating a sorted main failed bit count list tabulating addresses in the M number of main word lines and a per word line bit failed count in descending order of the per word line bit failed count; generating a sorted replacement failed bit count list tabulating addresses of the R number of replacement word lines and the per word line bit failed count in ascending order of the per word line bit failed count; performing a redundancy fuse programming process in which first redundancy fuse elements within the array of redundancy fuse elements are programmed to logically replace main word lines on the sorted main failed bit count list with corresponding word lines having a same list order number in the sorted replacement failed bit count list until a main failed bit count equals a replacement failed bit count or until all of the R number of replacement word lines are used to replace R number of topmost main word lines on the sorted main failed bit count list, wherein the random access memory device includes replacement storage cells located within a replacement storage bit array configured to be individually accessed by corresponding access lines; and programming second redundancy fuse elements within the array of redundancy fuse elements such that the programmed second redundancy fuse elements logically replace each failed storage bit located within a main storage array region and connected to a corresponding main word line that is not logically replaced by a corresponding replacement word line with a corresponding one of the replacement storage cells.

2. The method of claim 1, wherein, the main word lines on the sorted main failed bit count list are replaced in order from top down to corresponding word lines having a same list order number on the sorted replacement failed bit count list.

3. The method of claim 1, wherein, generating the sorted main failed bit count list includes: performing at least one write operation in which at least one test data sample is written to a main storage array region; performing at least one read operation in which the at least one test data sample is read from the main storage array region; determining a per main word line storage bit failed count based on a change in the at least one test data sample between the at least one read operation and the at least one write operation; and sorting addresses of the main word lines such that a related per main word line storage bit failed count is arranged in descending order.

4. The method of claim 3, wherein, generating the sorted replacement failed bit count list includes: performing at least one write operation in which at least one test data sample is written to a replacement storage array; performing at least one read operation in which the at least one test data sample is read from the replacement storage array; determining a per replacement word line storage bit failed count based on a change in the at least one test data sample between the at least one read operation and the at least one write operation; and sorting addresses of the replacement word lines such that a related per replacement word line storage bit failed count is arranged in ascending order.

5. The method of claim 1, wherein: The first redundant fuse element comprises a programmable read-only memory element.

6. The method of claim 1, wherein, Each pair of access lines is configured to access only a single one of the replacement memory cells and is electrically isolated from all other replacement memory cells.

7. The method of claim 1, wherein, The replacement memory cells comprise an array of static random access memory cells comprising respective groups of at least six field effect transistors.

8. The method of claim 1, wherein, The second redundant fuse element is programmed such that: A control circuit connected to the second redundant fuse element re-routes data of each failed memory bit that is replaced by a respective one of the replacement memory cells to the respective one of the replacement memory cells during a programming operation; and The control circuit rewrites data of each failed memory bit that is replaced by a respective one of the replacement memory cells with data read from the respective one of the replacement memory cells during a read operation. The R replacement word lines are located in at least two redundant memory cell regions that are laterally spaced apart from each other or are laterally spaced apart from each other by at least a subset of the M main word lines.

9. The method of claim 1, wherein, The random access memory device comprises a dynamic random access memory device, each memory bit within the memory bank in the dynamic random access memory device comprising a respective series connection of a capacitor structure configured to store a charge of each memory bit and an access transistor configured to control a flow of charge to and from the capacitor structure.

10. The method of claim 1, wherein, 11. A method of manufacturing a random access memory device, comprising: providing a semiconductor device comprising a memory bank comprising M main word lines and R replacement word lines, a row / column decoder, and an array of redundant fuse elements; generating a sorted primary failed bit count list tabulating addresses in the M main word lines and a per word line bit failed count in descending order of per word line bit failed count; generating a sorted replacement failed bit count list tabulating addresses of the R replacement word lines and a per word line bit failed count in ascending order of per word line bit failed count; determining a total replacement count number equal to a minimum of an equal failed count row number and R, the equal failed count row number being a list order number in the sorted primary failed bit count list when a primary failed bit count is equal to a replacement failed bit count in the sorted replacement failed bit count list; generating a reordered primary failed bit count list modified from the sorted primary failed bit count list by reordering a highest subset of the total replacement count number of lists containing the main word lines in ascending address or descending address order; and performing a redundant fuse programming process in which first redundant fuse elements within the array of redundant fuse elements are programmed to logically replace main word lines on the sorted primary failed bit count list with respective word lines having a same list order number in the sorted replacement failed bit count list until the total replacement count number of lists in the reordered primary failed bit count list is replaced. ​ 12. The method of claim 11, wherein, The main word lines on the reordered main failed bit count list are replaced in top-to-bottom order with the corresponding word lines on the reordered replacement failed bit count list having the same list order number.

13. The method of claim 11, wherein: The random access memory device includes replacement storage cells located within a replacement storage bit array, the replacement storage bit array configured for individual access by a corresponding pair of access lines; and The method includes programming a second redundant fuse element within the array of redundant fuse elements such that the programmed second redundant fuse element logically replaces each failed storage bit located within the main storage array region and connected to a corresponding main word line that is not logically replaced by a corresponding replacement word line.

14. The method of claim 11, wherein, The addresses of the set of all replacement word lines that replace a corresponding one of the main word lines increase strictly or decrease strictly from one side of the R replacement word lines to the other.

15. A random access memory device, comprising: a memory bank including a main storage array region and a redundant storage array region, wherein the main storage array region includes M x N main storage cells connected to M main word lines and N bit lines, and the redundant storage array region includes R x N redundant storage cells connected to R replacement word lines and the N bit lines; a first redundant fuse element configured to logically replace each main word line within the main storage array region having more failed storage bits than a threshold number of per word line bit failure counts with a corresponding one of the replacement word lines having a corresponding number of failed bit counts that is not greater than the threshold number of per word line bit failure counts, wherein the threshold number of per word line bit failure counts is a positive integer, wherein the random access memory device includes at least one feature selected from: a first feature in which each replacement word line that does not replace any main word line includes a corresponding number of bit failure counts that is equal to or greater than the threshold number of per word line bit failure counts; and a second feature in which at least one main word line has a corresponding non-zero number of bit failure counts and is not replaced by any one of the replacement word lines, the non-zero number of bit failure counts being equal to or less than the threshold number of per word line bit failure counts; replacement storage cells located within a replacement storage bit array, the replacement storage bit array configured for individual access by a corresponding pair of access lines; and a second redundant fuse element configured to logically replace each failed storage bit located within the main storage array region and connected to a corresponding main word line that is not logically replaced by a corresponding replacement word line with a corresponding one of the replacement storage cells.

16. The random access memory device of claim 15, wherein, The random access memory device includes a dynamic random access memory device.

17. The random access memory device of claim 15, wherein, Each pair of access lines is configured to access only a single one of the replacement storage cells and is electrically isolated from all other replacement storage cells.

18. The random access memory device of claim 15, wherein, The replacement storage cells include an array of static random access memory cells, the static random access memory cells including a corresponding set of at least six field effect transistors.

19. The random access memory device of claim 15, further comprising: a control circuit configured to: during a programming operation, rewire data of each failed storage bit that is replaced by a corresponding one of the replacement storage units to the corresponding one of the replacement storage units; and and overwriting data of each failed storage bit that is replaced by a corresponding one of the replacement storage units with data read from the corresponding one of the replacement storage units during a read operation.

20. The random access memory device of claim 15, wherein, The random access memory device includes at least one feature selected from: a first feature, a set address of all replacement word lines that replace a corresponding one of the main word lines strictly increases or strictly decreases from one side to another side within the R x N redundant storage units; and a second feature, the R x N redundant storage units include at least two redundant storage unit regions that are laterally spaced apart from each other or are laterally spaced apart from each other by at least a subset of the M x N main storage units.

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