An analog content-addressable memory based on multi-level flash transistors

Abstract

The present invention discloses an analog content addressable memory based on multi-level flash memory transistors. Each analog content addressable memory unit stores at least two multi-bit data and can perform range content search of multi-bit input data, that is, to find out whether the input data is within the data range determined by the stored multi-bit data; each analog content addressable memory unit includes at least two multi-level flash memory transistors, and the connection method of the multi-level flash memory transistors can be divided into parallel connection method and series connection method; the analog content addressable memory based on multi-level flash memory transistors can be composed of units connected in parallel method or by units connected in series method, and can perform range content search and content addressing on multiple multi-bit data at the same time. The present invention adopts non-volatile flash memory, which can reduce static power consumption and simplify unit structure; in addition, the innovative application of multi-level flash memory transistors helps to promote the development of storage technology and is of great significance to the performance improvement of memory.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors and integrated circuits, and in particular relates to an analog content addressable memory capable of performing range content search on analog data. Background Art

[0002] At the core of a router, the routing table is a crucial concept. It stores the routing paths determined by the destination IP address in a data packet. The actual packet forwarding process involves searching for addresses based on the packet's content. Numerous traditional search methods exist, including linear search, binary tree search, and hash table search. These methods, all based on software algorithms, suffer from slow speeds and low efficiency. While numerous optimization methods have been developed for these search algorithms, they still struggle to meet the high-speed search requirements of today's high-speed, real-time communication systems.

[0003] Content-addressable memory (CAM) is a high-speed hardware search engine. Its most significant feature is that it can use stored content as keywords for search operations. Specifically, the data to be searched is input. After the search, the CAM returns the address where the data is stored in the CAM, as well as a match signal to indicate whether the search was successful. When searching using this method, all data in the entire table is searched at the same time. The search speed is not affected by the size of the data in the table space. One search is completed per clock cycle, and the average search speed is much faster than that of search methods based on software algorithms. In a general CAM, each cell has only two states ([0] or [1]), while in a ternary CAM, each cell has three states ([0], [1], or [X]). The third state of the ternary CAM enables it to perform both exact match searches and fuzzy match searches, improving efficiency. However, traditional CAM can only be used to search for specific single data, and there is still room for improvement.

[0004] Although content-addressable memory cells and content-addressable memories based on static random access memory (SRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM) and phase-change memory (PCM) have been implemented or proposed, they have many drawbacks, such as (1) complex circuit structure, (2) complex sequential logic, (3) high power consumption and area overhead, (4) interference between adjacent cells and (5) low information storage density. Summary of the Invention

[0005] To address these shortcomings, the present invention aims to implement an analog content-addressable memory (ADCM) cell, distinct from traditional digital DACM cells, by utilizing the switching characteristics of multi-level flash memory transistors capable of storing multiple bits of information in response to input voltage. Furthermore, this cell is used to implement a novel ADCM that improves ADC performance, simplifies the cell structure, reduces area, and lowers costs, thus providing a foundation for the widespread application of hardware addressing in router nodes.

[0006] The purpose of the present invention is achieved through the following technical solutions:

[0007] An analog content addressable memory cell, any one of which comprises at least two multi-level flash memory transistors, at least two input ports, and at least one output port;

[0008] The gates of the multi-level flash memory transistors are respectively connected to the input ports;

[0009] The drains of all the multi-level flash memory transistors are connected and then connected to the output port, and the sources of all the multi-level flash memory transistors are connected and then grounded. This situation is called a parallel connection method;

[0010] Alternatively, the drain of the multi-level flash memory transistor is connected to the source of an adjacent multi-level flash memory transistor, the unconnected drain is connected to the first type of the output port, and the unconnected source is connected to the second type of the output port. This is called a series connection method.

[0011] Any one of the units stores at least two multi-bit data, and can simultaneously perform size comparison between the at least two multi-bit data and the unit input data;

[0012] When the size comparison between all multi-bit data and unit input data is established, it is recorded as event 1; when the size comparison between at least one multi-bit data and unit input data is not established, it is recorded as event 2. The output ports of the units corresponding to event 1 and event 2 exhibit different electrical characteristics; by comparing the multi-bit data and the unit input data, the unit input data can be searched for range content to determine whether the unit input data is within the data range determined by the stored multi-bit data.

[0013] Furthermore, the threshold voltage of the multi-level flash memory transistor can be changed from 4 levels to 256 levels, that is, the multi-level flash memory transistor can store quantized 2-bit to 8-bit data.

[0014] Furthermore, each analog content addressable memory cell stores data within a range; the data stored in the multi-level flash memory transistor is represented by the threshold voltage of the multi-level flash memory transistor, which determines the upper and lower limits of the data range stored in the analog content addressable memory cell. The upper limit data stored in the analog content addressable memory cell undergoes a conversion, and the converted data is positively correlated with the size of the upper limit data, and is then stored in the multi-level flash memory transistor that stores the upper limit of the data range in a parallel connection method; or the converted data is negatively correlated with the size of the upper limit data, and is then stored in the multi-level flash memory transistor that stores the upper limit of the data range in a series connection method; the lower limit data stored in the analog content addressable memory cell undergoes a conversion, and the converted data is negatively correlated with the size of the lower limit data, and is then stored in the multi-level flash memory transistor that stores the lower limit of the data range in a parallel connection method; or the converted data is positively correlated with the size of the lower limit data, and is then stored in the multi-level flash memory transistor that stores the lower limit of the data range in a series connection method.

[0015] Furthermore, the input of the analog content addressable storage unit is a plurality of analog voltage signals derived from a single analog signal, which are applied to a plurality of input ports respectively; some of the derived analog voltage signals are positively correlated with the magnitude of the input analog signal, and are applied to the input ports corresponding to the multi-level flash memory transistors storing the upper limit of the data range in the parallel connection method, or are applied to the input ports corresponding to the multi-level flash memory transistors storing the lower limit of the data range in the series connection method; other derived analog voltage signals are negatively correlated with the magnitude of the input analog signal, and are applied to the input ports corresponding to the multi-level flash memory transistors storing the lower limit of the data range in the parallel connection method, or are applied to the input ports corresponding to the multi-level flash memory transistors storing the upper limit of the data range in the series connection method.

[0016] Furthermore, the unit of the parallel connection method works as follows: when the positive correlation derived analog voltage signal is greater than the threshold voltage of the multi-level flash memory transistor at the upper limit of the storage data range, that is, when the input data is greater than the upper limit of the storage data range, the multi-level flash memory transistor is turned on and the output port is pulled down to ground, representing a mismatch state result; when the negative correlation derived analog voltage signal is greater than the threshold voltage of the multi-level flash memory transistor at the lower limit of the storage data range, that is, when the input data is less than the lower limit of the storage data range, the multi-level flash memory transistor is turned on and the output port is pulled down to ground, representing a mismatch state result; only when the positive correlation derived analog voltage signal is less than the threshold voltage of the multi-level flash memory transistor at the upper limit of the storage data range and the negative correlation derived analog voltage signal is less than the threshold voltage of the multi-level flash memory transistor at the lower limit of the storage data range, that is, when the input data is less than the upper limit of the storage data range and greater than the lower limit of the storage data range, all multi-level flash memory transistors are turned off and the output port voltage is maintained, representing a matching state result.

[0017] Furthermore, the unit of the series connection method works as follows: when the positive correlation derived analog voltage signal is less than the threshold voltage of the multi-level flash memory transistor at the lower limit of the storage data range, that is, when the input data is less than the lower limit of the storage data range, the multi-level flash memory transistor is turned off, and the first type output port and the second type output port are disconnected, representing a mismatch state result; when the negative correlation derived analog voltage signal is less than the threshold voltage of the multi-level flash memory transistor at the upper limit of the storage data range, that is, when the input data is greater than the upper limit of the storage data range, the multi-level flash memory transistor is turned off, and the first type output port and the second type output port are disconnected, representing a mismatch state result; only when the positive correlation derived analog voltage signal is greater than the threshold voltage of the multi-level flash memory transistor at the lower limit of the storage data range and the negative correlation derived analog voltage signal is greater than the threshold voltage of the multi-level flash memory transistor at the upper limit of the storage data range, that is, when the input data is less than the upper limit of the storage data range and greater than the lower limit of the storage data range, all the multi-level flash memory transistors are turned on, and the first type output port and the second type output port are connected, representing a match state result.

[0018] An analog content addressable memory based on multi-level flash memory transistors, the analog content addressable memory comprising a plurality of analog content addressable memory cells as described above arranged in an array; the analog content addressable memory cells having storage, read, write and comparison functions; the multi-level flash memory transistors of all memory cells of the memory are connected in parallel; the corresponding input ports of all the memory cells in the same column are connected to the same signal search line; and the output ports of all the memory cells in the same row are connected to the same match line.

[0019] Before the search begins, the match line needs to be precharged to a level corresponding to logic [1]. During the search process, when the cell storage data is consistent with the search signal, the output is a match state. Only when all storage cells on the same match line are in a match state, the match line outputs the precharge result [1], indicating that the row is matched. When the storage cell storage data is inconsistent with the search signal, the output is a mismatch state. When any one or more storage cells on the same match line are in a mismatch state, the match line outputs [0], indicating that the row is mismatched.

[0020] Another analog content addressable memory based on multi-level flash memory transistors is composed of a plurality of analog content addressable memory cells as described above arranged in an array; the analog content addressable memory cells have storage, read, write and comparison functions; the multi-level flash memory transistors of all memory cells of the memory are connected in series; the corresponding input ports of all the memory cells in the same column are connected to the same signal search line; the first type output ports and the second type output ports of all the memory cells in the same row are connected in sequence, the unconnected first type output ports are connected to the matching line, and the unconnected second type output ports are grounded.

[0021] Before the search begins, the match line needs to be precharged to a level corresponding to logic [1]. During the search, when the cell storage data is consistent with the search signal, the output is a match state. Only when all storage cells on the same match line are in a match state, the match line outputs [0], indicating that the row is matched. When the storage cell storage data is inconsistent with the search signal, the output is a mismatch state. When any one or more storage cells on the same match line are in a mismatch state, the match line outputs the precharged result [1], indicating that the row is mismatched.

[0022] The beneficial effects of the present invention are as follows: the present invention adopts non-volatile memory technology, which can reduce static power consumption and simplify the unit structure, which is of great help to improve the power consumption performance of data-intensive applications and greatly improves the router search efficiency at key nodes of the network; the present invention simulates the content-addressable memory unit with multi-bit data storage capacity, which can effectively improve the storage density, significantly reduce the chip area, and reduce the circuit layout cost; the present invention is different from other basic principles for implementing content-addressable memory, mainly in that the stored data and the search data are both multi-bit data in the near-analog domain, and data range content search can be performed, which is of great significance to the development of non-volatile storage technology and content-addressable memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1a Parallel connection method of analog content addressable storage unit;

[0024] Figure 1b Simulate the serial connection of content addressable storage units;

[0025] Figure 2 Positive and negative correlation conversion mode of input voltage and upper and lower limit data;

[0026] Figure 3a Matching of parallel connection units;

[0027] Figure 3b Mismatch of parallel connection units;

[0028] Figure 3c Matching of series connected units;

[0029] Figure 3d Mismatch of series-connected units;

[0030] Figure 4 A schematic diagram of the structure of an emulated content addressable memory based on an emulated content addressable memory unit;

[0031] Figure 5a The connection method when the parallel connection method units form an array;

[0032] Figure 5b The connection method when series connection units form an array. DETAILED DESCRIPTION

[0033] The following describes some of the multiple possible embodiments of the present invention, which are intended to provide a basic understanding of the present invention and are not intended to identify the key or decisive elements of the present invention or to limit the scope of protection. It is easy to understand that according to the technical solution of the present invention, without changing the essential spirit of the present invention, a person of ordinary skill in the art can propose other mutually interchangeable implementations. Therefore, the following specific embodiments and the accompanying drawings are only exemplary descriptions of the technical solution of the present invention and should not be regarded as the entirety of the present invention or as a definition or limitation of the technical solution of the present invention.

[0034] Each analog content addressable memory cell comprises at least two multi-level flash memory transistors, at least two input ports, and at least one output port; the gates of the multi-level flash memory transistors are respectively connected to the input ports;

[0035] The drains of all the multi-level flash memory transistors are connected and then connected to the output port, and the sources of all the multi-level flash memory transistors are connected and then grounded. This situation is called a parallel connection method ( Figure 1a );

[0036] The drain of the multi-level flash memory transistor is connected to the source of the adjacent multi-level flash memory transistor, the unconnected drain is connected to the first type of the output port, and the unconnected source is connected to the second type of the output port. This situation is called a series connection method ( Figure 1b ).

[0037] Any one of the units stores at least two multi-bit data and can simultaneously perform size comparison between the at least two multi-bit data and the unit input data;

[0038] When the size comparison between all multi-bit data and unit input data is valid, and when the size comparison between at least one multi-bit data and unit input data is invalid, the output port of the unit exhibits different electrical characteristics; through the comparison between the multi-bit data and the unit input data, the unit input data can be searched for range content to determine whether the unit input data is within the data range determined by the stored multi-bit data.

[0039] Figure 2 It is the positive correlation and negative correlation conversion method of input data.

[0040] Each analog content addressable memory cell stores data within a range; the data stored in the multi-level flash memory transistor is represented by the threshold voltage of the multi-level flash memory transistor, which determines the upper and lower limits of the data range stored in the analog content addressable memory cell. The upper limit data stored in the analog content addressable memory cell undergoes a conversion, and the converted data is positively correlated with the size of the upper limit data, and is then stored in the multi-level flash memory transistor that stores the upper limit of the data range in a parallel connection method; or the converted data is negatively correlated with the size of the upper limit data, and is then stored in the multi-level flash memory transistor that stores the upper limit of the data range in a series connection method; the lower limit data stored in the analog content addressable memory cell undergoes a conversion, and the converted data is negatively correlated with the size of the lower limit data, and is then stored in the multi-level flash memory transistor that stores the lower limit of the data range in a parallel connection method; or the converted data is positively correlated with the size of the lower limit data, and is then stored in the multi-level flash memory transistor that stores the lower limit of the data range in a series connection method.

[0041] The input of the analog content addressable storage unit is a plurality of analog voltage signals derived from a single analog signal, which are applied to a plurality of input ports respectively; some of the derived analog voltage signals are positively correlated with the magnitude of the input analog signal, and are applied to the input ports corresponding to the multi-level flash memory transistors storing the upper limit of the data range in the parallel connection method, or are applied to the input ports corresponding to the multi-level flash memory transistors storing the lower limit of the data range in the series connection method; other derived analog voltage signals are negatively correlated with the magnitude of the input analog signal, and are applied to the input ports corresponding to the multi-level flash memory transistors storing the lower limit of the data range in the parallel connection method, or are applied to the input ports corresponding to the multi-level flash memory transistors storing the upper limit of the data range in the series connection method.

[0042] Figure 3a is the matching status of the parallel connection method unit, Figure 3b is the mismatch state of the parallel connection method unit, Figure 3c is the matching status of the series connection unit, Figure 3d It is the mismatch state of the series connected unit.

[0043] The unit of the parallel connection method works as follows: when the positive correlation derived analog voltage signal is greater than the threshold voltage of the multi-level flash memory transistor at the upper limit of the storage data range, that is, when the input data is greater than the upper limit of the storage data range, the multi-level flash memory transistor is turned on and the output port is pulled down to ground, representing a mismatch state result (not shown); when the negative correlation derived analog voltage signal is greater than the threshold voltage of the multi-level flash memory transistor at the lower limit of the storage data range, that is, when the input data is less than the lower limit of the storage data range, the multi-level flash memory transistor is turned on and the output port is pulled down to ground, representing a mismatch state result ( Figure 3b); Only when the positive correlation derived analog voltage signal is less than the threshold voltage of the multi-level flash memory transistor at the upper limit of the storage data range, and the negative correlation derived analog voltage signal is less than the threshold voltage of the multi-level flash memory transistor at the lower limit of the storage data range, that is, when the input data is less than the upper limit of the storage data range and greater than the lower limit of the storage data range, all the multi-level flash memory transistors are turned off and the output port voltage is maintained, representing the matching state result ( Figure 3a ).

[0044] The unit of the series connection method works as follows: when the positive correlation derived analog voltage signal is less than the threshold voltage of the multi-level flash memory transistor at the lower limit of the storage data range, that is, when the input data is less than the lower limit of the storage data range, the multi-level flash memory transistor is turned off, and the first type output port and the second type output port are cut off, representing a mismatch state result ( Figure 3d ); when the negative correlation derived analog voltage signal is less than the threshold voltage of the multi-level flash memory transistor at the upper limit of the storage data range, that is, when the input data is greater than the upper limit of the storage data range, the multi-level flash memory transistor is turned off, and the first type output port and the second type output port are disconnected, representing a mismatch state result (not shown); only when the positive correlation derived analog voltage signal is greater than the threshold voltage of the multi-level flash memory transistor at the lower limit of the storage data range, and the negative correlation derived analog voltage signal is greater than the threshold voltage of the multi-level flash memory transistor at the upper limit of the storage data range, that is, when the input data is less than the upper limit of the storage data range and greater than the lower limit of the storage data range, all the multi-level flash memory transistors are turned on, and the first type output port and the second type output port are connected, representing a matching state result ( Figure 3c ).

[0045] Figure 4 The present invention is a schematic diagram of the structure of an analog content addressable memory based on analog content addressable memory cells. The analog content addressable memory is composed of the aforementioned analog content addressable memory cells arranged in an array; the analog content addressable memory cells have storage, read, write, and comparison functions; the multi-level flash memory transistors of all memory cells of the memory are connected in parallel; the corresponding input ports of all the memory cells in the same column are connected to the same signal search line; the output ports of all the memory cells in the same row are connected to the same match line ( Figure 4 Alternatively, the multi-level flash memory transistors of all the memory cells of the memory are connected in series; the corresponding input ports of all the memory cells in the same column are connected to the same signal search line; the first-type output ports and the second-type output ports of all the memory cells in the same row are connected in sequence, the unconnected first-type output ports are connected to the matching line, and the unconnected second-type output ports are grounded (not shown).

[0046] Figure 5aThis is the working mode when all the multi-level flash memory transistors of the memory cells of the analog content addressable memory are connected in parallel. Before the search operation begins, the match line needs to be precharged to the level corresponding to logic [1]. During the search process, when the cell storage data is consistent with the search signal, the output is a matching state. Only when all the memory cells on the same match line are in a matching state, the match line outputs the precharged result [1], indicating that the row is matched. When the storage cell storage data is inconsistent with the search signal, the output is a mismatch state. When any one or more memory cells on the same match line are in a mismatch state, the match line outputs [0], indicating that the row is mismatched.

[0047] Figure 5b This is the working mode when all the multi-level flash memory transistors of the memory cells of the analog content addressable memory are connected in series. Before the search operation begins, the match line needs to be precharged to the level corresponding to logic [1]. During the search process, when the cell storage data is consistent with the search signal, the output is a matching state. Only when all the memory cells on the same match line are in a matching state, the match line outputs [0], indicating that the row is matched. When the storage cell storage data is inconsistent with the search signal, the output is a mismatch state. When any one or more memory cells on the same match line are in a mismatch state, the match line outputs the precharged result [1], indicating that the row is mismatched.

[0048] The above description is only a preferred embodiment of the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present invention without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. An analog content addressable storage unit, characterized in that Any of the units: comprising at least two multi-level flash memory transistors, at least two input ports, and at least one output port; The gates of the multi-level flash memory transistors are respectively connected to the input ports; The drains of all the multi-level flash memory transistors are connected and then connected to the output port, and the sources of all the multi-level flash memory transistors are connected and then grounded. This situation is called a parallel connection method; Alternatively, the drain of the multi-level flash memory transistor is connected to the source of an adjacent multi-level flash memory transistor, the unconnected drain is connected to the first type of the output port, and the unconnected source is connected to the second type of the output port. This is called a series connection method. Any one of the units stores at least two multi-bit data and can simultaneously perform size comparison between the at least two multi-bit data and the unit input data; When the size comparison between all the multi-bit data and the unit input data is satisfied, and when the size comparison between at least one of the multi-bit data and the unit input data is not satisfied, the output port of the unit exhibits different electrical characteristics; by comparing the multi-bit data with the unit input data, a range content search can be performed on the unit input data to determine whether the unit input data is within a data range determined by the stored multi-bit data; Each analog content addressable memory cell stores data within a range; the data stored in the multi-level flash memory transistor is represented by the threshold voltage of the multi-level flash memory transistor, which determines the upper and lower limits of the data range stored in the analog content addressable memory cell; The upper limit data stored in the analog content addressable memory cell undergoes a conversion, and the converted data is positively correlated with the size of the upper limit data, and is then stored in a multi-level flash memory transistor that stores the upper limit of the data range in a parallel connection method; Alternatively, after one conversion, the converted data is negatively correlated with the size of the upper limit data, and is then stored in a multi-level flash memory transistor connected in series to store the upper limit of the data range; The lower limit data stored in the analog content addressable memory cell undergoes a conversion, and the converted data is negatively correlated with the size of the lower limit data, and is then stored in the multi-level flash memory transistor that stores the lower limit of the data range in the parallel connection method; Alternatively, after one conversion, the converted data is positively correlated with the size of the lower limit data, and is then stored in a multi-level flash memory transistor in a series connection that stores the lower limit of the data range.

2. The analog content addressable storage unit according to claim 1, wherein: The threshold voltage of the multi-level flash memory transistor varies from 4 levels to 256 levels, that is, the multi-level flash memory transistor stores quantized 2-bit to 8-bit data.

3. The analog content addressable storage unit according to claim 1, wherein: The input of the analog content addressable memory unit is a plurality of analog voltage signals derived from a single analog signal, which are applied to a plurality of input ports respectively; Some of the derived analog voltage signals are positively correlated with the magnitude of the input analog signal and are applied to input ports corresponding to the multi-level flash memory transistors storing the upper limit of the data range in the parallel connection method, or to input ports corresponding to the multi-level flash memory transistors storing the lower limit of the data range in the series connection method; Other derived analog voltage signals are negatively correlated with the magnitude of the input analog signal, and are applied to the input ports corresponding to the multi-level flash memory transistors storing the lower limit of the data range in the parallel connection method, or to the input ports corresponding to the multi-level flash memory transistors storing the upper limit of the data range in the series connection method.

4. The analog content addressable storage unit according to claim 3, wherein: The unit of the parallel connection method works as follows: When the positive correlation derived analog voltage signal is greater than the threshold voltage of the multi-level flash memory transistor at the upper limit of the storage data range, that is, when the input data is greater than the upper limit of the storage data range, the multi-level flash memory transistor is turned on and the output port is pulled down to the ground, representing a mismatch state result; When the negatively correlated derived analog voltage signal is greater than the threshold voltage of the multi-level flash memory transistor at the lower limit of the storage data range, that is, when the input data is less than the lower limit of the storage data range, the multi-level flash memory transistor is turned on and the output port is pulled down to the ground, representing a mismatch state result; Only when the positive correlation derived analog voltage signal is less than the threshold voltage of the multi-level flash memory transistor at the upper limit of the storage data range, and the negative correlation derived analog voltage signal is less than the threshold voltage of the multi-level flash memory transistor at the lower limit of the storage data range, that is, when the input data is less than the upper limit of the storage data range and greater than the lower limit of the storage data range, all multi-level flash memory transistors are turned off and the output port voltage is maintained, representing the matching state result.

5. The analog content addressable storage unit according to claim 3, wherein: The units connected in series work as follows: When the positive correlation derived analog voltage signal is smaller than the threshold voltage of the multi-level flash memory transistor at the lower limit of the storage data range, that is, when the input data is smaller than the lower limit of the storage data range, the multi-level flash memory transistor is turned off, and the first type of output port and the second type of output port are disconnected, representing a mismatch state result; When the negatively correlated derived analog voltage signal is less than the threshold voltage of the multi-level flash memory transistor at the upper limit of the storage data range, that is, when the input data is greater than the upper limit of the storage data range, the multi-level flash memory transistor is turned off, and the first type of output port and the second type of output port are disconnected, representing a mismatch state result; Only when the positive correlation derived analog voltage signal is greater than the threshold voltage of the multi-level flash memory transistor at the lower limit of the storage data range, and the negative correlation derived analog voltage signal is greater than the threshold voltage of the multi-level flash memory transistor at the upper limit of the storage data range, that is, when the input data is less than the upper limit of the storage data range and greater than the lower limit of the storage data range, all multi-level flash memory transistors are turned on, and the first type output port and the second type output port are connected, representing a matching state result.

6. An analog content addressable memory based on multi-level flash memory transistors, characterized in that: The analog content addressable memory is composed of a plurality of analog content addressable memory cells according to any one of claims 1 to 5 arranged in an array; the analog content addressable memory cells have storage, reading, writing and comparison functions; the multi-level flash memory transistors of all the memory cells of the memory are connected in parallel; The corresponding input ports of all the storage units in the same column are connected to the same signal search line; Output ports of all the memory cells in the same row are connected to the same match line.

7. The analog content addressable memory according to claim 6, wherein: Before the search begins, the match line needs to be precharged to the level corresponding to logic [1]; During the search process, when the cell storage data is consistent with the search signal, the output is a match state. Only when all the storage cells on the same match line are in a match state, the match line outputs the precharge result [1], which means that the row is matched; when the storage cell storage data is inconsistent with the search signal, the output is a mismatch state. When any one or more storage cells on the same match line are in a mismatch state, the match line outputs [0], which means that the row is mismatched.

8. An analog content addressable memory based on multi-level flash memory transistors, characterized in that: The analog content addressable memory is composed of a plurality of analog content addressable memory cells according to any one of claims 1 to 5 arranged in an array; the analog content addressable memory cells have storage, reading, writing and comparison functions; the multi-level flash memory transistors of all the memory cells of the memory are connected in series; The corresponding input ports of all the storage units in the same column are connected to the same signal search line; The first type output ports and the second type output ports of all the memory cells in the same row are connected in sequence, the unconnected first type output ports are connected to the matching line, and the unconnected second type output ports are grounded.

9. The analog content addressable memory according to claim 8, wherein: Before the search begins, the match line needs to be precharged to the level corresponding to logic [1]; During the search process, when the cell storage data is consistent with the search signal, the output is a match state. Only when all storage cells on the same match line are in a match state, the match line outputs [0], indicating that the row is matched; when the storage cell storage data is inconsistent with the search signal, the output is a mismatch state. When any one or more storage cells on the same match line are in a mismatch state, the match line outputs the pre-charge result [1], indicating that the row is mismatched.

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