Memory device and method of operation thereof

Abstract

A memory device and an operating method thereof include a plurality of pages, a peripheral circuit, and control logic. The peripheral circuit is configured to receive a command, an address, and data from an external controller to program a page selected from the plurality of pages, and to generate internal input data according to an input pattern for the command, the address, and the data. The control logic is configured to determine whether to generate the internal input data based on the data according to the input pattern, and to control the peripheral circuit such that a program operation to program the internal input data is performed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0138382, filed on October 23, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure generally relate to electronic devices, and more specifically, to memory devices and methods of operating memory devices. Background Technology

[0004] A storage device is a device that stores data under the control of a host device such as a computer, smartphone, or smart tablet. Examples of storage devices, depending on the type of data stored, include devices that store data on disks (such as hard disk drives (HDDs)) and devices that store data in semiconductor memory, particularly non-volatile memory (such as solid-state drives (SSDs) or memory cards).

[0005] Storage devices can include memory devices that store data and memory controllers that control the storage of data within the memory devices. Such memory devices can be classified as volatile memory devices or non-volatile memory devices. Representative examples of non-volatile memory include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Summary of the Invention

[0006] Various embodiments of this disclosure relate to memory devices and methods of operating memory devices that increase data input speed when only some of a large number of input / output lines are used to input data.

[0007] According to one embodiment of this disclosure, the memory device includes a plurality of pages, peripheral circuitry, and control logic. The peripheral circuitry is configured to receive commands, addresses, and data from an external controller to program pages selected from the plurality of pages, and to generate internal input data based on an input pattern used for the commands, addresses, and data. The control logic is configured to determine whether to generate internal input data based on the input pattern, and to control the peripheral circuitry such that a programming operation for programming the internal input data is executed.

[0008] According to another embodiment of this disclosure, the memory device includes a plurality of pages, a mode setter, an input controller, and a control signal generator. The mode setter is configured to set a mode in which it receives commands, addresses, and data from an external controller to program pages selected from the plurality of pages. The input controller is configured to generate internal input data based on the mode set by the mode setter, and the control signal generator is configured to generate control signals for controlling the input controller to generate the internal input data.

[0009] According to an additional embodiment of this disclosure, there is a method of operating a memory device. The method includes: setting a mode in which commands, addresses, and data are received from an external controller to program pages selected from a plurality of pages. The method further includes: receiving data based on the set mode; generating control signals according to the set mode to generate internal input data based on the data; and generating the internal input data based on the control signals. Attached Figure Description

[0010] Figure 1 It is a block diagram illustrating a storage device.

[0011] Figure 2 It's a diagram. Figure 1 A diagram of the structure of a memory device.

[0012] Figure 3 It's a diagram. Figure 2 A diagram of one embodiment of a memory cell array.

[0013] Figure 4 It is used to describe Figure 1 A diagram showing the pin configuration of a memory device.

[0014] Figure 5 This is a diagram illustrating one embodiment in which the memory device and the test device are coupled to each other during a test operation.

[0015] Figure 6 This is a diagram illustrating one embodiment in which a memory device is coupled to a test device during a test operation.

[0016] Figure 7 The illustration shows that Figure 6 The method of inputting data into multiple dies during the test operation.

[0017] Figure 8 It is a timing diagram illustrating the process of inputting commands, addresses, and data in X8 mode.

[0018] Figure 9 It is a timing diagram illustrating the process of data being input in X8 mode.

[0019] Figure 10 The diagram illustrates a method to reduce data input time in X4 mode.

[0020] Figures 11A to 11C The diagram illustrates how data is input in X4 and X8 modes.

[0021] Figure 12 The diagram illustrates the control signals required for data input in X4 mode and the generated internal input data.

[0022] Figure 13 The diagram illustrates the process of generating Figure 12 Configuration of the control signal generator for fast mode signals.

[0023] Figure 14 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0024] Figure 15 It's a diagram. Figure 1 A diagram of one embodiment of a memory controller.

[0025] Figure 16 This is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present disclosure.

[0026] Figure 17 This is a block diagram illustrating a solid-state drive (SSD) system using a storage device according to an embodiment of the present disclosure.

[0027] Figure 18 This is a block diagram illustrating a user system using a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0028] Specific structural or functional descriptions of embodiments of this disclosure, incorporated herein by reference, are for illustrative purposes only. These descriptions should not be construed as limiting the scope to the embodiments described in the specification or application.

[0029] Various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments of the present disclosure are illustrated, so that those skilled in the art can implement the technical concept of the present disclosure.

[0030] Figure 1 It is a block diagram illustrating a storage device.

[0031] refer to Figure 1 The storage device 50 may include the memory device 100 and the memory controller 200.

[0032] Storage device 50 may be a device that stores data under the control of host 300, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television (TV), tablet PC, or in-vehicle infotainment system.

[0033] Depending on the host interface used for communication with host 300, storage device 50 can be manufactured as any of various types of storage devices. For example, storage device 50 can be implemented as any of various types of storage devices, such as solid-state drives (SSDs); multimedia cards such as MMC, embedded MMC (eMMC), small form factor MMC (RS-MMC), or micro-MMC; secure digital cards such as SD, mini-SD, or micro-SD; universal serial bus (USB) storage devices; universal flash memory (UFS) devices; PCMCIA (Personal Computer Memory Card International Association) card type storage devices; peripheral component interconnect (PCI) card type storage devices; PCI Express (PCI-E) card type storage devices; compact flash (CF) cards; smart media cards; and Memory Stick.

[0034] Storage device 50 can be manufactured in any of a variety of package types. For example, storage device 50 can be manufactured as a stacked package (POP), system-in-package (SIP), system-on-a-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), or wafer-level stacked package (WSP).

[0035] Memory device 100 can store data. Memory device 100 is operated in response to control by memory controller 200. Memory device 100 may include a memory cell array, which includes a plurality of memory cells for storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells that can form a plurality of pages. In one embodiment, each page may be a unit for storing data in memory device 100 or retrieving data stored in memory device 100. A memory block may be a unit for erasing data.

[0036] In one embodiment, the memory device 100 may take many alternative forms, such as including Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory devices, Resistive RAM (RRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). For ease of description, it is assumed in this specification that the memory device 100 includes NAND flash memory.

[0037] The memory device 100 can be implemented as a two-dimensional (2D) array structure or a three-dimensional (3D) array structure. Although a 3D array structure is described below as an example, this disclosure is not limited to 3D array structures. This disclosure can be applied not only to flash memory devices in which the charge storage layer is formed by conductive floating gates (FGs), but also to charge trap flash memory (CTF) devices in which the charge storage layer is formed by an insulating layer.

[0038] In one embodiment, the memory device 100 may operate as a single-level cell (SLC) in which one data bit is stored in a memory cell. Alternatively, the memory device 100 may operate as a multi-level cell (MLC) in which two data bits are stored in a memory cell, a three-level cell (TLC) in which three data bits are stored in a memory cell, or a four-level cell (QLC) in which four data bits are stored in a memory cell.

[0039] Memory device 100 can receive commands and addresses from memory controller 200 and can access address-selected regions of the memory cell array. That is, memory device 100 can perform operations corresponding to commands on address-selected regions. For example, memory device 100 can perform write operations (i.e., programming operations), read operations, or erase operations in response to received commands. When a programming command is received, memory device 100 can program data into the address-selected region. When a read command is received, memory device 100 can read data from the address-selected region. When an erase command is received, memory device 100 can erase the data stored in the address-selected region.

[0040] In one embodiment, memory device 100 may include a mode setter 150. Mode setter 150 may set an input / output mode to use all or some of the input / output lines coupled to memory device 100.

[0041] Specifically, when all input / output lines coupled to memory device 100 are used to input / output data, the input / output mode can be X8 mode. However, when half of the input / output lines coupled to memory device 100 are used to input / output data, the input / output mode can be X4 mode. Therefore, mode setter 150 can set either X4 mode or X8 mode based on the number of lines determined for input / output of data by memory device 100.

[0042] The mode setter 150 can generate a high-state line enable signal TM_X4_MODE to set either X4 or X8 mode. For example, when the line enable signal TM_X4_MODE transitions from low to high, the memory device 100 can input / output data in X4 mode. As used herein, signals with a high state (such as the line enable signal TM_X4_MODE) are distinguished from signals with a low state. The high and low states can represent different logical states. For example, a high state can correspond to a signal with a first voltage, and a low state can correspond to a signal with a second voltage. In some embodiments, the first voltage is greater than the second voltage. In other embodiments, different characteristics of the signal (such as frequency or amplitude) determine whether the signal is in a high or low state. In some cases, the high and low states of the signal represent logical binary states.

[0043] In one embodiment, when a test operation is performed on the memory device 100, the mode setter 150 can configure the input / output lines to couple the memory device 100 to the test apparatus (test equipment). Therefore, during a test operation, the mode setter 150 can set the input / output mode of the memory device 100 to either X4 mode or X8 mode.

[0044] In one embodiment, memory device 100 may include an input controller 170. When data is input using only some of the input / output lines coupled to memory device 100, input controller 170 may generate new data based on the input data.

[0045] The time required for data input can be reduced by inputting new data into the memory device 100, which is generated by the input controller 170 based on data received through some lines. That is, compared to inputting data through all lines, inputting data through some lines may take a lot of time, but such data input time can be reduced by the input controller 170 through data control.

[0046] In one embodiment, the control signal generator 190 can generate a control signal for controlling the input controller 170 to generate new data based on data received through some input / output lines. Here, the control signal generator 190 can generate a fast mode signal X4_FASTLOAD or a normal mode signal X4_CURRENT.

[0047] In detail, when the control signal generator 190 generates the fast mode signal X4_FASTLOAD and outputs it to the input controller 170, the input controller 170 can generate new data based on the data received through some lines. However, when the control signal generator 190 generates the normal mode signal X4_CURRENT and outputs it to the input controller 170, the input controller 170 can output the data received through all lines without making any changes.

[0048] The memory controller 200 can control the overall operation of the storage device 50.

[0049] When a power supply voltage is applied to the storage device 50, the memory controller 200 can run firmware. When the storage device 100 is a flash memory device 100, the memory controller 200 can run firmware such as a flash translation layer (FTL) to control communication between the host 300 and the storage device 100.

[0050] In one embodiment, the memory controller 200 may include firmware (not shown) that can receive data and logical block addresses (LBAs) from the host 300 and can translate the LBAs into physical block addresses (PBAs), the PBAs indicating the addresses of memory cells included in the memory device 100 where data is to be stored. Furthermore, the memory controller 200 may store a logical-physical address mapping table in a buffer memory that configures the mapping relationship between logical block addresses (LBAs) and physical block addresses (PBAs).

[0051] The memory controller 200 can control the memory device 100, causing programming, reading, or erasing operations to be executed in response to requests received from the host 300. For example, when a programming request is received from the host 300, the memory controller 200 can translate the programming request into a programming command and provide the programming command, physical block address (PBA), and data to the memory device 100. When a read request and a logical block address are received from the host 300, the memory controller 200 can translate the read request into a read command, select the physical block address corresponding to the logical block address, and then provide the read command and the physical block address (PBA) to the memory device 100. When an erase request and a logical block address are received from the host 300, the memory controller 200 can translate the erase request into an erase command, select the physical block address corresponding to the logical block address, and then provide the erase command and the physical block address (PBA) to the memory device 100.

[0052] In one embodiment, the memory controller 200 can autonomously generate programming commands, addresses, and data without receiving a request from the host 300, and can transmit them to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 to perform background operations, such as programming operations for wear leveling and programming operations for garbage collection.

[0053] In one embodiment, storage device 50 may include a buffer memory (not shown). Memory controller 200 may control data exchange between host 300 and the buffer memory (not shown). Alternatively, memory controller 200 may temporarily store system data used to control storage device 100 in the buffer memory. For example, memory controller 200 may temporarily store data input from host 300 in the buffer memory, and then transfer the temporarily stored data in the buffer memory to storage device 100.

[0054] In various embodiments, the buffer memory can be used as the working memory or cache memory of the memory controller 200. The buffer memory can store code or commands executed by the memory controller 200. Alternatively, the buffer memory can store data processed by the memory controller 200.

[0055] In one embodiment, the buffer memory can be implemented as DRAM or static RAM (SRAM), such as Double Data Rate SDRAM (DDR SDRAM), Double Data Rate Generation 4 (DDR4) SDRAM, Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, or Rambus DRAM (RDRAM).

[0056] In various embodiments, a buffer memory may be coupled to the storage device 50 externally. In this case, a volatile memory device coupled to the outside of the storage device 50 can be used as a buffer memory.

[0057] In one embodiment, the memory controller 200 can control at least two memory devices. In this case, the memory controller 200 can control the memory devices according to an interleaving scheme to improve operational performance.

[0058] The host 300 can communicate with the storage device 50 using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Fast (PCIe), Non-Volatile Memory Fast (NVMe), Universal Flash (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM) communication methods.

[0059] Figure 2 It's a diagram. Figure 1 A diagram showing the structure of the memory device 100.

[0060] refer to Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0061] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are coupled to row decoder 121 via row lines RL. Each memory block in BLK1 to BLKz can be coupled to page buffer group 123 via bit lines BL1 to BLn. Each memory block in BLK1 to BLKz may include multiple memory cells. In one embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells coupled to the same word line can be defined as a single page. Therefore, a single memory block may include multiple pages.

[0062] A row line RL may include at least one source select line, multiple word lines, and at least one drain select line.

[0063] Each memory cell in the memory cell array 110 can be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0064] The peripheral circuit 120 can perform programming, reading, or erasing operations on selected regions of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 can drive the memory cell array 110. For example, under the control of the control logic 130, the peripheral circuit 120 can apply various operating voltages to the row lines RL and bit lines BL1 to BLn or discharge the applied voltages.

[0065] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126.

[0066] The row decoder 121 is coupled to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, multiple word lines, and at least one drain select line. In one embodiment, the word lines may include ordinary word lines and dummy word lines. In another embodiment, the row lines RL may further include pipe select lines.

[0067] The row decoder 121 can decode the row address RADD received from the control logic 130. The row decoder 121 selects at least one memory block from BLK1 to BLKz based on the decoded address. In addition, the row decoder 121 can select at least one word line WL of the selected memory block, such that the voltage generated by the voltage generator 122 is applied to at least one word line WL according to the decoded address.

[0068] For example, during a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage with a lower level than the programming voltage to the unselected word line. During a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage with a higher level than the verification voltage to the unselected word line. During a reading operation, the line decoder 121 can apply a read voltage to the selected word line and a read pass voltage with a higher level than the read voltage to the unselected word line.

[0069] In one embodiment, the erase operation of memory device 100 is performed based on memory blocks. During the erase operation, row decoder 121 can select a memory block based on the decoded address. During the erase operation, row decoder 121 can apply a ground voltage to the word line coupled to the selected memory block.

[0070] Voltage generator 122 can operate under the control of control logic 130. Voltage generator 122 can generate multiple voltages using the external power supply voltage provided to memory device 100. Specifically, voltage generator 122 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc., under the control of control logic 130.

[0071] In one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 is used as the operating voltage of memory device 100.

[0072] In one embodiment, voltage generator 122 can use an external power supply voltage or an internal power supply voltage to generate multiple voltages.

[0073] For example, voltage generator 122 may include a plurality of pump capacitors for receiving internal power supply voltage, and generate a plurality of voltages by selectively enabling the plurality of pump capacitors under the control of control logic 130.

[0074] The generated voltage can be provided to the memory cell array 110 via the row decoder 121.

[0075] Page buffer group 123 includes first page buffers to nth page buffers PB1 to PBn. First page buffers to nth page buffers PB1 to PBn are coupled to memory cell array 110 via first bit lines to nth bit lines BL1 to BLn. First page buffers to nth page buffers PB1 to PBn operate under the control of control logic 130. Specifically, first page buffers to nth page buffers PB1 to PBn can operate in response to page buffer control signals PBSIGNALS. For example, first page buffers to nth page buffers PB1 to PBn can temporarily store data received via first bit lines to nth bit lines BL1 to BLn, or the voltage or current of bit lines BL1 to BLn can be sensed during read or verification operations.

[0076] Specifically, during programming operations, when a programming voltage is applied to the selected word line, the first page buffer to the nth page buffer PB1 to PBn can transmit the data DATA received via the input / output circuit 125 to the selected memory cell via the first bit line to the nth bit line BL1 to BLn. The memory cell in the selected page is programmed based on the received data DATA. During programming verification operations, the first page buffer to the nth page buffer PB1 to PBn can read page data by sensing the voltage or current received from the selected memory cell via the first bit line to the nth bit line BL1 to BLn.

[0077] During a read operation, the first page buffer to the nth page buffers PB1 to PBn can read data DATA from the memory cell in the selected page through the first bit line to the nth bit line BL1 to BLn, and the read data DATA can be output to the input / output circuit 125 under the control of the column decoder 124.

[0078] During the erase operation, the first page buffer to the nth page buffer PB1 to PBn can allow the first bit line to the nth bit line BL1 to BLn to float, or the erase voltage can be applied to the first bit line to the nth bit line BL1 to BLn.

[0079] The column decoder 124 can transfer data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can exchange data with the first page buffer to the nth page buffer PB1 to PBn via the data line DL, or it can exchange data with the input / output circuitry 125 via the column line CL.

[0080] The input / output circuit 125 can be derived from the above reference. Figure 1 The memory controller described (e.g., Figure 1The command CMD and address ADDR received by the 200) are passed to the control logic 130, or data DATA can be exchanged with the column decoder 124.

[0081] During a read or verification operation, the sensing circuit 126 can generate a reference current in response to the enable bit VRYBIT, and can compare the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current, and then output a pass signal PASS or a failure signal FAIL.

[0082] Control logic 130 can control peripheral circuitry 120 in response to commands CMD and address ADDR by outputting operation signals OPSIG, row address RADD, page buffer control signals PBSIGNALS, and enable bit VRYBIT. For example, control logic 130 can control read operations on selected memory blocks in response to sub-block read commands and addresses. Furthermore, control logic 130 can control erase operations on selected sub-blocks included within selected memory blocks in response to sub-block erase commands and addresses. Additionally, control logic 130 can determine whether a verification operation has passed or failed via signals PASS or FAIL. Control logic 130 can be implemented in hardware, software, or a combination of both. For example, control logic 130 can be control logic circuitry operating according to an algorithm and / or processor executing control logic code.

[0083] In one embodiment, control logic 130 may include a mode setter 150 and a control signal generator 190, and input / output circuitry 125 may include an input controller 170. In other embodiments, mode setter 150 and control signal generator 190 may be located external to control logic 130. In other embodiments, input controller 170 may be located external to input / output circuitry 125.

[0084] In one embodiment, mode setter 150 can output line enable signal TM_X4_MODE to control signal generator 190, and control signal generator 190 can output fast mode signal X4_FASTLOAD based on line enable signal TM_X4_MODE, which is used to control data input to input controller 170.

[0085] In one embodiment, when the memory device 100 operates in X8 mode, the line enable signal TM_X4_MODE can be output as a low-state signal to the control signal generator 190, and when the memory device operates in X4 mode, the line enable signal TM_X4_MODE can be output as a high-state signal to the control signal generator 190. Here, it is assumed that the memory device 100 and the memory controller (e.g., ...) are coupled... Figure 1 The total number of input / output lines between the 200 is 8. When data is received through all input / output lines, the data input mode can be X8 mode, and when data is received through four input / output lines that are some of the input / output lines, the data input mode can be X4 mode.

[0086] In one embodiment, when the control signal generator 190 receives a high-state line enable signal TM_X4_MODE in X4 mode, the control signal generator 190 can generate control signals for generating internal input data based on data received through some input / output lines. The control signals for generating internal input data can be a fast mode signal X4_FASTLOAD. The fast mode signal X4_FASTLOAD can indicate the start of data input X4_MODE_START and the end of data input X4_MODE_END in X4 mode.

[0087] In one embodiment, the input controller 170 may generate internal input data based on the fast mode signal X4_FASTLOAD. Specifically, the input controller 170 may generate internal input data when receiving data from an external controller via some input / output lines in X4 mode. The generated internal input data may be programmed into a memory cell in a selected page.

[0088] Figure 3 It's a diagram. Figure 2 A diagram of one embodiment of a memory cell array.

[0089] refer to Figure 2 and Figure 3 , Figure 3 It is illustrated in Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz included in the memory cell array 110.

[0090] The memory block BLKa can be coupled to a first select line, a word line, and a second select line arranged parallel to each other. For example, the word lines can be arranged parallel to each other between the first select line and the second select line. Here, the first select line can be the source select line SSL, and the second select line can be the drain select line DSL.

[0091] In detail, the memory block BLKa may include multiple strings coupled between bit lines BL1 to BLn and source lines SL. Bit lines BL1 to BLn may be coupled to strings individually, and source lines SL may be coupled to strings collectively. Because strings can be configured in the same way, the string ST coupled to the first bit line BL1 will be described in detail by way of example.

[0092] A string ST may include a source selection transistor SST coupled in series with each other between the source line SL and the first bit line BL1, a plurality of memory cells F1 to F16, and a drain selection transistor DST. A single string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and may include more memory cells than the memory cells F1 to F16 shown in the figure.

[0093] The source of the source select transistor SST can be coupled to the source line SL, and the drain of the drain select transistor DST can be coupled to the first bit line BL1. Memory cells F1 to F16 can be coupled in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors included in different string STs can be coupled to the source select line SSL, the gates of the drain select transistors included in different string STs can be coupled to the drain select line DSL, and the gates of memory cells F1 to F16 can be coupled to multiple word lines WL1 to WL16 respectively. A group of memory cells coupled to the same word line in memory cells included in different string STs can be referred to as a "physical page: PPG". Therefore, a memory block BLKa can include multiple physical pages PPGs, the same number as word lines WL1 to WL16.

[0094] A memory cell can store one bit of data. This cell is typically referred to as a "Single-Level Cell (SLC)". Here, a physical page (PPG) can store data corresponding to a logical page (LPG). The data corresponding to a logical page (LPG) can include multiple data bits, the same number as the number of memory cells included in a physical page (PPG). Alternatively, a memory cell can store two or more data bits. This cell is typically referred to as a "Multi-Level Cell (MLC)". Here, a physical page (PPG) can store data corresponding to two or more logical pages (LPGs).

[0095] A memory cell storing two or more data bits is called a multilevel cell (MLC). However, recently, with the increase in the number of data bits stored in a memory cell, a multilevel cell (MLC) refers to a memory cell storing two data bits, and therefore a memory cell storing three data bits is called a three-level cell (TLC), and a memory cell storing four data bits is called a four-level cell (QLC). Additionally, memory cell schemes storing multiple data bits have been developed, and this embodiment can be applied to a memory device 100 storing two or more data bits.

[0096] In one embodiment, each memory block in the memory block may have a three-dimensional (3D) structure. Each memory block may include multiple memory cells stacked on a substrate. The multiple memory cells are arranged along the +X, +Y, and +Z directions.

[0097] Figure 4 It is used to describe memory devices (e.g., Figure 1 A diagram showing the pin configuration of the memory device 100.

[0098] refer to Figure 4 The memory device 100 can communicate with an external controller via multiple data input / output lines. For example, the memory device 100 can communicate with an external controller via control signal lines, including chip enable line CE#, write enable line WE#, read enable line RE#, address latch enable line ALE, command latch enable line CLE, write protection line WP#, ready / busy line RB, and data input / output line DQ.

[0099] Memory device 100 can receive a chip enable signal from an external controller via the chip enable line CE#. Memory device 100 can receive a write enable signal from an external controller via the write enable line WE#. Memory device 100 can receive a read enable signal from an external controller via the read enable line RE#. Memory device 100 can receive an address latch enable signal from an external controller via the address latch enable line ALE. Memory device 100 can receive a command latch enable signal from an external controller via the command latch enable line CLE. Memory device 100 can receive a write protection signal from an external controller via the write protection line WP#.

[0100] In one embodiment, the memory device 100 can communicate with the memory controller (e.g., via the ready / busy line RB) through the ready / busy line RB. Figure 1 The 200) provides a ready / busy signal that indicates whether the memory device 100 is in a ready state or a busy state.

[0101] The chip enable signal can be a control signal used to select the memory device 100. When the chip enable signal is in a "high" state and the memory device 100 is in a "ready" state, the memory device 100 can enter a low-power standby state.

[0102] The write enable signal can be a control signal used to perform control so that commands, addresses and input data applied to the memory device 100 are stored in the latch.

[0103] The read enable signal can be a control signal used to enable the output of serial data.

[0104] The address latch enable signal can be one of the control signals used by the host to indicate which of the commands, addresses, and data corresponds to the type of signal input to the data input / output line DQ.

[0105] The command latch enable signal can be one of the control signals used by the host to indicate which of the command, address, and data corresponds to the type of signal input to the data input / output line DQ.

[0106] For example, when the command latch enable signal is activated (e.g., logic high), the address latch enable signal is deactivated (e.g., logic low), and the write enable signal is activated (e.g., logic low) and then deactivated (e.g., logic high), the memory device 100 can identify that the signal input via the data input / output line DQ is a command.

[0107] For example, when the command latch enable signal is deactivated (e.g., logic low), the address latch enable signal is activated (e.g., logic high), and the write enable signal is activated (e.g., logic low) and then deactivated (e.g., logic high), the memory device 100 can identify that the signal input via the data input / output line DQ is an address.

[0108] The write protection signal can be a control signal used to deactivate programming and erasing operations performed by the memory device 100.

[0109] The ready / busy signal can be a signal used to identify the state of the memory device 100. A low ready / busy signal indicates that the memory device 100 is currently performing at least one operation. A high ready / busy signal indicates that the memory device 100 is not currently performing any operation.

[0110] While the memory device 100 is performing any of the following operations: programming, reading, and erasing, the ready / busy signal can be low. In one embodiment of this disclosure, reference is made to... Figure 1The described memory controller 200 can determine the termination point based on a ready / busy signal, which is the point at which a programming operation or an erase operation terminates.

[0111] Figure 5 This is a diagram illustrating one embodiment in which the memory device and the test device are coupled to each other during a test operation.

[0112] refer to Figure 5 ,exist Figure 5 The diagram illustrates the configuration in which the memory device 100 and the test device TEST_DEVICE are coupled to each other via multiple lines during a test operation.

[0113] In one embodiment, for testing memory device 100, memory device 100 and test equipment TEST_DEVICE can be coupled to each other via a probe card PROBE_CARD. For example, when a probe mounted on the probe card PROBE_CARD contacts the wafer of memory device 100, the probe card PROBE_CARD transmits power, and the probe card PROBE_CARD determines whether memory device 100 is defective based on signals returned from memory device 100.

[0114] Here, the probe card PROBE_CARD and the memory device 100 can be coupled to each other via multiple lines.

[0115] refer to Figure 5 The probe card PROBE_CARD and the memory device 100 can be coupled to each other via the command latch enable line CLE, the address latch enable line ALE, the write enable line WE#, the read enable line RE#, and the input / output lines DQ<7:4> and DQ<3:0>.

[0116] exist Figure 5 In this figure, the probe card PROBE_CARD and the memory device 100 can be coupled to each other through all input / output lines DQ<7:4> and DQ<3:0>. That is, in this figure, the input / output mode of the memory device 100 can be X8 mode.

[0117] However, as the number of dies included in the memory device 100 increases, the number of lines required to couple the pins of the respective dies to the probe card PROBE_CARD may also increase. Furthermore, the associated costs may also increase with the increased number of lines required.

[0118] Therefore, in order to increase testing efficiency, it is necessary to reduce the number of lines used to couple the pins of the corresponding die to the probe card PROBE_CARD while setting the input / output mode of the memory device 100 to X4 mode.

[0119] The following will be referenced Figure 6 This section describes in detail a method to reduce the number of lines used to couple the pins of the corresponding die to the PROBE_CARD probe card.

[0120] Figure 6 This is a diagram illustrating one embodiment in which the memory device and the test device are coupled to each other during a test operation.

[0121] refer to Figure 6 , Figure 6 The diagram illustrates the configuration in which the memory device 100 and the test device TEST_DEVICE are coupled to each other via multiple lines during a test operation.

[0122] exist Figure 6 In this context, it is assumed that the memory device 100 consists of two dies, each of which includes multiple planes, and each plane includes multiple memory blocks. That is, Figure 6 The memory device 100 may include a first die and a second die, and each of the first die and the second die may include a plurality of planes, each of which includes a plurality of memory blocks.

[0123] In one embodiment, for testing memory device 100, memory device 100 and test device TEST_DEVICE can be coupled to each other via probe card PROBE_CARD. Probe card PROBE_CARD and memory device 100 can be coupled to each other via multiple lines. These multiple lines may include command latch enable line CLE, address latch enable line ALE, write enable line WE#, read enable line RE#, and input / output lines DQ<7:4> and DQ<3:0> between probe card PROBE_CARD and memory device 100.

[0124] However, with Figure 5 The difference lies in Figure 6 In the process, the probe card PROBE_CARD and the memory device 100 can be coupled to each other through some of the input / output lines DQ<7:4> and DQ<3:0>, and the input / output mode of the memory device 100 can be X4 mode.

[0125] Specifically, the probe card PROBE_CARD and the memory device 100 can be coupled to each other by applying some lines DQ<7:4> of the high data bits input via the input / output lines. In this case, among the dies included in the memory device 100, the first die can be coupled to the probe card PROBE_CARD via some lines DQ<7:4>.

[0126] That is, the line DQ<3:0> through which low data bits are applied can be uncoupled from the probe card PROBE_CARD, and the probe card PROBE_CARD and the first die can be coupled to each other via the line DQ<7:4> through which high data bits are applied. In this case, line DQ<3:0> can be coupled to the line of the second die through which high bits are applied, and line DQ<3:0> is another line located between the probe card PROBE_CARD and the first die through which low bits are applied.

[0127] Therefore, because the lines related to command and address inputs can be shared between the first and second dies, and the PROBE_CARD probe card, which is only coupled to the first die, is coupled to both the first and second dies, the number of lines used to couple the memory device 100 to the PROBE_CARD probe card can be reduced. When the number of lines used to couple the memory device 100 to the PROBE_CARD probe card is reduced, test performance can be improved.

[0128] Figure 7 The illustration shows that Figure 6 The method of inputting data into multiple dies during the test operation.

[0129] refer to Figure 6 and Figure 7 , Figure 7 The diagram illustrates the lines used to couple the probe card PROBE_CARD and the memory device 100 to each other when the memory device 100 is in X4 mode. Figure 7 The memory device 100 may include a first die 101 and a second die 103, and each of the first die 101 and the second die 103 may include multiple planes, each plane including multiple memory blocks.

[0130] In one embodiment, when the memory device is in X4 mode, the first die 101 and the second die 103 can share command latch enable line CLE, address latch enable line ALE, write enable line WE#, and read enable line RE#, which are lines related to command and address input. Therefore, the memory device 100 can perform test operations on the first die 101 and the second die 103 during a test operation.

[0131] However, the first die 101 and the probe card PROBE_CARD can be coupled to each other via some lines DQ<7:4> through which high-order bits are applied in the lines through which data is input to the first die 101, and the second die 103 and the probe card PROBE_CARD can be coupled to each other via some lines DQ<7:4> through which high-order bits are applied in the lines through which data is input to the second die 103. Therefore, some lines DQ<3:0> through which low-order bits are applied in the lines through which data is input to the first die 101 and the second die 103 may not be used.

[0132] In one embodiment, when the memory device 100 is in X4 mode, data can be input via some lines DQ<7:4>, and therefore the time required for data input may be twice that required when the memory device 100 is in X8 mode. For example, the cycle time for inputting a data slice in X4 mode may be twice the cycle time for inputting a data slice in X8 mode.

[0133] As a result, the time required for the test operation (test time) may also increase as the number of cycles during which data is input increases.

[0134] Therefore, this disclosure proposes a method to reduce test time in X4 mode by controlling data, so that the same test can be performed in X4 mode as in X8 mode.

[0135] Figure 8 It is a timing diagram illustrating the process of inputting commands, addresses, and data in X8 mode.

[0136] refer to Figure 5 and Figure 8 ,exist Figure 8 The diagram in the middle shows Figure 5 In the input / output mode, signals are input through multiple lines. That is, Figure 8 The diagram illustrates the input and output of data in memory device 100 when using all input / output lines DQ<7:0> in X8 mode. Figure 5 Internal input data generated within the memory device 100.

[0137] In one embodiment, when a programming operation is tested during a test operation, the memory device 100 can receive a command latch enable signal from an external controller via the command latch enable line CLE. The command latch enable signal can be a signal indicating that the input received via the input / output lines DQ<7:0> is a command. Therefore, when the command latch enable signal received via the command latch enable line CLE is high, the input received via the input / output lines DQ<7:0> can be a command.

[0138] As a result, when the command latch enable signal is high, the command "80h" can be received from the external controller.

[0139] Subsequently, when the reception of command "80h" is complete, the command latch enable signal can transition from a high state to a low state, and the address latch enable signal received via the address latch enable line ALE can transition to a high state. Here, the address latch enable signal can be a signal indicating that the input received via the input / output lines DQ<7:0> is an address. Therefore, when the address latch enable signal received via the address latch enable line ALE is high, the input received via the input / output lines DQ<7:0> can be an address.

[0140] As a result, when the address latch enable signal is high, addresses “A1”, “A2”, “A3”, “A4” and “A5” can be received from the external controller.

[0141] Subsequently, when the reception of addresses “A1”, “A2”, “A3”, “A4”, and “A5” is complete, the address latch enable signal transitions from a high state to a low state, and the write enable signal received from the external controller via the write enable line WE# can transition from a high state to a low state. When the write enable signal transitions to a low state, the memory device 100 can receive data via the input / output lines DQ<7:0>. For example, when the write enable signal is low, data segments “AA”, “55”, “AA”, and “55” can be received via the input / output lines DQ<7:0>.

[0142] Here, because all input / output lines DQ<7:0> coupled to memory device 100 are used to receive data slices, data received from the outside can be output as internal input data DQ_INT<7:0> in the same way, without the need for separate data control within memory device 100. That is, data slices received via input / output lines DQ<7:0> can be programmed into memory cells as internal input data DQ_INT<7:0>.

[0143] Figure 9 It is a timing diagram illustrating the process of data being input in X8 mode.

[0144] refer to Figure 6 and Figure 9 , Figure 9 The illustration shows when a memory device (e.g., Figure 6 The memory device 100) in Figure 6 In the input / output mode, when receiving data from an external controller, the signal is input through multiple lines. That is, Figure 9 The illustration shows the input of data and the internal input data DQ_INT<7:0> generated within the memory device 100 when some of the input / output lines DQ<7:0> are used in X4 mode.

[0145] refer to Figure 8 and Figure 9 ,exist Figure 9 In this context, when memory device 100 receives commands and addresses, memory device 100 operates in X8 mode. In X8 mode, all input / output lines DQ<7:0> are connected to... Figure 8 The same approach is used, and therefore its detailed description will be omitted.

[0146] In one embodiment, the memory device 100 can receive data from an external controller when the write enable signal received via the write enable line WE# is low. Here, the memory device 100 can receive data via some of the input / output lines DQ<7:4> that apply the high bits therethrough in the input / output lines DQ<7:0>. Therefore, some of the input / output lines DQ<3:0> that apply the low bits therethrough in the input / output lines DQ<7:0> may be unused.

[0147] Furthermore, when the write protection signal received via the write protection line WP# is in a low state, the memory device 100 can receive data via some of the input / output lines DQ<7:4> in the input / output lines DQ<7:0>, through which the high bits are applied.

[0148] When the memory device 100 operates in X4 mode, because data is received through some of the input / output lines DQ<7:4> in the input / output lines DQ<7:0>, data segments “A”, “A”, “5”, “5”, “A”, “5”, and “5” are received through the input / output lines DQ<7:4> when the write enable signal is low. That is, because some of the input / output lines DQ<3:0> that apply the lower bits are not used, data segments “A”, “A”, “5”, “5”, “A”, “A”, “5”, or data segments “A0”, “A0”, “50”, “50”, “A0”, “A0”, “50”, and “50” can be received.

[0149] In this case, because data is received through some of the input / output lines DQ<7:4> out of all input / output lines DQ<7:0>, the time required to receive data may be [time missing]. Figure 8 This takes twice as long as the time required in the first cycle. For example, when receiving data through some input / output lines DQ<7:4>, data segments “A0”, “A0”, “50”, and “50” can be received during the first cycle, and data segments “A0”, “A0”, “50”, and “50” can be received during the second cycle. That is, data that can be received through all input / output lines DQ<7:0> in one cycle can be received through some input / output lines DQ<7:4> in two cycles.

[0150] In one embodiment, memory device 100 can generate internal input data DQ_INT<7:0> by internally combining data "A0", "A0", "50", "50", "A0", "A0", "50", and "50" received via some input / output lines DQ<7:4>. For example, memory device 100 can generate data "AA" by combining "A0" with "A0", and can generate data "55" by combining "50" with "50". The generated data can be programmed into the memory cells of memory device 100.

[0151] Figure 10 The diagram illustrates a method to reduce data input time in X4 mode.

[0152] refer to Figure 6 and Figure 10 , Figure 10 The illustration shows when a memory device (e.g., Figure 6 The memory device 100) in Figure 6 In the input / output mode, when receiving data from an external controller, the signal is input through multiple lines. That is, Figure 10 The illustration shows the input of data and the internal input data DQ_INT<7:0> generated within the memory device 100 when some of the input / output lines DQ<7:0> are used in X4 mode.

[0153] However, with Figure 9 Unlike in this diagram, memory device 100 can receive all data in one cycle in X4 mode.

[0154] exist Figure 9In the X4 mode, when the memory device 100 operates, the data input cycle is extended because data is received through some of the input / output lines DQ<7:4> of the input / output lines DQ<7:0>. That is, data that could be received through all input / output lines DQ<7:0> in one cycle can be received through some input / output lines DQ<7:4> in two cycles. Specifically, while the write enable signal received from the external controller via the write enable line WE# is low, data segments “A0”, “A0”, “50”, and “50” can be received through some input / output lines DQ<7:4> in one cycle. Here, “0” can mean no data input.

[0155] However, in this figure, even if data has been received via some input / output lines DQ<7:4>, the memory device 100 can internally generate input data based on the received data. For example, the memory device 100 can generate internal input data DQ_INT<7:0>, such as "AA", "AA", "55" and "55", based on data slices "A0", "A0", "50" and "50" received via some input / output lines DQ<7:4>.

[0156] In one embodiment, when input data is generated internally by the memory device 100, the same effect can be obtained as if data were received through all input / output lines DQ<7:0>, even if data is received through only some input / output lines DQ<7:4> during a cycle.

[0157] The following description, with reference to the accompanying figures, illustrates a method for generating internal input data DQ_INT<7:0> based on data received via some input / output lines DQ<7:4>.

[0158] Figures 11A to 11C The diagram illustrates how data is input in X4 and X8 modes.

[0159] refer to Figures 11A to 11C , Figure 11A The diagram shows... Figure 1 Input controller (e.g., Figure 1 The configuration of 170). Figure 11B The diagram illustrates the internal input data DQ_INT<7:0> generated by the input controller 170 when a command or address is entered in X4 mode. Figure 11C The diagram illustrates the internal input data DQ_INT<7:0> generated by the input controller 170 when data is input in X4 mode.

[0160] In one embodiment, the input controller 170 may include a first gate 171, a second gate 173, and a multiplexer assembly 175. The multiplexer assembly 175 may include first multiplexers to fourth multiplexers 175_1 to 175_4. The first gate 171 may be an OR gate (i.e., a logical OR gate), and the second gate 173 may be an AND gate (i.e., a logical AND gate).

[0161] In one embodiment, the normal mode signal X4_CURRENT and the fast mode signal X4_FASTLOAD can be input to the first gate 171. When the memory device (e.g., memory device 100) receives a command or address from an external controller in X4 mode, the normal mode signal X4_CURRENT can transition from a high state to a low state. Additionally, when the memory device 100 receives data from an external controller in X4 mode, the fast mode signal X4_FASTLOAD can transition from a low state to a high state.

[0162] In one embodiment, when the high-state normal mode signal X4_CURRENT and / or the high-state fast mode signal X4_FASTLOAD are input, the first gate 171 can output a high-state signal, and when the low-state normal mode signal X4_CURRENT and the low-state fast mode signal X4_FASTLOAD are input, the first gate 171 can output a low-state signal.

[0163] A high or low state signal output from the first gate 171 can be input to the second gate 173. The signal output from the first gate 171 and the line enable signal TM_X4_MODE can be input to the second gate 173. The line enable signal TM_X4_MODE can be input from... Figure 1 The mode setter 150 is output.

[0164] For example, when memory device 100 operates in X8 mode, the line enable signal TM_X4_MODE can be input as a low-state signal, while when memory device 100 operates in X4 mode, the line enable signal TM_X4_MODE can be input as a high-state signal. Therefore, when memory device 100 operates in X4 mode, the line enable signal TM_X4_MODE can be in a high state.

[0165] In one embodiment, when the low-state normal mode signal X4_CURRENT is input to the first gate 171, commands or addresses received from the outside can be output in X4 mode without modification. Furthermore, when the high-state fast mode signal X4_FASTLOAD is input to the first gate 171, new internal inputs can be output based on data received from the outside.

[0166] Specifically, when receiving a command or address in X4 mode, the line enable signal TM_X4_MODE is high, the normal mode signal X4_CURRENT is low, and the fast mode signal X4_FASTLOAD is low, thus a low-state signal can be output from the first gate 171. Because the signal output from the first gate 171 is a low-state signal, a low-state signal can also be output from the second gate 173 even if the line enable signal TM_X4_MODE is high. The low-state signal output from the second gate 173 can be input to the first to fourth multiplexers 175_1 to 175_4.

[0167] When the low-state signal output from the second gate 173 is input to the first to fourth multiplexers 175_1 to 175_4, the multiplexer component 175 may not output the internal input data DQ_INT<3:0>. That is, when the memory device 100 receives commands or addresses in X4 mode through some input / output lines DQ<7:4>, the remaining lines DQ<3:0> besides some input / output lines DQ<7:4> may not be used, and the commands or addresses received through some input / output lines DQ<7:4> can be output as internal input data DQ_INT<7:4> in the same way without separate control.

[0168] refer to Figure 11B The diagram illustrates the internal input data DQ_INT<7:0> output from the first multiplexer to the fourth multiplexer 175_1 to 175_4 when the line enable signal TM_X4_MODE is low and the normal mode signal X4_CURRENT and the fast mode signal X4_FASTLOAD are low. That is, internal input data DQ_INT<3:0> can be omitted, and data received through some input / output lines DQ<7:4> can be output as internal input data DQ_INT<7:4> without modification.

[0169] Furthermore, when receiving data in X4 mode, the line enable signal TM_X4_MODE is high, the normal mode signal X4_CURRENT is high, and the fast mode signal X4_FASTLOAD is high, thus a high-state signal can be output from the first gate 171. Because the signal output from the first gate 171 is high and the line enable signal TM_X4_MODE is high, a high-state signal can be output from the second gate 173. The high-state signal output from the second gate 173 can be input to the first to fourth multiplexers 175_1 to 175_4.

[0170] When the high-state signal output from the second gate 173 is input to the first to fourth multiplexers 175_1 to 175_4, the memory device 100 can generate internal input data DQ_INT<3:0> based on data received through some input / output lines DQ<7:4>. Here, the remaining lines DQ<3:0> besides some input / output lines DQ<7:4> can be omitted.

[0171] For example, internal input data DQ_INT <0> It can be based on the DQ input to the first multiplexer 175_1 <0> And DQ <4> Generated (MUX(DQ)) <0> DQ <4> Here, the first multiplexer 175_1 can be used in DQ. <0> And DQ <4> Choose DQ <4> And then you can DQ <4> DQ_INT as internal input data <0> Output.

[0172] Similarly, the second multiplexer 175_2 can be used at the input DQ <1> And input DQ <5> Choose DQ <5> And DQ <5> DQ_INT as internal input data <1> Output (MUX (DQ) <1> DQ <5> The third multiplexer 175_3 can access the input DQ. <2> And input DQ <6> Choose DQ <6> Then DQ <6> DQ_INT as internal input data <2> Output (MUX (DQ) <2> DQ <6> Furthermore, the fourth multiplexer 175_4 can access the input DQ. <3> And input DQ <7> Choose DQ <7> And can DQ <7> DQ_INT as internal input data <3> Output (MUX (DQ) <3> DQ <7> ).

[0173] refer to Figure 11C The diagram illustrates the internal input data output from the first to the fourth multiplexers 175_1 to 175_4 when the line enable signal TM_X4_MODE is high and the normal mode signal X4_CURRENT and the fast mode signal X4_FASTLOAD are both high. That is, although the remaining lines DQ<3:0> besides some input / output lines DQ<7:4> are not used, the internal input data DQ_INT<3:0> can be output from the first to the fourth multiplexers 175_1 to 175_4, and data received through some input / output lines DQ<7:4> can be output as internal input data DQ_INT<7:4>.

[0174] Therefore, although the memory device 100 receives data through some input / output lines DQ<7:4> in X4 mode, data of the same size as when operating in X8 mode can be input in the same cycle as in X8 mode.

[0175] In other embodiments, when the memory device (e.g., Figure 6 When the memory device 100 operates in X8 mode, the line enable signal TM_X4_MODE can be low. Therefore, regardless of the state of the normal mode signal X4_CURRENT and the fast mode signal X4_FASTLOAD, a low-state signal can be output from the second gate 173. Furthermore, when the low-state signal output from the second gate 173 is input to the first to fourth multiplexers 175_1 to 175_4, the multiplexer component 175 may not output the internal input data DQ_INT<3:0>. Additionally, in X8 mode, the internal input data DQ_INT<7:0> may not be generated, and the memory device 100 can output the data received via the input / output lines DQ<7:0> without modification.

[0176] Figure 12 The diagram illustrates the control signals used for data input and the generated internal input data in X4 mode.

[0177] refer to Figure 12 ,exist Figure 12 The diagram illustrates: a line enable signal TM_X4_MODE for setting the input mode of a memory device (e.g., memory device 100) to X4 mode or X8 mode; a write enable signal input via the write enable line WE#; a data input DQ<7:0> input via the data input / output line DQ; a write protection signal input via the write protection line WP#; a fast mode signal X4_FASTLOAD indicating the start and end of data input in X4 mode; a first control signal TM_BIT_X4_FASTLOAD for generating the fast mode signal X4_FASTLOAD; a second control signal DATA_IN_START; a third control signal COLUMN_COUNTER_END; and a control signal from the input controller (e.g., ...). Figure 1 The internal input data DQ_INT<7:4> is output by 170).

[0178] exist Figure 12 In this context, it is assumed that memory device 100 receives data from an external controller in X4 mode. Here, X4 mode can be a mode in which only some of the large number of input / output lines coupled to memory device 100 are used to receive input from the external controller, and X8 mode can be a mode in which all input / output lines coupled to memory device 100 are used to receive input from the external controller.

[0179] In one embodiment, when the memory device 100 starts operating in X4 mode, the line enable signal TM_X4_MODE can transition from a low state to a high state. Figure 1 The mode setter 150 is output.

[0180] When the memory device 100 starts operating in X4 mode, data can be received through some input / output lines DQ<7:4> when the write protection signal input via the write protection line WP# is low. In this figure, because the memory device 100 receives data from an external controller in X4 mode, it can receive data slices "A0", "50", "A0", and "50" through some input lines DQ<7:4>. While data is being input through some input / output lines DQ<7:4>, the write protection signal input via the write protection line WP# can be high.

[0181] In one embodiment, the fast mode signal X4_FASTLOAD can indicate the start of data input X4_MODE_START and the end of data input X4_MODE_END in X4 mode. In another embodiment, the fast mode signal X4_FASTLOAD can be generated based on a first control signal TM_BIT_X4_FASTLOAD, a second control signal DATA_IN_START, and a third control signal COLUMN_COUNTER_END.

[0182] Specifically, when data input begins in X4 mode, the first control signal TM_BIT_X4_FASTLOAD can transition from a low state to a high state. For example, in this disclosure, when the memory device 100 internally generates input data in X4 mode, that is, when data input for enabling the input controller 170 to output internal input data DQ_INT<7:0> begins, the first control signal TM_BIT_X4_FASTLOAD can transition from a low state to a high state.

[0183] When a data input command for command input data is received from an external controller, the second control signal DATA_IN_START can change from a low state to a high state.

[0184] When data input terminates in X4 mode, the third control signal COLUMN_COUNTER_END can transition from a low state to a high state. For example, when the last column of page data has been reached during data input or output, the third control signal COLUMN_COUNTER_END can transition to a high state.

[0185] In one embodiment, the fast mode signal X4_FASTLOAD can be generated based on the first control signal TM_BIT_X4_FASTLOAD, the second control signal DATA_IN_START, and the third control signal COLUMN_COUNTER_END described above. Specifically, when the first control signal TM_BIT_X4_FASTLOAD is high, the fast mode signal X4_FASTLOAD can be enabled by transitioning to a high state on the rising edge of the second control signal DATA_IN_START, and disabled by transitioning to a low state on the rising edge of the third control signal COLUMN_COUNTER_END. Therefore, the fast mode signal X4_FASTLOAD can indicate the start of data input X4_MODE_START and the end of data input X4_MODE_END in X4 mode.

[0186] In one embodiment, when the fast mode signal X4_FASTLOAD transitions from a low state to a high state, data can be received through some input / output lines DQ<7:4>. Here, the remaining input / output lines DQ<3:0> besides some input / output lines DQ<7:4> can be omitted. Alternatively, even if data has been input through input / output lines DQ<3:0>, the corresponding data can be ignored.

[0187] Therefore, based on the data received through some input / output lines DQ<7:4>, it is possible to obtain data from the input controller (e.g., Figure 1 The 170) outputs internal input data DQ_INT<7:0>. For example, although data slices “A0”, “50”, “A0”, and “50” are actually received through some input / output lines DQ<7:4>, the internal input data DQ_INT<7:0> can be “AA”, “55”, “AA”, and “55”.

[0188] Therefore, although data is input through some input / output lines DQ<7:4> in X4 mode, data of the same size as when operating in X8 mode can be input in the same cycle. Thus, data input speed can be improved in X4 mode.

[0189] Figure 13 The diagram illustrates the process of generating Figure 12 Configuration of the control signal generator 190 for the fast mode signal.

[0190] refer to Figure 13 , Figure 13The control signal generator 190 may include an input start signal generator 191, an input enable signal generator 193, an input disable signal generator 195, and a D flip-flop 197. Figure 13 In this context, the control signal generator 190 can be based on... Figure 1 The mode setter 150 receives the line enable signal TM_X4_MODE to output the fast mode signal X4_FASTLOAD.

[0191] In one embodiment, the control signal generator 190 can be derived from... Figure 1 The mode setter 150 receives the line enable signal TM_X4_MODE. When the memory device (e.g., Figure 6 When starting operation in X4 mode (100), the line enable signal TM_X4_MODE can transition from a low state to a high state. When the line enable signal TM_X4_MODE is received, it can be passed to the input start signal generator 191, the input enable signal generator 193, and the input disable signal generator 195.

[0192] In one embodiment, the input start signal generator 191 can generate a first control signal TM_BIT_X4_FASTLOAD based on a high-state line enable signal TM_X4_MODE. The generated first control signal TM_BIT_X4_FASTLOAD can be input to the input pin D of the D flip-flop 197.

[0193] When the data input used to enable the input controller 170 to output internal input data DQ_INT<7:0> begins in X4 mode, the first control signal TM_BIT_X4_FASTLOAD output from the input start signal generator 191 can change from a low state to a high state.

[0194] In one embodiment, the input enable signal generator 193 can generate a second control signal DATA_IN_START based on a high-state line enable signal TM_X4_MODE. The generated second control signal DATA_IN_START can be input to the clock pin CK of the D flip-flop 197.

[0195] When a data input command for command input data is received from an external controller, the second control signal DATA_IN_START output from the input enable signal generator 193 can change from a low state to a high state.

[0196] In one embodiment, the input disable signal generator 195 can generate a third control signal COLUMN_COUNTER_END based on a high-state line enable signal TM_X4_MODE. The generated third control signal COLUMN_COUNTER_END can be input to the reset pin R of the D flip-flop 197.

[0197] When inputting or outputting data in X4 mode, the last column of page data has been reached, the third control signal COLUMN_COUNTER_END output from the input disable signal generator 195 can be switched to a high state.

[0198] In one embodiment, the D flip-flop 197 can output the fast mode signal X4_FASTLOAD via the output pin Q based on the first control signal TM_BIT_X4_FASTLOAD input through the input pin D.

[0199] Specifically, when the first control signal TM_BIT_X4_FASTLOAD is input through the input pin D of the D flip-flop 197, the fast mode signal X4_FASTLOAD can be enabled on the rising edge of the second control signal DATA_IN_START, which is input through the clock pin CK. That is, on the rising edge of the second control signal DATA_IN_START, the first control signal TM_BIT_X4_FASTLOAD can transition from a low state to a high state.

[0200] Subsequently, when the third control signal COLUMN_COUNTER_END is input through the reset pin R of the D flip-flop 197, the fast mode signal X4_FASTLOAD can be disabled on the rising edge of the third control signal COLUMN_COUNTER_END. That is, on the rising edge of the third control signal COLUMN_COUNTER_END, the fast mode signal X4_FASTLOAD can transition from a low state to a high state.

[0201] Therefore, since the fast mode signal X4_FASTLOAD is generated based on the first control signal TM_BIT_X4_FASTLOAD, the second control signal DATA_IN_START, and the third control signal COLUMN_COUNTER_END, the fast mode signal X4_FASTLOAD can indicate the start of data input X4_MODE_START and the end of data input X4_MODE_END in X4 mode.

[0202] Figure 14 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0203] refer to Figure 14 At step S1401, the memory device can set the data input mode to X4 mode. Here, X4 mode can be a mode in which only some of the large number of input / output lines coupled to the memory device are used to receive input from the external controller, and X8 mode can be a mode in which all the input / output lines coupled to the memory device are used to receive input from the external controller.

[0204] Therefore, when the memory device is set to X4 mode, data can be received from an external controller via some input / output lines at step S1403.

[0205] At step S1405, the memory device can generate internal input data based on data received through some input / output lines.

[0206] In one embodiment, when the memory device receives data in X4 mode, the time it may take is more than twice that of receiving data in X8 mode. Therefore, in this disclosure, although the memory device receives data in X4 mode, the memory device can internally generate internal input data based on the data received through some input / output lines.

[0207] Through the above process, even if the memory device receives data in X4 mode, it can receive the same amount of data in the same period as in X8 mode, compared to receiving data in X8 mode.

[0208] At step S1407, the memory device can perform a programming operation based on internal input data. For example, the memory device can program the internal input data into a selected memory cell.

[0209] Figure 15 This diagram illustrates one embodiment of a memory controller, in which the memory controller represents... Figure 1 The memory controller 200.

[0210] The memory controller 1000 is coupled to both the host and the memory device. In response to a request received from the host, the memory controller 1000 can access the memory device. For example, the memory controller 1000 can be configured to control write operations, read operations, erase operations, and background operations of the memory device. The memory controller 1000 provides an interface between the memory device and the host. The memory controller 1000 can run firmware for controlling the memory device.

[0211] refer to Figure 15The memory controller 1000 may include a processor 1010, a memory buffer 1020, an error correction code (ECC) circuit 1030, a host interface 1040, a buffer control circuit 1050, a memory interface 1060, and a bus 1070.

[0212] Bus 1070 can provide a channel between components of memory controller 1000.

[0213] Processor 1010 can control the overall operation of memory controller 1000 and can execute logical operations. Processor 1010 can communicate with an external host through host interface 1040 and with memory devices through memory interface 1060. Furthermore, processor 1010 can communicate with memory buffer 1020 through buffer control circuit 1050. Processor 1010 can control the operation of storage devices by using memory buffer 1020 as working memory, cache memory, or buffer memory.

[0214] Processor 1010 can perform the functions of a Flash Translation Layer (FTL). Processor 1010 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) via the FTL. The FTL can receive LBAs and use a mapping table to translate LBAs into PBAs. Depending on the mapping unit, examples of address mapping methods performed via the FTL can include various methods. Representative address mapping methods include page mapping, block mapping, and hybrid mapping.

[0215] Processor 1010 can randomize data received from the host. For example, processor 1010 can use a randomization seed to randomize data received from the host. The randomized data can be provided to the memory device as data to be stored and can be programmed in the memory cell array.

[0216] The processor 1010 can run software or firmware to perform randomization or derandomization operations.

[0217] In one embodiment, the processor 1010 may run software or firmware to perform randomization and derandomization operations.

[0218] The memory buffer 1020 can be used as the working memory, cache memory, or buffer memory of the processor 1010. The memory buffer 1020 can store code and commands executed by the processor 1010. The memory buffer 1020 can store data processed by the processor 1010. The memory buffer 1020 may include static RAM (SRAM) or dynamic RAM (DRAM).

[0219] ECC circuit 1030 can perform error correction. ECC circuit 1030 can perform error correction code (ECC) encoding based on data to be written to the memory device through memory interface 1060. ECC-encoded data can be transmitted to the memory device through memory interface 1060. ECC circuit 1030 can perform ECC decoding based on data received from the memory device through memory interface 1060. In one example, ECC circuit 1030 can be included as a component of memory interface 1060 within memory interface 1060.

[0220] The host interface 1040 can communicate with an external host under the control of the processor 1010. The host interface 1040 can perform communication using at least one of various communication methods, such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Fast (NVMe), Universal Flash Memory (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM) communication methods.

[0221] The buffer control circuit 1050 can control the memory buffer 1020 under the control of the processor 1010.

[0222] The memory interface 1060 can communicate with the memory device under the control of the processor 1010. The memory interface 1060 can transmit commands, addresses, and data to the memory device, or receive commands, addresses, and data from the memory device, through channels.

[0223] In one embodiment, the memory controller 1000 may not include the memory buffer 1020 and the buffer control circuit 1050.

[0224] In one embodiment, processor 1010 can use code to control the operation of memory controller 1000. Processor 1010 can load code from a non-volatile memory device (e.g., ROM) disposed in memory controller 1000. In one embodiment, processor 1010 can load code from a memory device via memory interface 1060.

[0225] In one embodiment, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to transmit data within the memory controller 1000, and the control bus can be configured to transmit control information, such as commands or addresses, within the memory controller 1000. The data bus and the control bus can be isolated from each other and can neither interfere with nor affect each other. The data bus can be coupled to the host interface 1040, the buffer control circuit 1050, the ECC circuit 1030, and the memory interface 1060. The control bus can be coupled to the host interface 1040, the processor 1010, the buffer control circuit 1050, the memory buffer 1020, and the memory interface 1060.

[0226] Figure 16 This is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present disclosure.

[0227] refer to Figure 16 The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

[0228] Memory controller 2100 is coupled to memory device 2200. Memory controller 2100 can access memory device 2200. For example, memory controller 2100 can control read operations, write operations, erase operations, and background operations of memory device 2200. Memory controller 2100 can provide an interface between memory device 2200 and the host. Memory controller 2100 can run firmware for controlling memory device 2200. Memory device 2200 can be configured with the above references. Figure 1 The described memory device (e.g., Figure 1 The same method as 100) is used.

[0229] In one embodiment, the memory controller 2100 may include components such as RAM, a processor, a host interface, a memory interface, and ECC circuitry.

[0230] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) based on a specific communication protocol. In one embodiment, the memory controller 2100 can communicate with external devices via at least one of various communication protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and Non-Volatile Memory Faster (NVMe) protocol. In one embodiment, connector 2300 can be defined by at least one of the aforementioned communication protocols.

[0231] In one embodiment, the memory device 2200 may be implemented as any of a variety of non-volatile memory devices, including, for example, electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), or spin-transfer torque magnetic RAM (STT-MRAM).

[0232] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card, such as a PC card (Personal Computer Memory Card International Association: PCMCIA), a compact flash memory card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro or eMMC), an SD card (SD, miniSD, microSD or SDHC), or universal flash memory (UFS).

[0233] In one embodiment, memory device 2200 may use some of the input / output lines of a plurality of input / output lines coupled to memory device 2200 to receive data from memory controller 2100. Here, assuming a total of eight input / output lines, the data input mode may be X8 mode when data is received through all eight input / output lines, and may be X4 mode when data is received through only four of the eight input / output lines.

[0234] In one embodiment, when the memory device 2200 receives data in X4 mode, it may take longer than when receiving data in X8 mode. Therefore, when receiving data in X4 mode, the memory device 2200 can generate internal input data based on the data received through some input / output lines.

[0235] In one embodiment, the memory device 2200 can receive input such that receiving commands or addresses from the memory controller 2100 in X4 mode is distinguished from receiving data in X4 mode.

[0236] For example, when receiving a command or address from the memory controller 2100 in X4 mode, the memory device 2200 can receive the command or address through some input / output lines, and may not internally generate internal input commands or internal input addresses. That is, when receiving a command or address in X4 mode, the generation of internal input data by the memory device 2200 can be skipped.

[0237] However, when receiving data from memory controller 2100 in X4 mode, memory device 2200 can receive data via some input / output lines and can generate internal input data based on the received data. The received data can be generated as internal input data via a multiplexer component (e.g., 175 in FIG11).

[0238] Figure 17 This is a block diagram illustrating an example of a solid-state drive (SSD) system that applies a storage device according to an embodiment of the present disclosure.

[0239] refer to Figure 17 The SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals SIG with the host 3100 through a signal connector 3001 and can receive power PWR through a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memory modules 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240. Here, flash memory refers to non-volatile memory (NVM).

[0240] In one embodiment, the SSD controller 3210 can perform the above-mentioned reference. Figure 1 The memory controller described (e.g., Figure 1 The function of (200).

[0241] SSD controller 3210 can control multiple flash memory modules 3221 to 322n in response to a signal SIG received from host 3100. In one embodiment, signal SIG can be a signal based on the interface between host 3100 and SSD 3200. For example, signal SIG can be a signal defined by at least one of various interfaces, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and Non-Volatile Memory Fast (NVMe) interface.

[0242] Auxiliary power supply 3230 can be coupled to host 3100 via power connector 3002. Power PWR can be supplied from host 3100 to auxiliary power supply 3230, and auxiliary power supply 3230 can be charged. When power supply from host 3100 is not stable, auxiliary power supply 3230 can supply power to SSD 3200. In one embodiment, auxiliary power supply 3230 can be located inside or outside SSD 3200. For example, auxiliary power supply 3230 can be located in the motherboard and can supply auxiliary power to SSD 3200.

[0243] Buffer memory 3240 serves as a buffer for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memory modules 3221 to 322n, or it may temporarily store metadata (e.g., a mapping table) of flash memory modules 3221 to 322n. Buffer memory 3240 may include volatile memory or non-volatile memory, such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, and non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0244] In one embodiment, each of the plurality of flash memory flashes 3221 to 322n can receive data from the SSD controller 3210 using some of the plurality of input / output lines. Here, assuming a total of eight input / output lines, the data input mode can be X8 mode when data is received through all eight input / output lines, and the data input mode can be X4 mode when data is received through only four of the eight input / output lines.

[0245] In one embodiment, when multiple flash memory modules 3221 to 322n receive data in X4 mode, it can take a longer time compared to receiving data in X8 mode. Therefore, when multiple flash memory modules 3221 to 322n receive data in X4 mode, each flash memory module 3221 to 322n can generate internal input data based on the data received through some input / output lines.

[0246] In one embodiment, each of the flash memory flashes 3221 to 322n can receive input, such that receiving commands or addresses from the SSD controller 3210 in X4 mode is distinguished from receiving data in X4 mode.

[0247] For example, when receiving a command or address from the SSD controller 3210 in X4 mode, each of the multiple flash memory flashes 3221 to 322n can receive the command or address through some input / output lines, and may not internally generate internal input commands or internal input addresses. That is, when receiving a command or address in X4 mode, the generation of internal input data by each of the flash memory flashes 3221 to 322n can be skipped.

[0248] However, when receiving data from the SSD controller 3210 in X4 mode, each of the flash memory flashes 3221 to 322n can receive data via some input / output lines and can generate internal input data based on the received data. The received data can be generated as internal input data via a multiplexer component (e.g., 175 in Figure 11).

[0249] Figure 18 This is a block diagram illustrating a user system using a storage device according to an embodiment of the present disclosure.

[0250] refer to Figure 18 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0251] Application processor 4100 can run components, operating systems (OS), or user programs included in user system 4000. In one embodiment, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0252] The memory module 4200 can be used as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile RAM or non-volatile RAM, such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, and non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In one embodiment, the application processor 4100 and the memory module 4200 may be packaged in a stacked package (POP) and then provided as a single semiconductor package.

[0253] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communication such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi communication. In one embodiment, network module 4300 may be included in application processor 4100.

[0254] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. In one embodiment, storage module 4400 can be implemented as a non-volatile semiconductor memory device, including phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. In one embodiment, storage module 4400 can be provided as a removable storage medium (i.e., a removable drive), such as a memory card of user system 4000 or an external drive.

[0255] In one embodiment, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may be configured as described above. Figure 2 and Figure 3 The memory device described above operates in the same manner. The memory module 4400 can operate in the same manner as the referenced above. Figure 1 The storage device 50 described operates in the same manner.

[0256] User interface 4500 may include an interface for inputting data or instructions to application processor 4100 or outputting data to external devices. In one embodiment, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. User interface 4500 may also include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0257] In one embodiment, the storage module 4400 may receive data from the application processor 4100 using some of the multiple input / output lines coupled to the storage module 4400. Here, assuming a total of eight input / output lines, the data input mode may be an X8 mode when data is received through all input / output lines, and an X4 mode when data is received through only four of the eight input / output lines.

[0258] In one embodiment, when the storage module 4400 receives data in X4 mode, it may take longer than when receiving data in X8 mode. Therefore, when receiving data in X4 mode, the storage module 4400 can generate internal input data based on the data received through some input / output lines.

[0259] In one embodiment, the storage module 4400 can receive input such that receiving commands or addresses from the application processor 4100 in X4 mode is distinguished from receiving data in X4 mode.

[0260] For example, when receiving commands or addresses from application processor 4100 in X4 mode, storage module 4400 can receive commands or addresses via some input / output lines and may not internally generate internal input commands or internal input addresses. That is, when receiving commands or addresses in X4 mode, the generation of internal input data by storage module 4400 can be skipped.

[0261] However, when receiving data from the application processor 4100 in X4 mode, the storage module 4400 can receive data via some input / output lines and can generate internal input data based on the received data. The received data can be generated as internal input data via a multiplexer component (e.g., 175 in Figure 11).

[0262] According to this disclosure, data input is controlled such that when data is input using only some of a large number of input / output lines, data is input in one cycle, and thus the time required for data input can be reduced.

Claims

1. A memory device, comprising: Multiple pages; Peripheral circuitry receives commands, addresses, and data from an external controller to program a page selected from the plurality of pages, and generates internal input data based on the input patterns used for the commands, addresses, and data. as well as The control logic determines whether to generate the internal input data based on the input pattern, and controls the peripheral circuitry to execute a programming operation that programs the internal input data. The control logic includes: An input start signal generator generates a first control signal based on a high-state line enable signal, the first control signal indicating that the input of the data is started, the high-state line enable signal being used to set the input mode to receive the command, the address and the data only through some of the multiple input / output lines; An input enable signal generator generates a second control signal, which indicates that a data input command has been received from the external controller, the data input command being used to command the input of the data; An input disable signal generator generates a third control signal when the data is input, the third control signal indicating that the last column of data in the selected page has been reached; and A D flip-flop, which outputs a fast mode signal based on the first control signal, the second control signal, and the third control signal, the fast mode signal being used to command the generation of the internal input data.

2. The memory device of claim 1, wherein the input mode is one of the following modes: In a first mode, the command, the address, and the data are received via all input / output lines of a plurality of input / output lines; and In the second mode, the command, the address, and the data are received only through some of the plurality of input / output lines.

3. The memory device of claim 2, wherein when the command or the address is received from the external controller in the input mode being the first mode, the peripheral circuitry performs the programming operation based on the received command or address.

4. The memory device of claim 2, wherein the peripheral circuitry generates the internal input data when the data is received from the external controller in the input mode being the second mode.

5. The memory device of claim 2, wherein when the input mode is the second mode, the peripheral circuit generates the internal input data by combining the second input data with first input data indicating the data, wherein the second input data is selected and output based on the data and the inputs of the remaining lines of the plurality of input / output lines other than some of the plurality of input / output lines.

6. A memory device, comprising: Multiple pages; A mode setter, wherein the mode setter is configured to receive commands, addresses and data from an external controller to program a page selected from the plurality of pages; An input controller that generates internal input data based on the data according to the pattern set by the pattern setter; as well as A control signal generator generates control signals that control the input controller to generate the internal input data. The control signal generator includes: An input start signal generator generates a first control signal based on a high-state line enable signal, the first control signal indicating that the input of the data is started, the high-state line enable signal being used to set the mode of receiving the command, the address and the data only through some of the multiple input / output lines; An input enable signal generator generates a second control signal, which indicates that a data input command has been received from the external controller, the data input command being used to command the input of the data; An input disable signal generator generates a third control signal when the data is input, the third control signal indicating that the last column of data in the selected page has been reached; and A D flip-flop, which outputs a fast mode signal based on the first control signal, the second control signal, and the third control signal, the fast mode signal being used to command the generation of the internal input data.

7. The memory device of claim 6, wherein the mode setter outputs the line enable signal for setting one of the following modes: In a first mode, the command, the address, and the data are received via all input / output lines of a plurality of input / output lines; and In the second mode, the command, the address, and the data are received only through some of the plurality of input / output lines.

8. The memory device of claim 7, wherein the mode setter outputs the line enable signal in the high state to the control signal generator to set the second mode.

9. The memory device of claim 6, wherein the fast mode signal indicates the start and end of the data input.

10. The memory device of claim 6, wherein the input start signal generator outputs the first control signal to the input pin of the D flip-flop.

11. The memory device of claim 6, wherein the input enable signal generator outputs the second control signal to the clock pin of the D flip-flop.

12. The memory device of claim 11, wherein the D flip-flop enables the fast mode signal on the rising edge of the second control signal.

13. The memory device of claim 6, wherein the input disable signal generator outputs the third control signal to the reset pin of the D flip-flop.

14. The memory device of claim 13, wherein the D flip-flop disables the fast mode signal on the rising edge of the third control signal.

15. The memory device of claim 6, wherein when a control signal in a high state is received from the control signal generator, the input controller generates the internal input data by combining the second input data with first input data indicating the data, wherein the second input data is selected and output based on the data and the inputs of the remaining lines of the plurality of input / output lines other than some of the plurality of input / output lines.

16. A method of operating a memory device, comprising: A mode is set up in which commands, addresses, and data are received from an external controller to program a page selected from multiple pages; The data is received based on the set pattern; Control signals are generated according to the set mode, and internal input data is generated based on the data. as well as The internal input data is generated based on the control signal. The generation of the control signal includes: A first control signal is generated based on a line enable signal that is in a high state. The first control signal indicates that the input of the data is initiated. The line enable signal in the high state is used to set the mode of receiving the command, the address and the data only through some of the multiple input / output lines. A second control signal is generated, indicating that a data input command has been received from the external controller, the data input command being used to command the input of the data; When the data is input, a third control signal is generated, indicating that the last column of data in the selected page has been reached; and A fast mode signal is output based on the first control signal, the second control signal, and the third control signal. The fast mode signal is used to command the generation of the internal input data.

17. The method of claim 16, wherein setting the mode comprises: The mode is set to a first mode, in which the command, the address, and the data are received through all input / output lines of the plurality of input / output lines; or The mode is set to a second mode, in which the command, the address, and the data are received only through some of the plurality of input / output lines.

18. The method of claim 17, wherein generating the control signal comprises: The fast mode signal is generated when the data is received in the second mode, and the fast mode signal indicates the start and end of the data input.

19. The method of claim 17, wherein generating the internal input data comprises: When the control signal is generated in a high state in the second mode, the internal input data is generated by combining the second input data with the first input data indicating the data, wherein the second input data is selected and output based on the data and the input of the remaining lines of the plurality of input / output lines other than some of the plurality of input / output lines.

Images