Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a substrate having a plurality of dummy gate structures; forming an initial dielectric layer on the substrate, the initial dielectric layer being located on the sidewall surface of the dummy gate structures; etching the initial dielectric layer to form a dielectric layer, wherein the top surface of the dielectric layer is lower than the top surface of the dummy gate structures; removing the dummy gate structures to form a first opening in the dielectric layer; forming a gate structure material film in the first opening and on the surface of the dielectric layer; and planarizing the gate structure material film until the top surface of the dielectric layer is exposed to form a gate structure. This method is beneficial for improving the performance of the formed semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] As semiconductor device sizes shrink, more and more device units are integrated per unit area, leading to increased device density and smaller inter-device dimensions. This, in turn, increases manufacturing complexity. With the shrinking critical dimension (CD) of integrated circuits, a "back-gate process" is typically used to form the metal gate. This process requires forming a gate opening in the dielectric layer and filling that opening with gate material.

[0003] However, controlling the height of existing metal gates is difficult, resulting in poor height uniformity and potentially leading to inconsistent resistance and threshold voltage drift among different metal gates. Furthermore, in self-aligned contact hole formation processes, the fill material in the planarized contact hole typically stops at the protective layer on the metal gate. Inconsistent metal gate heights can also result in poor uniformity of the self-aligned contact hole, ultimately leading to poor performance of the resulting semiconductor device.

[0004] Therefore, the performance of existing semiconductor devices is poor. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having a plurality of dummy gate structures; forming an initial dielectric layer on the substrate, the initial dielectric layer being located on the sidewall surface of the dummy gate structures; etching the initial dielectric layer to form a dielectric layer, wherein the top surface of the dielectric layer is lower than the top surface of the dummy gate structures; removing the dummy gate structures to form a first opening in the dielectric layer; forming a gate structure material film in the first opening and on the surface of the dielectric layer; and planarizing the gate structure material film until the top surface of the dielectric layer is exposed to form a gate structure.

[0007] Optionally, the etching process for the initial dielectric layer is remote plasma chemical etching; the parameters of the remote plasma chemical etching process include: the gas includes chlorine-containing gas, the power is 200 watts to 700 watts, and the time is 20 seconds to 120 seconds.

[0008] Optionally, the method for forming the initial dielectric layer includes: forming a dielectric material film on the substrate and the dummy gate structure; planarizing the dielectric material film until the top surface of the dummy gate structure is exposed, thereby forming the initial dielectric layer from the dielectric material film.

[0009] Optionally, the dummy gate structure includes: a dummy gate dielectric layer located on the substrate surface, a dummy gate layer located on the surface of the dummy gate dielectric layer, and a protective layer located on the surface of the dummy gate layer; the planarization process is performed until the top surface of the dummy gate layer is exposed.

[0010] Optionally, the method for forming the dielectric material film includes: forming a first dielectric material film on the surface of the substrate, the first dielectric material film being located on the sidewall surface of the dummy gate structure and exposing the top surface of the dummy gate structure; and forming a second dielectric material film on the surface of the first dielectric material film and the dummy gate structure.

[0011] Optionally, it further includes: after forming the first dielectric material film and before forming the second dielectric material film, etching the first dielectric material film and the dummy gate structure until the substrate surface is exposed, forming a second opening in the first dielectric material film and the dummy gate structure, and the second opening penetrating the dummy gate structure along a direction perpendicular to the extension of the dummy gate structure; the second dielectric material film filling the second opening.

[0012] Optionally, it further includes: after forming the second opening and before forming the second dielectric material film, forming a third dielectric material film on the surface exposed by the second opening and the surface of the first dielectric material film, wherein the third dielectric material film and the first dielectric material film are made of different materials, and the materials of the third dielectric material film and the second dielectric material film are different; the second dielectric material film is located on the surface of the third dielectric material film.

[0013] Optionally, the first dielectric film and the second dielectric film are made of the same material; the materials of the first dielectric film and the second dielectric film include: silicon oxide, silicon nitride, silicon carbide nitride, silicon boroide nitride, silicon carbide nitride, or silicon oxynitride.

[0014] Optionally, the material of the third dielectric material film includes: silicon oxide, silicon nitride, silicon carbide nitride, silicon boroide nitride, silicon carbide nitride, or silicon oxynitride.

[0015] Optionally, the sidewall surface of the dummy gate structure further has an initial sidewall structure; the method of forming the semiconductor structure further includes: after forming the dielectric layer and before removing the dummy gate structure, forming a sacrificial structure on the surface of the dielectric layer, the sacrificial structure exposing the top surface of the dummy gate structure.

[0016] Optionally, during the formation of the sacrificial structure, the initial sidewall structure is also formed into a sidewall structure; the method for forming the sacrificial structure and the sidewall structure includes: forming a sacrificial structure material film on the surfaces of the dummy gate structure, the dielectric layer, and the initial sidewall structure; performing a smoothing process until the top surfaces of the dummy gate structure and the initial sidewall structure are exposed, so that the sacrificial structure material film forms a sacrificial structure and the initial sidewall structure forms a sidewall structure; after forming the sidewall structure and the sacrificial structure, removing the sacrificial structure.

[0017] Optionally, the initial sidewall structure includes: an adjacent first sidewall and a second sidewall located between the first sidewalls; the material of the first sidewall includes: silicon oxide or a low-k dielectric material; the material of the second sidewall includes: a low-k dielectric material.

[0018] Optionally, the method for forming the sacrificial structure material film includes: forming a first sacrificial material film on the surfaces of the dummy gate structure, the dielectric layer, and the initial sidewall structure; forming a second sacrificial material film on the surface of the first sacrificial material film, wherein the materials of the first sacrificial material film and the second sacrificial material film are different.

[0019] Optionally, the planarization process includes: using a first planarization process to etch the second sacrificial material film until the top surface of the first sacrificial material film is exposed; using a first etching process to etch the first sacrificial material film and remove the remaining second sacrificial material film; using a second etching process to etch the first sacrificial material film; and using a second planarization process to etch the remaining first sacrificial material film and the initial sidewall structure to form the sacrificial structure and the sidewall structure.

[0020] Optionally, the first planarization process is a chemical mechanical polishing process.

[0021] Optionally, the etching selectivity ratio of the first etching process for the first sacrificial material film and the second sacrificial material film ranges from 0.9:1 to 1.3:1.

[0022] Optionally, the etching rate of the second etching process on the first sacrificial material film is positively correlated with the thickness of the first sacrificial material film; the parameters of the second etching process include: the gas includes CH3F, CF4, Cl2, H2 and an inert gas, the inert gas includes He or Ar, the pressure is 2 mTorr to 10 mTorr, the power is 300 watts to 1000 watts, the temperature is 20 degrees Celsius to 50 degrees Celsius, and the temperature compensation range is 3 degrees Celsius to 10 degrees Celsius.

[0023] Optionally, the second planarization process is a chemical mechanical polishing process.

[0024] Optionally, the material of the first sacrificial material film is the same as the material of the dummy gate layer; the materials of the first sacrificial material film and the dummy gate layer include: amorphous silicon, polycrystalline silicon, monocrystalline silicon, or amorphous carbon.

[0025] Optionally, the sacrificial structure is removed during the process of removing the dummy gate structure.

[0026] Optionally, the dielectric layer between adjacent sidewall structures has a groove; the method for forming the gate structure material film includes: forming a high-K dielectric material film in the first opening, the groove, the surface of the dielectric layer, and the surface of the sidewall structure, wherein the high-K dielectric material film fills the first opening and the groove; forming a power function material film on the surface of the high-K dielectric material film; and forming a gate material film on the surface of the power function material film.

[0027] Optionally, the planarization process forms a high-k dielectric layer from the high-k dielectric material film, a power function layer from the work function material film, and a gate layer from the gate material film. The high-k dielectric layer, the work function layer, and the gate layer constitute the gate structure.

[0028] Optionally, the substrate includes: a substrate, a fin located on the surface of the substrate, and an isolation layer, the isolation layer covering a portion of the fin sidewall surface; the dummy gate structure is located on the surface of the isolation layer and spans the fin. Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] In the semiconductor structure formation method provided by the present invention, on the one hand, by etching the initial dielectric layer to achieve good height uniformity of the formed dielectric layer, the height of the dielectric layer determines the height of the gate structure during the planarization process of the gate structure material film. A dielectric layer with good height uniformity is beneficial for improving the height uniformity of the formed gate structure. On the other hand, the planarization process stops when the top surface of the dielectric layer is exposed, i.e., when the dielectric layer material is captured as a stop signal for the planarization process. Since the dielectric layer occupies a large area proportion in the entire film layer, the equipment can capture a strong corresponding signal generated by the dielectric layer material, thereby improving the accuracy of the planarization process and resulting in good height uniformity of the gate structure formed by planarizing the gate structure material film.

[0030] Furthermore, the etching process of the initial dielectric layer is remote plasma chemical etching. This etching process is less sensitive to differences in device density regions, that is, the difference in etching rate of materials in different device density regions is small. This results in better height uniformity of the dielectric layer formed after etching the initial dielectric layer, thereby planarizing the gate structure material film. The process based on the dielectric layer is beneficial to improving the height uniformity of the formed gate structure.

[0031] Furthermore, the second sacrificial material film is etched through a first planarization process until the surface of the first sacrificial material film is exposed. The exposed part of the surface of the first sacrificial material film is etched so that the recesses of the first sacrificial material film are covered by the second sacrificial material film. The first planarization process can reduce the height difference between the exposed surfaces of the first and second sacrificial material films, thereby improving the height uniformity of the sidewall structure formed after the planarization process, and further improving the overall height uniformity of the gate structure material film formed subsequently.

[0032] Furthermore, the first etching process etches the first sacrificial material film and removes the remaining second sacrificial material film. Since the first etching process has a relatively small selection range for etching the first and second sacrificial material films, on the one hand, removing the second sacrificial material film is beneficial for the subsequent second etching process to etch the exposed single material first sacrificial material film; on the other hand, after the first etching process, the surface height uniformity of the remaining first sacrificial material film is improved, which is beneficial for improving the height uniformity of the sidewall structure formed after the smoothing process, and thus for improving the overall height uniformity of the gate structure material film formed subsequently.

[0033] Furthermore, the remaining first sacrificial material film is etched through a second etching process. Since the second etching process can obtain the thickness of the material to be etched and adjust the etching parameters for materials of different thicknesses, especially by controlling the temperature, it can achieve a positively correlated etching rate for materials of different thicknesses. That is, the second etching process can reduce the height difference of the first sacrificial material film, so that the height uniformity of the surface exposed before the subsequent second planarization process is better. This is beneficial to improving the height uniformity of the sidewall structure formed after the planarization process, and thus beneficial to improving the overall height uniformity of the gate structure material film formed subsequently.

[0034] Furthermore, the method for forming the semiconductor structure further includes: after forming the second opening in the first dielectric material film and the dummy gate structure, and before forming the second dielectric material film, forming a third dielectric material film on the surface exposed by the second opening and the surface of the first dielectric material film. Since the stress of the third dielectric material film is less than that of the second dielectric material film, the third dielectric material film with lower stress is beneficial to reducing the probability of crystallization of the dummy gate structure. Attached Figure Description

[0035] Figures 1 to 4 This is a schematic diagram of a semiconductor structure.

[0036] Figures 5 to 24 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0037] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0038] First, the reasons for the poor performance of existing semiconductor structures will be explained in detail with reference to the accompanying drawings. Figures 1 to 4 This is a schematic diagram of the steps involved in forming an existing semiconductor structure.

[0039] Please refer to Figure 1 A substrate is provided, the substrate including a substrate 100 and a fin 101 located on the surface of the substrate 100 and an isolation layer (not shown in the figure), the isolation layer covering a portion of the sidewall surface of the fin 101, the substrate having a dummy gate structure 110 spanning the fin 101, the dummy gate structure 110 having sidewall structures 120 on both sides of its sidewall surface.

[0040] Please refer to Figure 2 A dielectric layer 130 is formed on the substrate, and the dielectric layer 130 is located on the sidewall surface of the sidewall structure 120.

[0041] Please refer to Figure 3 Remove the pseudo-gate structure 110 and form a gate opening 140 in the dielectric layer 130.

[0042] Please refer to Figure 4 A gate material film (not shown) is formed in the gate opening 140 and on the surface of the dielectric layer 130 and the sidewall structure 120, the gate material film filling the gate opening 140; the gate material film is planarized until the top surface of the sidewall structure 120 is exposed, and a gate structure 160 is formed in the gate opening 140.

[0043] In the above method, by using the height of the sidewall structure 120 as a reference for planarizing the gate material film, it is beneficial to improve the height uniformity of the formed gate structure 160.

[0044] However, on the one hand, the removal of the dummy gate structure 110 not only etches the material of the dummy gate structure 110, but also physically etches damage the exposed sidewall structure 120. Furthermore, the substrate has different device density regions, resulting in significant differences in the amount of etching damage to the sidewall structure 120 in different regions. This leads to poor uniformity of the top surface height of the sidewall structure 120 after removing the dummy gate structure 110, consequently resulting in poor uniformity of the height of the gate structure formed, which is determined by the height of the sidewall structure 120. On the other hand, the planarization process uses the capture of the sidewall structure 120 material as a stop signal. Since the sidewall structure 120 occupies a relatively small area in the entire film layer, the corresponding signal generated by the device capturing the sidewall structure 120 material is weak, which is detrimental to the accuracy of the planarization process, resulting in poor uniformity of the gate structure formed by planarizing the gate material film.

[0045] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: etching the initial dielectric layer to form a dielectric layer, wherein the top surface of the dielectric layer is lower than the top surface of the dummy gate structure; removing the dummy gate structure to form a first opening within the dielectric layer; forming a gate structure material film within the first opening and on the surface of the dielectric layer; and planarizing the gate structure material film until the top surface of the dielectric layer is exposed to form a gate structure. On the one hand, the height of the dielectric layer determines the height of the gate structure, and a dielectric layer with good height uniformity is beneficial to improving the height uniformity of the formed gate structure. On the other hand, since the dielectric layer occupies a large area proportion in the entire film layer, the device can capture a stronger corresponding signal generated by the dielectric layer material, thereby improving the accuracy of the planarization process.

[0046] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0047] Figures 5 to 24 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0048] Please refer to Figures 5 to 8 , Figure 6 for Figure 5 A schematic diagram of the cross-section along the tangent direction of AA. Figure 7 for Figure 5 A schematic diagram of the cross-section along the tangent direction of BB. Figure 8 for Figure 5 A cross-sectional schematic diagram along the CC tangent direction provides a substrate (not shown) having a plurality of pseudo-gate structures 210 on the substrate.

[0049] In this embodiment, the substrate includes: a substrate 201, a fin 202 located on the surface of the substrate 201, and an isolation layer 203, wherein the isolation layer 203 covers a portion of the sidewall surface of the fin 202; the dummy gate structure 210 is located on the surface of the isolation layer 203 and spans the fin.

[0050] In this embodiment, the substrate 201 is made of silicon; the fin 202 is made of silicon.

[0051] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP. The fin material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0052] In this embodiment, the dummy gate structure 210 includes: a dummy gate dielectric layer 211 located on the substrate surface, a dummy gate layer 212 located on the surface of the dummy gate dielectric layer 211, and a protective layer 213 located on the surface of the dummy gate layer 212.

[0053] The protective layer 213 is used to protect the top surface of the dummy gate layer 212 in order to maintain the morphology of the dummy gate layer 212.

[0054] The material of the pseudo-gate dielectric layer 211 includes silicon oxide.

[0055] The material of the pseudo gate layer 212 includes polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon-germanium.

[0056] The material of the protective layer 213 includes silicon nitride, silicon oxynitride, or silicon carbide nitride.

[0057] In this embodiment, the sidewall surface of the pseudo-gate structure 210 also has an initial sidewall structure 220.

[0058] In this embodiment, the initial sidewall structure 220 includes: an adjacent first sidewall (not shown) and a second sidewall (not shown) located between the first sidewalls; the material of the first sidewall includes: silicon oxide or a low-k dielectric material; the material of the second sidewall includes: a low-k dielectric material.

[0059] It should be noted that the low-K dielectric material refers to a dielectric material with a relative permittivity of less than 3.9.

[0060] In this embodiment, the first sidewall is made of silicon oxide and the second sidewall is made of silicon nitride. The first sidewall is used to protect the second sidewall and prevent subsequent processes from damaging the second sidewall. The second sidewall is made of a low-k dielectric material, which helps to reduce parasitic capacitance and thus improve the performance of the semiconductor structure.

[0061] Next, an initial dielectric layer is formed on the substrate, the initial dielectric layer being located on the sidewall surface of the dummy gate structure 210.

[0062] In this embodiment, the method for forming the initial dielectric layer includes: forming a dielectric material film on the substrate and the dummy gate structure 210; planarizing the dielectric material film until the top surface of the dummy gate structure 210 is exposed, thereby forming the initial dielectric layer. For a detailed description of the process for forming the initial dielectric layer, please refer to [reference needed]. Figures 9 to 18 .

[0063] Please refer to Figure 9 and Figure 10 , Figure 9 and Figure 7 The view directions are the same. Figure 10 and Figure 8 With the same viewing direction, a first dielectric material film 231 is formed on the surface of the substrate, and the first dielectric material film 231 is located on the sidewall surface of the pseudo gate structure 210.

[0064] The first dielectric material film 231 provides a material layer for the subsequent formation of the initial dielectric layer, and the first dielectric material film 231 provides support for the subsequent formation of the second opening.

[0065] In this embodiment, the first dielectric material film 231 exposes the top surface of the dummy gate structure 210. In other embodiments, the first dielectric material film may also be located on the top surface of the dummy gate structure.

[0066] Specifically, in this embodiment, the sidewall surface of the dummy gate structure 210 also has an initial sidewall structure 220, and the first dielectric material film 231 is located on the sidewall surface of the initial sidewall structure 220 and exposes the top surface of the initial sidewall structure 220.

[0067] Please refer to Figure 11 and Figure 12 , Figure 11 and Figure 6 The view directions are the same. Figure 12 and Figure 8With the same viewing direction, the first dielectric material film 231 and the dummy gate structure 210 are etched until the substrate surface is exposed, and a second opening 240 is formed in the first dielectric material film 231 and the dummy gate structure 210, and the second opening 240 penetrates the dummy gate structure 210 along the extension direction perpendicular to the dummy gate structure 210.

[0068] The method for forming the second opening 240 includes: forming a mask layer (shown in the figure) on the surface of the first dielectric material film 231, the mask layer having a pattern, the size and position of the pattern corresponding to the position and size of the second opening 240; using the mask layer as a mask, etching the first dielectric material film 231 and the dummy gate structure 210 until the substrate surface is exposed, thereby forming the second opening 240.

[0069] Please refer to Figure 13 and Figure 14 , Figure 13 and Figure 11 The view directions are the same. Figure 14 and Figure 12 With the same viewing direction, after forming the second opening 240, a third dielectric material film 232 is formed on the surface exposed by the second opening 240 and the surface of the first dielectric material film 231, and the third dielectric material film 232 is made of a different material than the first dielectric material film 231.

[0070] A third dielectric material film 232 is formed on the surface exposed by the second opening 240 and on the surface of the first dielectric material film 231. Since the stress of the third dielectric material film 232 is less than the stress of the second dielectric material film formed subsequently, the third dielectric material film 232 with lower stress is beneficial to reducing the probability of crystallization of the pseudo gate structure 210, thereby improving the performance of the formed semiconductor structure.

[0071] It should be noted that the second dielectric material film is subsequently formed to fill the second opening 240.

[0072] Please refer to Figure 15 and Figure 16 , Figure 15 and Figure 13 The view directions are the same. Figure 16 and Figure 14 With the same viewing direction, a second dielectric material film 233 is formed on the surface 210 of the first dielectric material film 231 and the pseudo-gate structure, and the second dielectric material film 233 fills the second opening 240.

[0073] The second dielectric material film 233 provides a material layer for the subsequent formation of the initial dielectric layer.

[0074] Specifically, in this embodiment, after the third dielectric material film 232 is formed, the second dielectric material film 233 is formed, and the materials of the third dielectric material film 232 and the first dielectric material film 231 are different, as are the materials of the third dielectric material film 232 and the second dielectric material film 233.

[0075] The second dielectric material film 233 is located on the surface of the third dielectric material film 232.

[0076] The first dielectric material film 231 and the second dielectric material film 233 are made of the same material; the materials of the first dielectric material film 231 and the second dielectric material film 233 include: silicon oxide, silicon nitride, silicon carbide nitride, silicon boroide nitride, silicon carbide nitride, or silicon oxynitride.

[0077] The material of the third dielectric material film 232 includes: silicon oxide, silicon nitride, silicon carbide nitride, silicon boroide nitride, silicon carbide nitride, or silicon oxynitride.

[0078] In this embodiment, the first dielectric material film 231 and the second dielectric material film 233 are made of silicon oxide, and the third dielectric material film 232 is made of silicon nitride.

[0079] The first dielectric material film 231 and the second dielectric material film 233 form the dielectric material film (not shown in the figure), which together provide a material layer for the subsequent formation of the initial dielectric layer.

[0080] Since the stress of the third dielectric material film 232 is less than that of the second dielectric material film 233, the third dielectric material film 232 with lower stress is beneficial to reducing the probability of crystallization of the pseudo gate structure.

[0081] Please refer to Figure 17 and Figure 18 , Figure 17 and Figure 15 The view directions are the same. Figure 18 and Figure 16 With the same viewing direction, the dielectric material film is planarized until the top surface of the dummy gate structure 210 is exposed, so that the dielectric material film forms the initial dielectric layer 240.

[0082] In this embodiment, the dummy gate structure 210 includes a dummy gate dielectric layer 211, a dummy gate layer 212, and a protective layer 213. The planarization process stops at the position where the top surface of the dummy gate layer 212 is exposed.

[0083] Through the planarization process, the first dielectric material film 231 is formed into a first dielectric film 241, and the second dielectric material film 233 is formed into a second dielectric film 243. The initial dielectric layer 240 includes the first dielectric film 241 and the second dielectric film 243.

[0084] Specifically, in this embodiment, the planarization process, during the etching of the first dielectric material film 231 and the second dielectric material film 233, also etches the third dielectric material film 232, the top surface of the third dielectric material film 232 being flush with the top surface of the initial dielectric layer 240.

[0085] In this embodiment, the planarization process results in a smooth surface of the initial dielectric layer 240, which is beneficial for subsequent etching of the initial dielectric layer 240 and results in a better uniformity of the height of the top surface of the dielectric layer 240.

[0086] Please refer to Figure 19 After the initial dielectric layer 240 is formed, the initial dielectric layer 240 is etched to form a dielectric layer 250, and the top surface of the dielectric layer 250 is lower than the top surface of the pseudo gate structure 210.

[0087] Specifically, the top surface of the dielectric layer 250 is lower than the top surface of the dummy gate layer 212.

[0088] The etching process for the initial dielectric layer 240 is remote plasma chemical etching; the parameters of the remote plasma chemical etching process include: gas including chlorine gas, power of 200 watts to 700 watts, and time of 20 seconds to 120 seconds.

[0089] The etching process is less sensitive to differences in device density regions, meaning that the etching rate of materials in different device density regions is relatively small. This results in better height uniformity of the dielectric layer 250 formed after etching the initial dielectric layer 240. Consequently, during the subsequent planarization of the gate structure material film to form the gate structure, the height of the dielectric layer 250 determines the height of the gate structure. A dielectric layer 250 with better height uniformity is beneficial for improving the height uniformity of the formed gate structure.

[0090] Next, a sacrificial structure is formed on the surface of the dielectric layer 250, which exposes the top surface of the dummy gate structure 210.

[0091] In this embodiment, during the formation of the sacrificial structure, the initial sidewall structure is also formed into a sidewall structure. For details on the formation process of the sacrificial structure and the sidewall structure, please refer to [reference needed]. Figures 20 to 21 .

[0092] Please refer to Figure 20A sacrificial structure material film is formed on the surfaces of the pseudo gate structure 210, the dielectric layer 250, and the initial sidewall structure 220.

[0093] The sacrificial structure material film provides a material layer for the subsequent formation of the sacrificial structure.

[0094] The method for forming the sacrificial structure material film includes: forming a first sacrificial material film 261 on the surfaces of the dummy gate structure 210, the dielectric layer 250, and the initial sidewall structure 220; forming a second sacrificial material film 262 on the surface of the first sacrificial material film 261, wherein the materials of the first sacrificial material film 261 and the second sacrificial material film 262 are different.

[0095] Specifically, the top surface of the first sacrificial material film 261 is higher than the top surface of the dummy gate layer 212.

[0096] The sacrificial material membrane includes a first sacrificial material membrane 261 and a second sacrificial material membrane 262, and the first sacrificial material membrane 261 and the second sacrificial material membrane 262 are made of different materials. Subsequently, by reasonably selecting a process, the two membrane layers with different materials are ground flat, which can improve the uniformity of the overall height of the membrane layers formed on the substrate.

[0097] Please refer to Figure 21 The material is ground smooth until the top surfaces of the dummy gate structure 210 and the initial sidewall structure 220 are exposed, so that the sacrificial structure material film forms the sacrificial structure 270 and the initial sidewall structure 220 forms the sidewall structure 221.

[0098] In this embodiment, the planarization process includes: using a first planarization process to etch the second sacrificial material film 262 until the top surface of the first sacrificial material film 261 is exposed; using a first etching process to etch the first sacrificial material film 261 and remove the remaining second sacrificial material film 262; using a second etching process to etch the first sacrificial material film 261; and using a second planarization process to etch the remaining first sacrificial material film 261 and the initial sidewall structure 220 to form the sacrificial structure 270 and the sidewall structure 221.

[0099] Through the grinding process, the sacrificial structural material film is formed into a sacrificial structure 270, and the initial sidewall structure is formed into a sidewall structure 221, with the top surface of the sacrificial structure 270 being flush with the top surface of the sidewall structure 221.

[0100] The first planarization process is a chemical mechanical polishing process.

[0101] The second sacrificial material film 262 is etched by the first planarization process, which etches a portion of the exposed surface of the first sacrificial material film 261, so that the recesses of the first sacrificial material film 261 are covered by the second sacrificial material film 262. The first planarization process can reduce the height difference of the overall exposed surfaces of the first sacrificial material film 261 and the second sacrificial material film 262, thereby improving the height uniformity of the sidewall structure 221 formed after the planarization process, and further improving the overall height uniformity of the gate structure material film formed subsequently.

[0102] The etching selectivity ratio of the first etching process for the first sacrificial material film 261 and the second sacrificial material film 262 ranges from 0.9:1 to 1.3:1.

[0103] The first etching process etches the first sacrificial material film 261 and removes the remaining second sacrificial material film 262. Since the first etching process has a relatively small selection range for etching the first sacrificial material film 261 and the second sacrificial material film 262, on the one hand, removing the second sacrificial material film 262 is beneficial for the subsequent second etching process 261 to etch the exposed single material first sacrificial material film 261; on the other hand, after the first etching process, the surface height uniformity of the remaining first sacrificial material film 261 is improved, which is beneficial for improving the height uniformity of the sidewall structure formed after the smoothing process, and further beneficial for improving the overall height uniformity of the gate structure material film formed subsequently.

[0104] The etching rate of the second etching process on the first sacrificial material film 261 is positively correlated with the thickness of the first sacrificial material film 261; the parameters of the second etching process are: the gas includes CH3F, CF4, Cl2, H2 and an inert gas, the inert gas includes He or Ar, the pressure is 2 mTorr to 10 mTorr, the power is 300 watts to 1000 watts, the temperature is 20 degrees Celsius to 50 degrees Celsius, and the temperature compensation range is 3 degrees Celsius to 10 degrees Celsius.

[0105] Since the second etching process can obtain the thickness of the material to be etched, and adjust the etching parameters for materials of different thicknesses, especially by controlling the temperature, it can achieve etching at a positively correlated rate for materials of different thicknesses. That is, the second etching process can reduce the height difference of the first sacrificial material film 261, so that the height uniformity of the surface exposed before the subsequent second planarization process is better, which is conducive to improving the height uniformity of the sidewall structure formed after the planarization process, and further conducive to improving the overall height uniformity of the gate structure material film formed subsequently.

[0106] The second planarization process is a chemical mechanical polishing process.

[0107] After the first planarization process, the first etching process, and the second etching process, the second dielectric material film 262 has been removed. Meanwhile, the overall height uniformity of the remaining first dielectric material film 261 surface is good. By etching the first dielectric material film 261 through the second planarization process, the overall height uniformity of the first dielectric material film 261 surface can be further improved. That is, through the planarization process, the overall height uniformity of the surface of the sacrificial structure 270 is greatly improved. Furthermore, since the top surface of the sidewall structure 221 is flush with the top surface of the sacrificial structure 270, the surface height uniformity of the sidewall structure 221 is good.

[0108] The material of the first sacrificial material film 261 is the same as that of the dummy gate layer 212; the material of the first sacrificial material film 261 includes amorphous silicon, polycrystalline silicon, monocrystalline silicon, or amorphous carbon. In this embodiment, the material of the first sacrificial material film 261 is polycrystalline silicon.

[0109] The material of the second sacrificial material film 262 includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide nitride. In this embodiment, the material of the second sacrificial material film 262 is silicon oxide.

[0110] Please refer to Figure 22 After forming the dielectric layer 250, the dummy gate structure 210 is removed, and a first opening 280 is formed in the dielectric layer 250.

[0111] In this embodiment, after the dielectric layer 250 is formed, and after the initial sidewall structure 220 is ground to form the sidewall structure 221, the uniformity of the overall height of the sidewall structure 221 surface is improved, which is beneficial to the uniformity of the overall height of the gate structure material film formed on the sidewall structure 221 surface.

[0112] Please continue to refer to this. Figure 22 During the process of removing the pseudo-gate structure 210, the sacrificial structure 270 is also removed.

[0113] Specifically, removing the pseudo gate structure 210 refers to removing the pseudo gate layer 212. Since the pseudo gate layer 212 and the first sacrificial material film 261 are made of the same material, and the sacrificial structure 270 is formed by the first sacrificial material film 261, the sacrificial structure 270 is removed during the process of removing the pseudo gate structure 210, which helps to reduce process steps and improve process efficiency.

[0114] It should be noted that, after removing the sacrificial structure 270, a groove 271 is formed in the medium layer 250 between adjacent sidewall structures 221.

[0115] Please refer to Figure 23A gate structure material film 290 is formed inside the first opening 280 and on the surface of the dielectric layer 250.

[0116] In this embodiment, a groove 271 is provided in the dielectric layer 250 between adjacent sidewall structures 221; the method for forming the gate structure material film 290 includes: forming a high-K dielectric material film (not shown in the figure) in the first opening 280, the groove 271, the surface of the dielectric layer 250, and the surface of the sidewall structure 221, wherein the high-K dielectric material film fills the first opening 280 and the groove 271; forming a work function material film (not shown in the figure) on the surface of the high-K dielectric material film; and forming a gate material film (not shown in the figure) on the surface of the work function material film.

[0117] Since the top surface of the sidewall structure 221 has good height uniformity, it is beneficial to improve the overall height uniformity of the gate structure material film 290, which in turn is beneficial to improve the overall height uniformity of the gate structure formed by the subsequent planarization process.

[0118] Please refer to Figure 24 The gate structure material film 290 is planarized until the top surface of the dielectric layer 250 is exposed to form the gate structure 291.

[0119] Specifically, the planarization process forms a high-K dielectric layer (not shown in the figure) from the high-K dielectric material film, a power function layer (not shown in the figure) from the work function material film, and a gate layer (not shown in the figure) from the gate material film. The high-K dielectric layer, the work function layer, and the gate layer constitute the gate structure 291.

[0120] It should be noted that the high K refers to a relative permittivity greater than 3.9.

[0121] The height of the dielectric layer 250 determines the height of the gate structure 291. A dielectric layer 250 with good height uniformity is beneficial for improving the height uniformity of the formed gate structure 291. On the other hand, the planarization process ends when the top surface of the dielectric layer 250 is exposed; that is, the dielectric layer 250 material is captured as a stop signal for the planarization process. Since the dielectric layer 250 occupies a large area in the entire film layer, the equipment can capture a strong corresponding signal generated by the dielectric layer 250 material, thereby improving the accuracy of the planarization process and resulting in better height uniformity of the gate structure 291 formed by planarizing the gate structure material film 290.

[0122] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, on which a plurality of pseudo-gate structures are provided; An initial dielectric layer is formed on the substrate, the initial dielectric layer being located on the sidewall surface of the dummy gate structure; The initial dielectric layer is etched by remote plasma chemical etching to form a dielectric layer. The height of the dielectric layer determines the height of the gate structure, and the top surface of the dielectric layer is lower than the top surface of the dummy gate structure. Remove the dummy gate structure and form a first opening in the dielectric layer; A gate structure material film is formed inside the first opening and on the surface of the dielectric layer; In the step of planarizing the gate structure material film until the top surface of the dielectric layer is exposed to form a gate structure, the dielectric layer material is grabbed as a stop signal for the planarization process. The forming method further includes: after forming the dielectric layer and before removing the dummy gate structure, forming a sacrificial structure on the surface of the dielectric layer, the sacrificial structure exposing the top surface of the dummy gate structure; the step of forming the sacrificial structure on the surface of the dielectric layer includes: forming a sacrificial structure material film on the dummy gate structure and the surface of the dielectric layer, the sacrificial structure material film including: a first sacrificial material film on the surface of the dummy gate structure and the dielectric layer; a second sacrificial material film on the surface of the first sacrificial material film, the top surface of the first sacrificial material film being higher than the top surface of the dummy gate layer, and the materials of the first sacrificial material film and the second sacrificial material film being different; performing a polishing process until the top surface of the dummy gate structure is exposed, so that the sacrificial structure material film forms a sacrificial structure; The step of removing the dummy gate structure includes: removing the sacrificial structure during the process of removing the dummy gate structure, and forming a groove in the dielectric layer between adjacent sidewall structures; The step of forming a gate structure material film within the first opening and on the surface of the dielectric layer includes: forming a gate structure material film within the first opening, within the groove, and on the surface of the dielectric layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The etching process for the initial dielectric layer is remote plasma chemical etching; The parameters of the remote plasma chemical etching process include: gas including chlorine-containing gas, power of 200 watts to 700 watts, and time of 20 seconds to 120 seconds.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the initial dielectric layer includes: forming a dielectric material film on the substrate and the dummy gate structure; planarizing the dielectric material film until the top surface of the dummy gate structure is exposed, thereby forming the initial dielectric layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The dummy gate structure includes: a dummy gate dielectric layer located on the substrate surface, a dummy gate layer located on the surface of the dummy gate dielectric layer, and a protective layer located on the surface of the dummy gate layer; the planarization process is performed until the top surface of the dummy gate layer is exposed.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method for forming the dielectric material film includes: forming a first dielectric material film on the surface of the substrate, the first dielectric material film being located on the sidewall surface of the dummy gate structure and exposing the top surface of the dummy gate structure; and forming a second dielectric material film on the surface of the first dielectric material film and the dummy gate structure.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, Also includes: After the first dielectric material film is formed and before the second dielectric material film is formed, the first dielectric material film and the dummy gate structure are etched until the substrate surface is exposed. A second opening is formed in the first dielectric material film and the dummy gate structure, and the second opening penetrates the dummy gate structure along the direction perpendicular to the extension of the dummy gate structure. The second dielectric material film fills the second opening.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, Also includes: After the second opening is formed and before the second dielectric material film is formed, a third dielectric material film is formed on the surface exposed by the second opening and on the surface of the first dielectric material film, and the materials of the third dielectric material film and the first dielectric material film are different; the materials of the third dielectric material film and the second dielectric material film are different; the second dielectric material film is located on the surface of the third dielectric material film.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The first dielectric material film and the second dielectric material film are made of the same material; the materials of the first dielectric material film and the second dielectric material film include: silicon oxide, silicon nitride, silicon carbide nitride, silicon boroide nitride, silicon carbide nitride, or silicon oxynitride.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The materials of the third dielectric material film include: silicon oxide, silicon nitride, silicon carbide nitride, silicon boroide nitride, silicon carbide nitride, or silicon oxynitride.

10. The method for forming a semiconductor structure as described in claim 4, characterized in that, The sidewall surface of the dummy gate structure also has an initial sidewall structure; the method of forming the semiconductor structure further includes: after forming the dielectric layer and before removing the dummy gate structure, forming a sacrificial structure on the surface of the dielectric layer, the sacrificial structure exposing the top surface of the dummy gate structure.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, During the formation of the sacrificial structure, the initial sidewall structure is also formed into a sidewall structure. The method for forming the sacrificial structure and the sidewall structure includes: forming a sacrificial structure material film on the surfaces of the dummy gate structure, the dielectric layer, and the initial sidewall structure; performing a smoothing process until the top surfaces of the dummy gate structure and the initial sidewall structure are exposed, so that the sacrificial structure material film forms the sacrificial structure and the initial sidewall structure forms the sidewall structure; and removing the sacrificial structure after forming the sidewall structure and the sacrificial structure.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, The initial sidewall structure includes: an adjacent first sidewall and a second sidewall located between the first sidewalls; the material of the first sidewall includes: silicon oxide or a low-k dielectric material; the material of the second sidewall includes: a low-k dielectric material.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method for forming the sacrificial structure material film includes: forming a first sacrificial material film on the surfaces of the dummy gate structure, the dielectric layer, and the initial sidewall structure; forming a second sacrificial material film on the surface of the first sacrificial material film, wherein the materials of the first sacrificial material film and the second sacrificial material film are different.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The planarization process includes: using a first planarization process to etch the second sacrificial material film until the top surface of the first sacrificial material film is exposed; using a first etching process to etch the first sacrificial material film and remove the remaining second sacrificial material film; using a second etching process to etch the first sacrificial material film; and using a second planarization process to etch the remaining first sacrificial material film and the initial sidewall structure to form the sacrificial structure and the sidewall structure.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The first planarization process is a chemical mechanical polishing process.

16. The method for forming a semiconductor structure as described in claim 14, characterized in that, The etching selectivity ratio of the first etching process for the first sacrificial material film and the second sacrificial material film ranges from 0.9:1 to 1.3:

1.

17. The method for forming a semiconductor structure as described in claim 14, characterized in that, The etching rate of the second etching process on the first sacrificial material film is positively correlated with the thickness of the first sacrificial material film; the parameters of the second etching process include: the gas includes CH3F, CF4, Cl2, H2 and an inert gas, the inert gas includes He or Ar, the pressure is 2 mTorr to 10 mTorr, the power is 300 watts to 1000 watts, the temperature is 20 degrees Celsius to 50 degrees Celsius, and the temperature compensation range is 3 degrees Celsius to 10 degrees Celsius.

18. The method for forming a semiconductor structure as described in claim 14, characterized in that, The second planarization process is a chemical mechanical polishing process.

19. The method for forming a semiconductor structure as described in claim 14, characterized in that, The material of the first sacrificial material film is the same as the material of the dummy gate layer; the materials of the first sacrificial material film and the dummy gate layer include: amorphous silicon, polycrystalline silicon, monocrystalline silicon or amorphous carbon.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, During the removal of the dummy gate structure, the sacrificial structure is also removed.

21. The method for forming a semiconductor structure as described in claim 11, characterized in that, The dielectric layer between adjacent sidewall structures has a groove; the method for forming the gate structure material film includes: forming a high-K dielectric material film in the first opening, the groove, the surface of the dielectric layer, and the surface of the sidewall structure, wherein the high-K dielectric material film fills the first opening and the groove; forming a power function material film on the surface of the high-K dielectric material film; and forming a gate material film on the surface of the power function material film.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, The planarization process forms a high-k dielectric layer from the high-k dielectric material film, a power function layer from the work function material film, and a gate layer from the gate material film. The high-k dielectric layer, the work function layer, and the gate layer constitute the gate structure.

23. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate includes: a substrate, a fin located on the surface of the substrate, and an isolation layer, the isolation layer covering a portion of the sidewall surface of the fin; the dummy gate structure is located on the surface of the isolation layer and spans the fin.

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