Integrated circuit structure and method of forming the same

Abstract

Methods of forming an integrated circuit structure include forming a source / drain region of a transistor, forming a first interlayer dielectric over the source / drain region, and forming a lower source / drain contact plug over the source / drain region, and the lower source / drain contact plug is electrically coupled to the source / drain region. The lower source / drain contact plug extends into the first interlayer dielectric. The methods also include depositing an etch stop layer over the first interlayer dielectric and the lower source / drain contact plug, depositing a second interlayer dielectric over the etch stop layer; and performing an etching process to etch an upper portion of the second interlayer dielectric, the etch stop layer, and the first interlayer dielectric to form an opening, and a top surface and sidewalls of the lower source / drain contact plug are exposed to the opening; and forming an upper contact plug in the opening. Embodiments of the invention also relate to an integrated circuit structure and another integrated circuit structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuit structures and methods for manufacturing the same. Background Technology

[0002] In integrated circuit manufacturing, contact plugs are used to electrically couple to the source and drain regions and gate of transistors. Typically, source / drain contact plugs are connected to source / drain silicide regions. The formation process includes forming contact openings to expose the source / drain regions, depositing a metal layer, depositing a barrier layer over the metal layer, performing an annealing process to react the metal layer with the source / drain regions, filling the remaining contact openings with metal, and performing a chemical mechanical polishing (CMP) process to remove excess metal. Summary of the Invention

[0003] Some embodiments of the present invention provide a method for forming an integrated circuit structure, comprising: forming a source / drain region of a transistor; forming a first interlayer dielectric over the source / drain region; forming a lower source / drain contact plug over the source / drain region, wherein the lower source / drain contact plug extends into the first interlayer dielectric; depositing an etch stop layer over the first interlayer dielectric and the lower source / drain contact plug; depositing a second interlayer dielectric over the etch stop layer; performing an etching process to etch the upper portion of the second interlayer dielectric, the etch stop layer, and the first interlayer dielectric to form an opening, wherein the top surface and sidewalls of the lower source / drain contact plug are exposed to the opening; and forming an upper contact plug in the opening.

[0004] Other embodiments of the present invention provide an integrated circuit structure including: a gate stack above a semiconductor region; a source / drain region on one side of the gate stack; a source / drain silicide region above the source / drain region; a first interlayer dielectric above the source / drain silicide region; a lower source / drain contact plug above and in contact with the source / drain silicide region; an etch stop layer above the first interlayer dielectric and the lower source / drain contact plug; a second interlayer dielectric above the etch stop layer; and an upper source / drain contact plug extending through the second interlayer dielectric and the etch stop layer and into the upper portion of the first interlayer dielectric, wherein a first sidewall of the upper source / drain contact plug contacts a second sidewall of the lower source / drain contact plug.

[0005] Further embodiments of the present invention provide an integrated circuit structure including: a semiconductor region; a source / drain region extending into the semiconductor region; a first interlayer dielectric located above the source / drain region; and a first source / drain contact plug located above and electrically coupled to the source / drain region, wherein the first source / drain contact plug includes: a metal region; a metal nitride layer having a first portion surrounding the metal region; and a metal layer having a second portion surrounding the metal nitride layer; and the second source / drain contact plug includes: a first sidewall physically contacting the second sidewall of the metal region to form a vertical interface; and a bottom edge physically contacting the top edge of the metal nitride layer and the metal layer. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of the invention can be best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1 to 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B as well as Figures 11 to 20 These are perspective and cross-sectional views of the intermediate stages of forming transistors and corresponding contact plugs according to some embodiments.

[0008] Figure 21 A process flow for forming transistors and contact plugs according to some embodiments is shown. Detailed Implementation

[0009] The following disclosure provides numerous different embodiments or examples of various components for implementing the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include instances where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various embodiments. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0010] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other) element or component as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0011] A contact plug having both a top contact and a side contact with a conductive component extending downwards is provided, and a method for forming the same. According to some embodiments, a lower source / drain contact plug is formed in a first interlayer dielectric, and a second interlayer dielectric is formed above the first interlayer dielectric. An upper source / drain contact plug is then formed in the second interlayer dielectric. During the etching of the interlayer dielectric forming the contact opening for the upper source / drain contact plug, the contact opening is intentionally perpendicularly offset from the lower source / drain contact plug, and a portion of the first interlayer dielectric is etched. The sidewall portion (including a diffusion barrier) of the lower source / drain contact plug is etched. Therefore, the upper source / drain contact plug contacts not only the top surface of the lower source / drain contact plug but also the sidewall of the lower source / drain contact plug. This improves adhesion between the upper and lower source / drain contact plugs and reduces contact resistance. It is understood that, although the FinFET (Fin Field-Effect Transistor) is used as an example, other types of transistors, such as planar transistors and gate-all-around (GAA) transistors, can also employ embodiments of the present invention. Furthermore, although the source / drain contact plug is used as an example, other conductive components can also employ embodiments of the present invention, including but not limited to wires, conductive plugs, and conductive vias. The embodiments discussed herein are intended to provide examples to ensure that the subject matter of the present invention can be made or used, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. Similar reference numerals are used to denote similar elements throughout the various views and embodiments shown. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0012] Figures 1 to 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B as well as Figures 11 to 20Perspective and cross-sectional views of intermediate stages in the formation of a fin field-effect transistor (FinFET) and corresponding contact plugs according to some embodiments of the present invention are shown. The corresponding processes are also schematically reflected in, for example... Figure 21 The process flow shown is 200.

[0013] Figure 1 A perspective view of the initial structure formed on wafer 10 is shown. Wafer 10 includes a substrate 20. Substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed of other semiconductor materials. Substrate 20 may be doped with p-type or n-type dopants. Isolation regions 22, such as shallow trench isolation (STI) regions, may be formed to extend from the top surface of substrate 20 into substrate 20. The corresponding process is shown as follows. Figure 21 Process 202 in the process flow 200 shown. A portion of the substrate 20 between adjacent STI regions 22 is referred to as a semiconductor strip 24. The top surface of the semiconductor strip 24 and the top surface of the STI region 22 may be substantially flush with each other. According to some embodiments of the invention, the semiconductor strip 24 is a portion of the original substrate 20, and therefore the material of the semiconductor strip 24 is the same as the material of the substrate 20. According to an alternative embodiment of the invention, the semiconductor strip 24 is a replacement strip formed by etching a portion of the substrate 20 between the STI regions 22 to form a trench and performing an epitaxial process to grow another semiconductor material in the trench. Therefore, the semiconductor strip 24 is formed of a semiconductor material different from the material of the substrate 20. According to some embodiments, the semiconductor strip 24 is formed of silicon germanium, silicon carbide, or a group III-V compound semiconductor material.

[0014] STI region 22 may include an oxide layer of the pad semiconductor strip 24 (not shown), which may be a thermal oxide layer formed by thermal oxidation of the surface layer of the substrate 20. The oxide layer may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), etc. STI region 22 may also include a dielectric material above the oxide layer, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc.

[0015] refer to Figure 2 The STI region 22 is recessed, causing the top of the semiconductor strip 24 to protrude above the top surface 22A of the remaining portion of the STI region 22 to form a protruding fin 24'. The corresponding process is shown as follows. Figure 21 Process 204 in the process flow 200 shown. Etching can be performed using a dry etching process, for example, using NF3 and NH3 as etching gases. According to an alternative embodiment of the invention, a wet etching process is used to create the depressions in the STI region 22. For example, the etching chemicals may include a diluted HF solution.

[0016] In the embodiments shown above, semiconductor strips can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the fins, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0017] refer to Figure 3 The dummy gate stack 30 is formed to extend on the top surface and sidewalls of the (protruding) fin 24'. The corresponding process is shown as follows. Figure 21 Process 206 in process flow 200 shown. The dummy gate stack 30 may include a dummy gate dielectric (not shown) on the sidewall of the protruding fin 24', and a dummy gate electrode 34 above the corresponding dummy gate dielectric. The dummy gate dielectric may include silicon oxide. For example, polysilicon may be used to form the dummy gate electrode 34, or other materials may be used. Each dummy gate stack 30 may also include one (or more) hard mask layers 36 located above the corresponding dummy gate electrode 34. The hard mask layers 36 may be formed of silicon nitride, silicon oxide, silicon oxynitride, or multiple layers thereof. The dummy gate stack 30 may span one or more protruding fins 24' and / or STI regions 22. The dummy gate stack 30 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fin 24'.

[0018] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. The corresponding process is shown below. Figure 21 Process 206 in the process flow 200 shown. According to some embodiments of the present invention, the gate spacer 38 is formed of a dielectric material such as silicon nitride, silicon carbonitride, etc., and may have a single-layer structure or a multilayer structure including multiple dielectric layers.

[0019] Then an etching process is performed to etch the portion of the protruding fin 24' not covered by the dummy gate stack 30 and the gate spacer 38, creating a shape as shown. Figure 4 The structure is shown. The corresponding process is shown as follows. Figure 21Process 208 in process flow 200 shown. The recess can be anisotropic, and therefore the portion of fin 24' located directly beneath the dummy gate stack 30 and gate spacer 38 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 24 can be lower than the top surface 22A of the STI region 22. The space left by etching the protruding fin 24' and semiconductor strip 24 is called a recess 40. The recess 40 is located on opposite sides of the dummy gate stack 30.

[0020] Next, as Figure 5 As shown, epitaxial regions (source / drain regions) 42 are formed by selectively growing (by epitaxy) semiconductor material in the recess 40. The corresponding process is shown as follows. Figure 21 Process 210 in the process flow 200 shown. Depending on whether the generated FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type dopants can be doped in situ during the epitaxial process. For example, when the generated FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc., can be grown. Conversely, when the generated FinFET is an n-type FinFET, silicon phosphide (SiP), silicon carbon phosphide (SiCP), etc., can be grown. According to an optional embodiment of the invention, the epitaxial region 42 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiple layers thereof. After the trench 40 is filled with the epitaxial region 42, further epitaxial growth of the epitaxial region 42 causes the epitaxial region 42 to expand horizontally and can form a sectional shape. Further growth of the epitaxial region 42 can also cause adjacent epitaxial regions 42 to merge with each other. Voids (air gaps) 44 may be generated. According to some embodiments of the present invention, the formation of the epitaxial region 42 can be completed while the top surface of the epitaxial region 42 is still corrugated, or when the top surface of the merged epitaxial regions 42 has become flat. This is achieved by further growth on the epitaxial region 42, such as... Figure 6 As shown.

[0021] Following the epitaxial process, the epitaxial region 42 can be further implanted with p-type or n-type dopants to form source and drain regions, which are also indicated by reference numeral 42. According to an optional embodiment of the invention, when the epitaxial region 42 is in-situ doped with p-type or n-type dopants during epitaxy, the implantation process is skipped.

[0022] Figure 7 A perspective view of the structure after the formation of the contact etch stop layer (CESL) 46 and the interlayer dielectric (ILD) 48 is shown. The corresponding process is illustrated as follows. Figure 21Process 212 in process flow 200 shown. CESL 46 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 48 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition processes. ILD 48 can be formed from an oxygen-containing dielectric material, which can be a silicon oxide-based dielectric material, such as silicon oxide (e.g., formed using tetraethyl orthosilicate (TEOS) as a process gas), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. Planarization processes such as chemical mechanical polishing (CMP) or mechanical polishing can be performed to flush the top surfaces of ILD 48, dummy gate stack 30, and gate spacer 38 with each other.

[0023] Next, the dummy gate stack 30, including the hard mask layer 36, the dummy gate electrode 34, and the dummy gate dielectric, is replaced with a gate stack 56 including the metal gate electrode 54 and the gate dielectric 52, as follows. Figure 8A and Figure 8B As shown. The corresponding process is illustrated as follows. Figure 21 Process 214 in the process flow 200 shown. When forming the replacement gate stack 56, the hard mask layer 36 and the dummy gate electrode 34 (as shown) are first removed in one or more etching processes. Figure 7 (As shown) and a dummy gate dielectric, thereby creating trenches / openings between gate spacers 38. The top surface and sidewalls of the protruding semiconductor fins 24' are exposed to the created trenches.

[0024] Next, as Figure 8A and Figure 8B As shown, they respectively illustrate a perspective view and a cross-sectional view, forming a replacement gate dielectric layer 52 in a trench extending between gate spacers 38. Figure 8B It shows Figure 8A Reference cross-section 8B-8B is shown in the figure. According to some embodiments of the invention, each gate dielectric layer 52 includes an interface layer (IL) serving as the lower portion of the gate dielectric layer 52, which contacts the exposed surface of the corresponding protruding fin 24'. The IL may include an oxide layer, such as a silicon oxide layer, formed by a thermal oxidation, chemical oxidation, or deposition process of the protruding fin 24'. The gate dielectric layer 52 may also include a high-k dielectric layer formed above the IL. The high-k dielectric layer may include a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, etc. The dielectric constant (k value) of the high-k dielectric material is greater than 3.9 and may be greater than about 7.0. The high-k dielectric layer is formed as a conformal layer and extends on the sidewalls of the protruding fin 24' and the sidewalls of the gate spacer 38. According to some embodiments of the invention, the high-k dielectric layer is formed using ALD or CVD.

[0025] Further reference Figure 8A and Figure 8B A gate electrode 54 is formed over a gate dielectric 52. The gate electrode 54 includes stacked conductive layers. The stacked conductive layers are not shown separately, but they can be distinguished from each other. The deposition of the stacked conductive layers can be performed using conformal deposition methods such as ALD or CVD. The stacked conductive layers may include a diffusion barrier layer (sometimes called a binder layer) and one (or more) work function layers above the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN), which may (or may not) be doped with silicon. The work function layers determine the work function of the gate and include at least one layer, or multiple layers formed of different materials. The material of the work function layer is selected depending on whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer may include a TaN layer and a titanium aluminum (TiAl) layer above the TaN layer. When the FinFET is a p-type FinFET, the work function layer may include a TaN layer and a TiN layer above the TaN layer. After depositing the work function layer, a binder layer is formed, which can be another TiN layer. The binder layer can completely or partially fill the trenches left by removing the dummy gate stack.

[0026] The deposited gate dielectric and conductive layers are formed as conformal layers extending into the trench and including portions above the ILD 48. Next, if the adhesive layer does not completely fill the trench, a metal material is deposited to fill the remaining trench. For example, the metal material can be formed of tungsten or cobalt. Subsequently, a planarization process, such as CMP or mechanical polishing, is performed to remove portions of the gate dielectric layer, the stacked conductive layers, and the metal material above the ILD 48. As a result, a gate electrode 54 and a gate dielectric 52 are formed. The gate electrode 54 and the gate dielectric 52 are collectively referred to as the replacement gate stack 56. At this point, the top surfaces of the replacement gate stack 56, the gate spacer 38, the CESL 46, and the ILD 48 can be substantially coplanar.

[0027] Figure 8A and Figure 8B The formation of a (self-aligned) hard mask 58 according to some embodiments is also shown. The corresponding process is illustrated as follows. Figure 21 Process 216 in the process flow 200 shown. Forming the hard mask 58 may include performing an etching process to recess the gate stack 56, thereby forming a trench between the gate spacers 38, filling the trench with a dielectric material, and then performing a planarization process such as a CMP process or a polishing process to remove excess dielectric material. The hard mask 58 may be formed of silicon nitride, silicon oxynitride, silicon carbonitride, etc.

[0028] Figure 9A and Figure 9B A perspective view and a cross-sectional view are shown respectively when forming the source / drain contact opening 60. The corresponding process is shown as follows. Figure 21 Process 218 in the process flow 200 shown. Figure 9B It shows Figure 9A Reference cross-section 9B-9B is shown in the figure. Forming the contact opening 60 involves etching the ILD 48 to expose a portion of the underlying CESL 46, and then etching the exposed portion of the CESL 46 to expose the epitaxial region 42. According to some embodiments of the invention, such as... Figure 9A As shown, the gate spacer 38 is spaced from the nearest contact opening 60 by portions of CESL 46 and ILD 48.

[0029] refer to Figure 10A and Figure 10B This forms the silicide region 66 and the lower source / drain contact plug 70. Figure 10B It shows Figure 10A The reference cross section 10B-10B is shown. According to some embodiments, a metal layer 62 (such as a titanium or cobalt layer) is deposited, for example, using physical vapor deposition (PVD) or a similar method. Figure 10B Metal layer 62 is a conformal layer and extends to the top surface of source / drain region 42 and the sidewalls of ILD 48. A metal nitride layer (such as a titanium nitride layer) 64 is deposited as a capping layer. An annealing process is then performed to form source / drain silicide regions 66, as shown. Figure 10A and Figure 10B As shown. The corresponding process is illustrated as follows. Figure 21 Process 220 in the process flow 200 shown. Next, metal material 68 is filled into the remaining portion of the contact opening. Metal material 68 may include cobalt, tungsten, etc. Then, a planarization process such as CMP or mechanical polishing is performed to remove excess portions of metal layer 62, metal nitride layer 64, and metal material 68, leaving contact plug 70. The corresponding process is shown as follows. Figure 21 Process 220 in the process flow 200 shown. Thus, FinFET 100 is formed.

[0030] refer to Figure 11 The etch stop layer 72 and ILD 74 are deposited. The corresponding process is shown as follows. Figure 21 Process 222 in the process flow 200 shown. The etch stop layer 72 can be formed of a dielectric material such as SiN, SiCN, SiC, AlO, AlN, SiOCN, or a composite layer thereof. The formation method can include PECVD, ALD, CVD, etc.

[0031] ILD 74 is deposited over etch stop layer 72. The material and formation method of ILD 74 can be selected from the same candidate materials and formation methods used to form ILD 48. For example, ILD 74 may include silicon oxide, PSG, BSG, BPSG, etc., which contain silicon. According to some embodiments, ILD 74 is formed using PECVD, FCVD, spin coating, etc. According to optional embodiments, ILD 74 may be formed from a low-k dielectric material.

[0032] An etch mask 76, which can be three layers, is then formed. The etch mask 76 may include a bottom layer (sometimes also called the lower layer) 76BL, an intermediate layer 76ML above the bottom layer 76BL, and a top layer (sometimes also called the upper layer) 76TL above the intermediate layer 76ML. According to some embodiments, the bottom layer 76BL and the top layer 76TL are formed of photoresist, and the bottom layer 76BL is cross-linked. The intermediate layer 76ML may be formed of an inorganic material, such as a nitride (e.g., silicon nitride), an oxide oxynitride (e.g., silicon oxynitride), an oxide (e.g., silicon oxide), etc. The intermediate layer 76ML has high etch selectivity relative to the top layer 76TL and the bottom layer 76BL, and therefore the top layer 76TL can be used as an etch mask for patterning the intermediate layer 76ML, and the intermediate layer 76ML can be used as an etch mask for patterning the bottom layer 76BL. The top layer 76TL is patterned to form an opening 78, which is used to define a pattern of contact openings in the ILD 74. For example, a slag removal process can be performed using process gases H2 and N2. The pressure of the process gas can be in the range of approximately 40 mTorr to approximately 120 mTorr. The frequency of the source power can be approximately 60 MHz.

[0033] Next, the intermediate layer 76ML is etched using a patterned top layer 76TL as an etching mask, thereby extending the opening 78 into the intermediate layer 76ML. For example, process gases including CHF3, N2, and CF4 can be used to perform the etching process. The pressure of the process gases can be in the range of approximately 20 mTorr to approximately 60 mTorr. The frequency of the source power can include 60 MHz and 27 MHz. After etching through the intermediate layer 76ML, the bottom layer 76BL is further patterned while the intermediate layer 76ML is used as an etching mask. During the patterning of the bottom layer 76BL, the top layer 76TL is consumed. During the patterning of the bottom layer 76BL, the intermediate layer 76ML can be partially or completely consumed. For example, process gases including N2, H2, carbonyl sulfide (COS), and O2 can be used to perform the etching process. The pressure of the process gases can be in the range of approximately 5 mTorr to approximately 25 mTorr. The frequency of the source power can include 60 MHz and 27 MHz. In the patterning of the bottom layer 76BL, opening 78 extends downwards, exposing ILD74. The resulting structure is as follows: Figure 12 As shown.

[0034] Figure 13 The etching of ILD 74 to form source / drain contact opening 80 is shown. The corresponding process is illustrated below. Figure 21 Process 224 in the process flow 200 shown. According to some embodiments, the etching process includes a main etching process followed by an over-etching process. For example, the main etching process can be performed using a process gas comprising CF4. The pressure of the process gas can be in the range of about 5 mTorr and about 45 mTorr. The frequency of the source power can include 2 MHz and 27 MHz. For example, the main etching can extend the opening 80 to a depth in the upper part of the ILD 74 in the range of about 10 nm and about 20 nm. The main etching process has a high etch selectivity ER74 / ER76BL, where ER74 is the etch rate of the ILD 74 and ER76BL is the consumption rate of the bottom layer 76BL.

[0035] For example, an over-etch process can be performed using process gases including C4F6, O2, and Ar. The pressure of the process gas can range from approximately 5 mTorr to approximately 45 mTorr. The frequency of the source power can include 2 MHz, 27 MHz, and 60 MHz. For example, the over-etch process can extend the opening 80 to the lower part of the ILD 74, with an etching depth ranging from approximately 10 nm to approximately 30 nm. The over-etch process has lower etch selectivity for ER74 / ER76BL than the main etch. During the over-etch process, a photoresist pullback process can be performed, for example using O2 as the process gas, with the O2 pressure ranging from approximately 20 mTorr to approximately 60 mTorr. The pullback process is isotropic, thus enlarging the opening 80. This can cause the top corner portion of the ILD 74 in region 79 to be removed, and the corner to be rounded, making it easier to fill with conductive material in subsequent processes.

[0036] After exposing the etch stop layer 72, a wet cleaning process can be performed. Process gases such as N2 and H2 can also be used to perform the process. The pressure of the process gas can be in the range of approximately 40 mTorr to approximately 80 mTorr. The frequency of the source power can include 60 MHz. Next, a purification process using N2 (also known as an N2 charging process) can be performed to remove moisture from the etching chamber.

[0037] Further reference Figure 13 Etching stop layer 72. The corresponding process is shown as follows. Figure 21Process 224 in the process flow 200 shown. Etching can also be performed using process gases such as CHF3, with carrier gases such as N2 and / or Ar added. The pressure of the process gas can be in the range of approximately 70 mTorr to approximately 170 mTorr. The frequency of the source power can include 2 MHz and 60 MHz. The aforementioned purification process using N2 removes moisture from the corresponding process chamber, and therefore the contact plug 70, which might be damaged by process gases containing fluorine and water, will not be damaged in this etching process.

[0038] Figure 14 The etching process for etching ILD 48, metal layer 62, and metal nitride layer 64 is shown. The corresponding process is illustrated as follows. Figure 21 Process 226 in the process flow 200 shown. For example... Figure 13 As shown, the opening 80 has a first portion located directly above the contact plug 70, and a second portion perpendicularly offset from the contact plug 70. Etching can also be performed using process gases such as CHF3 and H2O, while carrier gases such as N2 and / or Ar can be added. The pressure of the process gas can be in the range of approximately 20 mTorr to approximately 120 mTorr. The frequency of the source power can include 60 MHz. During the etching process, as the ILD 48 is etched, the opening 80 extends into the ILD 48, thus exposing the sidewalls of the lower contact plug 70. The metal in the contact plug 70 reacts with the fluorinated process gas to form a metal fluoride, and the metal fluoride can be removed by H2O. Furthermore, the metal nitride layer 64 can also be etched by the process gas. Therefore, as... Figure 14 As shown, the sidewalls of the metal region 68, which may be formed of cobalt or other metals, are exposed through the opening 80. In the previous etching process, the metal region 68 was also etched vertically and laterally, the top surface of the metal region 68 was lowered, the sidewalls of the metal region 68 were laterally recessed, and the corners of the metal region 68 were rounded. The resulting structure is as follows. Figure 14 As shown. The generated opening 80 includes a lower portion 80A located in ILD 48 and an upper portion 80B located in etch stop layers 72 and ILD 74. In... Figure 14 Following the process shown, the bottom layer 76BL is removed, for example, by using an ashing process with O2.

[0039] According to an optional embodiment, instead of offsetting the opening 80 to one side of the lower contact plug 70, the opening 80 is wider than the lower contact plug 70, and therefore the opening 80 extends into the ILD 48 on the opposite side of the contact plug 70, and contacts the opposite sidewall of the metal region 68. The corresponding sidewalls and bottom of the opening 80 are... Figure 14 It is shown using dashed line 77.

[0040] refer to Figure 15 Further etching of ILD 74 and etch stop layer 72 to form opening 82. The corresponding process is shown below. Figure 21 Process 228 in process flow 200 shown. An etching mask 83 may be formed and patterned, and the etching mask 83 may include photoresist (or may be three layers). The etching gas used to etch ILD 74 and etch stop layer 72 is selected based on the materials of ILD 74, etch stop layer 72, ILD 48, and CESL 46. According to some embodiments, opening 82 includes portions 82A and 82B, with portion 82A extending to the corresponding underlying gate electrode 54 and portion 82B extending to the corresponding underlying bottom source / drain contact plug 70.

[0041] According to some embodiments, the formation of opening 82 includes multiple etching processes, including, for example, a first etching process forming portion 82A and a second etching process forming portion 82B. Furthermore, portion 82B may stop at the top surface of ILD 48 or may extend into ILD 48, depending on the selected etching gas. Therefore, ILD 48, metal layer 62, and metal nitride layer 64 may also be etched. The corresponding sidewalls and bottom of the corresponding portion of opening 82 are indicated by dashed lines 84. This portion of opening 82 can be formed using an additional etching mask similar to that used for forming opening portion 82A. The etching mask 83 is then removed. The resulting structure is as follows... Figure 16 As shown.

[0042] In subsequent processes, pretreatment can be performed, for example, using H2 as a process gas. H2 forms Si-H bonds at the surface of the ILD 74 in openings 80 and 82, and metal-H bonds (e.g., Co-H bonds) at the surface of the metal material 68. According to some embodiments, the H2 pressure is in the range of approximately 5 Torr to approximately 40 Torr. Openings 80 and 82 are then filled with a conductive material to form the upper source / drain contact plugs 86 and 88, such as... Figure 17 As shown. The corresponding process is shown as follows. Figure 21Process 230 in process flow 200 shown. The forming process includes depositing the desired conductive material / layer. According to some embodiments, contact plugs 86 and 88 are formed of a homogeneous conductive material, and the entire conductive material has the same composition, and may be formed of titanium nitride, tungsten, cobalt, etc. In an exemplary embodiment where tungsten is filled, the process gas may include WF6 and H2, which react to form elemental tungsten and HF gas. The reaction temperature may be in the range of about 250°C to about 450°C. The pressure of the process gas may be in the range of about 5 Torr to about 20 Torr. According to an alternative embodiment, each contact plug 86 and 88 has a composite structure including, for example, a barrier layer and a metallic material located above the barrier layer. The barrier layer may be formed of titanium nitride, titanium, tantalum nitride, tantalum, etc., and the metallic material may be formed of tungsten, cobalt, copper, etc. Contact plug 88 electrically and physically interconnects the gate electrode 54 and the corresponding lower source / drain contact plug 70.

[0043] Furthermore, because the contact plug 86 is intentionally (not due to overlay offset) offset from the corresponding lower source / drain contact plug 70, the center line 88AC of the gate contact plug 88A (i.e., the portion of the contact plug 88 in the hard mask 58) can be vertically aligned with the center line 54C of the gate 54 and the gate stack 56. Figure 17 It is also shown that contact plug 86 can extend to the location of dashed line 77, and contact plug 88 can extend to the location of dashed line 84.

[0044] Then, injection process 90 is performed. The corresponding process is shown below. Figure 21 Process 232 in the process flow 200 shown. During implantation process 90, dopant is implanted to densify ILD 74, and ILD 74 may attempt to expand, thereby compressing contact plugs 86 and 88, and reducing their lateral dimensions. According to some embodiments, the dopant includes Ge, Xe, Ar, Si, or combinations thereof. In the implantation process, the implanted dopant may be implanted primarily into the upper portion (e.g., the upper half) of ILD 74, and not into the lower portion (e.g., the lower half) of ILD 74. Contact plugs 86 and 88 are sufficiently dense, and the dopant is substantially outside of contact plugs 86 and 88, confining the implanted dopant to the shallow top surface portions of contact plugs 86 and 88. Furthermore, the implantation depth in contact plugs 86 and 88 is significantly smaller than the implantation depth in ILD 48, for example, the implantation depth ratio is less than about 1:5.

[0045] Figure 18 The deposition of the sacrificial adhesion layer 92 and the sacrificial metal layer 94 is shown. The corresponding process is shown as follows. Figure 21Process 234 in process flow 200 is shown. According to some embodiments, the adhesion layer 92 includes Ti, TiN, Ta, TaN, etc., and can be deposited as a conformal layer. The metal layer 94 may include tungsten, cobalt, etc. A planarization process is then performed to remove the metal layer 94 and the adhesion layer 92, and to planarize the top surfaces of the contact plugs 86 and 88. The corresponding process is shown as follows. Figure 21 Process 236 in process flow 200 shown. Although the metal layer 94 and the adhesion layer 92 are removed, the formation of these layers helps to reduce the stress on the contact plugs 86 and 88 during the planarization process and reduces delamination between the contact plugs 86 / 88 and ILD 74.

[0046] refer to Figure 19 The second injection process 96 can then be performed. The corresponding process is shown below. Figure 21 Process 238 in the process flow 200 shown. In implantation process 96, dopants such as Ge, Xe, Ar, Si, or combinations thereof can be implanted. In the second implantation process, similar to the first implantation process, the implanted dopants can be implanted primarily into the upper part (e.g., the upper half) of the ILD 74.

[0047] exist Figure 19 Some exemplary dimensions are marked. It should be understood that these dimensions are exemplary and can be changed to different values. The height H1 from the top surface of the upper source / drain contact plug 86 to the top surface of the lower source / drain contact plug 70 can be in the range of about 200 nm and about 500 nm. The width W1, i.e., the width of the upper source / drain contact plug 86 measured at the bottom surface of the etch stop layer 72, can be in the range of about 10 nm and about 20 nm. The height H2, i.e., the recess depth of ILD 48, can be in the range of about 0.5 nm and about 10 nm. The height H3, i.e., the recess depth of the metal nitride layer 62, can be in the range of about 0.5 nm and about 10 nm. It should be understood that although the height H2 is shown as equal to the height H3, the height H2 can also be greater than or less than the height H3. Therefore, the bottom surface of the corresponding contact plug 86 can also be at the level marked by the dashed line 89. Furthermore, according to some embodiments, the ratio of H2 to the thickness T1 of ILD 48 can be in the range of about 0.1 and about 0.5 (or between about 0.25 and about 0.5). The width W1, i.e., the width of the upper source / drain contact plug 86 measured at the top surface of the etch stop layer 72, can be in the range of about 10 nm and about 20 nm. The width W2, i.e., the width of the portion of the upper source / drain contact plug 86 below the etch stop layer 72, can be in the range of about 3 nm and about 10 nm.

[0048] Figure 20The formation of an etch stop layer 102, a dielectric layer 104 (also referred to as an intermetallic dielectric (IMD)), and a metal line / via 106 is illustrated. The etch stop layer 102 may be formed of SiON, alumina, aluminum nitride, or a composite layer thereof. According to some embodiments of the invention, the dielectric layer 104 may be formed of a low-k dielectric material having a dielectric constant (k value) below about 3.0. For example, the dielectric layer 104 may be formed of Black Diamond (a registered trademark of Applied Materials), a carbon-containing low-k dielectric material, Hydrogen Silsesquioxane (HSQ), MethylSilsesquioxane (MSQ), etc., or the dielectric layer 104 may include Black Diamond (a registered trademark of Applied Materials), a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to some embodiments of the present invention, the formation of dielectric layer 104 includes depositing a dielectric material containing a pore-forming agent, and then performing a curing process to remove the pore-forming agent, and thus the remaining dielectric layer 104 is porous.

[0049] Metal lines / vias 106 are formed in dielectric layer 104. The formation process may include an inlay process, such as... Figure 17 The single damascene process is shown. The formation process may include etching a dielectric layer 104 and an etch stop layer 102 to form a trench, filling the trench with conductive material, and performing a CMP process to remove excess conductive material. Each metal line / via 106 may include a diffusion barrier and metal material located above the diffusion barrier. The diffusion barrier may be formed of or include titanium nitride, tantalum nitride, titanium, tantalum, etc. The metal material may include copper or a copper alloy.

[0050] Embodiments of the present invention have several advantageous features. By forming an upper source / drain contact plug that extends into the underlying ILD and contacts the sidewalls and top surface of the lower source / drain contact plug, adhesion to the lower source / drain contact plug is improved without causing the upper source / drain contact plug to break.

[0051] According to some embodiments of the present invention, the method includes forming a source / drain region of a transistor; forming a first interlayer dielectric over the source / drain region; forming a lower source / drain contact plug over the source / drain region, and the lower source / drain contact plug being electrically coupled to the source / drain region, wherein the lower source / drain contact plug extends into the first interlayer dielectric; depositing an etch stop layer over the first interlayer dielectric and the lower source / drain contact plug; depositing a second interlayer dielectric over the etch stop layer; performing an etching process to etch the upper portion of the second interlayer dielectric, the etch stop layer, and the first interlayer dielectric to form an opening, exposing the top surface and sidewalls of the lower source / drain contact plug to the opening; and forming an upper contact plug in the opening. In an embodiment, the lower source / drain contact plug includes a diffusion barrier; and a metal material on the diffusion barrier, wherein, during the etching process, a portion of the diffusion barrier is etched to expose the vertical sidewalls of the metal material. In one embodiment, a process gas comprising fluorine and carbon is used to etch the etch stop layer and the upper portion of the first interlayer dielectric. In another embodiment, a process gas comprising fluorine and carbon and H2O is used to etch the diffusion barrier. In yet another embodiment, the method further includes performing an implantation process to implant the second interlayer dielectric after forming the upper contact plug. In yet another embodiment, a dopant comprising Ge, Xe, Ar, Si, or a combination thereof is used to perform the implantation process. In yet another embodiment, the first interlayer dielectric has a thickness, and the opening extends into the first interlayer dielectric to a depth, wherein the depth-to-thickness ratio is in the range of about 0.1 to about 0.5. In yet another embodiment, the same etch mask is used to etch the second interlayer dielectric and the upper portion of the first interlayer dielectric. In yet another embodiment, the method further includes forming a gate stack adjacent to the source / drain regions; and forming a gate contact plug aligned with the vertical centerline of the gate stack, wherein the upper contact plug contacts the sidewall of the lower source / drain contact plug.

[0052] Embodiments of the present invention provide an integrated circuit structure including a gate stack located above a semiconductor region; a source / drain region on one side of the gate stack; a source / drain silicide region located above the source / drain region; a first interlayer dielectric located above the source / drain silicide region; a lower source / drain contact plug located above the source / drain silicide region and contacting the source / drain silicide region; an etch stop layer located above the first interlayer dielectric and the lower source / drain contact plug; a second interlayer dielectric located above the etch stop layer; and an upper source / drain contact plug extending through the second interlayer dielectric and the etch stop layer and into the upper portion of the first interlayer dielectric, wherein a first sidewall of the upper source / drain contact plug contacts a second sidewall of the lower source / drain contact plug. In some embodiments, the lower source / drain contact plug includes a diffusion barrier and a metallic material on the diffusion barrier, wherein the first sidewall of the upper source / drain contact plug contacts the second sidewall of the metallic material. In some embodiments, the diffusion barrier includes titanium nitride, and the metallic material includes a material selected from tungsten, cobalt, and combinations thereof. In some embodiments, a gate contact plug is further included above and in contact with the gate stack, wherein the gate contact plug and the centerline of the gate stack are perpendicularly aligned. In some embodiments, the third sidewall of the upper source / drain contact plug contacts the fourth sidewall of the lower source / drain contact plug, and wherein the second sidewall and the fourth sidewall are opposite sidewalls of the lower source / drain contact plug. In some embodiments, the first interlayer dielectric has a thickness, and the upper source / drain contact plug extends into the first interlayer dielectric to a depth, wherein the ratio of the depth to the thickness is in the range of about 0.1 and about 0.5. In some embodiments, germanium is also included in the upper half of the second interlayer dielectric.

[0053] According to some embodiments of the present invention, an integrated circuit structure includes a gate stack located above a semiconductor region; a source / drain region on one side of the gate stack; a source / drain silicide region located above the source / drain region; a first interlayer dielectric located above the source / drain silicide region; a lower source / drain contact plug located above the source / drain silicide region and contacting the source / drain silicide region; an etch stop layer located above the first interlayer dielectric and the lower source / drain contact plug; a second interlayer dielectric located above the etch stop layer; and an upper contact plug extending through the second interlayer dielectric and the etch stop layer and into the upper portion of the first interlayer dielectric, wherein a first sidewall of the upper contact plug contacts a second sidewall of the lower source / drain contact plug. In an embodiment, the lower source / drain contact plug includes a diffusion barrier; and a metal material on the diffusion barrier, wherein the first sidewall of the upper source / drain contact plug contacts a second sidewall of the metal material. In one embodiment, the diffusion barrier comprises titanium nitride, and the metallic material comprises materials selected from tungsten, cobalt, and combinations thereof. In another embodiment, the integrated circuit structure further includes a gate contact plug located above and contacting the gate stack, wherein the centerline of the gate contact plug and the gate stack are perpendicularly aligned. In another embodiment, a third sidewall of the upper contact plug contacts a fourth sidewall of the lower source / drain contact plug, wherein the second and fourth sidewalls are opposing sidewalls of the lower source / drain contact plug. In another embodiment, the first interlayer dielectric has a thickness, and the upper contact plug extends into the first interlayer dielectric to a depth, wherein the depth-to-thickness ratio is in the range of about 0.1 and about 0.5. In another embodiment, the integrated circuit structure further includes germanium in the upper half of the second interlayer dielectric.

[0054] According to some embodiments of the present invention, an integrated circuit structure includes a semiconductor region; a source / drain region extending into the semiconductor region; a first interlayer dielectric located above the source / drain region; a first source / drain contact plug located above and electrically coupled to the source / drain region, wherein the first source / drain contact plug includes a metal region; a metal nitride layer having a first portion surrounding the metal region; and a metal layer having a second portion surrounding the metal nitride layer; and a second source / drain contact plug including a first sidewall physically contacting a second sidewall of the metal region to form a vertical interface; and a bottom edge physically contacting the top edge of the metal nitride layer and the metal layer. In embodiments, the second source / drain contact plug also contacts the top surface of the first source / drain contact plug. In embodiments, the second source / drain contact plug extends into the first interlayer dielectric to a depth, and the ratio of the depth to the thickness of the first interlayer dielectric is in the range of about 0.1 and about 0.5. In an embodiment, the integrated circuit structure further includes an etch stop layer located above the first interlayer dielectric; and a second interlayer dielectric located above the etch stop layer, wherein the second source / drain contact plug extends into the etch stop layer and the second interlayer dielectric.

[0055] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of the invention.

Claims

1. A method for forming an integrated circuit structure, comprising: Forming the source / drain regions of a transistor; A first interlayer dielectric is formed above the source / drain region; A lower source / drain contact plug is formed above the source / drain region, and the lower source / drain contact plug is electrically coupled to the source / drain region, wherein the lower source / drain contact plug extends into the first interlayer dielectric, and wherein the lower source / drain contact plug comprises: diffusion barrier; and Metallic material, on the diffusion barrier; An etch stop layer is deposited over the first interlayer dielectric and the lower source / drain contact plug; A second interlayer dielectric is deposited above the etch stop layer; An etching process is performed to etch the second interlayer dielectric, the etch stop layer, and the upper portion of the first interlayer dielectric to form an opening, and the top surface and sidewalls of the lower source / drain contact plug are exposed to the opening, wherein, during the etching process, a portion of the diffusion barrier is etched to expose the vertical sidewalls of the metal material; and An upper contact plug is formed in the opening, and the upper contact plug contacts the vertical sidewall of the metal material.

2. The method according to claim 1, wherein, The vertical sidewall is laterally offset relative to the inner sidewall of the diffusion barrier.

3. The method according to claim 2, wherein, The etching stop layer and the upper portion of the first interlayer dielectric are etched using a process gas comprising fluorine and carbon.

4. The method according to claim 3, wherein, The diffusion barrier is also etched using the process gas comprising the fluorine- and carbon-containing gas and H2O.

5. The method according to claim 1, further comprising: After the upper contact plug is formed, an injection process is performed to inject the second interlayer dielectric.

6. The method according to claim 5, wherein, The implantation process is performed using dopants including Ge, Xe, Ar, Si, or combinations thereof.

7. The method according to claim 1, wherein, The first interlayer dielectric has a thickness, and the opening extends into the first interlayer dielectric to a depth, wherein the ratio of the depth to the thickness is in the range of 0.1 and 0.

5.

8. The method according to claim 1, wherein, The same etching mask is used to etch the upper portion of the second interlayer dielectric and the first interlayer dielectric.

9. The method according to claim 1, further comprising: Forming a gate stack, wherein the gate stack is adjacent to the source / drain regions; and A gate contact plug is formed, wherein the gate contact plug is aligned with the vertical center line of the gate stack.

10. An integrated circuit structure, comprising: Gate stack, located above the semiconductor region; Source / drain regions are located on one side of the gate stack. Source / drain silicide regions are located above the source / drain regions; The first interlayer dielectric is located above the source / drain silicide region; A lower source / drain contact plug is located above and in contact with the source / drain silicide region, wherein the lower source / drain contact plug comprises: A diffusion barrier, the diffusion barrier comprising a first portion and a second portion, wherein a first tip of the first portion is lower than a second tip of the second portion; and A metallic material is located between the first and second portions of the diffusion barrier layer; An etch stop layer is located above the first interlayer dielectric and the lower source / drain contact plug; A second interlayer dielectric is located above the etch stop layer; and An upper source / drain contact plug penetrates the second interlayer dielectric and the etch stop layer, and extends into the upper part of the first interlayer dielectric, wherein the first sidewall of the upper source / drain contact plug contacts the second sidewall of the metal material, and the bottom surface of the upper source / drain contact plug contacts the first top end of the diffusion barrier layer.

11. The integrated circuit structure according to claim 10, wherein, The etch stop layer comprises a dielectric material of SiN, SiCN, SiC, AlO, AlN, SiOCN, or a composite thereof.

12. The integrated circuit structure according to claim 10, wherein, The diffusion barrier includes titanium nitride, and the metallic material includes materials selected from tungsten, cobalt, and combinations thereof.

13. The integrated circuit structure of claim 10, further comprising a gate contact plug located above and in contact with the gate stack, wherein, The center line of the gate contact plug and the gate stack are vertically aligned.

14. The integrated circuit structure according to claim 10, wherein, The third sidewall of the upper source / drain contact plug contacts the fourth sidewall of the lower source / drain contact plug, wherein the second sidewall and the fourth sidewall are opposite sidewalls of the lower source / drain contact plug.

15. The integrated circuit structure according to claim 10, wherein, The first interlayer dielectric has a thickness, and the upper source / drain contact plug extends into the first interlayer dielectric to a depth, wherein the ratio of the depth to the thickness is in the range of 0.1 and 0.

5.

16. The integrated circuit structure of claim 10, further comprising germanium in the upper half of the second interlayer dielectric.

17. An integrated circuit structure, comprising: Semiconductor region; The source / drain region extends into the semiconductor region; The first interlayer dielectric is located above the source / drain region; A first source / drain contact plug is located above the source / drain region and electrically coupled to the source / drain region, wherein the first source / drain contact plug comprises: Metallic area; A metal nitride layer having a first portion surrounding the metal region; and A metal layer having a second portion surrounding the metal nitride layer; and The second source / drain contact plug includes: The first sidewall is in physical contact with the second sidewall of the metal region to form a vertical interface; and The bottom edge is in physical contact with the metal nitride layer and the top edge of the metal layer. The bottom edge includes a first bottom surface and a second bottom surface. The first bottom surface contacts the first top surface of the first source / drain contact plug. The second bottom surface contacts the second top surface of the first source / drain contact plug. The second bottom surface is lower than the first bottom surface. The first sidewall connects the first bottom surface and the second bottom surface.

18. The integrated circuit structure according to claim 17, wherein, The metallic region includes materials selected from tungsten, cobalt, and combinations thereof.

19. The integrated circuit structure according to claim 17, wherein, The second source / drain contact plug extends into the first interlayer dielectric to a depth, and the ratio of the depth to the thickness of the first interlayer dielectric is in the range of 0.1 to 0.

5.

20. The integrated circuit structure according to claim 17, further comprising: An etch stop layer is located above the first interlayer dielectric; as well as The second interlayer dielectric is located above the etch stop layer, wherein the second source / drain contact plug extends into the etch stop layer and the second interlayer dielectric.

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