A process method for improving the reliability of metal gate high-voltage devices

Abstract

The present invention provides a process method for improving the reliability of metal gate high-voltage devices. A stack including a gate oxide layer and a polysilicon layer is formed on a substrate; the stack is etched to form a stack structure; a first sidewall layer covering the stack structure and the exposed substrate is deposited; the sidewall layer is etched to expose the top of the stack structure and the upper surface of the substrate, and a first sidewall is formed on the sidewall of the stack structure; a second sidewall is formed on the sidewall of the stack structure; the stack structure is etched to form a plurality of slots on the stack structure; the bottom of the slots is the polysilicon layer; a photoresist is etched back to form a dielectric layer covering the substrate and filling the slots; the dielectric layer is planarized; the polysilicon layer is removed to form a groove, and the gate oxide layer on the upper surface of the substrate is exposed; metal is filled in the groove, and the metal is planarized. By separating the process of polysilicon etching from the process of forming slots, the present invention minimizes the influence of slot formation on the gate oxide layer and greatly reduces the risk of reducing the reliability of high-voltage devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a process method for improving the reliability of metal gate high-voltage devices. Background Art

[0002] When the technology node enters below 28nm, logic devices become very small, and quantum effects and the like become more prominent. The original traditional polysilicon gate and silicon oxide dielectric layer can no longer meet the requirements of high device performance, so high-K materials and metal gates are introduced. In the traditional polysilicon gate (poly gate) process, polysilicon is directly used as the gate and is connected by contact holes. In the metal gate process, after filling the metal gate, there is a chemical mechanical polishing (CMP) process to remove the excess metal. In the CMP process, the middle part of the large metal gate is polished quickly, and the edge part is polished slowly, which is very easy to form depressions, seriously affecting the quality of the metal gate. Especially in HV devices, the channel area is large, and the area of the metal gate is also correspondingly large. Solving the problem of the dishing of the metal gate is crucial.

[0003] Currently, the method to solve the dishing of the metal gate is to add slots on the polysilicon to divide the large metal gate into many small pieces. There is a risk that the gate oxide at the slots is exposed, and various plasma metal ions and the like in the subsequent process will affect the gate oxide, which poses a serious challenge to the device reliability. Therefore, it is necessary to develop a new method for forming polysilicon slots to reduce the above reliability risks. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a process method for improving the reliability of metal gate high-voltage devices, which is used to solve the problem that in the prior art, during the formation of the metal gate, the gate oxide layer has a risk of being exposed, thereby affecting the device reliability.

[0005] To achieve the above purpose and other related purposes, the present invention provides a process method for improving the reliability of metal gate high-voltage devices, which at least includes:

[0006] Step 1: Provide a substrate, and sequentially form a stack including a gate oxide layer and a polysilicon layer on the substrate from bottom to top; wherein the gate oxide layer is located on the upper surface of the substrate, and the polysilicon layer is located on the upper surface of the gate oxide layer;

[0007] Step 2: Etch the stack to form a stack structure;

[0008] Step 3: Deposit a first sidewall layer covering the stack structure and the exposed upper surface of the substrate;

[0009] Step Four: Etch the sidewall layer to expose the top of the stacked structure and the upper surface of the substrate, and form a first sidewall on the sidewalls of the stacked structure.

[0010] Step Five: Form a second sidewall on the sidewalls of the stacked structure that adheres to the first sidewall.

[0011] Step Six: Etch the stacked structure to form a plurality of slots therein; the bottom of the slots is the polysilicon layer.

[0012] Step Seven: Back-etch the photoresist and form a dielectric layer on the substrate that covers the substrate and fills the slots; then planarize the dielectric layer.

[0013] Step Eight: Remove the polysilicon layer to form a groove and expose the gate oxide layer on the upper surface of the substrate.

[0014] Step Nine: Fill the groove with metal.

[0015] Step Ten: Planarize the metal.

[0016] Preferably, the stacked layer in Step One further includes: a silicon nitride layer on the upper surface of the polysilicon layer and a TEOS layer on the silicon nitride layer.

[0017] Preferably, the method of etching the stacked layer in Step Two includes: etching the TEOS layer, silicon nitride layer, polysilicon layer, and gate oxide layer in the stacked layer from top to bottom to expose the upper surface of the substrate, and forming a plurality of stacked structures of the active regions on the substrate.

[0018] Preferably, the method of forming the second sidewall in Step Five includes: depositing a second sidewall layer that covers the top of the stacked structure and its sidewalls, the first sidewall, and the exposed upper surface of the substrate; then etching the second sidewall layer to expose the top of the stacked structure and the upper surface of the substrate, and forming the second sidewall that adheres to the first sidewall on the sidewalls of the stacked structure.

[0019] Preferably, the method of etching the stacked structure to form a plurality of the slots in Step Six includes: (1) spin-coating a photoresist on the stacked structure now; (2) performing photolithography to form a photoresist structure; (3) etching the stacked structure according to the photoresist structure until the polysilicon layer in the stacked structure is not etched through, forming the plurality of slots, so that the bottom of the slots is the polysilicon layer and the gate oxide layer below the slots is not exposed.

[0020] Preferably, in Step Seven, the dielectric layer is planarized until the upper surface of the silicon nitride layer in the stacked structure is exposed.

[0021] Preferably, the thickness of the remaining polysilicon layer at the bottom of the slot in Step 6 is 100 - 150 angstroms.

[0022] Preferably, the method for etching the stacked structure in Step 6 is dry etching.

[0023] As described above, the process method for improving the reliability of the metal gate high-voltage device of the present invention has the following beneficial effects: By separating the polysilicon etching process from the process of forming the slot, the present invention minimizes the impact of slot formation on the gate oxide layer, greatly reducing the risk of reducing the reliability of high-voltage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It shows a schematic diagram of the stacked layer on the substrate in the present invention;

[0025] Figure 2 It shows a schematic diagram of the structure after forming the stacked structure in the present invention;

[0026] Figure 3 It shows a schematic diagram of the structure after forming the first sidewall layer in the present invention;

[0027] Figure 4 It shows a schematic diagram of the structure of forming the first sidewall on the sidewall of the stacked structure in the present invention;

[0028] Figure 5 It shows a schematic diagram of the structure after forming the second sidewall in the present invention;

[0029] Figure 6 It shows a schematic diagram of the structure of forming a photoresist pattern by lithography on the stacked structure in the present invention;

[0030] Figure 7 It shows a schematic diagram of the structure after etching to form a slot in the present invention;

[0031] Figure 8 It shows a schematic diagram of the structure formed by back-etching the photoresist in the present invention;

[0032] Figure 9 It shows a schematic diagram of the structure after back-etching the photoresist in the present invention;

[0033] Figure 10 It shows a schematic diagram of the structure after forming and planarizing the dielectric layer in the present invention;

[0034] Figure 11 It shows a schematic diagram of the structure after etching to form a groove in the present invention;

[0035] Figure 12 It shows a schematic diagram of the structure after filling and planarizing the metal in the groove in the present invention;

[0036] Figure 13 Shown is a process flow chart of a process for improving the reliability of a metal gate high-voltage device in the present invention. Specific embodiments

[0037] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] Please refer to Figures 1 to 12 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components during actual implementation. The types, quantities, and proportions of the components during actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0039] The present invention provides a process method for improving the reliability of a metal gate high-voltage device. As Figure 13 shown, Figure 13 Shown is a process flow chart of a process for improving the reliability of a metal gate high-voltage device in the present invention. This method at least includes the following steps:

[0040] Step 1: Provide a substrate, and sequentially form a stack including a gate oxide layer and a polysilicon layer on the substrate from bottom to top; wherein the gate oxide layer is located on the upper surface of the substrate, and the polysilicon layer is located on the upper surface of the gate oxide layer; as Figure 1 shown, Figure 1 Shown is a schematic diagram of the stack located on the substrate in the present invention. In this step 1, a stack including a gate oxide layer 01 and a polysilicon layer 02 is sequentially formed on the substrate from bottom to top; wherein the gate oxide layer 01 is located on the upper surface of the substrate, and the polysilicon layer 02 is located on the upper surface of the gate oxide layer 01.

[0041] Furthermore, in the present invention, the stack in step 1 of this embodiment further includes: a silicon nitride layer 03 located on the upper surface of the polysilicon layer 02 and a TEOS layer 04 located on the silicon nitride layer 03.

[0042] Step 2: Etch the stack to form a stack structure; as Figure 2 shown, Figure 2 Shown is a schematic diagram of the structure after forming the stack structure in the present invention. In this step 2, the stack is etched to form a stack structure, and the upper surface of the substrate is exposed after etching.

[0043] Further, in the present invention, the method for etching the stack in step two of this embodiment includes: etching the TEOS layer 04, silicon nitride layer 03, polysilicon layer 02, and gate oxide layer 01 in the stack from top to bottom, exposing the upper surface of the substrate, and forming a plurality of stacked structures of the active region on the substrate.

[0044] Step three, depositing a first sidewall layer covering the stacked structure and the exposed upper surface of the substrate; as Figure 3 shown, Figure 3 It shows a schematic structural diagram after forming the first sidewall layer in the present invention. In this step three, a first sidewall layer 05 covering the stacked structure and the exposed upper surface of the substrate is deposited.

[0045] Step four, etching the sidewall layer to expose the top of the stacked structure and the upper surface of the substrate, and forming a first sidewall on the sidewalls of the stacked structure; as Figure 4 shown, Figure 4 It shows a schematic structural diagram of forming a first sidewall on the sidewalls of the stacked structure in the present invention. In this step four, the sidewall layer 05 is etched to expose the top of the stacked structure and the upper surface of the substrate, and the first sidewall 05 is formed on the sidewalls of the stacked structure.

[0046] Step five, forming a second sidewall attached to the first sidewall on the sidewalls of the stacked structure; as Figure 5 shown, Figure 5 It shows a schematic structural diagram after forming the second sidewall in the present invention. In this step five, a second sidewall 06 attached to the first sidewall 05 is formed on the sidewalls of the stacked structure.

[0047] Further, in the present invention, the method for forming the second sidewall in step five of this embodiment includes: depositing a second sidewall layer covering the top and sidewalls of the stacked structure, the first sidewall, and the exposed upper surface of the substrate; and then etching the second sidewall layer to expose the top of the stacked structure and the upper surface of the substrate, and forming the second sidewall attached to the first sidewall on the sidewalls of the stacked structure.

[0048] Step six, etching the stacked structure to form a plurality of slots on the stacked structure; the bottom of the slots is the polysilicon layer; as Figure 6 and Figure 7 shown, where Figure 6 It shows a schematic structural diagram of performing photolithography to form a photoresist pattern on the stacked structure in the present invention. Figure 7 It shows a schematic structural diagram after etching to form slots in the present invention. In this step six, the stacked structure is etched to form a plurality of slots 10 on the stacked structure; the bottom of the slots is the polysilicon layer.

[0049] Furthermore, in the present invention, the method for etching the stacked structure to form a plurality of the slots in step six of this embodiment includes: (1) Spin-coating a photoresist on the stacked structure now; (2) Performing photolithography to form a photoresist structure; as Figure 6 shown; (3) Etching the stacked structure according to the photoresist structure until the polysilicon layer in the stacked structure is not etched through, thereby forming the plurality of slots, such that the bottom of the slots is the polysilicon layer and the gate oxide layer below the slots is not exposed.

[0050] Furthermore, in the present invention, the thickness of the remaining polysilicon layer at the bottom of the slots in step six of this embodiment is 100 - 150 angstroms.

[0051] Furthermore, in the present invention, the method for etching the stacked structure in step six of this embodiment is dry etching.

[0052] Step seven, performing photoresist back-etching and forming a dielectric layer covering the substrate and filling the slots on the substrate; then planarizing the dielectric layer; in this embodiment, before photoresist back-etching, as Figure 6 shown, an oxide layer 09 is formed on the stacked structure. The oxide layer 09 is formed by using a mixed gas of oxygen and nitrogen and performing plasma treatment. As Figure 8 shown, Figure 8 shows a schematic structural diagram formed by photoresist back-etching in the present invention. Before performing photoresist back-etching in this step, the thickness of the silicon nitride layer is 50 angstroms. Before performing photoresist back-etching in step seven, a photoresist 11 is first formed on the stacked structure and developed. The formed photoresist pattern covers the slots. Then photoresist back-etching is performed, as Figure 9 shown, Figure 9 shows a schematic structural diagram after photoresist back-etching in the present invention. As Figure 10 shown, Figure 10 shows a schematic structural diagram after forming the dielectric layer and planarizing in the present invention. The dielectric layer 12 fills the slots.

[0053] Furthermore, in the present invention, in step seven, the dielectric layer 12 is planarized until the upper surface of the silicon nitride layer in the stacked structure is exposed.

[0054] Step eight, removing the polysilicon layer to form a groove and exposing the gate oxide layer on the upper surface of the substrate; as Figure 11 shown, Figure 11 shows a schematic structural diagram after etching to form a groove in the present invention. In step eight, the polysilicon layer is removed to form a groove 13 and the gate oxide layer on the upper surface of the substrate is exposed.

[0055] Step nine, filling the groove with metal; as Figure 12 shown,Figure 12 It shows a schematic structural diagram after filling the groove with metal and planarizing in the present invention. In step nine, metal 14 is filled in the groove.

[0056] Step ten: planarize the metal.

[0057] In summary, by separating the process of polysilicon etching from the process of forming slots, the method of the present invention minimizes the impact of slot formation on the gate oxide layer and greatly reduces the risk of reduced reliability of high-voltage devices. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0058] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A process method for improving the reliability of high-voltage metal gate devices, characterized in that At least including: Step 1: Provide a substrate, and sequentially form a stack including a gate oxide layer and a polysilicon layer on the substrate from bottom to top; wherein the gate oxide layer is located on the upper surface of the substrate, and the polysilicon layer is located on the upper surface of the gate oxide layer; Step 2: Etch the stack to form a stack structure; Step 3: Deposit a first sidewall layer covering the stack structure and the exposed upper surface of the substrate; Step 4: Etch the sidewall layer to expose the top of the stack structure and the upper surface of the substrate, and form a first sidewall on the sidewall of the stack structure; Step 5: Deposit a second sidewall layer covering the top of the stack structure, the first sidewall on its sidewall, and the exposed upper surface of the substrate; then etch the second sidewall layer to expose the top of the stack structure and the upper surface of the substrate, and form a second sidewall attached to the first sidewall on the sidewall of the stack structure; Step 6: Spin-coat a photoresist on the stack structure; perform photolithography to form a photoresist structure; etch the stack structure according to the photoresist structure until the polysilicon layer in the stack structure is not etched through, and form a plurality of slots, so that the bottom of the slots is the polysilicon layer and the gate oxide layer below the slots is not exposed; Step 7: Back-etch the photoresist, and form a dielectric layer covering the substrate and filling the slots on the substrate; then planarize the dielectric layer; Step 8: Remove the polysilicon layer to form a groove and expose the gate oxide layer on the upper surface of the substrate; Step 9: Fill the groove with metal; Step 10: Planarize the metal.

2. The process method for improving the reliability of a metal gate high-voltage device according to claim 1, characterized in that: The stack in Step 1 further includes: a silicon nitride layer on the upper surface of the polysilicon layer and a TEOS layer on the silicon nitride layer.

3. The process method for improving the reliability of a metal gate high-voltage device according to claim 2, characterized in that: The method of etching the stack in Step 2 includes: etching the TEOS layer, silicon nitride layer, polysilicon layer, and gate oxide layer in the stack from top to bottom to expose the upper surface of the substrate, and form a plurality of stack structures of active regions on the substrate.

4. The process method for improving the reliability of a metal gate high-voltage device according to claim 2, characterized in that: In Step 7, planarize the dielectric layer until the upper surface of the silicon nitride layer in the stack structure is exposed.

5. The process method for improving the reliability of a metal gate high-voltage device according to claim 1, wherein: The thickness of the remaining polysilicon layer at the bottom of the slots in Step 6 is 100 - 150 angstroms.

6. The process method for improving the reliability of a metal gate high-voltage device according to claim 2, characterized in that: The method of etching the stack structure in Step 6 is dry etching.

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