A manufacturing method of a floating-gate flash memory

Abstract

The present invention provides a manufacturing method of a floating-gate flash memory. A semiconductor structure is provided, including a memory array and a logic region adjacent to the memory array. Then, the silicon of the memory array is etched back; a gate oxide is grown; a floating gate is deposited to cover the semiconductor structure; silicon oxide is deposited; then, the floating gate and the silicon oxide in the logic region are removed; silicon nitride is deposited to cover the memory array and the logic region; then, shallow trench isolation (STI) is formed in the memory array and the logic region respectively and surface planarization is performed; the silicon nitride and the silicon oxide are removed. On the basis of the existing Si etching back, the present invention further increases the etching back amount. By controlling the etching back thickness, it is ensured that the heights of the memory array and the logic region are close during the subsequent Al chemical mechanical polishing (CMP) process. After the gate oxide and the floating gate are deposited, a layer of silicon oxide is further deposited to make the heights of the memory array and the logic region close during the STI CMP process. After the STI CMP is completed, this layer of silicon oxide is removed by an etching process, and the subsequent standard process is continued.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for manufacturing a floating gate flash memory device. Background Art

[0002] Compared with memory process nodes of 40 nm and above, integrating a floating gate flash memory device into a 28 nm node process can further reduce the operating voltage, improve device performance, and save chip area. The traditional method of integrating the flash memory process into the logic process is to perform silicon back-etching on the storage array area before forming the floating gate process, and the back-etching thickness is matched with the floating gate thickness to ensure the smooth progress of the STI CMP process. When manufacturing a flash memory device based on the 28 nm HKMG logic (28 nm high-k metal gate logic) process, the total thickness of the floating gate, ONO, control gate, and CESL layers included in the flash memory device is often much higher than the MOS height in the logic area. Although there has been a certain amount of back-etching before the floating gate is formed, when performing the Al CMP process necessary for 28 nm HKMG, problems such as too high step height will still be encountered. Summary of the Invention

[0003] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for manufacturing a floating gate flash memory device, which is used to solve the process problems caused by the mismatch of device heights between the logic area and the storage array area in the prior art.

[0004] To achieve the above purpose and other related purposes, the present invention provides a method for manufacturing a floating gate flash memory device, at least including:

[0005] Step 1: Provide a semiconductor structure, including a storage array and a logic area adjacent to the storage array; then perform back-etching on the silicon of the storage array.

[0006] Step 2: Grow gate oxide.

[0007] Step 3: Deposit a floating gate to cover the semiconductor structure.

[0008] Step 4: Deposit silicon oxide; then remove the floating gate and silicon oxide in the logic area.

[0009] Step 5: Deposit silicon nitride to cover the storage array and the logic area; then form STI in the storage array and the logic area respectively and perform surface planarization.

[0010] Step 6: Remove the silicon nitride and the silicon oxide. Preferably, the method for performing back-etching on the silicon of the storage array in Step 1 is dry etching.

[0011] Preferably, the etch-back depth in Step 1 is 100 - 2000 angstroms.

[0012] Preferably, the method for growing the gate oxide in Step 2 is furnace tube or ISSG, and the temperature range is 400 - 1000 °C.

[0013] Preferably, the growth thickness range of the gate oxide in Step 2 is 10 - 200 angstroms. Preferably, the method for depositing the floating gate in Step 3 is furnace tube or CVD deposition, and the temperature range is 400 - 1000 °C.

[0014] Preferably, the deposition thickness range of the floating gate in Step 3 is 100 - 1000 angstroms.

[0015] Preferably, in Step 4, dry etching is used to remove the floating gate and silicon oxide in the logic region.

[0016] Preferably, in Step 4, wet etching is used to remove the floating gate and silicon oxide in the logic region.

[0017] Preferably, in Step 4, the floating gate and silicon oxide in the logic region are removed by sectional etching or one-step etching.

[0018] Preferably, in Step 6, dry etching or wet etching is used to remove the silicon nitride and the silicon oxide.

[0019] Preferably, the etch-back depth range for removing the silicon nitride and the silicon oxide in Step 6 is 100 - 1000 angstroms.

[0020] As described above, the manufacturing method of the floating gate type flash memory of the present invention has the following beneficial effects: On the basis of the existing Si etch-back, the present invention further increases the etch-back amount. By controlling the etch-back thickness, the heights of the storage array and the logic region are ensured to be close during the subsequent Al CMP process. After the floating gate is deposited, a layer of silicon oxide is continuously deposited to make the heights of the storage array and the logic region close during STI CMP. After the STI CMP is completed, this layer of silicon oxide is removed by an etching process, and the subsequent standard process is continued. Description of the Drawings

[0021] Figure 1 It shows a schematic structural diagram of the storage array after etch-back in the present invention;

[0022] Figure 2 It shows a schematic structural diagram of the storage array after depositing the floating gate in the present invention;

[0023] Figure 3 It shows a schematic structural diagram of the storage array and the logic region after depositing silicon nitride to cover them in the present invention;

[0024] Figure 4Shown is a schematic diagram of the structure after removing silicon nitride and silicon oxide in the present invention. Detailed implementation manners

[0025] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] Please refer to Figures 1 to 4 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0027] The present invention provides a manufacturing method for a floating-gate flash memory, which at least includes:

[0028] Step 1: Provide a semiconductor structure, including a memory array and a logic region adjacent to the memory array; then perform etch-back on the silicon of the memory array; as Figure 1 shown, Figure 1 Shown is a schematic diagram of the structure of the memory array after etch-back in the present invention. This step 1 provides a semiconductor structure, including a memory array (memory array region) and a logic region (Logic region) adjacent to the memory array; then perform etch-back on the silicon of the memory array to form a structure as Figure 1 shown.

[0029] Furthermore, in the present invention, the method for performing etch-back on the silicon of the memory array in step 1 of this embodiment is dry etching.

[0030] Furthermore, in the present invention, the etch-back depth in step 1 of this embodiment is 100 - 2000 angstroms.

[0031] Step 2: Grow a gate oxide;

[0032] Furthermore, in the present invention, the method for growing the gate oxide in step 2 of this embodiment is the furnace tube or ISSG method, and the temperature range is 400 - 1000 °C. Further, the growth thickness range of the gate oxide in step 2 is 10 - 200 angstroms.

[0033] Step 3: Deposit a floating gate to cover the semiconductor structure; as Figure 2 shown, Figure 2It shows a schematic structural diagram after depositing a floating gate in the present invention. In step three, the deposited floating gate (FG) covers the semiconductor structure.

[0034] Furthermore, in the present invention, in step three of this embodiment, the method for depositing the floating gate is furnace tube or CVD deposition, and the temperature range is 400 - 1000 °C.

[0035] Furthermore, in the present invention, in step three of this embodiment, the growth thickness range of the deposited floating gate is 100 - 1000 angstroms.

[0036] Step four: Deposit silicon dioxide; then remove the floating gate and silicon dioxide in the logic region; as Figure 2 shown, Figure 2 It shows a schematic structural diagram after depositing a floating gate in the present invention. In this step four, silicon dioxide (SiO2) is deposited; then the floating gate and silicon dioxide in the logic region are removed.

[0037] Furthermore, in the present invention, in step three of this embodiment, dry etching is used to remove the floating gate and silicon dioxide in the logic region.

[0038] Furthermore, in the present invention, in step three of this embodiment, wet etching is used to remove the floating gate and silicon dioxide in the logic region.

[0039] Furthermore, in the present invention, in step three of this embodiment, partial etching or one-step etching is used to remove the floating gate and silicon dioxide in the logic region.

[0040] Step five: Deposit silicon nitride to cover the memory array and the logic region; then form STIs in the memory array and the logic region respectively and perform surface planarization; as Figure 3 shown, Figure 3 It shows a schematic structural diagram after depositing silicon nitride to cover the memory array and the logic region in the present invention. In this step five, silicon nitride 01 is deposited to cover the memory array and the logic region, and then STIs (02) are formed in the memory array and the logic region respectively and surface planarization is performed.

[0041] Step six: Remove the silicon nitride and the silicon dioxide. As Figure 4 shown, Figure 4 It shows a schematic structural diagram after removing the silicon nitride and the silicon dioxide in the present invention.

[0042] Furthermore, in the present invention, in step six of this embodiment, dry etching or wet etching is used to remove the silicon nitride and the silicon dioxide.

[0043] Furthermore, in the present invention, in step six of this embodiment, the etching depth range for removing the silicon nitride and the silicon dioxide is 100 - 1000 angstroms.

[0044] The present invention relates to a method for manufacturing a floating-gate flash memory based on a 28nm HKMG process, which solves the process problems caused by the height mismatch between the devices in the logic region and the memory array region of the flash memory. The main process flow is as follows. Before the flash memory device manufacturing process, a Si etch-back process is first performed on the memory array region. The etch-back thickness is determined according to the height difference between the designed memory device and the logic device, and the range is 100 Å to 2000 Å. Then, the deposition of the floating gate and silicon oxide is carried out. The floating gate deposition uses a furnace process to ensure the film quality, the temperature range is 400 - 1000 °C, and the growth thickness is determined according to the device design, with a range of 100 Å to 1000 Å. The silicon oxide uses a furnace or CVD process, the temperature range is 400 - 1000 °C, and the growth thickness is determined according to the Si etch-back thickness and the floating gate thickness, with a range of 100 Å to 1000 Å. This process is the key point of the present invention. Through the design of the thickness, it can ensure that there will be no process problems caused by the height mismatch of the devices in the memory array region during the subsequent STI CMP and the necessary Al CMP for 28nm HKMG. After that, the floating gate and silicon oxide in the logic region are removed by dry etching or wet etching, and it can be etched in parts or in one step. This process can share one mask layer with the Si etch-back, so it will not increase the additional mask cost. Subsequently, the standard STI process is carried out. Finally, after the STI CMP, the SIN removal process is carried out, and the silicon oxide on the floating gate is removed, and the removal method is dry etching or wet etching.

[0045] In summary, the present invention further increases the etch-back amount on the basis of the existing Si etch-back, and by controlling the etch-back thickness, it ensures that the heights of the memory array and the logic region are close during the subsequent Al CMP process. After the floating gate deposition, a layer of silicon oxide is continuously deposited to make the heights of the memory array and the logic region close during the STI CMP. After the STI CMP is completed, this layer of silicon oxide is removed by an etching process, and the subsequent standard processes are continued. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0046] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A manufacturing method of a floating gate type flash memory based on 28nm HKMG process, characterized in that, At least including: Step 1: Provide a semiconductor structure including a memory array and a logic region adjacent to the memory array; then perform back-etching on the silicon of the memory array. Step 2: Grow a gate oxide. Step 3: Deposit a floating gate to cover the semiconductor structure. Step 4: Deposit silicon oxide; then remove the floating gate and silicon oxide in the logic region. Step 5: Deposit silicon nitride to cover the memory array and the logic region; then form STI in the memory array and the logic region respectively and perform chemical mechanical polishing (CMP) planarization on the silicon nitride surface. Step 6: Remove the silicon nitride and the silicon oxide.

2. The manufacturing method of the floating gate type flash memory according to claim 1, wherein: The method for performing back-etching on the silicon of the memory array in Step 1 is dry etching.

3. The manufacturing method of the floating gate type flash memory according to claim 1, characterized in that: The back-etching depth in Step 1 is 100 - 2000 angstroms.

4. The manufacturing method of the floating gate type flash memory according to claim 1, characterized in that: The method for growing the gate oxide in Step 2 is furnace tube or ISSG method, and the temperature range is 400 - 1000 °C.

5. The manufacturing method of the floating gate type flash memory according to claim 1, characterized in that: The growth thickness range of the gate oxide in Step 2 is 10 - 200 angstroms.

6. The manufacturing method of the floating gate type flash memory according to claim 1, wherein: The method for depositing the floating gate in Step 3 is furnace tube or CVD deposition, and the temperature range is 400 - 1000 °C.

7. The manufacturing method of the floating gate type flash memory according to claim 1, characterized in that: The deposition thickness range of the floating gate in Step 3 is 100 - 1000 angstroms.

8. The manufacturing method of the floating gate type flash memory according to claim 1, characterized in that: The method for removing the floating gate and silicon oxide in the logic region in Step 4 is dry etching.

9. The manufacturing method of the floating gate type flash memory according to claim 1, characterized in that: The method for removing the floating gate and silicon oxide in the logic region in Step 4 is wet etching.

10. The manufacturing method of the floating gate type flash memory according to claim 1, characterized in that: The method for removing the floating gate and silicon oxide in the logic region in Step 4 is step-by-step etching or one-step etching.

11. The manufacturing method of the floating gate flash memory according to claim 1, characterized in that: The method for removing the silicon nitride and the silicon oxide in Step 6 is dry etching or wet etching.

12. The manufacturing method of the floating gate type flash memory according to claim 1, characterized in that: The etching depth range for removing the silicon nitride and the silicon oxide in Step 6 is 100 - 1000 angstroms.

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