Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor structure, a manufacturing method thereof and electronic equipment. The manufacturing method comprises the following steps: forming a first stack structure on a semiconductor substrate; forming a horizontal opening in the first region of the first stack structure, and forming a first vertical opening exposing the semiconductor substrate and a second vertical opening not exposing the semiconductor substrate at two sides of the first region; epitaxially growing using the first vertical opening to form a single crystal active pattern in the horizontal opening; a transistor is formed based on the active pattern. The process difficulty of forming the single crystal active pattern can be reduced, the defect that holes exist in the active pattern can be avoided or reduced, and the electrical performance of the transistor can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure, a method for manufacturing the same, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared to static memory, DRAM has advantages such as simpler structure, lower manufacturing cost, and higher storage density. With the development of technology, the application of DRAM is becoming increasingly widespread.

[0003] To improve storage density, a three-dimensional stacked DRAM structure has been proposed, comprising several vertically stacked memory cells. Each memory cell includes a transistor and a capacitor. The active region of the transistor extends generally along a horizontal direction, and a capacitor electrode electrically connected to the transistor also extends generally along this horizontal direction. In the manufacturing process of this DRAM structure, the active region of the transistor is typically formed as a polycrystalline material (e.g., polycrystalline silicon) or an amorphous material (e.g., amorphous silicon), and it is difficult to form it as a single-crystal material (e.g., single-crystal silicon). Compared to transistors formed using polycrystalline or amorphous silicon, transistors formed using single-crystal silicon typically have larger drive currents, smaller leakage currents, and higher on / off ratios, which is beneficial for improving the performance of the aforementioned DRAM structure. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: forming a first stacked structure, a first initial vertical opening, and a second vertical opening on a semiconductor substrate, wherein the first stacked structure includes a first dielectric layer, a second dielectric pattern, and a third dielectric pattern and a fourth dielectric pattern alternately stacked between the first dielectric layer and the second dielectric pattern, the first stacked structure includes a first region, the first initial vertical opening exposes a sidewall of the first stacked structure on a first side in a second horizontal direction in the first region and a portion of the first dielectric layer located on the first side of the first region, and the second vertical opening exposes a sidewall of the first stacked structure on a second side in the second horizontal direction in the first region and a portion of the first dielectric layer located on the second side of the first region: from the first... A portion of the fourth dielectric pattern is removed from an initial vertical opening and a second vertical opening to form a first horizontal opening, wherein the first horizontal opening connects the first initial vertical opening and the second vertical opening; the first dielectric layer at the bottom of the first initial vertical opening is removed to form the first vertical opening, wherein the remaining first dielectric layer is formed as a first dielectric pattern; semiconductor material is epitaxially grown from the semiconductor substrate exposed from the first vertical opening to fill the first vertical opening and the first horizontal opening; the epitaxially grown semiconductor material located outside the first horizontal opening is removed, wherein the semiconductor material retained in the first horizontal opening serves as an active pattern, the active pattern extending along a first horizontal direction intersecting with a second horizontal direction; a transistor is formed based on the active pattern.

[0005] In some embodiments, after removing the epitaxially grown semiconductor material located outside the first horizontal opening, the surface of the semiconductor substrate at the bottom of the first vertical opening is lower than the surface of the semiconductor substrate at the bottom of the second vertical opening.

[0006] In some embodiments, the first stacked structure further includes a second region adjacent to the first region in the first horizontal direction; forming the first stacked structure, the first initial vertical opening, and the second vertical opening on the semiconductor substrate includes: sequentially forming a first dielectric layer, alternatingly stacked third and fourth dielectric layers, and a second dielectric layer on the semiconductor substrate; etching the second dielectric layer and the alternatingly stacked third and fourth dielectric layers to form the first stacked structure, a first groove located on a first side of the first region and the second region of the first stacked structure, and a second groove located on a second side of the first region and the second region of the first stacked structure; forming fifth dielectric patterns in a portion of the first groove on the first side of the second region and a portion of the second groove on the second side of the second region, wherein the remaining portion of the first groove on the first side of the first region forms the first initial vertical opening, and the remaining portion of the second groove on the second side of the first region forms the second vertical opening.

[0007] In some embodiments, forming the transistor based on the active pattern includes: removing a portion of the third dielectric pattern from the first vertical opening and the second vertical opening to expose a portion of the circumferential surface of the active pattern; forming a gate dielectric pattern on the portion of the circumferential surface of the active pattern; and forming a word line covering the gate dielectric pattern, wherein the active pattern and the gate dielectric pattern pass through the interior of the word line.

[0008] In some embodiments, the first stacked structure further includes a second region adjacent to the first region; the manufacturing method further includes forming a capacitor coupled to the transistor in the second region.

[0009] In some embodiments, the first stacked structure further includes a fourth region adjacent to the second region, the fourth region being located on the side of the second region away from the first region; forming the capacitor coupled to the transistor in the second region includes: etching the second dielectric pattern and alternating layers of the third dielectric pattern and the fourth dielectric pattern to form a third vertical opening in the fourth region; removing the fourth dielectric pattern in the second region from the third vertical opening to form a second horizontal opening, wherein the second horizontal opening exposes a first end of the transistor; forming a first electrode in the second horizontal opening, wherein the inner wall of the first electrode surrounds a first receiving groove; forming a capacitor dielectric layer covering the inner wall of the first electrode, and forming a second electrode filling the first receiving groove and the third vertical opening; wherein the first electrode, the capacitor dielectric layer, and the second electrode form the capacitor.

[0010] In some embodiments, the first stacked structure further includes a fourth region adjacent to the second region, the fourth region being located on the side of the second region away from the first region; forming the capacitor coupled to the transistor in the second region includes: etching the second dielectric pattern and alternating layers of the third dielectric pattern and the fourth dielectric pattern to form a third vertical opening in the fourth region; removing the fourth dielectric pattern in the second region from the third vertical opening to form a second horizontal opening, wherein the second horizontal opening exposes one end of the capacitor; forming a first electrode in the second horizontal opening, wherein the inner wall of the first electrode forms a first receiving groove; removing a portion of the third dielectric pattern in the second region from the third vertical opening to form a second receiving groove, wherein the second receiving groove exposes a portion of the outer wall of the first electrode; forming a capacitor dielectric layer covering the inner wall and the portion of the outer wall of the first electrode, and forming a second electrode filling the first receiving groove, the second receiving groove, and the third vertical opening; wherein the first electrode, the capacitor dielectric layer, and the second electrode form the capacitor.

[0011] In some embodiments, the first stack structure further includes a third region adjacent to the first region, the third region being located on the side of the first region away from the second region; the manufacturing method further includes: forming bit lines coupled to the transistor and contact plugs coupled to the bit lines in the third region.

[0012] In some embodiments, forming the bit line coupled to the transistor and the contact plug coupled to the bit line in the third region includes: etching the second dielectric pattern and alternately stacked third and fourth dielectric patterns to form a plurality of fourth vertical openings in the third region, wherein the plurality of fourth vertical openings are arranged along the second horizontal direction, each of the plurality of fourth vertical openings exposes a portion of the first dielectric pattern in the third region, the third region includes a first sub-region located between adjacent fourth vertical openings, and the third region also includes a sub-region located near the first dielectric pattern between the plurality of fourth vertical openings and the first sub-region. A second sub-region on one side of the region; etching the first stacked structure in the first sub-region to form a contact hole, wherein the contact hole exposes a portion of the fourth dielectric pattern at the same level as the transistor; forming a protective dielectric layer covering the sidewalls of the contact hole; forming a contact plug filling the contact hole; removing a portion of the fourth dielectric pattern from the plurality of fourth vertical openings to form a third horizontal opening, wherein the third horizontal opening exposes the second end of the transistor and the bottom of the contact plug; forming the bit line in the third horizontal opening, wherein the bit line is coupled to the second end of the transistor, and the portion of the bit line extending to the bottom of the contact plug is coupled to the contact plug.

[0013] According to a second aspect of the present disclosure, a semiconductor structure is provided, comprising: a semiconductor substrate; a stacked structure located on the semiconductor substrate, wherein the stacked structure includes a transistor located in a first region, the active pattern of the transistor extending along a first horizontal direction, the stacked structure further including a first dielectric pattern located between the active pattern and the semiconductor substrate; a first isolation region and a second isolation region located on the semiconductor substrate, wherein the first isolation region is located on a first side of the first region in a second horizontal direction, the second isolation region is located on a second side of the first region in the second horizontal direction, the second horizontal direction intersecting the first horizontal direction; wherein the first dielectric pattern extends from the first region into the second isolation region, and the first dielectric pattern does not extend into the first isolation region.

[0014] In some embodiments, the semiconductor structure further includes: a first isolation pattern located in the first isolation region; and a second isolation pattern located in the second isolation region; wherein the first isolation pattern is located on a portion of the first dielectric pattern extending from the first region into the second isolation region, and the orthographic projection of the second isolation pattern on the semiconductor substrate does not overlap with the orthographic projection of the first dielectric pattern on the semiconductor substrate.

[0015] In some embodiments, the average doping concentration of the surface region of the semiconductor substrate at the bottom of the first isolation pattern is greater than the average doping concentration of the surface region of the semiconductor substrate at the bottom of the second isolation pattern.

[0016] In some embodiments, the stacked structure further includes word lines extending in a vertical direction, wherein the vertical direction is perpendicular to both the first horizontal direction and the second horizontal direction, the active pattern passes through the interior of the word lines, and the word lines include a first conductive portion located on a first side of the active pattern in the second horizontal direction and a second conductive portion located on a second side of the active pattern in the second horizontal direction, wherein the size of the first conductive portion in the vertical direction is larger than the size of the second conductive portion in the vertical direction.

[0017] In some embodiments, the stacked structure further includes a capacitor located in a second region adjacent to the first region. The capacitor includes a first electrode, a second electrode, and a capacitor dielectric layer located between the first electrode and the second electrode. The first electrode extends horizontally and is coupled to the transistor. The second electrode covers the inner wall of the first electrode, or the second electrode covers the inner wall of the first electrode and a portion of the outer wall of the first electrode.

[0018] In some embodiments, the stacked structure further includes a bit line and a contact plug located in a third region, and a protective dielectric layer covering the sidewalls of the contact plug, the third region being adjacent to the first region and located on the side of the first region away from the second region, the bit line being coupled to the transistor, and a portion of the bit line extending to the bottom of the contact plug being coupled to the contact plug.

[0019] According to a third aspect of the present disclosure, an electronic device is provided, including a processor and a memory. The memory is coupled to the processor, and the memory includes a semiconductor structure provided in any embodiment of the present disclosure.

[0020] In the embodiments of this disclosure, the vertically stacked and horizontally extended active patterns are formed by unilateral lateral epitaxial growth on a semiconductor substrate. This not only helps to reduce the process difficulty of forming single-crystal active patterns, but also avoids or reduces the defects of voids inside the active patterns, thereby improving the electrical performance of transistors. Attached Figure Description

[0021] Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of this disclosure;

[0022] Figure 2A and Figure 2BA schematic diagram of a semiconductor structure in one stage of a manufacturing method provided in some embodiments of this disclosure;

[0023] Figures 3A-3D A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0024] Figures 4A-4D A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0025] Figures 5A-5C A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0026] Figures 6A-6C A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0027] Figure 7A This disclosure provides schematic diagrams of the epitaxial growth process (single-sided lateral epitaxial growth) of semiconductor materials according to some embodiments;

[0028] Figure 7B This is a schematic diagram illustrating the epitaxial growth process (bilateral lateral epitaxial growth) of a semiconductor material.

[0029] Figures 8A-8E A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0030] Figures 9A-9C A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0031] Figure 10A-10D A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0032] Figure 11A-11C A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0033] Figure 12 A schematic flowchart illustrating a method for manufacturing another semiconductor structure provided in some embodiments of this disclosure;

[0034] Figure 13A and Figure 13B A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0035] Figures 14A-14C A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0036] Figures 15A-15C A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0037] Figures 16A-16D A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0038] Figures 17A-17C A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0039] Figures 18A-18D A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure;

[0040] Figures 19A-19D A schematic diagram of a semiconductor structure for another stage of a manufacturing method provided in some embodiments of this disclosure.

[0041] Figure 20 A schematic block diagram of a memory structure provided for some embodiments of this disclosure;

[0042] Figures 21A-21D A schematic diagram of a semiconductor structure provided for some embodiments of this disclosure;

[0043] Figure 22 This is a schematic block diagram of the structure of an electronic device provided in some embodiments of this disclosure. Detailed Implementation

[0044] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0045] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0046] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0047] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0048] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0049] In embodiments of this disclosure, the term "coupling" refers to the operative connection of two (or more) conductive structures to each other. Depending on actual needs, this may include, but is not limited to, the following: 1) two conductive structures are directly electrically connected; 2) two conductive structures are indirectly electrically connected (through other conductive structures); 3) although two conductive structures are not electrically connected (e.g., an insulating layer is provided between them), one of the two conductive structures can control the electrical performance of the other two conductive structures in response to an electrical signal, for example, a gate (or word line) is coupled to an active region (or channel region).

[0050] It should be noted that the technical solutions and technical features described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0051] This disclosure provides at least some embodiments of a method for manufacturing a semiconductor structure. The method includes: forming a first stacked structure, a first initial vertical opening, and a second vertical opening on a semiconductor substrate, wherein the first stacked structure includes a first dielectric layer, a second dielectric pattern, and a third dielectric pattern and a fourth dielectric pattern alternately stacked between the first dielectric layer and the second dielectric pattern. The first stacked structure includes a first region. The first initial vertical opening exposes a sidewall of the first stacked structure on a first side in a second horizontal direction and a portion of the first dielectric layer located on the first side of the first region. The second vertical opening exposes a sidewall of the first stacked structure on a second side in a second horizontal direction and a portion of the first dielectric layer located on the second side of the first region. A portion of the fourth dielectric pattern is removed to form a first horizontal opening, wherein the first horizontal opening connects a first initial vertical opening and a second vertical opening; the first dielectric layer at the bottom of the first initial vertical opening is removed to form a first vertical opening, wherein the remaining first dielectric layer is formed as a first dielectric pattern; semiconductor material is epitaxially grown from the semiconductor substrate exposed by the first vertical opening to fill the first vertical opening and the first horizontal opening; the epitaxially grown semiconductor material located outside the first horizontal opening is removed, wherein the semiconductor material retained in the first horizontal opening serves as an active pattern, the active pattern extending along a first horizontal direction intersecting with a second horizontal direction; a transistor is formed based on the active pattern.

[0052] In the manufacturing method provided in the embodiments of this disclosure, active patterns that are vertically stacked and horizontally extended are formed by unilateral lateral epitaxial growth on a semiconductor substrate. This not only helps to reduce the process difficulty of forming single-crystal active patterns, but also helps to reduce defects in the formation of incomplete active patterns, thereby improving the electrical performance of transistors.

[0053] Figure 1 This is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of this disclosure. For example, as... Figure 1 As shown, some embodiments of this disclosure provide a method for manufacturing a semiconductor structure that may include the following steps S100 to S600.

[0054] S100: A first stacked structure, a first initial vertical opening, and a second vertical opening are formed on a semiconductor substrate, wherein the first stacked structure includes a first dielectric layer, a second dielectric pattern, and a third dielectric pattern and a fourth dielectric pattern alternately stacked between the first dielectric layer and the second dielectric pattern. The first stacked structure includes a first region. The first initial vertical opening exposes the sidewall of the first stacked structure in the first region on a first side in a second horizontal direction and a portion of the first dielectric layer located on the first side of the first region. The second vertical opening exposes the sidewall of the first stacked structure in the first region on a second side in a second horizontal direction and a portion of the first dielectric layer located on the second side of the first region.

[0055] For example, in some embodiments, step S100 may include the following steps S110 to S130.

[0056] S110: A first dielectric layer, an alternately stacked third dielectric layer, a fourth dielectric layer, and a second dielectric layer are sequentially formed on a semiconductor substrate.

[0057] Figure 2A A top view of the structure obtained according to step S110, provided for some embodiments of this disclosure; Figure 2B For along Figure 2A A schematic diagram of the cross-section taken from the N1-N2 line. For example, as shown... Figure 2A and Figure 2B As shown, a first dielectric layer 110M, an alternately stacked third dielectric layer 130M and fourth dielectric layer 140M, and a second dielectric layer 120M can be sequentially formed on a semiconductor substrate 100.

[0058] For example, the semiconductor substrate 100 can be a single-crystal substrate, including but not limited to single-crystal silicon substrates, single-crystal germanium substrates, etc. The embodiments of this disclosure are described with the semiconductor substrate 100 being a single-crystal silicon substrate, but this should not be regarded as a limitation of this disclosure.

[0059] For example, the material of the first dielectric layer 110M may include silicon carbide (SiC) or silicon carbon nitride (SiCN). For example, the material of the third dielectric layer 130M may include silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON). For example, the material of the fourth dielectric layer 140M may include silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON). For example, the material of the second dielectric layer 120M may include silicon carbide (SiC) or silicon carbon nitride (SiCN). It is understood that the material of the third dielectric layer 130M differs from the material of the fourth dielectric layer 140M, and there is typically a certain etching selectivity between them. It is also understood that the materials of the first dielectric layer 110M and the second dielectric layer 120M may be the same or different.

[0060] For example, in some examples, the fourth dielectric layer 140M is disposed between two adjacent third dielectric layers 130M.

[0061] For example, in some examples, an interface layer 105M may also be formed on the surface of the semiconductor substrate 100, with a first dielectric layer 110M, alternating layers of a third dielectric layer 130M and a fourth dielectric layer 140M, and a second dielectric layer 120M all located on the interface layer 105M. For example, the material of the interface layer 105M may be silicon oxide (SiO2). For example, the interface layer 105M may be formed by natural oxidation of the semiconductor substrate 100, or it may be formed through an oxidation process. For example, the interface layer 105M may serve as a buffer layer for forming the first dielectric layer 110M.

[0062] S120: Etch the second dielectric layer and the alternately stacked third and fourth dielectric layers to form a first stacked structure, a first groove located on the first side of the first region and the second region of the first stacked structure, and a second groove located on the second side of the first region and the second region of the first stacked structure.

[0063] Figure 3A A top view of the structure obtained according to step S120, provided for some embodiments of this disclosure; Figure 3B For along Figure 3A A schematic diagram of the cross-section taken by line A1-A2 in the diagram; Figure 3C For along Figure 3A A schematic diagram of the cross-section taken by line B1-B2 in the diagram;

[0064] Figure 3D For along Figure 3A A schematic diagram of the cross-section taken by line D1-D2 in the diagram. For example, as shown... Figures 3A-3D As shown, in step S120, in Figure 2A and Figure 2B Based on the structure shown, a second dielectric layer 120M and alternating layers of a third dielectric layer 130M and a fourth dielectric layer 140M can be etched to form a first stacked structure. Grooves (as shown in Figures T0-1, T0-2, T0-3, T0-4, T0-5) are located on opposite sides of the first region (as shown in Figures R1-1, R1-2, R1-3, R1-4) and the second region (as shown in Figures R2-1, R2-2, R2-3, R2-4) in the second horizontal direction Y. For example, as... Figures 3A-3D As shown, grooves T0-1, T0-2, T0-3, T0-4, and T0-5 expose portions of the top surface of the first dielectric layer 110M. The first dielectric layer 110M can serve as an etching stop layer.

[0065] For example, such as Figures 3A-3DAs shown, the first stacking structure includes multiple first regions R1 (as defined by the vertical dashed lines R1-1, R1-2, R1-3, and R1-4, collectively referred to as R1) and multiple second regions R2 corresponding one-to-one with the multiple first regions R1 (as defined by the vertical dashed lines R2-1, R2-2, R2-3, and R2-4, collectively referred to as R2). For example, the first regions R1-1, R1-2, R1-3, and R1-4 and the second regions R2-1, R2-2, R2-3, and R2-4 all extend along the first horizontal direction X. For example, the first region R1-i and the second region R2-i are adjacent to each other in the first horizontal direction X, where i = 1, 2, 3, and 4.

[0066] For example, such as Figure 3A and Figure 3D As shown, for the first region R1-1 and the second region R2-1, the groove T0-1 is located on its second side ( Figure 3D The second groove (on the left side of R1-1), groove T0-2 is located on its first side ( Figure 3D The first groove (right side of R1-1); for the first region R1-2 and the second region R2-2, the groove T0-2 is located on its first side ( Figure 3D The first groove (on the left side of R1-2), groove T0-3 is located on its second side ( Figure 3D The second groove (to the right of R1-2); for the first region R1-3 and the second region R2-3, groove T0-3 is located on its second side ( Figure 3D The second groove (on the left side of R1-3), groove T0-4 is located on its first side ( Figure 3D The first groove (right side of R1-3); for the first region R1-4 and the second region R2-4, the groove T0-4 is located on its first side ( Figure 3D The first groove (on the left side of R1-4), groove T0-5 is located on its second side ( Figure 3D The second groove (on the right side of R1-4). For example, the first groove is used to form a subsequent first vertical opening, and the second groove is used to form a subsequent second vertical opening.

[0067] It is understood that, in the embodiments of this disclosure, for a single region / structure, the first side refers to one of the two opposite sides, and the second side refers to the other of the two opposite sides, neither of which is limited to a specific side (such as the left / right side mentioned above); for different regions / structures, the meanings of the first side and the second side may be different, for example, they can be interchanged.

[0068] For example, in some examples, such as Figures 3A-3DAs shown, the first stacking structure may further include a third region R3; the third region R3 is adjacent to the first region R1 in the first horizontal direction X, and the third region R3 is located on the side of the first region R1 away from the second region R2.

[0069] For example, in some examples, such as Figures 3A-3D As shown, the first stacked structure may further include a fourth region R4; the fourth region R4 is adjacent to the second region R2 in the first horizontal direction X, and the fourth region R4 is located on the side of the second region R2 away from the first region R1.

[0070] Understandably, along Figure 3A A schematic diagram of the cross-section taken by line C1-C2 in the diagram and Figure 3C Similar; along Figure 3A A schematic diagram of the cross-section taken from line E1-E2 in the diagram. Figure 3D Similarly. For the sake of brevity, this disclosure omits the criterion of tracing along... Figure 3A A schematic diagram of the cross-sections taken from lines C1-C2 and E1-E2.

[0071] For example, after step S120, the second dielectric layer 120M is formed into a second dielectric pattern 120, the third dielectric layer 130M is formed into a third dielectric pattern 130, and the fourth dielectric layer 140M is formed into a fourth dielectric pattern 140.

[0072] S130: A fifth medium pattern is formed in a portion of the first groove on the first side of the second region and a portion of the second groove on the second side of the second region, respectively, wherein the remaining portion of the first groove on the first side of the first region is formed as a first initial vertical opening and the remaining portion of the second groove on the second side of the first region is formed as a second vertical opening.

[0073] Figure 4A A top view of the structure obtained according to step S130, provided for some embodiments of this disclosure; Figure 4B For along Figure 4A A schematic diagram of the cross-section taken by line B1-B2 in the diagram; Figure 4C For along Figure 4A A schematic diagram of the cross-section taken by line D1-D2 in the diagram;

[0074] Figure 4D For along Figure 4A A schematic diagram of the cross-section taken from line E1-E2. For example, as shown... Figures 4A-4D As shown, in step S130, in Figures 3A-3DBased on the structure shown, a fifth medium pattern 150 can be formed in a portion of the first groove (such as grooves T0-2 and T0-4) on the first side of the second region R2 and a portion of the second groove (such as grooves T0-1, T0-3, and T0-5) on the second side of the second region R2. The remaining portion of the first groove located on the first side of the first region R1 is formed as a first initial vertical opening (as shown by vertical openings P02 and P04 in the figure), and the remaining portion of the second groove located on the second side of the first region R1 is formed as a second vertical opening (as shown by vertical openings P1, P3, and P5 in the figure).

[0075] For example, the material of the fifth dielectric pattern 150 may be the same as the material of the third dielectric pattern 130 (i.e., the material of the third dielectric layer 130M), but is not limited thereto.

[0076] For example, in some examples, in step S130, it is possible to first... Figures 3A-3D A first mask layer (e.g., a photoresist layer or an amorphous carbon layer) is formed on the structure shown. The first mask layer fills part of the grooves on both sides of the first region R1 and exposes part of the grooves on both sides of the second region R2. Then, a dielectric material filling the exposed grooves on both sides of the second region R2 can be formed by spin coating and planarized by chemical mechanical polishing (CMP) to obtain a fifth dielectric pattern 150. Finally, the remaining first mask layer is removed to obtain a first initial vertical opening (as shown by vertical openings P02 and P04 in the figure) and a second vertical opening (as shown by vertical openings P1, P3, and P5 in the figure).

[0077] For example, such as Figure 4A and Figure 4C As shown, for the first region R1-1, the first initial vertical opening P02 exposes the first stacked structure in the first region R1-1 on the first side of the second horizontal direction Y ( Figure 4C The side wall of R1-1 (right side) and the first side of the first region R1-1 ( Figure 4C The first dielectric layer 110M (right side of R1-1) is partially exposed by a second vertical opening P1, which exposes the first stacked structure in the first region R1-1 on the second side of the second horizontal direction Y. Figure 4C The side wall of R1-1 (left side) and the second side located in the first region R1-1 ( Figure 4C The first dielectric layer 110M is located on the left side of R1-1; for the first region R1-2, the first initial vertical opening P02 exposes the first stacked structure in the first region R1-2 on the first side of the second horizontal direction Y. Figure 4C The side wall of R1-2 (left side) and the first side of the first region R1-2 ( Figure 4CThe first dielectric layer 110M (left side of R1-2) is partially exposed by the second vertical opening P3, which exposes the first stacked structure in the first region R1-2 on the second side of the second horizontal direction Y. Figure 4C The side wall of the right side of R1-2 and the second side located in the first region R1-2 ( Figure 4C The first dielectric layer 110M is located to the right of R1-2. The situation of the first region R1-3 is similar to that of the first region R1-1, and the situation of the first region R1-4 is similar to that of the first region R1-2. These will not be repeated here.

[0078] Understandably, along Figure 4A The schematic diagram of the cross section intercepted by line A1-A2 in the diagram is as follows: Figure 3B Similar; along Figure 4A A schematic diagram of the cross-section taken by line C1-C2 in the diagram and Figure 4B Similarly. For the sake of brevity, this disclosure omits the criterion of tracing along... Figure 4A A schematic diagram of the cross-sections taken from lines A1-A2 and C1-C2 in the diagram.

[0079] S200: Remove a portion of the fourth medium pattern from the first initial vertical opening and the second vertical opening to form a first horizontal opening, wherein the first horizontal opening connects the first initial vertical opening and the second vertical opening.

[0080] Figure 5A A top view of the structure obtained according to step S200, provided for some embodiments of this disclosure; Figure 5B For along Figure 5A A schematic diagram of the cross-section taken by line A1-A2 in the diagram; Figure 5C For along Figure 5A A schematic diagram of the cross-section taken by line D1-D2 in the diagram. For example, as shown... Figures 5A-5C As shown, in Figures 4A-4D Based on the structure shown, a portion of the fourth dielectric pattern 140 can be removed laterally by etching from the first initial vertical opening (such as vertical openings P02, P04) and the second vertical opening (such as vertical openings P1, P3, P5) to form a first horizontal opening HP1, wherein the first horizontal opening HP1 connects the first initial vertical opening and the second vertical opening.

[0081] For example, in some examples, in step S200, it is possible to first... Figures 4A-4D A second mask layer (e.g., a photoresist layer or an amorphous carbon layer) is formed on the structure shown, and the second mask layer has an opening DF1 (e.g., Figure 5A(As shown in the dashed box), the second mask layer covers the two ends of the first stacked structure in the first region R1 in the first horizontal direction X. The opening DF1 of the second mask layer only exposes the middle part of the first stacked structure in the first region R1 and the partial vertical openings on both sides of the middle part, thereby avoiding or reducing the etching of the fourth dielectric pattern 140 in the remaining regions (such as the second region R2 and the third region R3). Then, the fourth dielectric pattern 140 in the first region R1 is removed by lateral etching to form the first horizontal opening HP1 in the first region R1. Finally, the remaining second mask layer is removed.

[0082] Since the length (dimension in the first horizontal direction X) of the subsequently formed active pattern is usually greater than its width (dimension in the second horizontal direction Y), the method of etching the first horizontal opening HP1 in the second horizontal direction Y can reduce the amount of etching and reduce the difficulty of etching, thereby simplifying the manufacturing process, compared with the method of etching to form a horizontal opening to accommodate the active pattern in the first horizontal direction X.

[0083] Understandably, along Figure 5A The schematic diagram of the cross-sections taken by lines B1-B2 and C1-C2 in the diagram is as follows: Figure 4B Similar; along Figure 5A A schematic diagram of the cross-section taken from line E1-E2 in the diagram. Figure 4D Similarly. For the sake of brevity, this disclosure omits the criterion of tracing along... Figure 5A A schematic diagram of the cross-sections taken from lines B1-B2, C1-C2, and E1-E2.

[0084] S300: Remove the first dielectric layer at the bottom of the first initial vertical opening to form the first vertical opening, wherein the remaining first dielectric layer is formed as a first dielectric pattern.

[0085] Figure 6A A top view of the structure obtained according to step S300 is provided for some embodiments of this disclosure; Figure 6B For along Figure 6A A schematic diagram of the cross-section taken by line B1-B2 in the diagram; Figure 6C For along Figure 6A A schematic diagram of the cross-section taken by line D1-D2 in the diagram. For example, as shown... Figures 6A-6C As shown, in Figures 5A-5C Based on the structure shown, the first dielectric layer at the bottom of the first initial vertical opening (such as vertical openings P02, P04) can be removed to form the first vertical opening (such as vertical openings P2, P4), wherein the remaining first dielectric layer 110M is formed as the first dielectric pattern 110.

[0086] For example, in some examples, in step 300, it is possible to first... Figures 5A-5CA third mask layer (e.g., a photoresist layer or an amorphous carbon layer) is formed on the structure shown, and the third mask layer has an opening DF2 (e.g. Figure 6A As shown in the dashed box in the diagram, the third mask layer fills the second vertical opening (such as vertical openings P1, P3, P5) and the first horizontal opening HP1. The opening DF2 of the second mask layer exposes the first initial vertical opening (such as vertical openings P02, P04). Then, the first dielectric layer 110M at the bottom of the first initial vertical opening is removed by an etching process to form the first vertical opening (such as vertical openings P2, P4), which exposes a portion of the semiconductor substrate 100. Finally, the remaining third mask layer is removed. It is understood that when an interface layer 105M is formed on the surface of the semiconductor substrate 100, in order to form the first vertical opening, it is necessary to further remove the interface layer 105M at the bottom of the first initial vertical opening by an etching process.

[0087] For example, such as Figures 6A-6C As shown, the first vertical opening and the second vertical opening are arranged alternately along the second horizontal direction, and the first region R1 is located between the adjacent first vertical opening and the second vertical opening.

[0088] Understandably, along Figure 6A The schematic diagram of the cross section intercepted by line A1-A2 in the diagram is as follows: Figure 5B Similar; along Figure 6A A schematic diagram of the cross-section taken by line C1-C2 in the diagram and Figure 4B Similar; along Figure 6A A schematic diagram of the cross-section taken from line E1-E2 in the diagram. Figure 4D Similarly. For the sake of brevity, this disclosure omits the criterion of tracing along... Figure 6A A schematic diagram of the cross-sections taken from lines A1-A2, C1-C2, and E1-E2.

[0089] For example, after step S300, the first dielectric layer 110M is formed as a first dielectric pattern 110; in the case of the interface layer 105M, after step S300, the interface layer 105M is formed as an interface pattern 105 (also called an insulating pattern 105).

[0090] S400: Semiconductor material is epitaxially grown from the semiconductor substrate exposed by the first vertical opening to fill the first vertical opening and the first horizontal opening.

[0091] Figure 7A This disclosure provides schematic diagrams of the epitaxial growth process (unilateral lateral epitaxial growth) of semiconductor materials according to some embodiments. For example, as... Figure 7A As shown, in Figures 6A-6CBased on the structure shown, a semiconductor material 200 can be epitaxially grown on the semiconductor substrate 100 exposed from the first vertical opening (such as vertical openings P2, P4) to fill the first vertical opening and the first horizontal opening HP1. For example, the material of the semiconductor substrate 100 and the semiconductor material 200 are the same single-crystal semiconductor material.

[0092] For example, in some examples, in step S400, the semiconductor substrate 100 exposed by the first vertical opening can serve as a seed material for the epitaxial growth of the semiconductor material 200. For example, as Figure 7A As shown, when the semiconductor substrate 100 is a single-crystal silicon substrate, a silicon-based gas (e.g., silane, dichlorosilane, etc.) can be introduced into the vertical openings P1-P5. The silicon-based gas can flow in the vertical openings P1-P5 and the first horizontal opening HP1, and the semiconductor material 200 begins to grow when it comes into contact with the exposed semiconductor substrate 100. Since the second vertical openings (such as vertical openings P1, P3, P5) do not expose the semiconductor substrate 100, the semiconductor material 200 is epitaxially grown along the first vertical opening and epitaxially grown from the side of the first horizontal opening HP1 closest to the first vertical opening along the first horizontal opening HP1.

[0093] It is understood that in the manufacturing method provided in the embodiments of this disclosure, the semiconductor material 200 can be epitaxially grown to completely fill the first vertical opening (such as vertical openings P2, P4) and the first horizontal opening HP1, while partially filling the second vertical opening (such as vertical openings P1, P3, P5). For example, as Figure 7A As shown, even if one end of the first horizontal opening HP1 (the end closest to the first vertical opening) is filled with the epitaxially grown semiconductor material 200, silicon-based gas can still flow into the first horizontal opening HP1 from the other end of the first horizontal opening HP1 (the end closest to the second vertical opening) (as shown). Figure 7A (As indicated by the middle arrow), thus ensuring that the epitaxially grown semiconductor material 200 can completely fill the first horizontal opening HP1.

[0094] Figure 7B This is a schematic diagram illustrating the epitaxial growth process (bilateral lateral epitaxial growth) of a semiconductor material. Figure 7B In the example shown, the vertical openings P1'-P5' all expose portions of the semiconductor substrate 100'. Therefore, the semiconductor material 200' grows epitaxially along the vertical openings P1-P5 simultaneously, and also grows epitaxially from both sides of the first horizontal opening (corresponding to the first horizontal opening HP1 in this embodiment) towards and beyond the first horizontal opening. For example, as... Figure 7BAs shown, the two ends of the first horizontal opening may close prematurely due to being filled with semiconductor material 200', preventing the silicon-based gas from continuously flowing into the first horizontal opening. This results in the semiconductor material 200' only partially filling the first horizontal opening, meaning there is an unfilled area V (i.e., a void) in the first horizontal opening. It is understandable that... Figure 7B The diagram also shows interface pattern 105', first medium pattern 110', second medium pattern 120', third medium pattern 130', fourth medium pattern 140', and first regions R1_1, R1_2, R1_3, and R1_4. These structures or regions can be referred to the corresponding descriptions of the structures or regions in the embodiments of this disclosure, and will not be repeated here.

[0095] and Figure 7B Compared to the examples shown, in the embodiments of this disclosure, such as Figure 7A As shown, the epitaxially grown semiconductor material 200 can completely fill the first horizontal opening HP1, thereby avoiding or reducing defects such as voids inside the subsequently formed active pattern.

[0096] S500: Remove the epitaxially grown semiconductor material located outside the first horizontal opening, wherein the semiconductor material retained in the first horizontal opening is an active pattern, the active pattern extends along the first horizontal direction, and the first horizontal direction intersects with the second horizontal direction.

[0097] Figure 8A A top view of the structure obtained according to step S500, provided for some embodiments of this disclosure; Figure 8B For along Figure 8A A schematic diagram of the cross-section taken by line A1-A2 in the diagram; Figure 8C For along Figure 8A A schematic diagram of the cross-section taken by line B1-B2 in the diagram;

[0098] Figure 8D For along Figure 8A A schematic diagram of the cross-section taken by line C1-C2 in the diagram; Figure 8E For along Figure 8A A schematic diagram of the cross-section taken by line D1-D2 in the diagram. For example, as shown... Figures 8A-8E As shown, in Figure 7A Based on the structure shown, the epitaxially grown semiconductor material 200 located outside the first horizontal opening HP1 can be removed. The semiconductor material 200 retained in the first horizontal opening HP1 serves as an active pattern 210, which extends along a first horizontal direction X and intersects with a second horizontal direction Y. For example, the first horizontal direction X and the second horizontal direction Y can be perpendicular to each other.

[0099] For example, in some examples, in Figure 7ABased on the structure shown, an etching process can be used to remove the semiconductor material 200 outside the first horizontal opening HP1. For example, in order to ensure complete removal of the semiconductor material 200 outside the first horizontal opening HP1 (especially the semiconductor material in the first vertical opening), the semiconductor substrate 100 at the bottom of the first vertical opening is usually over-etched; that is, after removing the epitaxially grown semiconductor material 200 located outside the first horizontal opening HP1, the surface of the semiconductor substrate 200 at the bottom of the first vertical opening (such as vertical openings P2, P4) is lower than the surface of the semiconductor substrate 200 at the bottom of the second vertical opening (such as vertical openings P1, P3, P5).

[0100] Understandably, along Figure 8A A schematic diagram of the cross-section taken from line E1-E2 in the diagram. Figure 4D Similarly. For the sake of brevity, this disclosure omits the criterion of tracing along... Figure 8A A schematic diagram of the cross-section taken from line E1-E2 in the diagram.

[0101] S600: Transistor formed based on active patterning.

[0102] For example, in some embodiments, step S600 may include the following steps S610 to S630.

[0103] S610: Remove a portion of the third dielectric pattern from the first vertical opening and the second vertical opening to expose a portion of the circumferential surface of the active pattern.

[0104] Figure 9A A top view of the structure obtained according to step S610, provided for some embodiments of this disclosure; Figure 9B For along Figure 9A A schematic diagram of the cross-section taken by line A1-A2 in the diagram; Figure 9C For along Figure 9A A schematic diagram of the cross-section taken by line D1-D2 in the diagram. For example, as shown... Figures 9A-9C As shown, in Figures 8A-8E Based on the structure shown, a portion of the third dielectric pattern 130 can be removed laterally by etching from the first vertical opening (e.g., vertical openings P02, P04) and the second vertical opening (e.g., vertical openings P1, P3, P5) to expose a portion of the circumferential surface of the active pattern 210. For example, as Figures 9A-9C As shown, after removing part of the third medium pattern 130, a fourth horizontal opening HP4 is formed.

[0105] For example, in some examples, in step S610, it is possible to first... Figures 8A-8E A fourth mask layer (e.g., a photoresist layer or an amorphous carbon layer) is formed on the structure shown, and the fourth mask layer has an opening DF3 (e.g., Figure 9A(As shown in the dashed box), the fourth mask layer covers the two ends of the first stacked structure in the first region R1 in the first horizontal direction X. The opening DF3 of the fourth mask layer only exposes the middle part of the first stacked structure in the first region R1 and the partial vertical openings on both sides of the middle part. Then, a portion of the third dielectric pattern 130 in the first region R1 is removed by lateral etching to form a fourth horizontal opening HP4 that exposes a portion of the circumferential surface of the active pattern 210. Finally, the remaining fourth mask layer is removed.

[0106] For example, in some examples, in Figures 9A-9C Based on the structure shown, the active pattern 210 can be channel-doped using vapor-phase doping or diffusion doping methods. Simultaneously, the surface region of the semiconductor substrate 100 at the bottom of the first vertical opening (e.g., vertical openings P2, P4) will also be doped due to its exposure, while the surface region of the semiconductor substrate 100 at the bottom of the second vertical opening (e.g., vertical openings P1, P3, P5) will not be doped due to its shielding. Therefore, the average doping concentration of the surface region of the semiconductor substrate 100 at the bottom of the first vertical opening is different from the average doping concentration of the surface region of the semiconductor substrate 100 at the bottom of the second vertical opening; for example, the former is greater than the latter.

[0107] For example, gas-phase doping can be achieved by doping a dopant (e.g., boron or phosphorus) into the active pattern 210 using a doping gas and thermal annealing. Alternatively, diffusion doping can involve forming a dielectric material containing dopant atoms (e.g., borosilicate glass (BSG) or phosphorus silicate glass (PSG)) within a vertical opening, followed by thermal annealing to allow the dopant atoms to diffuse into the active pattern 210. Of course, after doping, any remaining dielectric material containing dopant atoms needs to be removed.

[0108] Understandably, along Figure 9A The schematic diagram of the cross-section taken by line B1-B2 in the diagram is as follows: Figure 8C Similar; along Figure 9A A schematic diagram of the cross-section taken by line C1-C2 in the diagram and Figure 8D Similar; along Figure 9A A schematic diagram of the cross-section taken from line E1-E2 in the diagram. Figure 4D Similarly. For the sake of brevity, this disclosure omits the criterion of tracing along... Figure 9A A schematic diagram of the cross-sections taken from lines B1-B2, C1-C2, and E1-E2.

[0109] S620: A gate dielectric pattern is formed on a portion of the circumferential surface of an active pattern.

[0110] Figure 10A A top view of the structure obtained according to step S620, provided for some embodiments of this disclosure; Figure 10B For along Figure 10AA schematic diagram of the cross-section taken by line A1-A2 in the diagram; Figure 10C For along Figure 10A A schematic diagram of the cross-section taken by line B1-B2 in the diagram; Figure 10D For along Figure 10A A schematic diagram of the cross-section taken by line D1-D2 in the diagram. For example, as shown... Figure 10A-10D As shown, in Figures 9A-9C Based on the structure shown, a gate dielectric pattern 215 can be formed on a portion of the circumferential surface of the active pattern 210.

[0111] For example, in some examples, in step S620, an oxide gate dielectric pattern 215 can be formed on a portion of the circumferential surface of the active pattern 210 using an in-situ steam generation (ISSG) process; in this case, a sixth oxide dielectric pattern 115 is formed on the surface of the semiconductor substrate exposed at the bottom of the first vertical opening (such as vertical openings P2, P4). Further, for example, another gate dielectric pattern (e.g., a high-K dielectric pattern, but not limited to) can be conformally deposited on the surface of the gate oxide layer 215; it is understood that in this case, the bottom and sidewalls of the vertical openings P1-P5 are also covered by a high-K dielectric layer formed synchronously with the high-K dielectric pattern.

[0112] For example, in other examples, in step S620, a gate dielectric pattern can be conformally deposited directly on a portion of the circumferential surface of the active pattern 210; it is understood that in this case, the bottom and sidewalls of the vertical openings P1-P5 will also be covered by a dielectric layer formed synchronously with the gate dielectric pattern.

[0113] Understandably, along Figure 10A A schematic diagram of the cross-section taken by line C1-C2 in the diagram and Figure 8D Similar; along Figure 10A A schematic diagram of the cross-section taken from line E1-E2 in the diagram. Figure 4D Similarly. For the sake of brevity, this disclosure omits the criterion of tracing along... Figure 10A A schematic diagram of the cross-sections taken from lines C1-C2 and E1-E2.

[0114] S630: A word line forming a cover grid dielectric pattern, wherein the active pattern and the grid dielectric pattern pass through the interior of the word line.

[0115] Figure 11A A top view of the structure obtained according to step S630, provided for some embodiments of this disclosure; Figure 11B For along Figure 11A A schematic diagram of the cross-section taken by line A1-A2 in the diagram; Figure 11C For along Figure 11A A schematic diagram of the cross-section taken by line D1-D2 in the diagram. For example, as shown... Figure 11A-11C As shown, in Figure 10A-10D Based on the structure shown, word lines 220 covering the gate dielectric pattern 215 can be formed. For example, word lines 220 extend in a vertical direction that is perpendicular to a first horizontal direction X and a second horizontal direction Y. For example, active pattern 210 and gate dielectric pattern 215 pass through the interior of word lines 220.

[0116] For example, in some examples, it is possible to first... Figure 10A-10D The structure shown is conformally deposited with a first conductive material layer, which completely fills the fourth horizontal opening HP4. Then, the first conductive material layer is etched back to remove portions of the first conductive material layer located on the top surfaces of the second dielectric pattern 120 and the fifth dielectric pattern 150, as well as portions of the first conductive material layer located on the bottom walls of the vertical openings P1-P5, retaining portions of the first conductive material layer located on the sidewalls of the vertical openings P1-P5 and portions of the first conductive material layer located in the fourth horizontal opening HP4. Afterwards, a fifth mask layer (such as...) is formed. Figure 11A As shown in the dashed box DF4, the fourth mask layer covers the portion of the first conductive material layer located on the sidewalls of the vertical openings P1-P5 used to form the word line 220. Next, the portion of the first conductive material layer on the sidewalls of the vertical openings P1-P5 and the portion of the first conductive material layer in the fourth horizontal opening HP4 are etched away, leaving the remaining first conductive material layer to form the word line 220. For example, the material of the first conductive material layer may include titanium nitride and / or tungsten, but is not limited to these.

[0117] For example, such as Figure 11A-11C As shown, the word line 220 includes a first conductive portion 221 located in a first vertical opening (such as vertical openings P2, P4) and a second conductive portion 222 located in a second vertical opening (such as vertical openings P1, P3, P5). The height H1 of the first conductive portion 221 is greater than the height H2 of the second conductive portion 222. Here, the height is the dimension in the vertical direction.

[0118] Understandably, along Figure 11A The schematic diagram of the cross-section taken by line B1-B2 in the diagram is as follows: Figure 10C Similar; along Figure 11A A schematic diagram of the cross-section taken by line C1-C2 in the diagram and Figure 8D Similar; along Figure 11A A schematic diagram of the cross-section taken from line E1-E2 in the diagram. Figure 4D Similarly. For the sake of brevity, this disclosure omits the criterion of tracing along... Figure 11A A schematic diagram of the cross-sections taken from lines B1-B2, C1-C2, and E1-E2.

[0119] It should be noted that the above-described method for forming character lines is exemplary. In other embodiments, double-sided character lines (including only the first conductive portion 221 and the second conductive portion 222 of the character line 220, excluding the portion of the character line 220 located in the fourth horizontal opening HP4) or single-sided character lines (including only one of the first conductive portion 221 and the second conductive portion 222) can be formed; in this case, it is not necessary to form the fourth horizontal opening HP4.

[0120] For example, in some examples, in Figure 11A-11C Based on the structure shown, the active pattern 210 can be doped for source / drain using vapor-phase doping or diffusion doping methods. For example, during source / drain doping, it may be necessary to first remove the portions of the gate dielectric pattern 215 located on both sides of the word line 220 to expose the portions of the active pattern used to form the source / drain doped regions. Details of vapor-phase doping or diffusion doping can be found in the foregoing descriptions and will not be repeated here.

[0121] For example, in some examples, in Figure 11A-11C Based on the structure shown, a seventh medium pattern 170 (reference) can be formed that completely fills the vertical openings P1-P5 and the fourth horizontal opening HP. Figure 13A and Figure 13B (As shown). It is understood that the seventh medium pattern 170 may include one or more sub-medium patterns.

[0122] Figure 12 This is a schematic flowchart illustrating a method for manufacturing another semiconductor structure provided in some embodiments of this disclosure. For example, as... Figure 12 As shown, in Figure 1 Based on steps S100 to S600 included in the method embodiment shown, the manufacturing method may further include step S700.

[0123] S700: Forms a capacitor coupled to the transistor.

[0124] For example, in some embodiments, step S700 may include steps S710 to S740.

[0125] S710: Etch a second dielectric pattern and alternating layers of a third dielectric pattern and a fourth dielectric pattern to form a third vertical opening located in the fourth region.

[0126] S720: Remove the fourth dielectric pattern from the second region from the third vertical opening to form a second horizontal opening, wherein the second horizontal opening exposes the first end of the transistor.

[0127] Figure 13A A top view schematic diagram of the structure obtained according to steps S710 and S720, provided for some embodiments of this disclosure; Figure 13BFor along Figure 13A A schematic diagram of the cross-section taken by line A1-A2 in the diagram. For example, as shown... Figure 13A and Figure 13B As shown, in Figure 11A-11C Based on the structure shown, the second dielectric pattern 120 and the alternately stacked third dielectric pattern 130 and fourth dielectric pattern 140 can be etched first to form the third vertical opening VP1 in the fourth region R4; then, the fourth dielectric pattern 140 in the second region R2 (as shown in R2-1, R2-2, R2-3, and R2-4 in the figure) is removed by lateral etching from the third vertical opening VP1 to form the second horizontal opening HP2, wherein the second horizontal opening HP2 exposes the first terminal (drain or source) of the transistor.

[0128] Step S730: A first electrode is formed in the second horizontal opening, wherein the inner wall of the first electrode forms a first receiving groove.

[0129] Figure 14A A top view of the structure obtained according to step S730 is provided for some embodiments of this disclosure; Figure 14B For along Figure 14A A schematic diagram of the cross-section taken by line A1-A2 in the diagram. For example, as shown... Figure 14A and Figure 14B As shown, in Figure 13A and Figure 13B Based on the structure shown, a first electrode 310 can be formed in the second horizontal opening HP2, wherein the inner wall of the first electrode forms a first receiving groove HS1.

[0130] For example, in some examples, it is possible to first... Figure 13A and Figure 13B A second conductive material layer is conformally deposited on the structure shown; then, the second conductive material layer is etched back to remove the portion of the second conductive material layer outside the second horizontal opening HP2, with the portion of the second conductive material layer remaining in the second horizontal opening HP2 serving as the first electrode 310. For example, the material of the second conductive material layer may include titanium nitride and / or tungsten, but is not limited thereto.

[0131] Step S740: Form a capacitor dielectric layer covering the inner wall of the first electrode, and form a second electrode filling the first receiving groove and the third vertical opening.

[0132] Figure 15A A top view of the structure obtained according to step S740 is provided for some embodiments of this disclosure; Figure 15B For along Figure 15A A schematic diagram of the cross-section taken by line A1-A2 in the diagram. For example, as shown... Figure 15A and Figure 15B As shown, in Figure 14A and Figure 14BBased on the structure shown, a capacitor dielectric layer 315 is formed covering the inner wall of the first electrode 30, and a second electrode 320 is formed filling the first receiving groove HS1 and the third vertical opening VP1. The first electrode 310, the capacitor dielectric layer 315, and the second electrode 320 form a capacitor.

[0133] For example, in some examples, it is possible to first... Figures 14A-14B The structure shown conformally deposits a dielectric material layer, followed by a third conductive material layer covering the dielectric material layer. The third conductive material layer fills the first receiving trench HS1 and the third vertical opening VP1. Finally, the portions of the third conductive material layer and the dielectric material layer (which are treated as a single unit) outside the third vertical opening VP1 and the second horizontal opening HP2 are removed by etching or planarization. The remaining portion of the dielectric material layer serves as the capacitor dielectric layer 315, and the remaining portion of the third conductive material layer serves as the second electrode 320. For example, the dielectric material layer may include silicon oxide, a high-k dielectric material, etc.; for example, the dielectric material layer may also include a ferroelectric or antiferroelectric dielectric material, such as ferroelectric hafnium oxide, ferroelectric hafnium zirconium oxide, etc. For example, the material of the third conductive material layer may include titanium nitride and / or tungsten, but is not limited to these.

[0134] For example, in some other embodiments, step S700 may include the following steps S710' to S750'.

[0135] S710': Etch a second dielectric pattern and alternating layers of a third dielectric pattern and a fourth dielectric pattern to form a third vertical opening located in the fourth region.

[0136] S720': Remove the fourth dielectric pattern from the second region from the third vertical opening to form a second horizontal opening, wherein the second horizontal opening exposes the first end of the transistor.

[0137] S730': A first electrode is formed in the second horizontal opening, wherein the inner wall of the first electrode forms a first receiving groove.

[0138] Steps S710' to S730' correspond to the aforementioned steps S710 to S730, respectively. Therefore, details of steps S710' to S730' can be found in the aforementioned steps S710 to S730 and... Figure 13A , Figure 13B , Figure 14A and Figure 14B The relevant descriptions will not be repeated here.

[0139] S740': Remove a portion of the third dielectric pattern from the third vertical opening in the second region to form a second receiving groove, wherein the second receiving groove exposes a portion of the outer wall of the first electrode.

[0140] Figure 14C Cross-sectional schematic diagrams of the structure obtained according to step S740' provided for some embodiments of this disclosure (along...) Figure 14A (The A1-A2 line in the diagram is cut off). For example, as shown in the diagram. Figure 14C As shown, in Figure 14B Based on the structure shown, a portion of the third dielectric pattern 130 in the second region R2 (as shown in R2-1, R2-2, R2-3, and R2-4 in the figure) is removed by transverse etching from the third vertical opening VP1 to form a second receiving groove HS2, wherein the second receiving groove HS2 exposes a portion of the outer wall of the first electrode 310. For example, in some examples, in order to maintain the stability of the first electrode 310, the length of the exposed portion of the outer wall of the first electrode 310 is less than or equal to 1 / 3 of the length of the outer wall of the first electrode 310, where the length is the dimension in the first horizontal direction X.

[0141] S750': A capacitor dielectric layer is formed covering the inner wall and part of the outer wall of the first electrode, and a second electrode is formed filling the first receiving groove, the second receiving groove and the third vertical opening.

[0142] Figure 15C Cross-sectional schematic diagrams of the structure obtained according to step S750' provided for some embodiments of this disclosure (along...) Figure 15A (The A1-A2 line in the diagram is cut off). For example, as shown in the diagram. Figure 15C As shown, in Figure 14C Based on the structure shown, a capacitor dielectric layer 315 is formed covering the inner wall and part of the outer wall of the first electrode 310, and a second electrode 320 is formed filling the first receiving groove HS1, the second receiving groove HS2, and the third vertical opening VP1. The first electrode 310, the capacitor dielectric layer 315, and the second electrode 320 form a capacitor.

[0143] For example, in some examples, it is possible to first... Figure 14C The structure shown is conformally deposited with a dielectric material layer, and then a third conductive material layer is deposited to cover the dielectric material layer. The third conductive material layer fills the first receiving trench HS1, the second receiving trench HS2 and the third vertical opening VP1. Finally, the portions of the third conductive material layer and the dielectric material layer (which are treated as a whole) located outside the third vertical opening VP1, the second horizontal opening HP2 and the second receiving trench HS2 are removed by etching or planarization. The remaining portion of the dielectric material layer serves as the capacitor dielectric layer 315 and the remaining portion of the third conductive layer serves as the second electrode 320.

[0144] It is understandable that the capacitor formed according to steps S710' to S750' can have a larger capacitance value.

[0145] S800: Forms a bit line coupled to a transistor and a contact plug coupled to the bit line.

[0146] For example, in some embodiments, step S800 may include the following steps S810 to S860.

[0147] S810: Etch a second dielectric pattern and alternating layers of a third dielectric pattern and a fourth dielectric pattern to form a plurality of fourth vertical openings in a third region, wherein the plurality of fourth vertical openings are arranged along a second horizontal direction, each of the plurality of fourth vertical openings exposes a portion of the first dielectric pattern in the third region, the third region includes a first sub-region located between adjacent fourth vertical openings, and the third region also includes a second sub-region located on the side of the plurality of fourth vertical openings and the first sub-region closer to the first region.

[0148] S820: Etch the first stacked structure in the first sub-region to form a contact hole, wherein the contact hole exposes a portion of the fourth dielectric pattern located on the same level as the transistor.

[0149] Figure 16A A top view schematic diagram of a portion of the structure obtained according to steps S810 and S820, provided for some embodiments of this disclosure; Figure 16B For along Figure 16A A schematic diagram of the cross-section taken by line A1-A2 in the diagram; Figure 16C For along Figure 16A A schematic diagram of the cross-section intercepted by the F1-F2 line in the diagram; Figure 16D For along Figure 16A A schematic diagram of the cross-section taken by line G1-G2. It can be understood that... Figure 16A Only the first region R1, the second region R2, and part of the third region R3 are shown, while the fourth region R4 is omitted.

[0150] For example, such as Figures 16A-16D As shown, in Figure 14A and Figure 14B (or Figure 14CBased on the structure shown, the second dielectric pattern 120 and alternatingly stacked third dielectric patterns 130 and fourth dielectric patterns 140 can be etched first to form a plurality of fourth vertical openings VP2 in the third region R3. The plurality of fourth vertical openings VP2 are arranged along the second horizontal direction Y. Each fourth vertical opening VP2 exposes a portion of the first dielectric pattern 110 in the third region R3. The third region R3 includes a first sub-region R3-1 located between adjacent fourth vertical openings VP2. The third region R3 also includes a second sub-region R3-2 located on the side of the plurality of fourth vertical openings VP2 and the first sub-region R3-1 closest to the first region R1 (as shown by R1-1, R1-2, R1-3, and R1-4 in the figure). Then, the first stacked structure in the first sub-region R3-1 is etched to form contact holes V (as shown by V1, V2, and V3 in the figure). The contact holes V expose a portion of the fourth dielectric pattern 140 located at the same level as the corresponding transistor. For example, in Figures 16A-16D In the example shown, three levels (low-level, intermediate-level, and high-level) of transistors are provided in the first region R1. Contact hole V1 exposes a portion of the top surface of the fourth dielectric pattern 140 at the same level as the low-level transistors, contact hole V2 exposes a portion of the top surface of the fourth dielectric pattern 140 at the same level as the intermediate-level transistors, and contact hole V3 exposes a portion of the top surface of the fourth dielectric pattern 140 at the same level as the high-level transistors.

[0151] For example, in some examples, after forming multiple fourth vertical openings VP2, a sacrificial pattern (not shown) that completely fills the multiple fourth vertical openings VP2 can be formed. For example, the material of the sacrificial pattern is different from the material of any of the first dielectric layer 110, the second dielectric layer 120, the third dielectric layer 130, and the fourth dielectric layer 140.

[0152] S830: Forms a protective medium layer covering the sidewalls of the contact hole.

[0153] S840: A contact plug that forms a filling contact hole.

[0154] Figure 17A A top view schematic diagram of a portion of the structure obtained according to steps S830 and S840, provided for some embodiments of this disclosure; Figure 17B For along Figure 17A A schematic diagram of the cross-section taken by line A1-A2 in the diagram; Figure 17C For along Figure 17A A schematic diagram of the cross-section intercepted by lines F1-F2 in the diagram. For example, as shown... Figures 17A-17C As shown, in Figures 16A-16DBased on the structure shown (the fourth vertical opening VP2 is filled with a sacrificial pattern), a protective medium layer 415 covering the sidewalls of the contact hole V (as shown in V1, V2, and V3 in the figure) can be formed first, and then a contact plug 420 filling the contact hole V can be formed.

[0155] For example, in some examples, it is possible to first... Figures 16A-16D A protective dielectric material layer is conformally deposited on the structure shown (the fourth vertical opening VP2 is filled with a sacrificial pattern); then, the protective dielectric material layer is etched back to remove the portion of the protective dielectric material layer outside the contact hole V and the portion of the protective dielectric material layer on the bottom wall of the contact hole V, with the portion of the protective dielectric material layer remaining on the sidewall of the contact hole V serving as the protective dielectric layer 410; subsequently, a fourth conductive material layer is deposited, filling the contact hole V; finally, the portion of the fourth conductive material layer outside the contact hole V is removed by an etching process or a planarization process, with the portion of the fourth conductive material layer remaining in the contact hole V serving as the contact plug 420. For example, the material of the fourth conductive material layer may include titanium nitride and / or tungsten, but is not limited thereto.

[0156] For example, in some examples, the sacrificial pattern in the fourth vertical opening VP2 can be removed after the protective medium layer 415 and the contact plug 420 are formed.

[0157] Understandably, along Figure 17A A schematic diagram of the cross-section intercepted by the G1-G2 line and Figure 16D Similarly. For the sake of brevity, this disclosure omits the criterion of tracing along... Figure 17A A schematic diagram of the cross-section taken from line G1-G2 in the diagram.

[0158] S850: A portion of the fourth dielectric pattern is removed from multiple fourth vertical openings to form a third horizontal opening, wherein the third horizontal opening exposes the second end of the transistor and the bottom of the contact plug.

[0159] Figure 18A A top view schematic diagram of a portion of the structure obtained according to step S850, provided for some embodiments of this disclosure; Figure 18B For along Figure 18A A schematic diagram of the cross-section taken by line A1-A2 in the diagram; Figure 18C For along Figure 18A A schematic diagram of the cross-section intercepted by the F1-F2 line in the diagram; Figure 18D For along Figure 18A A schematic diagram of the cross-section taken by the G1-G2 line. For example, as shown... Figures 18A-18D As shown, in Figures 17A-17CBased on the structure shown, a portion of the fourth dielectric pattern in the third region R3 can be removed by lateral etching from multiple fourth vertical openings VP2 to form a third horizontal opening HP3, wherein the third horizontal opening HP3 exposes the second end (source or drain) of the transistor and the bottom of the contact plug 420.

[0160] S860: A bit line is formed in the third horizontal opening, wherein the bit line is coupled to the second end of the transistor, and the portion of the bit line extending to the bottom of the contact plug is coupled to the contact plug.

[0161] Figure 19A A top view schematic diagram of a portion of the structure obtained according to step S860, provided for some embodiments of this disclosure; Figure 19B For along Figure 19A A schematic diagram of the cross-section taken by line A1-A2 in the diagram; Figure 19C For along Figure 19A A schematic diagram of the cross-section intercepted by the F1-F2 line in the diagram; Figure 19D For along Figure 19A A schematic diagram of the cross-section taken by the G1-G2 line. For example, as shown... Figures 19A-19D As shown, in Figures 18A-18D Based on the structure shown, a bit line 410 can be formed in the third horizontal opening HP3, wherein the bit line 410 is coupled to the second end of the transistor, and the portion of the bit line 410 extending to the bottom of the contact plug 420 is coupled to the contact plug 420. For example, as Figure 19A and Figure 19D As shown, the main body of bit line 410 extends along the second horizontal direction Y.

[0162] For example, in some examples, it is possible to first... Figures 18A-18D A fifth conductive material layer is conformally deposited on the structure shown; then, the fifth conductive material layer is etched back to remove the portion of the fifth conductive material layer outside the third horizontal opening HP3, with the portion of the fifth conductive material layer remaining in the third horizontal opening HP3 serving as bit line 410. For example, the material of the fifth conductive material layer may include titanium nitride and / or tungsten, but is not limited thereto.

[0163] It is understandable that, in some embodiments, for the convenience of performing step S800, it may be necessary to first... Figure 14A and Figure 14B (or Figure 14C A dielectric layer is formed on the structure shown in the figure. The material of the dielectric layer can be the same as that of the second dielectric layer, so as to protect the second region R2, the third region R3, and the fourth region R4 during the execution of step S800.

[0164] It should be noted that one or more steps in the above manufacturing method may include multiple sub-steps, which may be executed sequentially or in parallel as needed; furthermore, depending on actual needs, the sub-steps within different steps may be executed sequentially, in parallel, or alternately. For example, for Figure 12 The manufacturing method shown can be performed by executing step S700 first and then step S800; or by executing step S800 first and then step S700.

[0165] For example, in some embodiments, a semiconductor structure (referred to as the first semiconductor structure) obtained according to the above manufacturing method (e.g., steps S100 to S800) can be bonded to another semiconductor structure (referred to as the second semiconductor structure) to obtain a memory. Figure 20 This is a schematic block diagram illustrating the structure of a memory provided for some embodiments of this disclosure. For example, as... Figure 20 As shown, the first semiconductor structure 1000 and the second semiconductor structure 2000 can be bonded together through the bonding interface 3000 to obtain the memory 10. For example, the above bonding can be achieved using hybrid bonding technology.

[0166] For example, in some examples, such as Figure 20 As shown, the second semiconductor structure 2000 may include peripheral circuitry 2100, which may include multiple transistors for implementing the structure and function of control circuits such as word line drivers (e.g., sub-word line drivers) and sense amplifiers (SA).

[0167] For example, in some examples, such as Figure 20 As shown, after bonding, word lines 220 and contact plugs 420 in the stacked structure of the first semiconductor structure 1000 can be coupled to the peripheral circuits 2100 in the second semiconductor structure 2000.

[0168] This disclosure also provides a semiconductor structure in at least some embodiments. For example, the semiconductor structure can be obtained by the manufacturing method described above, but is not limited thereto. Figure 21A A top view schematic diagram of a semiconductor structure provided for at least some embodiments of this disclosure; Figure 21B For along Figure 21A A schematic diagram of the cross-section taken by line B1-B2 in the diagram; Figure 21C For along Figure 21A A schematic diagram of the cross-section taken by line C1-C2 in the diagram; Figure 21D For along Figure 21A A schematic diagram of the cross-section taken along line D1-D2. Along... Figure 21A The schematic diagram of the cross-section taken by line A1-A2 in the diagram can be referenced. Figure 15B (or Figure 15C )and Figure 19B The combination of these elements, where the cross-sectional structures of the second region R2 (R2-2) and the fourth region R4 can be referenced. Figure 15B (or Figure 15C The cross-sectional structures of the corresponding regions in the diagram, including the third region R3 and the first region R1 (e.g., R1-2), can be referenced. Figure 19B (or Figure 15C The cross-sectional structure of the corresponding region in ); along Figure 21A The schematic diagram of the cross-section intercepted by the F1-F2 line can be referenced. Figure 19C As shown; along Figure 21A The schematic diagram of the cross-section taken by the G1-G2 line can be referenced. Figure 19D As shown.

[0169] For example, such as Figures 21A-21D , Figure 15B (or Figure 15C )as well as Figure 19B-19D As shown, the semiconductor structure includes a semiconductor substrate 100 and a stacked structure located on the semiconductor substrate 100. The stacked structure includes transistors located in a first region R1 (as shown in R1-1, R1-2, R1-3, and R1-4 in the figure), with active patterns 210 of the transistors extending along a first horizontal direction X. The stacked structure also includes a first dielectric pattern 110 located between the active pattern 210 and the semiconductor substrate 100. The semiconductor structure also includes a first isolation region (as shown in I2 and I4 in the figure) and a second isolation region (as shown in I1, I3, and I5 in the figure) located on the semiconductor substrate 210, wherein the first isolation region is located on a first side of the first region in a second horizontal direction Y, and the second isolation region is located on a second side of the first region in the second horizontal direction Y, and the second horizontal direction Y intersects the first horizontal direction X; for example, the first horizontal direction X and the second horizontal direction Y can be perpendicular to each other. The first dielectric pattern 110 extends from the first region into the second isolation region (as shown in I1, I3, and I5 in the figure), and the first dielectric pattern 110 does not extend into the first isolation region (as shown in I2 and I4 in the figure).

[0170] For example, in some embodiments, such as Figures 21A-21D As shown, the semiconductor structure may further include a first isolation pattern 171 (i.e., a seventh dielectric pattern 170 located in the first isolation region) located in the first isolation region (as shown in I2 and I4 in the figure) and a second isolation pattern 172 (i.e., a seventh dielectric pattern 170 located in the second isolation region) located in the second isolation region (as shown in I1, I3, and I5 in the figure). For example, as Figures 21A-21DAs shown, the first isolation pattern 171 is located on the portion of the first dielectric pattern 110 extending from the first region into the second isolation region, and the orthographic projection of the second isolation pattern 172 on the semiconductor substrate 100 does not overlap with the orthographic projection of the first dielectric pattern 110 on the semiconductor substrate 100. For example, the first isolation pattern 171 and the second isolation pattern 172 have the same structure (the dimensions may differ) and material composition. For example, as... Figures 21A-21D As shown, the height of the first isolation pattern 171 is greater than the height of the second isolation pattern 172, where the height refers to the dimension in the vertical direction.

[0171] For example, in some embodiments, the average doping concentration of the surface region of the semiconductor substrate 100 at the bottom of the first isolation pattern 171 (i.e., the surface region of the semiconductor substrate 100 directly below the first isolation pattern 171) is different from the average doping concentration of the surface region of the semiconductor substrate 100 at the bottom of the second isolation pattern 172 (i.e., the surface region of the semiconductor substrate 100 directly below the second isolation pattern 172), for example, the former is greater than the latter. Here, reference can be made to the relevant description in step S610 above. It is understood that the surface region can be a region of the semiconductor substrate 100 with a certain thickness from the top surface inwards; for example, the thickness can range from 30nm to 100nm.

[0172] For example, in some embodiments, such as Figure 21A , Figure 19B and Figure 21D As shown, the stacked structure may further include word lines 220 extending in a vertical direction, wherein the vertical direction is perpendicular to the first horizontal direction X and perpendicular to the second horizontal direction Y. An active pattern 210 passes through the interior of the word lines 220. The word lines 220 include a first conductive portion 221 located on a first side of the active pattern 210 in the second horizontal direction Y and a second conductive portion 222 located on a second side of the active pattern 220 in the second horizontal direction Y. The height of the first conductive portion 221 is greater than the height of the second conductive portion 222, where the height refers to the dimension in the vertical direction. For example, as... Figure 19B and Figure 21D As shown, the semiconductor structure may also include a gate dielectric pattern 215 located between the active pattern 210 and the word line 220.

[0173] For example, in some embodiments, such as Figure 21A and Figure 15B (or Figure 15CAs shown, the stacked structure also includes a capacitor located in a second region (corresponding to regions R2 and R4 in the method embodiment). The second region is adjacent to the first region R1. The capacitor includes a first electrode 310, a second electrode 320, and a capacitor dielectric layer 315 located between the first electrode 310 and the second electrode 320. The first electrode 310 extends along a first horizontal direction X and is coupled to a transistor. The second electrode 320 covers the inner wall of the first electrode 310 (see...). Figure 15B Alternatively, the second electrode 320 covers the inner wall of the first electrode 310 and a portion of the outer wall of the first electrode 310 (see...). Figure 15C ).

[0174] For example, in some embodiments, such as Figures 21A-21C and Figure 19B-19D As shown, the stacked structure may further include a bit line 410 and a contact plug 420 located in a third region R3, and a protective dielectric layer 415 covering the sidewall of the contact plug 420. The third region R3 is adjacent to the first region R1 and is located on the side of the first region R1 away from the second region (R2 and R4). The main body of the bit line 410 extends along the second horizontal direction Y and is coupled to the transistor. The portion of the bit line 410 extending to the bottom of the contact plug 420 is coupled to the contact plug 420.

[0175] It is understood that in some embodiments, the semiconductor structure may include multiple stacked structures arranged in an array. For example, the multiple stacked structures may include stacked structures SS1, SS2, and SS3 arranged sequentially along a first horizontal direction X. Among them, stacked structure SS1 and stacked structure SS2 are substantially mirror-symmetrical and share a contact plug 420 (i.e., share region R3-1 in the method embodiment); stacked structure SS3 and stacked structure SS2 are substantially mirror-symmetrical and share a second electrode 320 (i.e., share region R4 in the method embodiment).

[0176] More details and technical effects of the semiconductor structure provided by the embodiments of this disclosure can be found in the relevant descriptions in the embodiments of the above manufacturing method, and will not be repeated here.

[0177] At least some embodiments of this disclosure also provide an electronic device. Figure 22 This is a schematic block diagram illustrating the structure of an electronic device provided in some embodiments of this disclosure. For example... Figure 22 As shown, the electronic device 1 may include a processor 20 and Figure 20 The memory 10 in the illustrated embodiment is coupled to the processor 20.

[0178] For example, processor 20 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc. Memory 10 may be configured to store data to be processed by processor 20 and / or data already processed by the processor.

[0179] For example, electronic device 1 includes, but is not limited to, mobile phones, tablets, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, in-vehicle devices, servers, workstations, etc.

[0180] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A first stacked structure, a first initial vertical opening, and a second vertical opening are formed on a semiconductor substrate. The first stacked structure includes a first dielectric layer, a second dielectric pattern, and a third and fourth dielectric pattern alternately stacked between the first dielectric layer and the second dielectric pattern. The first stacked structure includes a first region. The first initial vertical opening exposes a sidewall of the first stacked structure on a first side in a second horizontal direction within the first region, and a portion of the first dielectric layer located on the first side of the first region. The second vertical opening exposes a sidewall of the first stacked structure on a second side in the second horizontal direction within the first region, and a portion of the first dielectric layer located on the second side of the first region. A portion of the fourth medium pattern is removed from the first initial vertical opening and the second vertical opening to form a first horizontal opening, wherein the first horizontal opening connects the first initial vertical opening and the second vertical opening; The first dielectric layer at the bottom of the first initial vertical opening is removed to form the first vertical opening, wherein the remaining first dielectric layer is formed as a first dielectric pattern; Semiconductor material is epitaxially grown on the semiconductor substrate exposed from the first vertical opening to fill the first vertical opening and the first horizontal opening; Remove the epitaxially grown semiconductor material located outside the first horizontal opening, wherein the semiconductor material retained in the first horizontal opening is an active pattern that extends along a first horizontal direction and intersects with a second horizontal direction; Transistors are formed based on the active pattern.

2. The manufacturing method according to claim 1, characterized in that, After removing the epitaxially grown semiconductor material located outside the first horizontal opening, the surface of the semiconductor substrate at the bottom of the first vertical opening is lower than the surface of the semiconductor substrate at the bottom of the second vertical opening.

3. The manufacturing method according to claim 1 or 2, characterized in that, The first stacked structure further includes a second region adjacent to the first region in the first horizontal direction; Forming the first stacked structure, the first initial vertical opening, and the second vertical opening on the semiconductor substrate includes: A first dielectric layer, an alternately stacked third dielectric layer, a fourth dielectric layer, and a second dielectric layer are sequentially formed on the semiconductor substrate; The second dielectric layer and the alternately stacked third and fourth dielectric layers are etched to form the first stacked structure, a first groove located on the first side of the first region and the second region of the first stacked structure, and a second groove located on the second side of the first region and the second region of the first stacked structure. A fifth medium pattern is formed in the portion of the first groove on the first side of the second region and the portion of the second groove on the second side of the second region, respectively. The remaining portion of the first groove on the first side of the first region is formed as the first initial vertical opening, and the remaining portion of the second groove on the second side of the first region is formed as the second vertical opening.

4. The manufacturing method according to claim 1 or 2, characterized in that, Forming the transistor based on the active pattern includes: A portion of the third dielectric pattern is removed from the first vertical opening and the second vertical opening to expose a portion of the circumferential surface of the active pattern; A gate dielectric pattern is formed on the circumferential surface of the active pattern. A word line is formed that covers the gate dielectric pattern, wherein the active pattern and the gate dielectric pattern pass through the interior of the word line.

5. The manufacturing method according to claim 1 or 2, characterized in that, The first stacked structure also includes a second region adjacent to the first region; The manufacturing method further includes: A capacitor coupled to the transistor is formed in the second region.

6. The manufacturing method according to claim 5, characterized in that, The first stacked structure further includes a fourth region adjacent to the second region, the fourth region being located on the side of the second region away from the first region; Forming the capacitor coupled to the transistor in the second region includes: The second dielectric pattern and the alternately stacked third and fourth dielectric patterns are etched to form a third vertical opening located in the fourth region; The fourth dielectric pattern in the second region is removed from the third vertical opening to form a second horizontal opening, wherein the second horizontal opening exposes the first end of the transistor; A first electrode is formed in the second horizontal opening, wherein the inner wall of the first electrode forms a first receiving groove; A capacitor dielectric layer is formed covering the inner wall of the first electrode, and a second electrode is formed filling the first receiving groove and the third vertical opening; The capacitor is formed by the first electrode, the capacitor dielectric layer, and the second electrode.

7. The manufacturing method according to claim 5, characterized in that, The first stacked structure further includes a fourth region adjacent to the second region, the fourth region being located on the side of the second region away from the first region; Forming the capacitor coupled to the transistor in the second region includes: The second dielectric pattern and the alternately stacked third and fourth dielectric patterns are etched to form a third vertical opening located in the fourth region; The fourth dielectric pattern in the second region is removed from the third vertical opening to form a second horizontal opening, wherein the second horizontal opening exposes one end of the capacitor; A first electrode is formed in the second horizontal opening, wherein the inner wall of the first electrode forms a first receiving groove; A portion of the third dielectric pattern in the second region is removed from the third vertical opening to form a second receiving groove, wherein the second receiving groove exposes a portion of the outer wall of the first electrode; A capacitor dielectric layer is formed covering the inner wall and part of the outer wall of the first electrode, and a second electrode is formed filling the first receiving groove, the second receiving groove and the third vertical opening; The capacitor is formed by the first electrode, the capacitor dielectric layer, and the second electrode.

8. The manufacturing method according to claim 1 or 2, characterized in that, The first stacked structure further includes a third region adjacent to the first region, the third region being located on the side of the first region away from the second region; The manufacturing method further includes: Bit lines coupled to the transistor and contact plugs coupled to the bit lines are formed in the third region.

9. The manufacturing method according to claim 8, characterized in that, The third region comprises forming the bit line coupled to the transistor and the contact plug coupled to the bit line, including: The second dielectric pattern and the alternately stacked third and fourth dielectric patterns are etched to form a plurality of fourth vertical openings in the third region, wherein the plurality of fourth vertical openings are arranged along the second horizontal direction, each of the plurality of fourth vertical openings exposes a portion of the first dielectric pattern in the third region, the third region includes a first sub-region located between adjacent fourth vertical openings, and the third region also includes a second sub-region located on the side of the plurality of fourth vertical openings and the first sub-region closer to the first region; The first stacked structure in the first sub-region is etched to form a contact hole, wherein the contact hole exposes a portion of the fourth dielectric pattern located at the same level as the transistor; A protective dielectric layer is formed covering the sidewalls of the contact hole; To form a contact plug that fills the contact hole; A portion of the fourth dielectric pattern is removed from the plurality of fourth vertical openings to form a third horizontal opening, wherein the third horizontal opening exposes the second end of the transistor and the bottom of the contact plug; The bit line is formed in the third horizontal opening, wherein the bit line is coupled to the second end of the transistor, and the portion of the bit line extending to the bottom of the contact plug is coupled to the contact plug.

10. A semiconductor structure, characterized in that, include: Semiconductor substrate; A stacked structure located on the semiconductor substrate, wherein the stacked structure includes a transistor located in a first region, the active pattern of the transistor extending along a first horizontal direction, and the stacked structure further includes a first dielectric pattern located between the active pattern and the semiconductor substrate; A first isolation region and a second isolation region are located on the semiconductor substrate, wherein the first isolation region is located on a first side of the first region in a second horizontal direction, and the second isolation region is located on a second side of the first region in the second horizontal direction, the second horizontal direction intersecting the first horizontal direction; Wherein, the first medium pattern extends from the first region into the second isolation region, and the first medium pattern does not extend into the first isolation region.

11. The semiconductor structure according to claim 10, characterized in that, Also includes: A first isolation pattern located in the first isolation area; The second isolation pattern is located in the second isolation area; Wherein, the first isolation pattern is located on the portion of the first dielectric pattern that extends from the first region into the second isolation region, and the orthographic projection of the second isolation pattern on the semiconductor substrate does not overlap with the orthographic projection of the first dielectric pattern on the semiconductor substrate.

12. The semiconductor structure according to claim 10 or 11, characterized in that, The average doping concentration of the surface region of the semiconductor substrate at the bottom of the first isolation pattern is greater than the average doping concentration of the surface region of the semiconductor substrate at the bottom of the second isolation pattern.

13. The semiconductor structure according to any one of claims 10-12, characterized in that, The stacked structure further includes word lines extending in a vertical direction, wherein the vertical direction is perpendicular to the first horizontal direction and perpendicular to the second horizontal direction, the active pattern passes through the interior of the word lines, and the word lines include a first conductive portion located on a first side of the active pattern in the second horizontal direction and a second conductive portion located on a second side of the active pattern in the second horizontal direction, wherein the size of the first conductive portion in the vertical direction is larger than the size of the second conductive portion in the vertical direction.

14. The semiconductor structure according to any one of claims 10-12, characterized in that, The stacked structure also includes a capacitor located in a second region adjacent to the first region. The capacitor includes a first electrode, a second electrode, and a capacitor dielectric layer located between the first electrode and the second electrode. The first electrode extends horizontally and is coupled to the transistor. The second electrode covers the inner wall of the first electrode, or the second electrode covers both the inner wall and part of the outer wall of the first electrode.

15. The semiconductor structure according to claim 13, characterized in that, The stacked structure also includes a bit line and a contact plug located in a third region, and a protective dielectric layer covering the sidewalls of the contact plug. The third region is adjacent to the first region and located on the side of the first region away from the second region. The bit line is coupled to the transistor, and the portion of the bit line extending to the bottom of the contact plug is coupled to the contact plug.

16. An electronic device, characterized in that, include: processor; as well as A memory, wherein the memory is coupled to the processor, the memory comprising a semiconductor structure according to any one of claims 10-15.

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