Semiconductor structure and method for forming the same

Abstract

The present application provides a semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a front side and a back side, both of which are sequentially stacked with a dielectric layer and a bonding layer; forming an isolation structure on the front side of the substrate, the isolation structure penetrating the bonding layer and the dielectric layer and extending into the substrate, and the isolation structure covering the surface of the bonding layer; forming a buffer layer on the surface of the isolation structure and the surface of the bonding layer on the back side of the substrate; removing the buffer layer, the bonding layer, and the isolation structure above the dielectric layer on the front side of the substrate; forming a gate material layer on the surface of the dielectric layer and the isolation structure on the front side of the substrate and on the surface of the buffer layer on the back side of the substrate; performing subsequent processes in the logic device area using the buffer layer and the gate material layer on the back side of the substrate as protective layers. The technical solution of the present application can protect the bonding layer from damage, ensure the integrity of the bonding layer, and improve the performance and yield of the logic wafer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensors have attracted widespread attention for overcoming the problem of metal wiring blocking and reflecting incident light, a problem present in earlier front-illuminated CMOS image sensors. To further reduce chip size and improve image quality, researchers have improved the back-illuminated structure and designed a three-dimensional stacked back-illuminated CMOS image sensor. This design separates the image area from the circuit area, further improving image quality, reducing noise, and significantly optimizing performance.

[0003] To successfully manufacture a 3D stacked back-illuminated CMOS image sensor, the backside of the logic circuit wafer must undergo specialized processing to ensure optimal bonding between the logic and image regions. Existing backside processing techniques have limitations. For example, growing silicon nitride (SiN) on the backside of a polysilicon (Poly-Si), offset spacer, or spacer wafer increases both time and cost. In the back-end of wafer production, the wafer-carrying device comes into direct contact with the SiN, causing surface defects. Furthermore, the electrostatic chuck (E-chuck) in the back-end tool struggles to hold the wafer, leading to the risk of wafer breakage. Summary of the Invention

[0004] The technical problem solved by the present application is to provide a semiconductor structure and a method for forming the same, so as to solve the defects existing in the prior art.

[0005] To solve the above technical problems, the technical solution of the present application provides a method for forming a semiconductor structure for use in a logic device area of ​​a back-illuminated image sensor, comprising: providing a substrate, the substrate comprising a front side of the substrate and a back side of the substrate, the front side of the substrate and the back side of the substrate being stacked with a dielectric layer and a bonding layer in sequence; forming an isolation structure on the front side of the substrate, the isolation structure penetrating the bonding layer and the dielectric layer and extending into the substrate, and the isolation structure covering the surface of the bonding layer; forming a buffer layer on the surface of the isolation structure and the surface of the bonding layer on the back side of the substrate; removing the buffer layer, the bonding layer and the isolation structure higher than the dielectric layer on the front side of the substrate; forming a gate material layer on the surface of the dielectric layer and the isolation structure on the front side of the substrate and on the surface of the buffer layer on the back side of the substrate; using the buffer layer and the gate material layer on the back side of the substrate as a protective layer, performing subsequent processes in the logic device area.

[0006] In an embodiment of the present application, after performing the subsequent process, the protective layer is removed.

[0007] In an embodiment of the present application, after performing the subsequent process, the protective layer is removed through a cleaning process.

[0008] In an embodiment of the present application, the subsequent process includes at least one of the following processes: etching the gate material layer and the dielectric layer on the front side of the substrate to form a gate structure; forming a source and a drain in the substrate on both sides of the gate structure respectively; forming several metal layers above the gate structure, the source and the drain; forming a top-level through-hole structure on the surface of the top metal layer of the several metal layers; and forming an aluminum pad on the surface of the top-level through-hole structure.

[0009] In an embodiment of the present application, the buffer layer includes a silicon-based oxide layer.

[0010] In an embodiment of the present application, the buffer layer further includes a gate material layer located on the surface of the silicon-based oxide layer.

[0011] In an embodiment of the present application, the gate material layer is made of at least one of polysilicon and metal.

[0012] In an embodiment of the present application, the process of forming an isolation structure on the front side of the substrate includes: etching the bonding layer, dielectric layer and substrate on the front side of the substrate to form grooves in the bonding layer, dielectric layer and substrate; using a HARP process to deposit a dielectric material in the groove, and making the dielectric material cover the surface of the bonding layer to form an isolation structure.

[0013] In an embodiment of the present application, the process of removing the buffer layer, the bonding layer and the isolation structure above the dielectric layer on the front side of the substrate includes: using a grinding process to remove the buffer layer on the front side of the substrate and the isolation structure above the bonding layer; using a wet etching process to remove the bonding layer on the front side of the substrate and the isolation structure above the dielectric layer.

[0014] In an embodiment of the present application, the material of the dielectric layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0015] In an embodiment of the present application, the material of the bonding layer includes at least one of silicon nitride, silicon carbide, aluminum oxide, thorium dioxide, diamond, boron nitride, titanium nitride, boron carbide, and titanium carbide.

[0016] In an embodiment of the present application, the thickness of the bonding layer on the back side of the substrate is not less than 100 angstroms.

[0017] The present application also provides a semiconductor structure for a logic device area of ​​a back-illuminated image sensor, comprising: a substrate, the substrate including a substrate front side and a substrate back side; a dielectric layer located on a portion of the surface of the substrate front side and the surface of the substrate back side; a bonding layer located on the surface of the dielectric layer on the back side of the substrate; a protective layer including a buffer layer located on the surface of the bonding layer and a gate material layer located on the surface of the buffer layer; a gate layer located on the surface of the dielectric layer on the front side of the substrate, the dielectric layer on the front side of the substrate and the gate layer constituting a gate structure.

[0018] In an embodiment of the present application, the buffer layer includes a silicon-based oxide layer.

[0019] In an embodiment of the present application, the buffer layer further includes a gate material layer located on the surface of the silicon-based oxide layer.

[0020] In an embodiment of the present application, the gate material layer is made of at least one of polysilicon and metal.

[0021] The method for forming a semiconductor structure of the technical solution of the present application forms a buffer layer and a gate material layer on the surface of the bonding layer on the back side of the substrate. The buffer layer and the gate material layer serve as protective layers for the bonding layer, which can effectively protect the bonding layer from damage in the subsequent process, thereby ensuring the integrity and uniformity of the bonding layer, significantly improving the yield of the logic wafer, and at the same time, due to the addition of the buffer layer and the gate material layer, the overly, warpage, defect and other performance of the formed logic wafer are improved.

[0022] The method for forming a semiconductor structure of the technical solution of the present application gradually removes the protective layer through the existing cleaning process when removing the buffer layer and the gate material layer. Since the gate material layer with conductive ability exists in the residual protective layer, the E-chuck of the machine can better adsorb the wafer when forming the metal layer, avoiding the risk of fragmentation.

[0023] The method for forming a semiconductor structure of the technical solution of the present application fully utilizes existing process steps without adding other additional process steps, thus saving production time and cost and being suitable for large-scale production. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following figures describe in detail exemplary embodiments disclosed in this application. Identical reference numerals denote similar structures in several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the same inventive intent as described in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0025] Figure 1 Schematic diagram of a process for forming a semiconductor structure according to an embodiment of the present application;

[0026] Figures 2 to 8 Schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present application;

[0027] Figure 9 Graphs showing overlay test results of logic wafers of the embodiment of the present application and the comparative example;

[0028] Figure 10 Graph showing Bow value test results of logic wafers according to the embodiment of the present application and the comparative example;

[0029] Figure 11 Graph showing electrical test results of logic wafers according to the embodiment of the present application and the comparative example. DETAILED DESCRIPTION

[0030] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0031] The method for forming a semiconductor structure of the technical solution of the present application forms a bonding layer on the back side of the substrate, and forms a buffer layer and a gate material layer on the surface of the bonding layer, so that the buffer layer and the gate material layer play a role in protecting the bonding layer from damage in subsequent processes, thereby ensuring the integrity of the bonding layer.

[0032] The technical solution of this application is described in detail below with reference to the embodiments and drawings.

[0033] refer to Figure 1 The method for forming a semiconductor structure according to an embodiment of the present application is used in a logic device region of a back-illuminated image sensor, comprising:

[0034] Step S1: providing a substrate, wherein the substrate comprises a substrate front side and a substrate back side, and a dielectric layer and a bonding layer are sequentially stacked on the substrate front side and the substrate back side;

[0035] Step S2: forming an isolation structure on the front surface of the substrate, wherein the isolation structure penetrates the bonding layer and the dielectric layer and extends into the substrate, and the isolation structure covers the surface of the bonding layer;

[0036] Step S3: forming a buffer layer on the surface of the isolation structure and the surface of the bonding layer on the back side of the substrate;

[0037] Step S4: removing the buffer layer, the bonding layer and the isolation structure higher than the dielectric layer on the front side of the substrate;

[0038] Step S5: forming a gate material layer on the dielectric layer and the isolation structure surface on the front side of the substrate and on the buffer layer surface on the back side of the substrate;

[0039] Step S6: using the buffer layer and gate material layer on the back side of the substrate as protection layers, performing subsequent processes in the logic device area.

[0040] Combine Figure 1 and Figure 2 , providing a substrate 100. The substrate 100 may be made of at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, and may also include a multilayer structure composed of layers of the aforementioned materials, or a silicon-on-insulator (SOI) or stacked silicon-on-insulator (SSOI) structure. In the embodiment of the present application, the semiconductor substrate 100 is made of single crystal silicon or silicon-on-insulator.

[0041] The substrate 100 includes a front surface and a back surface. The back surface serves as the backside of the logic circuit wafer and is bonded to the image wafer. The front surface is the side opposite the back surface and is used to form the device structure of the logic area. In the embodiment of the present application, the top surface of the substrate 100 serves as the front surface, and the bottom surface of the substrate 100 serves as the back surface.

[0042] The front and back sides of the substrate are sequentially stacked with a dielectric layer 110 and a bonding layer 120, and the dielectric layer 110 and the bonding layer 120 can be formed by a furnace tube process. The dielectric layer 110 on the back side of the substrate serves as a retained layer on the back side of the wafer during final shipment, and the dielectric layer 110 on the front side of the substrate can serve as a gate dielectric layer for the gate structure, eliminating the step of separately depositing a gate dielectric layer when forming the gate structure in the subsequent process, thereby saving production time and cost. The material of the dielectric layer 110 may include at least one of silicon oxide, silicon nitride, silicon oxynitride or a high-K material. The high-k material refers to a large dielectric constant. In the field of semiconductor device structure and manufacturing process, high-k refers to a dielectric constant greater than SiO2 (for example, greater than 3.9). For example, the high-k material may be hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide, etc. In some embodiments, the dielectric layer 110 on the front side of the substrate and the dielectric layer 110 on the back side of the substrate may be formed simultaneously and may have the same thickness.

[0043] The material of the bonding layer 120 must be non-conductive and have high hardness. In some embodiments, the material of the bonding layer 120 may include at least one of silicon nitride, silicon carbide, aluminum oxide, thorium dioxide, diamond, boron nitride, titanium nitride, boron carbide, and titanium carbide. The bonding layer 120 on the front side of the substrate will be removed in subsequent processes, while the bonding layer 120 on the back side of the substrate will be retained for bonding with the wafer in the image area. No additional process is required to form the bonding layer 120 on the back side of the substrate in subsequent processes. The bonding layer 120 on the front side of the substrate and the bonding layer 120 on the back side of the substrate can be formed simultaneously and have the same thickness. The thickness of the bonding layer 120 is not less than 100 angstroms.

[0044] refer to Figure 3 , forming an isolation structure 130 on the front side of the substrate. Specifically, the bonding layer 120, the dielectric layer 110, and the substrate 100 on the front side of the substrate are etched to form trenches in the bonding layer 120, the dielectric layer 110, and the substrate 100; a dielectric material is deposited in the trenches using a HARP (High Aspect Ratio Process) process, and the dielectric material covers the surface of the bonding layer to form the isolation structure 130. The formed isolation structure 130 penetrates the bonding layer 120 and the dielectric layer 110 and extends into the substrate 100, and the isolation structure 130 covers the surface of the bonding layer 120. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material, and / or other suitable insulating materials. Low-k refers to a small dielectric constant. In the field of semiconductor device structure and manufacturing process, low-k refers to a dielectric constant less than that of SiO2 (for example, less than 3.9).

[0045] In the embodiment of the present application, the isolation structure 130 can be considered as two parts, one part of which is located within the bonding layer 120, the dielectric layer 110, and the substrate 100, and the remaining part is higher than the bonding layer 120. In some embodiments, after the isolation structure 130 is formed, a CMP (Chemical Mechanical Polishing) process is performed to remove the isolation structure that is higher than the bonding layer 120. In the embodiment of the present application, after the isolation structure 130 is formed, the isolation structure 130 is not polished immediately, but is polished together with other structures in a subsequent process, thereby not adding additional process steps.

[0046] refer to Figure 4A buffer layer 140 is formed on the surface of the isolation structure 130 and on the surface of the bonding layer 120 on the back side of the substrate. The buffer layer 140 includes a silicon-based oxide layer 141. The material of the silicon-based oxide layer 141 includes a silicon-based oxide, such as TEOS (Tetra-ethyl Ortho-silicate). The buffer layer 140 can be a single-layer structure or a stacked-layer structure. In the embodiment of the present application, in addition to the silicon-based oxide layer 141, the buffer layer 140 also includes a gate material layer 142 located on the surface of the silicon-based oxide layer 141. The material of the gate material layer 142 can include at least one of polysilicon and metal. The process for forming the silicon-based oxide layer 141 and the gate material layer 142 can be an atomic deposition process (ALD), a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), or other deposition processes.

[0047] The buffer layer 140 on the surface of the isolation structure 130 will be removed in the subsequent process, while the buffer layer 140 on the surface of the bonding layer 120 on the back side of the substrate plays the role of protecting the buffer layer 140. After each step of the process is completed, the surface of the wafer must be cleaned, and each cleaning will remove part of the buffer layer 140. Due to the protection of the buffer layer 140, the bonding layer 120 will not be corroded by the cleaning solution. After the manufacturing process is completed, the buffer layer 140 is completely removed, exposing the bonding layer 120 for bonding with the wafer in the image area. If there is no buffer layer 140, or the buffer layer 140 is completely removed before entering the back-end process, on the one hand, the device that carries the wafer will damage the bonding layer 120, thereby causing surface defects; on the other hand, because the exposed bonding layer 120 is not conductive, the electrostatic suction seat (E-chuck) of the back-end machine cannot attract the wafer, increasing the risk of fragmentation. Therefore, the formation of the buffer layer 140 can significantly improve product yield and device performance.

[0048] refer to Figure 5 , removing the buffer layer 140, the bonding layer 120, and the isolation structure 130 above the dielectric layer 110 on the front side of the substrate. A grinding process is used to remove the buffer layer 140 on the front side of the substrate and the isolation structure 130 above the bonding layer 120. The grinding process can be a chemical mechanical grinding process or a physical mechanical grinding process. Then, a wet etching process is used to remove the bonding layer 120 on the front side of the substrate and the isolation structure 130 above the dielectric layer 110. The surface of the remaining isolation structure 130 is coplanar with the top surface of the dielectric layer 110. In some embodiments, the etching solvent of the wet etching process includes hot phosphoric acid.

[0049] The embodiment of the present application removes the bonding layer 120 and the buffer layer 140 on the front side of the substrate together through the existing isolation structure grinding process, which can save time and cost compared to adding an additional process to remove the bonding layer 120 and the buffer layer 140.

[0050] refer to Figure 6 , a gate material layer 150 is formed on the surface of the dielectric layer 110 and the isolation structure 130 on the front side of the substrate and on the surface of the buffer layer 140 on the back side of the substrate. The process for forming the gate material layer 150 may be an atomic deposition process (ALD), a chemical vapor deposition process (CVD) or a physical vapor deposition process (PVD), or other deposition processes. The material of the gate material layer 150 may include at least one of polysilicon and metal. The gate material layer 150 on the front side of the substrate is used to form a gate structure, and the gate material layer 150 on the back side of the substrate is used to protect the bonding layer 140 on the back side of the substrate to prevent the bonding layer 140 from being corroded by the cleaning solution.

[0051] The buffer layer 140 and gate material layer 150 on the back side of the substrate serve as protective layers for the bonding layer 140, and subsequent processes are performed in the logic device area. Because the bonding layer 140 surface is covered with a protective layer during subsequent processes, the bonding layer 140 does not directly contact the carrier during the back-end process, preventing damage to the bonding layer 140 from the carrier's support pins and preventing defects. This ensures the integrity of the backside bonding layer when the wafer is shipped.

[0052] The protective layer on the surface of the bonding layer 140 will eventually be removed to expose the bonding layer 140 so as to facilitate bonding with the image area wafer. In an embodiment of the present application, the protective layer is removed after executing the subsequent process. In an embodiment of the present application, the subsequent process includes a back-end process and part of the front-end process. A small amount of protective layer will also be removed in part of the front-end process. This is inevitable in the process operation, but it is not the main measure for removing the protective layer in the embodiment of the present application. The method for removing the protective layer in the embodiment of the present application is mainly to gradually remove the protective layer through the original cleaning process in the back-end process. The cleaning process in the back-end process is mainly concentrated in the backside cleaning process (BSC) when forming each metal layer, the backside cleaning process after forming the top through-hole structure (FTV), and the backside cleaning process when forming the aluminum pad (Al PAD).

[0053] Combine Figure 7 and Figure 8 , Figure 8 yes Figure 7 Cross-sectional view at position AA. In the embodiment of the present application, the subsequent process may include:

[0054] The gate material layer 150 and the dielectric layer 110 on the front side of the substrate are etched to form the gate material layer 150 into a gate layer and the dielectric layer 100 into a gate dielectric layer. The gate layer and the gate dielectric layer constitute a gate structure 160 .

[0055] A spacer material is deposited on the surface of the gate structure 160 and the substrate surfaces on both sides of the gate structure 160 , and the spacer material is etched to leave only the spacer material on the sidewalls of the gate structure 160 to form a spacer.

[0056] After forming the gate structure 160 and the sidewall spacers, a cleaning step is performed. The cleaning solution may slightly damage the protective layer on the back of the substrate, but this does not affect the protective layer's ability to protect the bonding layer in subsequent processes.

[0057] A source 170 and a drain 180 are respectively formed in the substrate 100 on both sides of the gate structure 160 by an ion implantation process.

[0058] Several metal conductive layers are formed above the gate structure 160, the source 170, and the drain 180. Specifically, an interlayer dielectric layer 190 is deposited on the substrate surface on both sides of the sidewall and on the surface of the gate structure 160; the interlayer dielectric layer 190 is ground to a desired height using a grinding process; the interlayer dielectric layer 190 is etched to expose a portion of the surface of the gate structure 160 and the surfaces of the source 170 and the drain 180 to form a contact hole; a conductive material 200 is filled into the contact hole, and the conductive material 200 fills the contact hole and covers the surface of the interlayer dielectric layer 190; the conductive material 200 is ground until the conductive material 200 fills the contact hole and the surface of the conductive material 200 is coplanar with the top surface of the interlayer dielectric layer 190; a first metal layer 210 (M1) is deposited on the surfaces of the interlayer dielectric layer 190 and the conductive material 200, and the first metal layer 210 (M1) is ground to a specific height.

[0059] Figure 7 and Figure 8 Only the first metal layer 210 is shown. A second metal layer M2, a third metal layer M3, ..., and an nth metal layer Mn will be formed on the first metal layer 210. The process for forming each metal layer after the second metal layer M2 is similar. First, an intermetallic dielectric layer is deposited on the surface of the previous metal layer; then, a contact hole is formed in the intermetallic dielectric layer and filled with a conductive material; then, a next metal layer is deposited on the surface of the intermetallic dielectric layer and the conductive material; and the deposited metal layer is planarized.

[0060] Then, an FTV (not shown) is formed on the surface of the top metal layer of the formed plurality of metal layers, followed by a cleaning process, which also removes part of the protective layer; an Al PAD (not shown) is formed on the surface of the FTV, followed by a cleaning process to remove the remaining protective layer to expose the surface of the bonding layer 120.

[0061] It should be understood that in the subsequent processes of the embodiments of the present application, a cleaning process will be performed each time a process step is completed. The cleaning process will remove part of the protective layer until the entire back-end process is completed, and the protective layer is completely removed to expose the bonding layer 120. By controlling the time of each cleaning process, the thickness of the removed protective layer is controlled to ensure that the protective layer is completely removed after the entire back-end process is completed. The cleaning processes for removing the protective layer are all process steps that exist in the original process, so there is no need to add additional removal processes, saving production time and cost. At the same time, since the gate material layer in the protective layer is conductive, when the protective layer is gradually removed through the cleaning process, the residual protective layer can enable the E-chuck of the machine to adsorb the wafer well when the metal layer is formed, avoiding the risk of fragmentation.

[0062] In other embodiments, the subsequent process may include only one or more of the above processes, and the protective layer is removed through a cleaning process after each process step. For example, the steps of forming a gate structure, forming a source and a drain, and forming a plurality of metal layers may be included, while the steps of forming a top-layer via structure and an aluminum liner are omitted. The protective layer is gradually removed through a cleaning process after each of the steps of forming a gate structure, forming a source and a drain, and forming a plurality of metal layers, until the remaining protective layer is completely removed by a cleaning process after the top-layer metal layer.

[0063] refer to Figure 7 and Figure 8 According to the semiconductor formation method of the embodiment of the present application, a semiconductor structure is manufactured for use in the logic device area of ​​a back-illuminated image sensor, including: a substrate 100, wherein the substrate 100 includes a substrate front side and a substrate back side; a dielectric layer 110, located on a portion of the surface of the substrate front side and the surface of the substrate back side; a bonding layer 120, located on the surface of the dielectric layer 110 on the back side of the substrate; a protective layer, including a buffer layer 140 located on the surface of the bonding layer 120 and a gate material layer 150 located on the surface of the buffer layer 140; a gate layer, located on the surface of the dielectric layer 110 on the front side of the substrate, wherein the dielectric layer 110 on the front side of the substrate and the gate layer constitute a gate structure 160.

[0064] In some embodiments, the semiconductor structure further includes: an isolation structure 130, located in the substrate 100 and the dielectric layer 110 on the front side of the substrate; a source 170 and a drain 180, respectively located in the substrate 100 on both sides of the gate structure 160; and several layers of metal layers (only the first metal layer 210 is shown in the figure), located above the gate structure 160, the source 170 and the drain 160.

[0065] In some embodiments, the material of the dielectric layer 110 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0066] In some embodiments, the material of the bonding layer 120 includes at least one of silicon nitride, silicon carbide, aluminum oxide, thorium dioxide, diamond, boron nitride, titanium nitride, boron carbide, and titanium carbide. The thickness of the bonding layer is not less than 100 angstroms.

[0067] In some embodiments, the buffer layer 140 includes a silicon-based oxide layer 141 .

[0068] In some embodiments, the buffer layer 140 further includes a gate material layer 142 located on the surface of the silicon-based oxide layer 141. The gate material layer 142 is made of at least one of polysilicon and metal.

[0069] In some embodiments, the isolation structure 130 is a shallow trench isolation structure with a high aspect ratio.

[0070] The following tests were conducted on a semiconductor structure fabricated according to an embodiment of the present application (hereinafter referred to as the “embodiment logic wafer”) and a semiconductor structure fabricated according to prior art (hereinafter referred to as the “comparative example logic wafer”):

[0071] Through SEM cross-section and Inline CD test, it can be seen that the thickness of the backside of the logic wafer of the embodiment at the wafer edge 3mm and 5mm position is and , its thickness is sufficient to meet the conditions for bonding with the image area wafer. Generally, it is usually greater than Just about.

[0072] refer to Figure 9, where Figures a and c are the overlay test results of the gate structure (poly) and contact hole (CT) of the comparative example logic wafer, respectively, and Figures b and d are the overlay test results of the poly and CT of the embodiment logic wafer. According to the overlay test results, the overlay accuracy values ​​tested by the embodiment logic wafer are all smaller than those of the comparative example logic wafer, and the Spec range of the embodiment logic wafer is also tighter than that of the comparative example logic wafer. Therefore, the overlay performance of the embodiment logic wafer is better than that of the comparative example logic wafer. This is because the embodiment logic wafer adds a protective layer (buffer layer and gate material layer) on the surface of the bonding layer, which reduces the hardness of the back of the logic wafer. Therefore, the embodiment logic wafer is easier to align during overlay and has higher accuracy.

[0073] refer to Figure 10 , are the Bow value test results of the embodiment logic wafer and the comparative example logic wafer after forming the second metal layer (M2), wherein Figure a and Figure b are the Bow values ​​of the comparative example logic wafer in the X direction and the Y direction, respectively, and Figure c and Figure d are the Bow values ​​of the embodiment logic wafer in the X direction and the Y direction, respectively. It can be seen that the Bow values ​​of the embodiment logic wafer in the X direction and the Y direction are both near the target value (Target), indicating that the Warpage performance of the embodiment logic wafer meets the requirements. At the same time, the absolute values ​​of the Bow values ​​in the X direction and the Y direction of the embodiment logic wafer are much smaller than those of the comparative example logic wafer, which indicates that after adding the protective layer, the overall bending degree of the logic wafer is reduced, and the risk of splitting the logic wafer is also reduced, so the Warpage performance of the embodiment logic wafer is better.

[0074] refer to Figure 11 , are the electrical test results of the embodiment logic wafer with a bonding layer (marked 2 in the figure) and the comparative example logic wafer without a bonding layer (marked 1 in the figure). As can be seen from Figures a to d, the N / PMOS electrical parameters (VT I / I dsat ) and the electrical parameters (VT I / I dsat ) are basically consistent. The protective layer added to the logic wafer of the embodiment has no effect on the electrical properties of the original logic wafer. Therefore, the electrical performance of the logic wafer of the embodiment is very stable.

[0075] To sum up, the method for forming a semiconductor structure in the embodiment of the present application forms a buffer layer and a gate material layer on the surface of the bonding layer on the back side of the substrate. The buffer layer and the gate material layer serve as protective layers for the bonding layer, which can effectively protect the bonding layer from damage in the subsequent process, thereby ensuring the integrity and uniformity of the bonding layer, significantly improving the yield of the logic wafer, and at the same time, due to the addition of the buffer layer and the gate material layer, the Overlay, Warpage, Defect and other performances of the formed logic wafer are improved.

[0076] After reading this application, those skilled in the art will appreciate that the foregoing application is presented by way of example only and is not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0077] It should be understood that the term "and / or" used in this embodiment includes any and all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present.

[0078] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" indicates the absence of intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0079] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0080] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure for a logic device region of a back-illuminated image sensor, characterized in that: include: Providing a substrate, the substrate comprising a substrate front side and a substrate back side, wherein a dielectric layer and a bonding layer are sequentially stacked on the substrate front side and the substrate back side; forming an isolation structure on the front surface of the substrate, wherein the isolation structure penetrates the bonding layer and the dielectric layer and extends into the substrate, and the isolation structure covers the surface of the bonding layer; forming a buffer layer on the surface of the isolation structure and the surface of the lamination layer on the back side of the substrate; removing the buffer layer, the bonding layer and the isolation structure higher than the dielectric layer on the front side of the substrate; forming a gate material layer on the surface of the dielectric layer and the isolation structure on the front side of the substrate and on the surface of the buffer layer on the back side of the substrate; The buffer layer and gate material layer on the back side of the substrate are used as protective layers, and subsequent processes are performed in the logic device area.

2. The method for forming a semiconductor structure according to claim 1, wherein: After performing the subsequent process, the protection layer is removed.

3. The method for forming a semiconductor structure according to claim 2, wherein: After the subsequent processes are performed, the protection layer is removed through a cleaning process.

4. The method for forming a semiconductor structure according to claim 2, wherein: The subsequent process includes at least one of the following processes: Etching the gate material layer and the dielectric layer on the front side of the substrate to form a gate structure; forming a source electrode and a drain electrode in the substrate on both sides of the gate structure respectively; forming a plurality of metal layers above the gate structure, the source electrode, and the drain electrode; forming a top-level through-hole structure on a surface of a top-level metal layer of the plurality of metal layers; An aluminum liner is formed on the surface of the top through-hole structure.

5. The method for forming a semiconductor structure according to claim 1, wherein: The buffer layer includes a silicon-based oxide layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: The buffer layer further includes a gate material layer located on the surface of the silicon-based oxide layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The gate material layer is made of at least one of polysilicon and metal.

8. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming an isolation structure on the front side of the substrate includes: Etching the bonding layer, the dielectric layer and the substrate on the front side of the substrate to form grooves in the bonding layer, the dielectric layer and the substrate; A dielectric material is deposited in the groove using a HARP process, and the dielectric material covers the surface of the adhesion layer to form an isolation structure.

9. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the buffer layer, the bonding layer and the isolation structure above the dielectric layer on the front side of the substrate includes: removing the buffer layer on the front side of the substrate and the isolation structure higher than the bonding layer by a grinding process; A wet etching process is used to remove the adhesion layer on the front side of the substrate and the isolation structure higher than the dielectric layer.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the dielectric layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the bonding layer includes at least one of silicon nitride, silicon carbide, aluminum oxide, thorium dioxide, diamond, boron nitride, titanium nitride, boron carbide, and titanium carbide.

12. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the bonding layer on the back side of the substrate is not less than 100 angstroms.

13. A semiconductor structure used in a logic device region of a back-illuminated image sensor, characterized in that: Formed by any one of the methods of claims 1 to 12, comprising: A substrate, the substrate comprising a substrate front side and a substrate back side; a dielectric layer, located on a portion of the front surface of the substrate and the back surface of the substrate; a bonding layer, located on the surface of the dielectric layer on the back side of the substrate; a protective layer, comprising a buffer layer located on a surface of the conforming layer and a gate material layer located on a surface of the buffer layer; The gate layer is located on the surface of the dielectric layer on the front side of the substrate. The dielectric layer on the front side of the substrate and the gate layer constitute a gate structure.

14. The semiconductor structure according to claim 13, wherein: The buffer layer includes a silicon-based oxide layer.

15. The semiconductor structure according to claim 14, wherein: The buffer layer further includes a gate material layer located on the surface of the silicon-based oxide layer.

16. The semiconductor structure according to claim 15, wherein: The gate material layer is made of at least one of polysilicon and metal.

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