Display device

Abstract

The present invention discloses a display device having a display area and a non-display area, wherein the display area has adjacent straight edges and curved edges. The display device includes: a substrate; an encapsulation portion disposed in the non-display area surrounding the display area; a signal line layer, wherein the signal line layer includes a first signal line and a second signal line insulated from each other; the first signal line includes a firstA signal line segment disposed between the display area and the encapsulation portion; the second signal line includes a secondA signal line segment disposed between the display area and the encapsulation portion; the firstA signal line segment has a first end adjacent to the secondA signal line segment, the secondA signal line segment has a second end adjacent to the firstA signal line segment, and the minimum distances from the first end and the second end to the curved edge are both less than or equal to a preset distance. By utilizing as little space as possible, the resistance of the first signal line is more efficiently reduced, its voltage drop is improved, the problem of uneven brightness in the display device is avoided, and the display effect of the display device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of display technology, and in particular relates to a display device. Background Art

[0002] With the continuous development of display technology, the application of display devices is becoming more and more extensive. OLED (Organic Light Emitting Diode) display devices have become a rising star in the display panel industry due to their advantages such as fast response speed, brilliant colors, light weight and convenience.

[0003] In the prior art, positive / negative voltage signal lines are usually arranged at the lower step of the OLED display device. Due to the limitations of the existing structural form, the routing space of the positive / negative voltage signal lines is limited, which affects the display effect of the display panel.

[0004] Therefore, a new display device is urgently needed. Summary of the Invention

[0005] An embodiment of the present invention provides a display device, which utilizes as little space as possible to more efficiently reduce the resistance of the first signal line, improve its voltage drop, avoid the problem of uneven brightness in the display device, and enhance the display effect of the display device by setting the minimum distance from the first end of the first signal line segment to the curved edge portion to be less than or equal to a preset distance, and setting the minimum distance from the second end of the second signal line segment to the curved edge portion to be less than or equal to a preset distance.

[0006] In a first aspect, an embodiment of the present invention provides a display device having a display area and a non-display area, wherein the non-display area surrounds the display area, and the display area has adjacent straight sides and curved sides, comprising: a substrate; a packaging portion, arranged in the non-display area around the display area; a signal line layer, the signal line layer comprising a first signal line and a second signal line insulated from each other; the first signal line comprises a firstA signal line segment arranged between the display area and the packaging portion, and the second signal line comprises a secondA signal line segment between the display area and the packaging portion; the firstA signal line segment has a first end adjacent to the secondA signal line segment, and the secondA signal line segment has a second end adjacent to the firstA signal line segment, and the minimum distances from the first end and the second end to the curved side are both less than or equal to a preset distance.

[0007] Compared to related art, the display device provided by an embodiment of the present invention includes a substrate, an encapsulation portion, and a signal line layer. The signal line layer includes a first signal line and a second signal line that are insulated from each other. The first signal line includes a firstA signal line segment disposed between the display area and the encapsulation portion, and the second signal line includes a secondA signal line segment disposed between the display area and the encapsulation portion. By setting the minimum distance from the first end of the firstA signal line segment to the curved edge portion to be less than or equal to a preset distance, and the minimum distance from the second end of the secondA signal line segment to the curved edge portion to be less than or equal to a preset distance, the firstA signal line segment terminates near the curved edge portion, and the secondA signal line segment begins near the curved edge portion. The present application sets the minimum distance from the first end of the firstA signal line segment to the curved edge portion to be less than or equal to a preset distance, and the minimum distance from the second end of the secondA signal line segment to the curved edge portion to be less than or equal to a preset distance, so that the firstA signal line segment terminates near the curved edge portion, and the secondA signal line segment begins near the curved edge portion. This minimizes space, more efficiently reduces the resistance of the first signal line, improves its voltage drop, avoids uneven brightness in the display device, and enhances the display effect of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0009] Figure 1 is a schematic structural diagram of a display device in the related art;

[0010] Figure 2 is a schematic diagram of a detection screen of a display device in a dimming mode in the related art;

[0011] Figure 3 This is a real picture of the detection screen of the display device in the dimming mode in the related art;

[0012] Figure 4 is a timing diagram of a display device in a dimming mode in the related art;

[0013] Figure 5 is a schematic diagram of an input screen of a display device in a dimming mode in the related art;

[0014] Figure 6 is a schematic structural diagram of a display device provided according to an embodiment of the present invention;

[0015] Figure 7 is a driving schematic diagram of a driving transistor in the related art;

[0016] Figure 8 is a schematic diagram of the current-voltage relationship in the related art;

[0017] Figure 9 An embodiment provides Figure 6 A partial enlarged view of point C in the middle;

[0018] Figure 10 Another embodiment provides Figure 6 A partial enlarged view of point C in the middle;

[0019] Figure 11 Yet another embodiment provides Figure 6 A partial enlarged view of point C in the middle;

[0020] Figure 12 Yet another embodiment provides Figure 6 A partial enlarged view of point C in the middle;

[0021] Figure 13 An embodiment provides Figure 12 A partial enlarged view of point G in the middle;

[0022] Figure 14 An embodiment provides Figure 12 The film structure diagram at EE in the middle;

[0023] Figure 15 Yet another embodiment provides Figure 5 A partial enlarged view of point C in the middle;

[0024] Figure 16 An embodiment provides Figure 15 A partial enlarged view of the H in the middle;

[0025] Figure 17 An embodiment provides Figure 15 Film structure diagram at the middle FF;

[0026] Figure 18 An embodiment provides Figure 11 A partial enlarged view of point D in the middle. DETAILED DESCRIPTION

[0027] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed in order to provide a comprehensive understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.

[0028] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0029] In the related art, positive / negative voltage signal lines are usually set at the lower step of the OLED display device and electrically connected to the control chip 5 respectively. Since the packaging part 3 is provided in the non-display area NA of the display device, the positive voltage signal line 20 and the negative voltage signal line 10 in the related art are arranged side by side inside the packaging part 3 to achieve a narrow frame. Figure 1 Optionally, the display device includes a pixel circuit, the positive voltage signal line 20 and the negative voltage signal line 10 are respectively a PVDD signal line and a PVEE signal line, which can provide driving signals for the pixel driving circuit, the PVDD signal line provides a positive driving voltage signal for the pixel driving circuit, and the PVEE signal line provides a negative driving voltage signal for the pixel driving circuit.

[0030] However, the inventors have discovered that due to the relative position of the positive voltage signal line 20 and the negative voltage signal line 10, there is insufficient routing space for the positive voltage signal line 20 or the negative voltage signal line 10, resulting in a large IR drop in the voltage signal transmitted by the positive voltage signal line 20 or the negative voltage signal line 10. This can cause mura in dimming mode. Figure 2 and Figure 3 As shown, Figure 2 is a schematic diagram of a detection screen of a display device in a dimming mode in the related art; Figure 3 This is a real picture of the detection screen of the display device in the dimming mode in the related art.

[0031] Figure 2 and Figure 3There is significant brightness unevenness between low grayscale 1 and low grayscale 2. Due to insufficient routing space for the positive voltage signal line 20 and the negative voltage signal line 10 inside the packaging portion 3, the width of the positive voltage signal line 20 is narrowed. In particular, where the positive voltage signal line 20 and the negative voltage signal line 10 are arranged side by side, the width of the positive voltage signal line 20 is directly narrowed by more than 3-4 times, greatly increasing the impedance of the positive voltage signal line 20. Because the impedance of the positive voltage signal line 20 increases, the difference in voltage drop of the positive voltage signal line 20 in the bright part of the detection image between the luminous stage and the non-luminous stage is amplified.

[0032] like Figure 4 and Figure 5 As shown, Figure 4 is a timing diagram of a display device in a dimming mode in the related art. Figure 5 Schematic diagram of an input screen of a display device in a dimming mode in the related art. Figure 5 The middle part is divided into a highlight part and a low grayscale part. The low grayscale part is optional and has 48 grayscales.

[0033] Figure 4 In the example, EMIT1 to EMIT9 represent the light control signal. When EMIT is black, it indicates that the system is in a non-light state, and when EMIT is white, it indicates that the system is in a light state. Figure 5 The luminous state of the low grayscale part of the display device, EMIT10 to EMIT12 characterizes Figure 5 The luminous state of the highlight portion of the display device, Figure 4 At time T1, EMIT10 to EMIT12 are turned on, and the highlighted portion is in a light-emitting state. At this time, the current of the PVDD signal line is very large. The voltage drop depends on the product of current and resistance. Due to the narrow frame design, the resistance of the PVDD signal line is also very large. Therefore, the voltage drop of the PVDD signal line is very large at this time. The voltage drop of the PVDD signal line far from the control chip 5 is severe, and the corresponding bright area will become darker. At time T2, the highlighted portion is in a non-light-emitting state, the current of the PVDD signal line is very small, and the voltage drop also becomes smaller. The voltage drop of the PVDD signal line far from the control chip 5 is relatively small. Therefore, although the signal input to the low grayscale portion is the same grayscale, the actual display will have different brightness due to the different voltage drops of the PVDD signal line. Therefore, the display device will have uneven brightness in dimming mode.

[0034] To solve the above problems, an embodiment of the present application provides a display device, which will be described in detail below with reference to the accompanying drawings.

[0035] See also Figure 6 , Figure 6: It is a structural schematic diagram of a display device provided according to an embodiment of the present invention; the embodiment of the present invention provides a display device, having a display area AA and a non-display area NA, the non-display area NA surrounds the display area AA, the display area AA has adjacent straight edge portions A1 and curved edge portions A2, the display device includes: a substrate 1; a packaging portion 3, arranged in the non-display area NA around the display area AA; a signal line layer 4, the signal line layer 4 includes a first signal line 41 and a second signal line 42 insulated from each other; the first signal line 41 includes a first-A signal line segment 41a arranged between the display area AA and the packaging portion 3, and the second signal line 42 includes a second-A signal line segment 42a between the display area AA and the packaging portion 3; the first-A signal line segment 41a has a first end N1 adjacent to the second-A signal line segment 42a, the second-A signal line segment 42a has a second end N2 adjacent to the first-A signal line segment 41a, and the minimum distances from the first end N1 and the second end N2 to the curved edge portion A2 are both less than or equal to the preset distance.

[0036] A display device provided by an embodiment of the present invention includes a substrate 1, an encapsulation portion 3, and a signal line layer 4. The signal line layer 4 includes a first signal line 41 and a second signal line 42, which are insulated from each other. The first signal line 41 includes a first-A signal line segment 41a disposed between the display area AA and the encapsulation portion 3, and the second signal line 42 includes a second-A signal line segment 42a disposed between the display area AA and the encapsulation portion 3. By setting the minimum distance a from the first end N1 of the first-A signal line segment 41a to the curved edge portion A2 to be less than or equal to a predetermined distance, and setting the minimum distance b from the second end N2 of the second-A signal line segment 42a to the curved edge portion A2 to be less than or equal to a predetermined distance, the first-A signal line segment 41a terminates near the curved edge portion A2, and the second-A signal line segment 42a begins near the curved edge portion A2.

[0037] Compared with the related art, the inventors have found through research and evaluation that in the bright part of the dimming mode, the PVDD signal line has a much greater impact on the picture than the PVEE signal line. Figure 7 and Figure 8 , Figure 7 is a driving schematic diagram of a driving transistor in the related art; Figure 8This is a diagram of the current-voltage relationship in the related art. The OLED panel is current-driven. When the corresponding grayscale voltage is input to the N1 node, the driving transistor DTFT is in the saturation region, and the luminous current depends on the voltage of the source and gate of the driving transistor DTFT. The voltage Vd at the drain of the driving transistor DTFT can remain stable within a certain range, as long as the voltage across Vd and the PVEE signal line is satisfied so that the OLED current is equal to the driving current. Therefore, when a highlighted part of the image appears in the dimming mode, excessive resistance of the PVEE signal line will also cause a large voltage drop difference. However, since Vd can fluctuate within a certain range, the signal fluctuation of the PVEE signal line is unlikely to affect the actual brightness (unless the fluctuation range is too large, causing the driving transistor DTFT to fall from the saturation region to the linear region). Moreover, the PVEE signal line covers the entire panel, so the above adverse phenomena are unlikely to occur. Furthermore, the inventors found that the overall current flow direction of the PVDD signal line is from the control chip 5 to the display area AA. Therefore, in the current path, the PVDD signal line extending in the direction of the panel display area AA is particularly important. In the present application, the minimum distance a from the first end N1 of the first A signal line segment 41a to the curved edge portion A2 is set to be less than or equal to a preset distance, and the minimum distance b from the second end N2 of the second A signal line segment 42a to the curved edge portion A2 is set to be less than or equal to a preset distance, so that the first A signal line segment 41a is terminated near the curved edge portion A2, and the second A signal line segment 42a starts near the curved edge portion A2, utilizing as little space as possible, more efficiently reducing the resistance of the first signal line 41, i.e., the PVDD signal line, improving its voltage drop, and avoiding the problem of uneven brightness in the display device.

[0038] On the other hand, during layout design, the spatial design of the curved edge A2 area differs from that of the left, right, and bottom borders. This curved edge requires both the VSR (clock signal line) and the data fanout (data signal fanout line). Therefore, the space in curved edge A2 is the most crowded, and the design is relatively complex. Designing the spacing between the PVDD and PVEE signal lines (i.e., the first and second signal lines 41, 42) near the last row in curved edge A2 avoids increasing design complexity.

[0039] Furthermore, the present application can also optimize the impedance of the second signal line 42. On the one hand, the routing of the second signal line 42 outside the package portion 3 is not restricted by space, and the width can be selected within the range of tens to hundreds of microns based on performance requirements. In the related art, the space of the second signal line 42 is limited, with the narrowest width being only 60 μm.

[0040] On the other hand, the portion of the second signal line 42 between the display area AA and the packaging portion 3 not only retains the design of the electrical transmission from the second signal line 42 to the display area AA, namely the second signal line segment A 42a, but also increases the electrical transmission area of ​​the second signal line segment A 42a of the second signal line 42 at the curved edge portion A2 compared to the related art. Because the portion of the first signal line 41 that is arranged side by side with the second signal line 42 in the related art is eliminated, the impedance of the second signal line 42 is reduced. While ensuring the improvement of the voltage drop of the first signal line 41, the present application also optimizes the electrical performance of the second signal line 42, thereby improving the display effect of the display device.

[0041] At the same time, since the first A signal line segment 41a and the second A signal line segment 42a are arranged relative to each other, and the minimum distances from the first end N1 and the second end N2 to the curved edge portion A2 are less than or equal to the preset distance, the first A signal line segment 41a and the second A signal line segment 42a are prevented from being arranged side by side on the inner side of the packaging portion 3, thereby ensuring that the first A signal line segment 41a and the second A signal line segment 42a have sufficient routing space, thereby improving the display effect of the display device.

[0042] Optionally, the display device further includes a device layer 2, which is disposed on one side of the substrate 1 and covers the display area AA. The device layer 2 specifically includes a pixel circuit (not shown in the figure), which includes multiple thin-film transistors, each of which includes a semiconductor layer, a gate layer, a source / drain layer, a capacitor layer, and other metal layers. Optionally, the first signal line 41, the second signal line 42, and the source / drain layer are disposed in the same layer. The first signal line 41, the second signal line 42, and the source / drain layer can be formed using the same process to save costs, or they can be formed separately to improve product yield.

[0043] To achieve encapsulation of the display device, the encapsulation portion 3 may include glass frit. Specifically, a fusion encapsulation process may be employed. This involves using a laser to heat the glass frit, causing it to melt and bond the substrate 1 to the display device's cover plate (not shown). This prevents the intrusion of moisture and oxygen from the outside, ensuring stable display performance.

[0044] The minimum distances between the first end N1 and the second end N2 and the curved edge A2 are both less than or equal to a preset distance. Optionally, the preset distance is 20 μm to 30 μm. The preset distance should not be too small. Considering process errors and other factors, if the preset distance is too small, etching residues may cause a short circuit between the first signal line 41 and the second signal line 42. If the preset distance is too large, in addition to affecting the space, it may also affect the load difference of the fan-out line 7. Optionally, the preset distance is 20 μm.

[0045] See also Figure 6 and Figure 9 , Figure 9 An embodiment provides Figure 6 A partial enlarged view of point C in the middle; in some optional embodiments, the first signal line 41 also includes a first B signal line segment 41b connected to the first A signal line segment 41a, the first B signal line segment 41b is at least partially located on the side of the packaging portion 3 away from the display area AA, the first A signal line segment 41a extends along the first direction X, the first B signal line segment 41b extends along the second direction Y, and the first direction X and the second direction Y intersect.

[0046] In this embodiment, the first B signal line segment 41b is at least partially located on the side of the packaging portion 3 away from the display area AA, so as to facilitate connection with the control chip 5 located on the side of the packaging portion 3 away from the display area AA, and the first A signal line segment 41a extends along the first direction X, and the first B signal line segment 41b extends along the second direction Y. Optionally, the first direction X and the second direction Y are perpendicular to each other, so as to reduce the overlapping area between the first B signal line segment 41b and the packaging portion 3 when the first B signal line segment 41b crosses the packaging portion 3, avoid signal interference, and improve display uniformity.

[0047] Please continue reading Figure 9 In some optional embodiments, the second signal line 42 further includes a second B signal line segment 42b and a second C signal line segment 42c connected to each other, the second B signal line segment 42b is connected to the second A signal line segment 42a, and the second B signal line segment 42b at least partially extends to the side of the packaging portion 3 away from the display area AA, and the second C signal line segment 42c is arranged on the side of the packaging portion 3 away from the display area AA; the minimum distance c from the second C signal line segment 42c to the packaging portion 3 is greater than or equal to 30 μm.

[0048] It should be noted that second B signal line segment 42b is connected to second A signal line segment 42a, and second B signal line segment 42b extends at least partially through the packaging portion 3 to the side of the packaging portion 3 away from the display area AA. Because second C signal line segment 42c is located on the side of the packaging portion 3 away from the display area AA, and to prevent overlap between the second C signal line segment 42c and the packaging portion 3 after lamination due to process errors and other factors, the minimum distance c from the second C signal line segment 42c to the packaging portion 3 is greater than or equal to 30 μm.

[0049] Since the space between the curved side portion A2 of the display area AA and the packaging portion 3 is more ample than the space between the straight side portion A1 of the display area AA and the packaging portion 3, compared with the related art, the embodiment of the present invention transfers part of the second signal line 42 provided between the packaging portion 3 and the display area AA to the side of the packaging portion 3 away from the display area AA, that is, the second C signal line segment 42c. Since in the related art, the second signal line 42 between the curved side portion A2 and the packaging portion 3 extends along the first direction X for a long time, the second signal line 42 and the first signal line 41 need to pass through the second signal line 42. The side-by-side arrangement is achieved by compressing the routing width. In an embodiment of the present invention, the portion of the second signal line 42 located between the curved portion A2 and the packaging portion 3 and extending along the first direction X is transferred to the side of the packaging portion 3 away from the display area AA, so as to reduce the routing length of the second signal line 42 located between the curved portion A2 and the packaging portion 3, that is, to reduce the second A signal line segment 42a. This part of the length is compensated by the second C signal line segment 42c. The width of the second C signal line segment 42c is not limited and can be selected in the range of tens to hundreds of microns according to performance requirements.

[0050] At the same time, since the length of the second A signal line segment 42a is reduced, the second A signal line segment 42a is terminated near the curved edge portion A2. Therefore, the length of the first A signal line segment 41a of the first signal line 41 can be correspondingly increased, starting from near the curved edge portion A2, and the first A signal line segment 41a and the second A signal line segment 42a will not interfere with each other, which can increase the width of the first A signal line segment 41a, thereby reducing the impedance of the first signal line 41 and improving the voltage drop of the first signal line 41, thereby improving the problem of uneven brightness of the display device in the Dimming mode.

[0051] The present application utilizes the space outside the packaging part 3 to set the second signal line 42, and sets the part with little impact on the display to the periphery of the packaging part 3, which reduces the risk, improves reliability, and has a larger space to maintain the resistance of the second signal line 42 not much different from the existing design, and reduces the impact on the COP bending zone design.

[0052] Optionally, the extension directions of the second B signal line segment 42b and the second C signal line segment 42c are perpendicular to each other, so as to reduce the overlapping area between the second B signal line segment 42b and the packaging part 3 when the second B signal line segment 42b crosses the packaging part 3, avoid signal interference, and improve display uniformity.

[0053] See also Figure 10 , Figure 10 Another embodiment provides Figure 6A partial enlarged view of point C in the middle; considering that sharp angles between the secondA signal line segment 42a, the secondB signal line segment 42b, and the secondC signal line segment 42c can easily cause ESD (electrostatic discharge) issues, in some optional embodiments, the secondA signal line segment 42a, the secondB signal line segment 42b, and the secondC signal line segment 42c are connected by chamfers. Specifically, a circular chamfer can be used to further improve the smoothness of the transition between the secondA signal line segment 42a, the secondB signal line segment 42b, and the secondC signal line segment 42c, thereby avoiding ESD issues or damage to the chamfered portions.

[0054] Considering that the distance between the first signal line 41 and the second signal line 42 should not be too close, it may cause the signals to interfere with each other and affect the display effect. Figure 9 As shown, optionally, the minimum distance d between the first terminal N1 and the second terminal N2 is greater than or equal to 10 μm. By limiting the minimum distance d between the first terminal N1 and the second terminal N2, the problem of signal interference or short circuit caused by the first terminal N1 and the second terminal N2 being too close can be avoided.

[0055] Since the space on the side of the packaging portion 3 away from the display area AA is more abundant than the space between the packaging portion 3 and the display area AA, in some optional embodiments, the width ratio of the second A signal line segment 42a to the second C signal line segment 42c is 1:1 to 1:1.5.

[0056] In this embodiment, the width of the second C signal line segment 42c, located on the side of the packaging portion 3 away from the display area AA, can be greater than the width of the second A signal line segment 42a. For example, the width ratio of the second A signal line segment 42a to the second C signal line segment 42c is 1:1.5, effectively reducing the voltage drop of the voltage signal transmitted by the second C signal line segment 42c. Furthermore, considering the impedance uniformity of the second A signal line segment 42a and the second C signal line segment 42c of the second signal line 42, the width of the second C signal line segment 42c can also be set to be equal to the width of the second A signal line segment 42a. Specifically, the line widths of the second A signal line segment 42a, the second B signal line segment 42b, and the second C signal line segment 42c of the second signal line 42 are all equal, thereby improving the uniformity of signal transmission.

[0057] See also Figure 6 、 Figure 9 and Figure 10 In order to achieve signal sending and transmission, in some optional embodiments, the display device further includes a control chip 5 provided on a side of the packaging portion 3 away from the display area AA, and the first signal line 41 and the second signal line 42 are electrically connected to the control chip 5 respectively.

[0058] The control chip 5 is used to send voltage signals, such as positive voltage signals or negative voltage signals, to the first signal line 41 and the second signal line 42 respectively. Figure 6 、 Figure 9 and Figure 10 As shown, for ease of connection, the first signal line 41 , the second signal line 42 and the control chip 5 are arranged on the same side of the display area AA to avoid excessive wiring distances that affect signal transmission effects.

[0059] See also Figure 11 , Figure 7 Yet another embodiment provides Figure 6 A local enlarged view of point C in the middle; in some optional embodiments, the display device also includes a clock signal line 6 electrically connected to the control chip 5, the clock signal line 6 includes a first clock signal connection segment 61 close to the control chip 5, and the first clock signal connection segment 61 is at least partially arranged between the first B signal line segment 41b and the second B signal line segment 42b.

[0060] The first clock signal connection segment 61 can specifically be a signal segment of the clock signal line 6 located between the control chip 5 and the packaging part 3. By arranging the first clock signal connection segment 61 at least partially between the first B signal segment 41b and the second B signal segment 42b, the first clock signal connection segment 61 can be avoided from crossing the first B signal segment 41b and extending to the display area AA, thereby effectively reducing the overlapping area of ​​the first clock signal connection segment 61 and the first B signal segment 41b along the thickness direction of the display device, thereby reducing the overlapping capacitance between the two, and reducing the instability of the signal on the first clock signal connection segment 61 and / or the first B signal segment 41b due to signal coupling, thereby improving display uniformity.

[0061] In addition to the above embodiments, the first clock signal connection section 61 can also be located at other locations, such as Figure 9 and Figure 10 As shown, the first clock signal connection segment 61 is at least partially arranged on the side of the first B signal line segment 41b away from the second B signal line segment 42b, so as to avoid the portion of the first clock signal connection segment 61 extending along the second direction Y being too close to the first B signal line segment 41b or the second B signal line segment 42b, thereby reducing the signal coupling between the two and avoiding the degree of mutual influence between the signals therebetween.

[0062] In order to save space, the clock signal line 6 and the second B signal line segment 42 b at least partially overlap in a direction perpendicular to the plane of the substrate 1 .

[0063] It should be noted that the packaging portion 3 includes glass frit, which is heated and melted using a laser. An additional metal pad is typically placed between the substrate 1 and the glass frit. This pad reflects laser energy, ensuring that it reaches the glass frit more effectively, thereby achieving a good adhesion and sealing effect. The metal pad also provides support for the second B signal line segment 42b.

[0064] In this embodiment, since the clock signal line 6 is usually also made of metal, the clock signal line 6 can act as a cushion metal in the overlapping part of the clock signal line 6 and the second B signal line segment 42b, and there is no need to set up an additional cushion metal to support the glass material and the second B signal line segment 42b, which effectively reduces costs and improves space utilization.

[0065] See also Figures 12 to 17 , Figure 12 Yet another embodiment provides Figure 6 A partial enlarged view of point C in the middle; Figure 13 An embodiment provides Figure 12 A partial enlarged view of point G in the middle; Figure 14 An embodiment provides Figure 12 The film structure diagram at EE in the middle; Figure 15 Yet another embodiment provides Figure 5 A partial enlarged view of point C in the middle; Figure 16 An embodiment provides Figure 15 A partial enlarged view of the H in the middle; Figure 17 An embodiment provides Figure 15 In order to clearly illustrate the positional relationship between the fan-out line 7 and the second signal line 42, Figure 12 and Figure 15 The first signal line 41 is hidden in the figure.

[0066] In some optional embodiments, the second B signal line segment 42b is connected to the second end N2 of the second A signal line segment 42a. Figure 12 or, the second B signal line segment 42b is connected to the second A signal line segment 42a and the other end opposite to the second end N2, as shown Figure 15 shown.

[0067] It should be noted that the display device further includes a fan-out line 7 electrically connected to the control chip 5. Since the second end N2 of the second A signal line segment 42a is closer to the control chip 5 than the other end of the second A signal line segment 42a, when the second B signal line segment 42b is connected to the second end N2 of the second A signal line segment 42a, the routing length is shortened, thereby reducing voltage drop. Furthermore, there is a minimum distance restriction between the cutting edge Q and the second signal line 42. The second B signal line segment 42b is connected to the other end of the second A signal line segment 42a opposite the second end N2. That is, placing the second B signal line segment 42b on the left side may interfere with cutting at a curved corner of the display device. However, placing the second B signal line segment 42b on the right side, connecting the second end N2 of the second A signal line segment 42a, can reduce the curved corner.

[0068] When the second B signal line segment 42b is connected to the second end N2 of the second A signal line segment 42a, a via K is required to adjust the reflectivity of the laser or release stress due to the portion of the second signal line 42 passing through the packaging portion 3. When the second B signal line segment 42b is connected to the second A signal line segment 42a and the second end N2, the fan-out line 7 will overlap with the second signal line 42. Figure 13 and Figure 14 As shown, some fan-out lines 7 pass through via K, while some do not, resulting in significant differences in the loads on fan-out lines 7. When writing the same data signal, differences in the loads on fan-out lines 7 can cause screen differences, such as split-screen issues.

[0069] In this embodiment, when the second B signal line segment 42b is connected to the other end of the second A signal line segment 42a opposite to the second end N2, the second B signal line segment 42b only overlaps with the related signal lines of the clock signal line 6 and does not overlap with the fan-out line 7. Figure 16 and Figure 17 As shown in FIG. 1 , the clock signal line 6 has a relatively large line width, and two adjacent clock signal lines 6 perform different functions. The clock signal line 6 is used to transmit clock signals, high and low level signals, and start signals. The clock signal line 6 has a strong driving capability, and the load difference caused by the via K has no effect on the clock signal line 6.

[0070] In some optional embodiments, the packaging portion 3 further includes a metal layer disposed between the substrate 1 and the signal line layer 4. The metal layer and the second signal line segment B 42b do not overlap in a direction perpendicular to the plane of the substrate 1. By preventing the metal layer and the second signal line segment B 42b from overlapping, the overlap capacitance between the metal layer and the second signal line segment B 42b is reduced, thereby ensuring stable signal transmission in the second signal line segment B 42b.

[0071] For details, please refer to Figure 14, the metal layer includes a first metal layer and a second metal layer stacked in a direction perpendicular to the plane where the substrate 1 is located; the clock signal line 6 and the first metal layer are arranged in the same layer; and / or the fan-out line 7 is arranged in the same layer as the second metal layer. By arranging the clock signal line 6 and the fan-out line 7 in different layers, sufficient routing space can be provided for the clock signal line 6 and the fan-out line 7, and mutual interference between the clock signal line 6 and the fan-out line 7 can be avoided. Specifically, the signal line layer 4 is at least partially arranged on the side of the packaging part 3 away from the substrate 1, that is, in the direction perpendicular to the plane where the substrate 1 is located, the first signal line 41, the second signal line 42 and the packaging part 3 at least partially overlap, so as to cross the packaging part 3 and electrically connect to the control chip 5.

[0072] See also Figure 18 , Figure 18 An embodiment provides Figure 11 A partial enlarged view of point D in the middle. In some optional embodiments, the display device further includes a multiplexing unit 8 and a third signal line 43. The multiplexing unit 8 is disposed between the packaging portion 3 and the display area AA. The fan-out line 7 is electrically connected to the multiplexing unit 8. Each third signal line 43 is electrically connected to the display area AA. The multiplexing units 8 are spaced apart along the first direction X. The first signal line segment A 41 a extends through the spaces between the multiplexing units 8 and is electrically connected to the third signal line 43.

[0073] It is understood that by providing multiplexing unit 8, the number of fan-out traces can be reduced, thereby achieving a narrow bezel. The signal transmitted by first signal line segment 41a, i.e., first signal line 41, needs to be transmitted to display area AA. However, due to the obstruction of multiplexing unit 8, first signal line segment 41a needs to extend through the gaps between multiplexing units 8 to electrically connect to third signal line 43 in order to transmit the signal to thin-film transistors and other devices in display area AA. Optionally, due to limited space, the gaps between some multiplexing units 8 away from curved edge A2 and away from control chip 5 are relatively small, making it difficult for first signal line segment 41a to pass through. Therefore, first signal line segment 41a can be terminated near curved edge A2. The gaps between multiplexing units 8 near curved edge A2 are relatively large, and first signal line segment 41a can be electrically connected to third signal line 43 through the gaps between these multiplexing units 8.

[0074] The above is only a specific embodiment of the present invention. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited to this. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be covered within the protection scope of the present invention.

[0075] It should also be noted that the exemplary embodiments described herein describe methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the steps described above. In other words, the steps may be performed in the order described in the embodiments, or in a different order, or several steps may be performed simultaneously.

Claims

1. A display device comprising a display area and a non-display area, wherein the non-display area surrounds the display area, and the display area has adjacent straight edges and curved edges, wherein: include: substrate; a packaging portion, arranged in the non-display area around the display area; A signal line layer, the signal line layer includes a first signal line and a second signal line insulated from each other; the first signal line includes a first A signal line segment arranged between the display area and the packaging part, and the second signal line includes a second A signal line segment arranged between the display area and the packaging part; the first A signal line segment has a first end adjacent to the second A signal line segment, and the second A signal line segment has a second end adjacent to the first A signal line segment, and the minimum distances from the first end and the second end to the adjacent curved edge portion are both less than or equal to a preset distance, so that the first A signal line segment is terminated near the curved edge portion, and the second A signal line segment starts near the curved edge portion.

2. The display device according to claim 1, wherein The first signal line also includes a first B signal line segment connected to the first A signal line segment, the first B signal line segment is at least partially located on a side of the packaging portion away from the display area, the first A signal line segment extends along a first direction, the first B signal line segment extends along a second direction, and the first direction and the second direction intersect.

3. The display device according to claim 2, wherein: The second signal line further includes a second B signal line segment and a second C signal line segment connected to each other, wherein the second B signal line segment is connected to the second A signal line segment, and the second B signal line segment at least partially extends to a side of the packaging portion away from the display area, and the second C signal line segment is provided on a side of the packaging portion away from the display area; A minimum distance between the second C signal line segment and the packaging portion is greater than or equal to 30 μm.

4. The display device according to claim 3, wherein: The extending directions of the second B signal line segment and the second C signal line segment are perpendicular to each other.

5. The display device according to claim 3, wherein The second A signal line segment, the second B signal line segment, and the second C signal line segment are connected by chamfers.

6. The display device according to claim 1, wherein A minimum distance between the first end and the second end is greater than or equal to 10 μm.

7. The display device according to claim 3, wherein: The width ratio of the second A signal line segment to the second C signal line segment is 1:1 to 1:1.

5.

8. The display device according to claim 3, wherein It also includes a control chip disposed on a side of the packaging portion away from the display area, and the first signal line and the second signal line are electrically connected to the control chip respectively.

9. The display device according to claim 8, wherein It also includes a clock signal line electrically connected to the control chip, the clock signal line including a first clock signal connection segment close to the control chip, the first clock signal connection segment being at least partially disposed between the first B signal line segment and the second B signal line segment; or The first clock signal connection segment is at least partially disposed on a side of the first B signal line segment away from the second B signal line segment.

10. The display device according to claim 9, wherein In a direction perpendicular to the plane of the substrate, the clock signal line and the second B signal line segment at least partially overlap.

11. The display device according to claim 9, wherein The second B signal line segment is connected to the second end of the second A signal line segment; or, the second B signal line segment is connected to the other end of the second A signal line segment opposite to the second end.

12. The display device according to claim 11, wherein It also includes a fan-out line electrically connected to the control chip. When the second end of the second signal line segment B is connected to the other end opposite to the second end of the second signal line segment A, the fan-out line and the second signal line segment B do not overlap in a direction perpendicular to the plane of the substrate.

13. The display device according to claim 12, wherein: The packaging portion further includes a metal layer disposed between the substrate and the signal line layer. In a direction perpendicular to a plane where the substrate is located, the metal layer and the second B signal line segment do not overlap.

14. The display device according to claim 13, wherein: The metal layer includes a first metal layer and a second metal layer stacked in a direction perpendicular to the plane where the substrate is located; The clock signal line and the first metal layer are arranged on the same layer; and / or, The fan-out line and the second metal layer are arranged on the same layer.

15. The display device according to claim 12, wherein: It also includes a multiplexing unit and a third signal line, the multiplexing unit is arranged between the packaging part and the display area, the multiplexing unit and the fan-out line are electrically connected, the third signal line is at least partially located in the display area, the multiplexing units are arranged at intervals along the first direction, and the first signal line segment extends through the intervals between the multiplexing units and is electrically connected to the third signal line.

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