Metal oxide semiconductor field effect transistor and method of manufacturing the same

Abstract

The metal oxide semiconductor field effect transistor and the manufacturing method thereof provided by the embodiment of the present application can reduce the on-resistance of the metal oxide semiconductor field effect transistor device under large current, and thus can reduce the heat generated during the operation of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more specifically, to a metal-oxide-semiconductor field-effect transistor and a method for manufacturing the same. Background Technology

[0002] Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are widely used in various fields due to their high reverse breakdown voltage, high reliability, and low cost. With the expansion of applications, the demand for diverse voltage levels of MOSFETs has also increased, such as 1000V, 1200V, 1500V, and even 1700V products. As the voltage increases, the on-resistance of the MOSFET also increases, leading to a rise in operating temperature. Therefore, how to reduce the resistance of MOSFETs while ensuring high voltage withstand capability has become a pressing issue. Summary of the Invention

[0003] To overcome the aforementioned shortcomings in the prior art, the present application aims to provide a method for manufacturing a metal-oxide-semiconductor field-effect transistor, the method comprising:

[0004] A substrate is provided, the substrate including a first side and a second side opposite to each other;

[0005] A first oxide layer is grown from the first side, and the pattern required for lateral doping is formed by photolithography.

[0006] Terminal doping is performed on the first oxide layer, followed by push-bonding and oxidation to form a second oxide layer;

[0007] The desired pattern for the source region is formed by photolithography from the first side, and phosphorus implantation is performed;

[0008] A gate oxide layer is formed from the first side by dry oxygen diffusion;

[0009] Junction field-effect transistor region push-in under nitrogen atmosphere;

[0010] Polycrystalline deposition was performed and activated by phosphorus oxychloride;

[0011] The polycrystalline field edge pattern of the source region and the lateral variable doping terminal is formed from the first side by photolithography and / or dry etching.

[0012] Boron implantation is performed on the source region from the first side, followed by P-well lithography and implantation.

[0013] N-type impurities are injected from the first side;

[0014] depositing a third oxide layer and borophosphosilicate glass from the first side;

[0015] forming a contact hole through the third oxide layer and borophosphosilicate glass from the first side by photolithography;

[0016] depositing an aluminum metal layer from the first side and performing photolithography on the aluminum metal layer to form a predetermined pattern;

[0017] forming a predetermined pattern on the second side of the substrate by photolithography;

[0018] implanting P-type impurities from the second side of the substrate and activating in a nitrogen and hydrogen atmosphere;

[0019] evaporating a metal on the second side of the substrate.

[0020] In one possible implementation, the step of growing a first oxide layer from the first side and forming a pattern required for lateral variable doping by photolithography comprises:

[0021] forming a 0.3-0.5um first oxide layer on the surface of the first side of the substrate by thermal oxidation growth.

[0022] In one possible implementation, the step of performing terminal doping and push bonding and oxidation based on the first oxide layer to form a second oxide layer comprises:

[0023] implanting boron ions based on the first oxide layer 102 under ion implantation conditions of a dose of 5E12-8E12 and an energy of 60-90keV and performing push bonding and oxidation at a temperature of 1000-1100°C to form a 1.5-2.0um second oxide layer.

[0024] In one possible implementation, the step of forming a pattern required for a source region by photolithography from the first side and implanting phosphorus comprises:

[0025] forming a pattern required for a source region by photolithography from the first side and implanting phosphorus under ion implantation conditions of a dose of 2.2E12 and an energy of 100keV;

[0026] The step of forming a gate oxide layer by dry oxygen diffusion from the first side comprises:

[0027] performing dry oxygen diffusion from the first side for 118-138 minutes at a temperature of 1000°C to form a 0.09-0.1um gate oxide layer.

[0028] In one possible implementation, the step of performing push bonding of a junction field effect transistor region in a nitrogen atmosphere comprises:

[0029] Performing a junction field effect transistor region push junction for 300 minutes at 1150 degrees Celsius in a nitrogen environment.

[0030] In one possible implementation, the step of performing a poly deposition activated by phosphorous oxychloride includes:

[0031] Depositing 0.6um to 0.8um of poly and activating by phosphorous oxychloride;

[0032] The step of performing a P-well photoetch and implant for a source region from the first side includes:

[0033] Performing a boron implant for a source region from the first side at an ion implant condition of a dose of 3E13 to 5E13 and an energy of 80keV;

[0034] Performing a photoetch for a P-well and a boron implant at an ion implant condition of a dose of 7E14 to 9E14 and an energy of 60keV.

[0035] In one possible implementation, the step of performing an N-type impurity implant from the first side includes:

[0036] Dry etching a second oxide layer of the first side to thin the oxide layer;

[0037] Performing a P-well push junction for 30 minutes at a temperature condition of 1150 degrees Celsius;

[0038] Performing an arsenic implant based on an ion implant condition of a dose of 2E15 to 5E15 and an energy of 120keV and a nitrogen anneal for 2 hours at a temperature condition of 600 degrees Celsius.

[0039] In one possible implementation, the step of depositing a third oxide layer and borophosphosilicate glass from the first side includes:

[0040] Depositing a 0.2um third oxide layer and 0.8um borophosphosilicate glass from the first side and performing a reflow process for 20 minutes at a temperature condition of 950 degrees Celsius to 1000 degrees Celsius.

[0041] In one possible implementation, the step of implanting a P-type impurity from a second side of the substrate and activating in a nitrogen and hydrogen atmosphere includes:

[0042] Implanting a set dose of boron from a second side of the substrate and performing an activation process for 30 minutes at a temperature condition of 450 degrees Celsius in a mixed gas atmosphere of nitrogen and hydrogen.

[0043] The application further provides a metal oxide semiconductor field effect transistor, which is manufactured by the metal oxide semiconductor field effect transistor manufacturing method.

[0044] Compared with the prior art, the application has the following beneficial effects:

[0045] The metal oxide semiconductor field effect transistor and the manufacturing method thereof provided by the embodiments of the application can reduce the on-resistance of the metal oxide semiconductor field effect transistor device under large current, and thus can reduce the heat generated during the operation of the device. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the application, and thus should not be regarded as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0047] Figure 1 The step flowchart of the metal oxide semiconductor field effect transistor manufacturing method provided by the embodiments of the application is shown in the figure.

[0048] Figures 2-7 The manufacturing process diagram of the metal oxide semiconductor field effect transistor provided by the embodiments of the application is shown in the figure. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the embodiments of the application more clear, the following will combine the drawings in the embodiments of the application to clearly and completely describe the technical solutions in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, but not all the embodiments. The components of the embodiments of the application described and shown in the drawings can be arranged and designed in various different configurations.

[0050] Therefore, the following detailed description of the embodiments of the application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of the application.

[0051] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, and thus, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0052] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0053] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0054] Please see Figure 1 , Figure 1 This is a schematic diagram illustrating the steps of a metal-oxide-semiconductor field-effect transistor manufacturing method provided in this embodiment. The following is a detailed explanation in conjunction with... Figures 2-7 The manufacturing process diagram provides a detailed explanation of each step of the method.

[0055] Step S101: A substrate 101 is provided, the substrate 101 including a first side and a second side opposite to each other.

[0056] In this embodiment, the substrate 101 can be a silicon substrate 101. Taking the manufacture of a 1700V ultra-high voltage MOSFET as an example, a silicon polished material substrate with a resistivity of 60Ω·cm to 70Ω·cm can be selected as the substrate 101.

[0057] Step S102: A first oxide layer 102 is grown from the first side, and the pattern required for Variation of Lateral Doping (VLD) is formed by photolithography.

[0058] In one possible implementation, in step S102, a first oxide layer 102 of 0.3 μm to 0.5 μm can be formed on the surface of the first oxide layer of the substrate 101 by thermo-oxidative growth, such as... Figure 2 As shown. The oxide layer mainly serves as a terminal isolation layer, preventing breakdown between the bulk and the surface under high voltage.

[0059] Then, photoresist 103 is coated on the first oxide layer 102, and the required pattern of the lateral doped terminal is obtained by photolithography, etching and other methods.

[0060] Step S103, terminal doping and push junction and oxidation are performed based on the first oxide layer 102, and the second oxide layer 104 is formed.

[0061] In a possible implementation, in step S103, boron ion implantation can be performed based on the first oxide layer 102 under ion implantation conditions of a dose of 5E12 to 8E12 and an energy of 60keV to 90keV, and push junction and oxidation are performed under temperature conditions of 1000℃ to 1100℃, and the second oxide layer 104 of 1.5um to 2.0um is formed, as shown in Figure 3 .

[0062] Step S104, a source region required pattern is formed from the first side, and phosphorus implantation is performed.

[0063] In a possible implementation, in step S104, a source region required pattern can be formed from the first side by a photoetching process. For example, the source region required pattern is formed by coating photoresist 103, and then photoetching, etching and the like are performed. Finally, phosphorus implantation is performed under ion implantation conditions of a dose of 2.2E12 and an energy of 100keV.

[0064] Step S105, gate oxide layer 105 is formed by dry oxygen diffusion from the first side.

[0065] In a possible implementation, in step S105, dry oxygen diffusion is performed from the first side for 118 to 138 minutes under temperature conditions of 1000℃, and the gate oxide layer 105 of 0.09 to 0.1um is formed, as shown in Figure 4 .

[0066] Step S106, junction field effect transistor region push junction is performed in a nitrogen environment.

[0067] In a possible implementation, in step S106, junction field effect transistor region push junction is performed in a nitrogen environment at 1150℃ for 300 minutes.

[0068] Step S107, polycrystal deposition is performed, and activation is performed by phosphorus oxychloride.

[0069] In a possible implementation, in step S107, polycrystal of 0.6um to 0.8um is deposited, and activation is performed by phosphorus oxychloride.

[0070] Step S108, source region and polycrystal field edge pattern of lateral variable doping terminal are formed from the first side by photoetching and / or dry etching.

[0071] In one possible implementation, in step S108, the source region and the polycrystalline field edge pattern of the lateral variable-doping termination can be obtained by coating photoresist 103 from the first side and by photolithography and dry etching. Figure 5

[0072] Step S109, boron implantation is performed for the source region from the first side, and P-well photolithography and implantation are performed.

[0073] In one possible implementation, in step S109, boron implantation is performed for the source region from the first side under ion implantation conditions of a dose of 3E13 to 5E13 and an energy of 80 keV, so as to dope the source region with impurities. Then, photolithography is performed for the P-well, and boron implantation is performed under ion implantation conditions of a dose of 7E14 to 9E14 and an energy of 60 keV.

[0074] Step S110, N-type impurity implantation is performed from the first side.

[0075] In one possible implementation, in step S110, dry etching is performed on the second oxide layer of the first side, so as to thin the oxide layer. In one example, the oxide layer can be thinned to a remaining oxide layer thickness of about 0.05 um. Then, P-well push junction is performed at a temperature of 1150 °C for 30 minutes, so as to form a required concentration distribution of termination impurities. Finally, arsenic implantation is performed under ion implantation conditions of a dose of 2E15 to 5E15 and an energy of 120 keV, and nitrogen annealing is performed at a temperature of 600 °C for 2 hours.

[0076] Step S111, a third oxide layer and boron phosphorus silicon glass are deposited from the first side.

[0077] In one possible implementation, in step S111, a third oxide layer of 0.2 um and boron phosphorus silicon glass of 0.8 um are deposited from the first side, and reflow processing is performed at a temperature of 950 °C to 1000 °C for 20 minutes.

[0078] Step S112, a contact hole is formed through the third oxide layer and the boron phosphorus silicon glass from the first side by photolithography.

[0079] In one possible implementation, in step S112, the contact hole 107 can be formed by coating photoresist 103 and etching the third oxide layer and the boron phosphorus silicon glass by photolithography, as shown in FIG. 1C. Figure 6

[0080] Step S113, an aluminum metal layer is deposited from the first side, and the aluminum metal layer is photolithographically formed into a preset pattern.

[0081] ​​Step S114, forming a set pattern on the second side of the substrate 101 by photoetching.

[0082] In a possible implementation, the back of the substrate 101 can be thinned to 180 um before step S114, and then the set pattern is formed by photoetching.

[0083] Step S115, injecting P-type impurities from the second side of the substrate 101, and activating under a nitrogen and hydrogen atmosphere.

[0084] In a possible implementation, a set dose of boron is injected from the second side of the substrate 101 in step S115, and the activation treatment is performed under a mixed gas atmosphere of nitrogen and hydrogen at 450℃ for 30 minutes, to form a device with a source, a gate, and a drain as shown in FIG. 4. Figure 7

[0085] Step S116, evaporating metal from the second side of the substrate 101.

[0086] Based on the same inventive concept, the embodiment also provides a metal oxide semiconductor field effect transistor, which is made by the metal oxide semiconductor field effect transistor method provided in the embodiment.

[0087] In conclusion, the metal oxide semiconductor field effect transistor and the manufacturing method thereof provided in the embodiment can reduce the on-resistance of the metal oxide semiconductor field effect transistor device under a large current by injecting P-type impurities from the back of the metal oxide semiconductor field effect transistor device, so as to reduce the heat generated during the operation of the device.

[0088] ​In the embodiments of the present disclosure, it should be understood that the disclosed apparatus and method can also be implemented in other manners. The embodiments described above are merely exemplary for implementing the present disclosure and should not be used in a limiting manner. For example, the flowcharts and block diagrams in the accompanying drawings merely show the possible implementation architec tures, functions and operation of the apparatus, method and computer program product according to the embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams can represent a module, a program segment or a part of code, which contains one or more executable instructions for implementing the specified logic function. It should also be noted that, in some alternative implementations, the functions noted in the blocks can occur in a different order from that noted in the accompanying drawings. For example, two consecutive blocks can actually be executed in a substantially parallel manner, or they can be executed in a reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and the combination of blocks in the block diagrams and / or flowcharts, can be implemented by a special-purpose hardware-based system, or by a combination of special-purpose hardware and computer instructions.

[0089] It should be noted that, in the present document, the terms such as first and second are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the phrase "including a" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0090] The above describes only various embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method of manufacturing a metal oxide semiconductor field effect transistor, characterized by, The method comprises: providing a substrate, the substrate comprising a first side and a second side opposite to each other; growing a first oxide layer from the first side and forming a pattern required for lateral variable doping by means of photolithography; performing terminal doping based on the first oxide layer and performing a push joint and oxidation to form a second oxide layer; forming a pattern required for a source region from the first side by means of photolithography and performing phosphorus implantation; forming a gate oxide layer from the first side by means of dry oxygen diffusion; performing a junction field effect transistor region push joint in a nitrogen environment; performing polycrystalline deposition and activation by means of phosphorus oxychloride; forming a polycrystalline field edge pattern of the source region and the terminal of lateral variable doping from the first side by means of photolithography and / or dry etching; performing boron implantation for the source region from the first side and performing P well photolithography and implantation; performing N type impurity implantation from the first side; depositing a third oxide layer and boron phosphorus silicon glass from the first side; forming a contact hole through the third oxide layer and boron phosphorus silicon glass from the first side by means of photolithography; depositing an aluminum metal layer from the first side and performing photolithography on the aluminum metal layer to form a preset pattern; forming a preset pattern from the second side of the substrate by means of photolithography; implanting P type impurities from the second side of the substrate and activating in a nitrogen and hydrogen atmosphere; evaporating metal from the second side of the substrate; the step of implanting P type impurities from the second side of the substrate and activating in a nitrogen and hydrogen atmosphere comprises: implanting a preset dose of boron from the second side of the substrate and activating in a mixed gas atmosphere of nitrogen and hydrogen at 450°C for 30 minutes.

2. The method of claim 1, wherein, the step of growing a first oxide layer from the first side and forming a pattern required for lateral variable doping by means of photolithography comprises: forming a 0.3um to 0.5um first oxide layer on the surface of the first side of the substrate by means of thermal oxygen growth.

3. The method of claim 1, wherein, the step of performing terminal doping based on the first oxide layer and performing a push joint and oxidation to form a second oxide layer comprises: implanting boron ions based on the first oxide layer 102 under ion implantation conditions of a dose of 5E12 to 8E12 and an energy of 60keV to 90keV and performing a push joint and oxidation at a temperature condition of 1000°C to 1100°C to form a 1.5um to 2.0um second oxide layer.

4. The method of claim 1, wherein, the step of forming a pattern required for a source region from the first side by means of photolithography and performing phosphorus implantation comprises: forming a pattern required for a source region from the first side by means of a photolithography process and implanting phosphorus under ion implantation conditions of a dose of 2.2E12 and an energy of 100keV; the step of forming a gate oxide layer from the first side by means of dry oxygen diffusion comprises: forming a 0.09 to 0.1um gate oxide layer by means of dry oxygen diffusion from the first side for 118 to 138 minutes at a temperature condition of 1000°C.

5. The method of claim 1, wherein, the step of performing a junction field effect transistor region push joint in a nitrogen environment comprises: performing a junction field effect transistor region push joint in a nitrogen environment at 1150°C for 300 minutes.

6. The method of claim 1, wherein, the step of performing polycrystalline deposition and activation by means of phosphorus oxychloride comprises: Depositing 0.6um to 0.8um polysilicon and activating by phosphorus trichloride; The step of performing P-well photoetching and implanting for the source region from the first side comprises: Performing boron implantation for the source region from the first side according to ion implantation conditions with a dose of 3E13 to 5E13 and an energy of 80keV; Performing photoetching for the P-well and boron implantation under ion implantation conditions with a dose of 7E14 to 9E14 and an energy of 60keV.

7. The method of claim 1, wherein, The step of implanting N-type impurities from the first side comprises: Performing dry etching on the second oxide layer of the first side to thin the second oxide layer; Performing P-well push junction at a temperature of 1150℃ for 30 minutes; Performing arsenic implantation based on ion implantation conditions with a dose of 2E15 to 5E15 and an energy of 120keV and nitrogen annealing at a temperature of 600℃ for 2 hours.

8. The method of claim 1, wherein, The step of depositing a third oxide layer and boron phosphorus silicon glass from the first side comprises: Depositing a third oxide layer of 0.2um and boron phosphorus silicon glass of 0.8um from the first side and performing reflow processing at a temperature of 950℃ to 1000℃ for 20 minutes.

9. A metal oxide semiconductor field effect transistor, characterized by, The metal oxide semiconductor field effect transistor is made by the method of any one of claims 1 to 8.

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