SGT device with a high-reliability upper and lower structure

Abstract

The present invention relates to an SGT device with a high-reliability up-and-down structure. It includes a semiconductor substrate of a first conductivity type and a cell region formed in the drift region of the semiconductor substrate, and the cells in the cell region adopt a trench structure; in the top view plane of the SGT device, the cells in the cell region include a square-ring-shaped cell peripheral trench and a cell center trench located in the central region of the inner circle of the cell peripheral trench; a base region of a second conductivity type is arranged on the outer circle of the cell center trench, and the base region of the second conductivity type is located above the corresponding trench bottoms of the cell center trench and the cell peripheral trench in the drift region, and the base region of the second conductivity type is in contact with the outer side wall of the cell center trench and the outer side wall of the inner circle of the cell peripheral trench; the present invention can effectively reduce the warping caused by the different stresses in the transverse and longitudinal directions, and can reduce the withstand voltage reliability caused by the difference in the breakdown voltage BV of the drift region.

Description

Technical Field

[0001] The present invention relates to an SGT device, in particular to an SGT device with a high-reliability up-and-down structure. Background Art

[0002] Currently, most of the drift regions of existing power devices such as MOSFETs only use epitaxial layers without other structures. For this structure, there is a trade-off relationship between the breakdown voltage BV and the on-resistance RDSON of the drift region with a silicon limit. In order to break through the performance limitations of existing trench power devices, the shield-gate transistor (SGT) came into being.

[0003] The main difference between SGT devices and traditional power devices is that a deep trench structure is introduced into the drift region. This deep trench structure depletes the drift region between the trenches through a lateral electric field, so that the drift region (the mesa region between the deep trenches) can adopt a higher doping concentration, further reducing the on-resistance and breaking through the silicon limit performance of traditional MOSFETs. The SGT cell structure is divided into an up-and-down structure and a left-and-right structure. Among them, in the up-and-down structure, the gate conductive polysilicon and the source conductive polysilicon are distributed in an up-and-down relationship in the deep trench, and in the left-and-right structure, the gate conductive polysilicon and the source conductive polysilicon are in a left-and-right relationship in the deep trench.

[0004] The cells of existing SGT devices are in a strip shape. The typical characteristic of this design is that the active deep trench 1 presents a periodic strip shape on the top view plane of the entire device, as Figure 1 shown. Figure 1 In, the active deep trench 1 in the active region is a longitudinal strip structure. Due to the relatively thick oxide layer and the deposition of source conductive polysilicon in the active deep trench 1, there will be a certain gravitational concentration in the left-and-right horizontal direction of the SGT device, and the structure is exactly the same in the longitudinal direction, that is, there is no stress in the longitudinal direction.

[0005] When the entire wafer is under excessive stress in one direction, such as the left-and-right direction, it will cause the wafer to warp severely in a wavy shape, resulting in difficulties in subsequent processing and testing of the wafer (wafer). Severe warping will directly lead to the scrapping of the wafer. For high-voltage SGT devices, due to the deeper trenches and thicker field oxide layers of high-voltage SGTs, the stress of the high-voltage SGT devices themselves will be relatively large. If the processing technology is not properly controlled, serious wafer warping will occur in traditional strip-shaped high-voltage SGT devices.

[0006] In addition, for Figure 1In the SGT device, a terminal region is also provided on the outer periphery of the active region. The terminal region includes an annular terminal trench 2. When there are both an active deep trench 1 and a terminal trench 2, the mesa region (the region between the active deep trenches 1) in the active region and the mesa region 3 of the terminal-cell region (the region between the active region and the terminal trench 2 in the terminal region) are different, and the depletion directions of the two mesa regions are also different. Figure 2 It is the corresponding relationship between the breakdown voltage BV of the drift region and the width of the mesa region. Figure 2 In it, the abscissa is the mesa width and the ordinate is the breakdown voltage BV of the drift region. From Figure 2 it can be obtained that there is an optimal mesa width that enables the breakdown voltage BV of the SGT device to reach the maximum value. When the mesa width is less than the optimal mesa width or greater than the optimal mesa width, the breakdown voltage BV of the SGT device decreases. Therefore, Figure 1 in it, the mesa region in the active region and the mesa region 3 of the terminal-cell region are different, which will cause a breakdown voltage difference in the edge regions of the active region and the terminal region, resulting in a decrease in the breakdown voltage reliability of the SGT device and making it difficult to meet the actual working requirements. Summary of the Invention

[0007] The object of the present invention is to overcome the deficiencies in the prior art and provide a high-reliability SGT device with an upper and lower structure, which can effectively reduce the warping caused by different stresses in the transverse and longitudinal directions and can reduce the breakdown voltage reliability caused by the difference in the breakdown voltage BV of the drift region.

[0008] According to the technical solution provided by the present invention, the high-reliability SGT device with an upper and lower structure includes a semiconductor substrate of a first conductivity type and a cell region prepared in the drift region of the semiconductor substrate. The cells in the cell region adopt a trench structure.

[0009] On the top view plane of the SGT device, the cells in the cell region include a square-ring-shaped cell peripheral trench and a cell center trench located in the central area of the inner circle of the cell peripheral trench; a base region of a second conductivity type is provided between the outer circle of the cell center trench and the inner circle of the cell peripheral trench.

[0010] In the cross-section of the SGT device, the base region of the second conductivity type is located above the corresponding trench bottoms of the cell center trench and the cell peripheral trench in the drift region, and the base region of the second conductivity type is in contact with the outer sidewalls of the cell center trench and the inner circle of the cell peripheral trench; a conductive polysilicon in the cell center trench is filled in the cell center trench, and the conductive polysilicon in the cell center trench is insulated from the inner sidewalls and the inner bottom wall of the cell center trench through a cell center trench oxide layer covering the inner sidewalls and the inner bottom wall of the cell center trench.

[0011] A shielding gate unit with an upper and lower structure distribution is arranged in the peripheral trench of the cell. Among them, the shielding gate unit with the upper and lower structure distribution includes a peripheral trench gate conductive polysilicon located above and a peripheral trench source conductive polysilicon located below the peripheral trench gate conductive polysilicon. The peripheral trench gate conductive polysilicon and the peripheral trench source conductive polysilicon are insulated and isolated from each other. The peripheral trench gate conductive polysilicon is electrically connected to the gate metal layer above the drift region, and the peripheral trench source conductive polysilicon, the trench conductive polysilicon at the center, and the base region of the second conductivity type are electrically connected to the source metal layer above the drift region.

[0012] It also includes a source region of the first conductivity type in contact with the upper side of the inner wall of the inner circle of the peripheral trench of the cell. The depth of the source region of the first conductivity type is less than the depth of the base region of the second conductivity type. The source region of the first conductivity type is in contact with the base region of the second conductivity type and has an ohmic contact with the source metal layer.

[0013] The inner sidewall of the inner circle of the peripheral trench of the cell is square or circular, and the base region of the second conductivity type is located above the bottom of the peripheral trench gate conductive polysilicon.

[0014] The width of the peripheral trench gate conductive polysilicon is greater than the width of the peripheral trench source conductive polysilicon. The peripheral trench source conductive polysilicon is insulated and isolated from the inner sidewall and the inner bottom wall of the peripheral trench of the cell through a peripheral trench lower insulating oxide layer. The peripheral trench gate conductive polysilicon is insulated and isolated from the corresponding inner sidewall of the peripheral trench of the cell through a peripheral trench upper insulating oxide layer. The peripheral trench gate conductive polysilicon in the peripheral trench of the cell is insulated and isolated from the source metal through an insulating dielectric layer covering the mouth of the peripheral trench of the cell.

[0015] It also includes a center trench contact hole corresponding to the trench at the center of the cell and a center trench outer contact hole located outside the center trench contact hole. Both the center trench contact hole and the center trench outer contact hole penetrate the insulating dielectric layer.

[0016] The source metal layer has an ohmic contact with the trench conductive polysilicon at the center through a first filling connector filled in the center trench contact hole. The source metal layer has an ohmic contact with the base region of the second conductivity type and the source region of the first conductivity type through a second filling connector filled in the center trench outer contact hole.

[0017] The trench at the center of the cell is square, and the width of the center trench contact hole is less than the width of the trench conductive polysilicon at the center of the cell in the center trench of the cell.

[0018] The center trench outer contact hole is annular outside the center trench of the cell.

[0019] The semiconductor substrate also includes a substrate of the first conductivity type adaptively connected to the drift region, and a back electrode structure is arranged on the back of the substrate.

[0020] It further includes a lead connection area located outside the cell area and lead connection units provided in the lead connection area. The source metal layer can be electrically connected to the peripheral trench source conductive polysilicon through the lead connection units, and the gate metal layer can be electrically connected to the peripheral trench gate conductive polysilicon through the lead connection units.

[0021] The lead connection units include a plurality of lead area lead trenches. A lead area lead trench corresponds exactly to the cell peripheral trench on one side inside the corresponding cell, and the peripheral trench gate conductive polysilicon and the peripheral source conductive polysilicon in the cell peripheral trench are respectively introduced into the lead area lead trench to form lead trench peripheral trench gate conductive polysilicon and lead trench peripheral trench source conductive polysilicon respectively;

[0022] The gate metal layer at least includes a gate lead connection part. The gate lead connection part is in ohmic contact with the lead trench peripheral trench gate conductive polysilicon in the lead area lead trench through a gate polysilicon lead contact hole corresponding exactly to the lead area lead trench;

[0023] The source metal layer includes a source lead connection part and a source cell connection part connected to the source lead connection part. It is in ohmic contact with the central trench conductive polysilicon in the trench at the center of the cell through the source cell connection part. The source lead connection part is in ohmic contact with the lead trench peripheral trench source conductive polysilicon in the lead area lead trench through a source polysilicon lead contact hole corresponding exactly to the lead area lead trench.

[0024] The length direction of the gate lead connection part is consistent with the length direction of the source lead connection part, and the gate lead connection part is located between the cell area and the source lead connection part;

[0025] The lead area lead trenches are strip-shaped, and the length direction of the lead area lead trenches is perpendicular to the length direction of the gate lead connection part.

[0026] A lead area transition trench is provided between two adjacent lead area lead trenches in the lead connection area. The transition trench conductive polysilicon in the lead area transition trench is in ohmic contact with the source metal layer;

[0027] It further includes lead area lead connection trenches adaptively connected to the ends of all lead area lead trenches. The two ends of the lead area lead trenches are respectively connected to the lead area lead connection trenches and the cell peripheral trenches on one side inside the corresponding cell;

[0028] The horizontal distance between the lead-out area transition trench and the lead-out trenches on both sides of the lead-out area is L1. The first end of the lead-out area transition trench corresponds exactly to a single cell, and the vertical distance between the first end of the lead-out area transition trench and the corresponding cell is L2. The vertical distance between the second end of the lead-out area transition trench and the inner side of the lead-out area lead-out connection trench is L3, and the distances L1, L2, and L3 match each other.

[0029] Among the "first conduction type" and "second conduction type", for an N-type SGT, the first conduction type refers to N-type and the second conduction type is P-type; for a P-type SGT device, the types referred to by the first conduction type and the second conduction type are exactly opposite to those of the N-type SGT device.

[0030] Advantages of the present invention:

[0031] For any cell unit, the cell unit can be made square through the cell peripheral trench ring. A central trench conductive polysilicon in ohmic contact with the source metal layer is arranged in the trench at the center of the cell. A shielding gate unit with an up-and-down structure distribution is arranged in the cell peripheral trench for forming the cell peripheral trench ring. Since the structures in the four directions of the cell unit are the same, the warping problem of the semiconductor substrate caused by different stresses in the horizontal and vertical directions can be effectively prevented.

[0032] During lead-out, the lead-out connection unit at least includes a lead-out trench in the lead-out area. The gate lead-out connection part is in ohmic contact with the lead-out trench peripheral trench gate conductive polysilicon in the lead-out trench through a gate polysilicon lead-out contact hole corresponding exactly to the lead-out trench in the lead-out area. At the same time, the source lead-out connection part is in ohmic contact with the lead-out trench peripheral trench source conductive polysilicon in the lead-out trench through a source polysilicon lead-out contact hole corresponding exactly to the lead-out trench in the lead-out area.

[0033] In the lead-out connection area, through the cooperation of the lead-out area transition trench and the lead-out area lead-out connection trench with the lead-out trench, the horizontal distance between the lead-out area transition trench and the lead-out trenches on both sides of the lead-out area can be made L1. The first end of the lead-out area transition trench corresponds exactly to a single cell, and the vertical distance between the first end of the lead-out area transition trench and the corresponding cell is L2. The vertical distance between the second end of the lead-out area transition trench and the inner side of the lead-out area lead-out connection trench is L3, and the distances L1, L2, and L3 match each other. According to the relationship between the distances L1, L2, and L3 and the breakdown voltage BV of the drift region, it can be known that it can be kept consistent with the mesa width and the depletion direction of the mesa width in the cell area. Therefore, the breakdown voltage BV of the drift region in the cell area and the lead-out connection area can be kept consistent, preventing the difference in the breakdown voltage BV of the drift region due to different mesa widths or depletion directions at different positions of the device, and further preventing the breakdown voltage reliability problem caused by the difference in the breakdown voltage BV of the drift region. Description of the Drawings

[0034] Figure 1 is a top view of an existing SGT device.

[0035] Figure 2 is a schematic diagram of the relationship between the existing mesa width and the breakdown voltage BV of the drift region.

[0036] Figure 3 is a top view of the cell inside the SGT device of the present invention.

[0037] Figure 4 is Figure 3 a cross-sectional view of the cell in

[0038] Figure 5 is a schematic diagram of the cooperation between the cell and the lead connection region in the cell region of the present invention.

[0039] Description of Reference Numerals: 1 - active deep trench, 2 - terminal trench, 3 - terminal-cell region mesa region, 4 - cell peripheral trench ring, 5 - trench at the center of the cell, 6 - outer contact hole ring of the center trench, 7 - contact hole of the center trench, 8 - P-type base region, 9 - inner ring of the cell peripheral trench, 10 - substrate, 11 - drift region, 12 - back electrode structure, 13 - cell peripheral trench, 14 - insulating oxide layer under the peripheral trench, 15 - conductive polysilicon of the center trench, 16 - source conductive polysilicon of the peripheral trench, 17 - oxide layer of the trench at the center of the cell, 18 - gate conductive polysilicon of the peripheral trench, 19 - inner isolation oxide layer of the peripheral trench, 20 - N+ source region, 21 - insulating dielectric layer, 22 - source-cell connection part, 23 - outer contact hole of the center trench, 24 - second connection body filling, 25 - first connection body filling, 26 - cell region, 27 - lead connection region, 28 - cell unit, 29 - end block of the gate lead connection part, 30 - gate lead connection part, 31 - gate polysilicon lead contact hole, 32 - source polysilicon lead contact hole, 33 - transition trench of the lead region, 34 - lead trench of the lead region, 35 - lead connection trench of the lead region, 36 - upper insulating oxide layer of the peripheral trench, and 37 - source lead connection part. Detailed Embodiments

[0040] The present invention will be further described below with reference to specific drawings and embodiments.

[0041] As Figure 3 , Figure 4 and Figure 5 shown: In order to effectively reduce the warping caused by different stresses in the horizontal and vertical directions, for an N-type SGT device, the present invention includes a semiconductor substrate having an N conductivity type and a cell region 26 formed in the drift region 11 of the semiconductor substrate, and the cells in the cell region 26 adopt a trench structure;

[0042] On the top view plane of the SGT device, the cells in the cell region 26 include a square-ring-shaped cell peripheral trench 13 and a cell center trench 5 located in the central region inside the cell peripheral trench 13; a P-type base region 8 is provided between the outer ring of the cell center trench and the inner ring of the cell peripheral trench 13;

[0043] In the cross-section of the SGT device, the P-type base region 8 is located above the corresponding bottom of the cell center trench 5 and the cell peripheral trench 13 in the drift region 11, and the P-type base region 8 is in contact with the outer sidewall of the cell center trench 5 and the outer sidewall of the inner ring of the cell peripheral trench 13; a center trench conductive polysilicon 15 is filled in the cell center trench 5, and the center trench conductive polysilicon 15 is insulated from the inner sidewall and the inner bottom wall of the cell center trench 5 by a cell center trench oxide layer 17 covering the inner sidewall and the inner bottom wall of the cell center trench 5;

[0044] A shield gate unit with an up-and-down structure distribution is provided in the cell peripheral trench 13. Specifically, the shield gate unit with the up-and-down structure distribution includes a peripheral trench gate conductive polysilicon 18 located above and a peripheral trench source conductive polysilicon 16 located below the peripheral trench gate conductive polysilicon 18. The peripheral trench gate conductive polysilicon 18 and the peripheral trench source conductive polysilicon 16 are insulated from each other. The peripheral trench gate conductive polysilicon 18 is electrically connected to the gate metal layer above the drift region 11, and the peripheral trench source conductive polysilicon 16, the center trench conductive polysilicon 15, and the P-type base region 8 are electrically connected to the source metal layer above the drift region 11.

[0045] Specifically, the semiconductor substrate can be made of commonly used semiconductor materials in the art, such as silicon, etc., and can be specifically selected according to needs. Generally, the semiconductor substrate includes a substrate 10 and a drift region 11 located on the substrate 10. The substrate 10 and the drift region 11 have the same conductivity type. That is, for an N-type SGT device, the conductivity types of both the substrate 10 and the drift region 11 are N-type. The doping concentration of the drift region 11 is generally lower than that of the substrate 10, and the thickness of the substrate 10 is less than that of the drift region 11. This is well-known to those skilled in the art and will not be elaborated here.

[0046] The front surface of the drift region 11 forms the front surface of the entire semiconductor substrate, and the back surface of the substrate 10 forms the back surface of the entire semiconductor substrate. The cell region 26 corresponds to the front surface of the semiconductor substrate. The cell region 26 is fabricated in the drift region 11. Generally, the cell region 26 is fabricated in the central region of the drift region 11. A terminal region is provided on the outer periphery of the cell region 26, and the terminal region can be used to protect the cell region 26. The specific functions and cooperation relationships of the terminal region and the cell region 26 are the same as those in the prior art. The cell region 26 includes a plurality of cells, that is, one cell can be formed by using a cell unit 28. All the cells in the cell region 26 are connected in parallel into a whole through the source metal layer. The specific manner of connecting the cells in parallel by using the source metal layer is the same as that in the prior art.

[0047] In the embodiment of the present invention, on the etching plane of the SGT device, any cell unit 28 that forms a cell includes a square-ring-shaped cell peripheral groove 13 and a cell center groove 5 located in the central region of the inner circle of the cell peripheral groove 13. The square-ring-shaped cell peripheral groove 13 is the cell peripheral groove ring 4. The cell peripheral groove ring 4 is square-shaped. The cell center groove 5 is provided in the central region within the cell peripheral groove ring 4. Generally, the cell center groove 5 can be square-shaped, such as Figure 3 shown; of course, the cell center groove 5 can also adopt other shapes, and can be specifically selected according to needs.

[0048] In addition, a P-type base region 8 is also provided on the inner circle of the cell peripheral groove 13 and the outer circle of the cell center groove 5. Generally, the P-type base region 8 penetrates through the drift region 11. The P-type base region 8 is located above the corresponding bottom surfaces of the cell center groove 5 and the cell peripheral groove 13 in the drift region 11, and the P-type base region 8 is in contact with the outer sidewalls of the cell center groove 5 and the inner circle of the cell peripheral groove 13.

[0049] such as Figure 4As shown, on the cross-section of the SGT device, the central trench 5 at the cell center is filled with central trench conductive polysilicon 15. The central trench conductive polysilicon 15 is insulated from the inner sidewall and the inner bottom wall of the central trench 5 at the cell center by a central trench oxide layer 17 that covers the inner sidewall and the inner bottom wall of the central trench 5 at the cell center. Specifically, the central trench oxide layer 17 is grown in the central trench 5 at the cell center. The central trench oxide layer 17 can be prepared by using the common oxide layer process in this technical field. The central trench oxide layer 17 is silicon dioxide. The specific process conditions and procedures for preparing the central trench oxide layer 17 are the same as those in the prior art and can be selected according to needs, based on being able to prepare the required central trench oxide layer 17. After the central trench oxide layer 17 is prepared, the central trench conductive polysilicon 15 can be prepared by using a filling process. The central trench conductive polysilicon 15 is insulated from the inner sidewall and the bottom wall of the central trench 5 at the cell center where it is located by the central trench oxide layer 17.

[0050] Since the cell peripheral trench ring 4 is annular, therefore, on the cross-section of the SGT device, there is a cell peripheral trench 13 on both sides of the central trench 5 at the cell center. The cell peripheral trench 13 and the central trench 5 at the cell center can be prepared in the same process step. The depth of the cell peripheral trench 13 and the central trench 5 at the cell center in the drift region 11 can be the same, as Figure 4 shown.

[0051] In specific implementation, a shield gate unit with an upper and lower structure distribution is arranged in the cell peripheral trench 13. Specifically, the shield gate unit can adopt the common form in the prior art, that is, the shield gate unit with an upper and lower structure distribution includes an upper peripheral trench gate conductive polysilicon 18 and a lower peripheral trench source conductive polysilicon 16 located below the peripheral trench gate conductive polysilicon 18. The peripheral trench gate conductive polysilicon 18 and the peripheral trench source conductive polysilicon 16 are insulated from each other. The peripheral trench gate conductive polysilicon 18 is electrically connected to the gate metal layer above the drift region 11. The peripheral trench source conductive polysilicon 16, the central trench conductive polysilicon 15, and the P-type base region 8 are electrically connected to the source metal layer above the drift region 11.

[0052] In the embodiments of the present invention, a source electrode of the SGT device can be formed by using a source metal layer, and a gate electrode of the SGT device can be formed by using a gate metal layer. In addition, a back electrode structure 12 is provided on the back surface of the substrate 10, and a back electrode can be formed by using the back electrode structure 12. At the same time, according to the specific form of the back electrode structure 12, the SGT device can be formed into a MOSFET device or an IGBT device. The manner of forming a MOSFET device or an IGBT device by using the back electrode structure 12 is consistent with the prior art. The specific implementation structure of the back electrode structure 12 can be selected according to actual needs, which is well known to those skilled in the art and will not be elaborated here. When the SGT device is a MOSFET device, a drain electrode is formed by using the back electrode structure. When the SGT device is an IGBT device, a collector is formed by using the back electrode structure.

[0053] In summary, for any cell unit 28, the cell unit 28 where it is located can be made square through the cell peripheral trench ring 4. A central trench conductive polysilicon 15 electrically connected to the source metal layer is arranged in the trench 5 at the cell center. Shield gate units with an up-and-down structure distribution are arranged in the cell peripheral trench 13 where the cell peripheral trench ring 4 is formed. Since the structures and sizes in the four directions of the cell unit 28 are the same, the warping problem of the semiconductor substrate (i.e., the wafer mentioned in the background art) caused by different stresses in the transverse direction and the longitudinal direction can be effectively prevented, the reliability and yield during the preparation of the SGT device are improved, and the requirements for the preparation process are reduced.

[0054] Furthermore, an N+ source region 20 in contact with the upper side of the inner wall of the inner circle of the cell peripheral trench 13 is further included. The depth of the N+ source region 20 is less than the depth of the P-type base region 8. The N+ source region 20 is in contact with the P-type base region 8, and the N+ source region 20 is in ohmic contact with the source metal layer;

[0055] The inner sidewall of the inner circle of the cell peripheral trench 13 is square or circular, and the P-type base region 8 is located above the bottom of the peripheral trench gate conductive polysilicon 18.

[0056] In the embodiments of the present invention, an N+ source region 20 is also provided above the outer wall side of the inner cavity of the cell peripheral trench 13. The doping concentration of the N+ source region 20 is greater than the doping concentration of the drift region 11. The depth of the N+ source region 20 is less than the depth of the P-type base region 8, that is, the bottom of the N+ source region 20 supports on the P-type base region 8. The N+ source region 20 is in ohmic contact with the source metal layer to form a required conductive channel.

[0057] As can be seen from the above description, a square-ring-shaped cell peripheral trench ring 4 is formed by the cell peripheral trench 13. Therefore, the cell peripheral trench ring 4 has an outer ring of the cell peripheral trench and an inner ring 9 of the cell peripheral trench. The outer ring of the cell peripheral trench needs to be square, while the inner ring 9 of the cell peripheral trench can be square or circular, that is, the inner sidewall of the cell peripheral trench 13 is square or circular. The specific shape of the inner ring 9 of the cell peripheral trench can be selected according to actual needs and will not be elaborated here. In specific implementation, the P-type base region 8 is located above the bottom of the peripheral trench gate conductive polysilicon 18. The bottom of the peripheral trench gate conductive polysilicon 18 specifically refers to the end of the peripheral trench gate conductive polysilicon 18 adjacent to the peripheral trench source conductive polysilicon 16.

[0058] Furthermore, the width of the peripheral trench gate conductive polysilicon 18 is greater than the width of the peripheral trench source conductive polysilicon 16; the peripheral trench source conductive polysilicon 16 is insulated and isolated from the inner sidewall and the inner bottom wall of the cell peripheral trench 13 through the peripheral trench lower insulating oxide layer 14, and the peripheral trench gate conductive polysilicon 18 is insulated and isolated from the corresponding inner sidewall of the cell peripheral trench 13 through the peripheral trench upper insulating oxide layer 36. The peripheral trench gate conductive polysilicon 18 in the cell peripheral trench 13 is insulated and isolated from the source metal through the insulating dielectric layer 21 covering the mouth of the cell peripheral trench 13.

[0059] In the embodiment of the present invention, the width of the peripheral trench gate conductive polysilicon 18 is greater than the width of the peripheral trench source conductive polysilicon 16. The peripheral trench lower insulating oxide layer 14 is arranged at the lower part inside the cell peripheral trench 13, and the inner sidewall and the inner bottom wall of the lower part of the cell peripheral trench 13 are covered by the peripheral trench lower insulating oxide layer 14, so that the peripheral trench source conductive polysilicon 16 is insulated and isolated from the inner sidewall and the inner bottom wall of the cell peripheral trench 13 through the peripheral trench lower insulating oxide layer 14. The peripheral trench upper insulating oxide layer 36 is arranged at the upper part inside the cell peripheral trench 13, and the sidewall of the area downward from the mouth of the cell peripheral trench 13 is covered by the peripheral trench upper insulating oxide layer 36. The peripheral trench gate conductive polysilicon 18 is insulated and isolated from the corresponding inner sidewall of the cell peripheral trench 13 through the peripheral trench upper insulating oxide layer 36; of course, the peripheral trench source conductive polysilicon 16 is insulated and isolated from the peripheral trench gate conductive polysilicon 18 through the peripheral trench inner isolation oxide layer 19.

[0060] The peripheral trench lower insulating oxide layer 14, the peripheral trench inner isolation oxide layer 19, and the peripheral trench upper insulating oxide layer 36 are all silicon dioxide layers, which can be specifically prepared by commonly used technical means in the technical field. Of course, the specific process methods and processes for preparing the peripheral trench gate conductive polysilicon 18 and the peripheral trench source conductive polysilicon 16 can also be the same as those in the prior art, and are specifically well-known to those skilled in the technical field. Generally, the thickness of the peripheral trench lower insulating oxide layer 14 is greater than the thickness of the peripheral trench upper insulating oxide layer 36.

[0061] Furthermore, it further includes a center trench contact hole 7 corresponding exactly to the trench 5 at the center of the cell and a center trench outer contact hole 23 located outside the center trench contact hole 7, and both the center trench contact hole 7 and the center trench outer contact hole 23 penetrate through the insulating dielectric layer 21;

[0062] The source metal layer is in ohmic contact with the center trench conductive polysilicon 15 through the first filler connector 25 filled in the center trench contact hole 7, and the source metal layer is in ohmic contact with the P-type base region 8 and the N+ source region 20 through the second filler connector 24 filled in the center trench outer contact hole 23.

[0063] In the embodiment of the present invention, the insulating dielectric layer 21 can be in the form of a commonly used silicon nitride layer in the prior art, and can be specifically selected according to needs. The insulating dielectric layer 21 covers the drift region 11, and the insulating dielectric layer 21 can cover the corresponding notch of the cell peripheral trench 13 and the cell center trench 5. The specific function of the insulating dielectric layer 21 is the same as that of the existing SGT device. In order to achieve contact connection with the source metal layer, a center trench contact hole 7 corresponding exactly to the trench 5 at the center of the cell and a center trench outer contact hole 23 located outside the center trench contact hole 7 need to be prepared, and both the center trench contact hole 7 and the center trench outer contact hole 23 penetrate through the insulating dielectric layer 21.

[0064] It can be seen from Figure 3 that the center trench outer contact hole 23 can be used to form a center trench outer contact hole ring 6. The center trench outer contact hole ring 6 is located outside the cell center trench 5, and the center trench outer contact hole ring 6 is annular, such as square annular or circular annular, and the specific shape can be selected according to needs. Figure 2 The implementation situation where the center trench outer contact hole ring 6 is square annular is shown in Figure 3In [description], there is a center trench outer contact hole 23 on both sides of the trench 5 at the center of the cell. After the source metal layer is prepared, the corresponding metal material will fill the center trench contact hole 7 and the center trench outer contact hole 23. The metal material filled in the center trench contact hole 7 forms a filled first connector 25, and the metal material filled in the center trench outer contact hole 23 forms a filled second connector 24. The filled first connector 25, the filled second connector 24, and the source metal layer are all made of the same metal material, which can be specifically prepared by common technical means in this technical field.

[0065] The source metal layer, the filled first connector 25, and the filled second connector 24 are integrated. Thus, the source metal layer makes an ohmic contact with the trench conductive polysilicon 15 at the center through the filled first connector 25 filled in the center trench contact hole 7, and the source metal layer makes an ohmic contact with the P-type base region 8 and the N+ source region 20 through the filled second connector 24 filled in the center trench outer contact hole 23.

[0066] During specific implementation, the width of the center trench contact hole 7 is smaller than the width of the trench conductive polysilicon 15 at the center in the cell center trench 5; of course, the width of the center trench outer contact hole 23 is smaller than the distance between the cell center trench 5 and the cell peripheral trench 13. The center trench contact hole 7 and the center trench outer contact hole 23 can be prepared in the same process step layer.

[0067] Furthermore, it further includes a lead connection area 27 located outside the cell area and a lead connection unit arranged in the lead connection area 27. The source metal layer can be electrically connected to the peripheral trench source conductive polysilicon 16 through the lead connection unit, and the gate metal layer can be electrically connected to the peripheral trench gate conductive polysilicon 18 through the lead connection unit.

[0068] In the embodiment of the present invention, through the lead connection area 27 and the lead connection unit, the shielding gate units in the cell peripheral trench 13 can be respectively led out to meet the above-mentioned electrical connection between the peripheral trench gate conductive polysilicon 18 and the gate metal layer above the drift region 11, and the electrical connection between the peripheral trench source conductive polysilicon 16 and the source metal layer above the drift region 11.

[0069] As Figure 4 shown, the lead connection unit includes a plurality of lead area lead trenches 34. A lead area lead trench 34 corresponds exactly to the cell peripheral trench 13 on one side inside the corresponding cell, and the peripheral trench gate conductive polysilicon 18 and the peripheral source conductive polysilicon 16 in the cell peripheral trench 13 are respectively introduced into the lead area lead trench 34 to respectively form the lead trench peripheral trench gate conductive polysilicon and the lead trench peripheral trench source conductive polysilicon located in the lead area lead trench 34;

[0070] The gate metal layer includes at least a gate lead connection portion 30, and the gate lead connection portion 30 is in ohmic contact with the lead trench peripheral trench gate conductive polysilicon in the lead trench 34 of the lead-out region through a gate polysilicon lead contact hole 31 corresponding exactly to the lead trench 34 of the lead-out region;

[0071] The source metal layer includes a source lead connection portion 37 and a source cell connection portion 22 connected to the source lead connection portion 37, and is in ohmic contact with the central trench conductive polysilicon 15 in the trench 5 at the center of the cell through the source cell connection portion 22. The source lead connection portion 37 is in ohmic contact with the lead trench peripheral trench source conductive polysilicon in the lead trench 34 of the lead-out region through a source polysilicon lead contact hole 32 corresponding exactly to the lead trench 34 of the lead-out region.

[0072] Figure 5 In the case where the cell unit 28 is square-shaped, adjacent cell units 28 can share the cell peripheral trench 13 on one side, so that the cell peripheral trench rings 4 in all cell regions 26 are interconnected, that is, the peripheral trench gate conductive polysilicons 18 in all cell units 28 are connected into one body, and the peripheral source conductive polysilicons 16 in all cell units 28 are connected into one body.

[0073] In the embodiment of the present invention, the lead connection region 27 is located between the cell region 26 and the terminal region. The lead connection unit includes a plurality of lead trench 34 in the lead-out region. Among them, a lead trench 34 corresponds exactly to the cell peripheral trench 13 on one side of the cell peripheral trench ring 4 in a cell unit 28, so that the distance between adjacent lead trenches 34 corresponds to the width of one side of the cell peripheral trench ring 4.

[0074] For the convenience of lead connection, the peripheral trench gate conductive polysilicon 18 and the peripheral source conductive polysilicon 16 in the cell peripheral trench 13 are respectively introduced into the lead trench 34 of the lead-out region. Among them, the peripheral trench gate conductive polysilicon 18 introduced into the lead trench 34 of the lead-out region forms the lead trench peripheral trench gate conductive polysilicon, and the peripheral source conductive polysilicon 16 introduced into the lead trench 34 of the lead-out region forms the lead trench peripheral trench source conductive polysilicon.

[0075] During specific implementation, a gate polysilicon lead contact hole 31 and a source polysilicon lead contact hole 32 are respectively arranged in different regions of the lead trench 34 of the lead-out region. Among them, the gate polysilicon lead contact hole 31 is relatively closer to the cell region 26, and the source polysilicon lead contact hole 32 is located outside the gate polysilicon lead contact hole 31. Through the gate polysilicon lead contact hole 31, it can correspond exactly to the lead trench peripheral trench gate conductive polysilicon, and through the source polysilicon lead contact hole 32, it can correspond exactly to the lead trench peripheral trench source conductive polysilicon.

[0076] In specific implementation, the gate metal layer at least includes a gate lead connection portion 30. Of course, the gate metal layer also includes a gate lead connection end block 29 located at the first end of the gate lead connection portion 30. The length direction of the gate lead connection end block 29 is perpendicular to the length direction of the gate lead connection portion 30. When the gate metal layer is prepared, the gate lead connection portion 30 is in ohmic contact with the lead trench peripheral trench gate conductive polysilicon in the lead trench 34 through a gate polysilicon lead contact hole 31 that corresponds exactly to the lead trench 34 in the lead area. That is, after the gate metal layer is in ohmic contact with the lead trench peripheral trench gate conductive polysilicon through the gate lead connection portion 30, the electrical connection between the gate metal layer and the peripheral trench gate conductive polysilicon 18 can be achieved.

[0077] Similarly, the source metal layer includes a source lead connection portion 37 and a source cell connection portion 22 connected to the source lead connection portion 37. The source lead connection portion 37 corresponds to the lead connection area 27, and the source cell connection portion 22 corresponds to the cell area 26. The source lead connection portion 37 and the source cell connection portion 22 are generally in the same process step layer, that is, prepared simultaneously. Of course, the first filler 25, the second filler 24, the source lead connection portion 37, and the source cell connection portion 22 are also prepared in the same process step. Through the ohmic contact between the source cell connection portion 22 and the central trench conductive polysilicon 15 in the trench 5 at the center of the cell, and the source lead connection portion 37 is in ohmic contact with the lead trench peripheral trench source conductive polysilicon in the lead trench 34 through a source polysilicon lead contact hole 32 that corresponds exactly to the lead trench 34 in the lead area. That is, through the electrical connection between the source lead connection portion 37 and the peripheral source conductive polysilicon 16, the electrical connection between the source metal layer and the peripheral trench source conductive polysilicon 16 is achieved.

[0078] The source metal layer and the gate metal layer can be prepared by using existing common processes. The source metal layer and the gate metal layer can select existing common metal materials, which can be specifically selected according to needs and will not be elaborated here.

[0079] Furthermore, the length direction of the gate lead connection portion 30 is consistent with the length direction of the source lead connection portion 37, and the gate lead connection portion 30 is located between the cell area 26 and the source lead connection portion 37;

[0080] The lead trench 34 in the lead area is strip-shaped, and the length direction of the lead trench 34 in the lead area is perpendicular to the length direction of the gate lead connection portion 30.

[0081] In the embodiment of the present invention, the gate lead connection portion 30 and the source lead connection portion 37 are parallel to each other, and the source lead connection portion 37 and the source cell connection portion 22 are connected integrally at the second end of the gate lead connection portion 30. The lead-out region lead-out trench 34 is strip-shaped, and the length direction of the lead-out region lead-out trench 34 is perpendicular to the length direction of the gate lead connection portion 30. Specifically, during implementation, in the lead-out region lead-out trench 34, no lead-out trench peripheral trench gate conductive polysilicon may be provided on the outer side corresponding to the gate polysilicon lead-out contact hole 31, that is, only the lead-out trench peripheral trench source conductive polysilicon exists, so that the source polysilicon lead-out contact hole 32 can correspond exactly to the lead-out trench peripheral trench source conductive polysilicon.

[0082] Further, a lead-out region transition trench 33 is provided between two adjacent lead-out region lead-out trenches 34 in the lead-out connection region 27, and the transition trench conductive polysilicon in the lead-out region transition trench 33 is in ohmic contact with the source metal layer;

[0083] It further includes a lead-out region lead-out connection trench 35 adaptively connected to the ends of all the lead-out region lead-out trenches 34. The two ends of the lead-out region lead-out trench 34 are respectively connected to the lead-out region lead-out connection trench 35 and the cell peripheral trench 13 on one side inside the corresponding cell;

[0084] The horizontal distance between the lead-out region transition trench 33 and the two adjacent lead-out region lead-out trenches 34 on both sides is L1. The first end of the lead-out region transition trench 33 corresponds to a cell, and the vertical distance between the first end of the lead-out region transition trench 33 and the corresponding cell is L2. The vertical distance between the second end of the lead-out region transition trench 33 and the inside of the lead-out region lead-out connection trench 35 is L3, and the distances L1, L2, and L3 match.

[0085] In the embodiment of the present invention, a lead-out region transition trench 33 is provided between two adjacent lead-out region lead-out trenches 34 in the lead-out connection region 27, and the transition trench conductive polysilicon in the lead-out region transition trench 33 is in ohmic contact with the source metal layer, that is, the transition trench conductive polysilicon in the lead-out region transition trench 33 is in ohmic contact with the source lead connection portion 37. The other ends of the lead-out region lead-out trenches 34 far from the cell region 26 are connected to each other through the lead-out region lead-out connection trench 35. The length direction of the lead-out region lead-out connection trench 35 is consistent with the length direction of the gate lead connection portion 30, so as to connect to the ends of all the lead-out region lead-out trenches 34 through the lead-out region lead-out connection trench 35. By using the cooperation between the lead-out region lead-out connection trench 35 and the lead-out region lead-out trench 34, the entire lead-out connection region 27 and the cell region 26 can be made to form a relatively closed region.

[0086] In the embodiment of the present invention, the lead-out area transition trench 33 is strip-shaped, and the length of the lead-out area transition trench 33 is less than the length of the lead-out area lead-out trench 34, that is, the lead-out area transition trench 33 does not contact and connect with the cell area 26 and the lead-out area lead-out connection trench 35. A transition trench conductive polysilicon is arranged in the lead-out area transition trench 33. Of course, the transition trench conductive polysilicon is insulated from the inner side wall and the bottom wall of the lead-out area transition trench 33 through a lead-out area transition trench oxide layer covering the inner side wall and the bottom wall of the lead-out area transition trench 33. In addition, a lead-out connection trench conductive polysilicon connected integrally with the lead-out trench peripheral trench source conductive polysilicon is arranged in the lead-out area lead-out connection trench 35. Of course, the lead-out connection trench conductive polysilicon needs to be insulated from the inner side wall and the inner bottom wall of the lead-out area lead-out connection trench 35 through a lead-out connection trench insulating oxide layer covering the lead-out area lead-out connection trench 35.

[0087] A lead-out area transition trench contact hole corresponding to the lead-out area transition trench 33 is prepared, and the source lead-out connection part 37 is in ohmic contact with the transition trench conductive polysilicon through the lead-out area transition trench contact hole, that is, the electrical connection between the transition trench conductive polysilicon and the source metal layer is realized. Generally, the lead-out area transition trench contact hole and the source polysilicon lead-out contact hole 32 are located on the same straight line.

[0088] During specific implementation, the horizontal distance between the lead-out area transition trench 33 and the two lead-out area lead-out trenches 34 on both sides is L1, the first end of the lead-out area transition trench 33 corresponds to a cell, and the vertical distance between the first end of the lead-out area transition trench 33 and the corresponding cell is L2. The vertical distance between the second end of the lead-out area transition trench 33 and the inner side of the lead-out area lead-out connection trench 35 is L3, and the distances L1, L2 and L3 are matched.

[0089] Specifically, the distances L1, L2 and L3 are matched, which specifically means that the distances L1, L2 and L3 are equal, or the distance differences between the distances L1, L2 and L3 are within an allowable range. The specific situation can be selected according to the actual situation and will not be elaborated here.

[0090] In summary, when the cell unit 28 is square-shaped, the shielding gate units in the cell peripheral trench 13 need to be respectively led out through the lead-out connection area 27 and the lead-out connection unit. During the lead-out, the lead-out connection unit at least includes the lead-out area lead-out trench 34. The gate lead-out connection part 30 is in ohmic contact with the lead-out trench peripheral trench gate conductive polysilicon in the lead-out area lead-out trench 34 through the gate polysilicon lead-out contact hole 31 corresponding to the lead-out area lead-out trench 34. At the same time, the source lead-out connection part 37 is in ohmic contact with the lead-out trench peripheral trench source conductive polysilicon in the lead-out area lead-out trench 34 through the source polysilicon lead-out contact hole 32 corresponding to the lead-out area lead-out trench 34.

[0091] In the lead connection area 27, through the cooperation of the lead area transition groove 33, the lead area lead connection groove 35 and the lead area lead groove 34, the horizontal distance between the lead area transition groove 33 and the two side lead area lead grooves 34 can be obtained as L1. The first end of the lead area transition groove 33 corresponds exactly to a unit cell, and the vertical distance between the first end of the lead area transition groove 33 and the corresponding unit cell is L2. The vertical distance between the second end of the lead area transition groove 33 and the inner side of the lead area lead connection groove 35 is L3, and the distances L1, L2 and L3 are matched. According to the relationship between the distances L1, L2 and L3 and the breakdown voltage BV of the drift region, it can be known that it can be kept consistent with the mesa width and the mesa width depletion direction in the cell area 26. Therefore, the breakdown voltage BV of the drift region in the cell area 26 and the lead connection area 27 can be kept consistent, preventing the breakdown voltage BV difference caused by different mesa widths or depletion directions at different positions of the device, and further preventing the breakdown voltage reliability problem caused by the breakdown voltage BV difference.

Claims

1. A high-reliability SGT device with an upper and lower structure, comprising a semiconductor substrate of a first conductivity type and a cell region prepared in the drift region of the semiconductor substrate, and the cells in the cell region adopt a trench structure; characterized in that: In On the top view plane of the SGT device, the cells in the cell region include a square-ring-shaped cell peripheral trench and a cell center trench located in the center region inside the cell peripheral trench; a base region of a second conductivity type is arranged between the outer circle of the cell center trench and the inner circle of the cell peripheral trench; In the cross-section of the SGT device, the base region of the second conductivity type is located above the corresponding trench bottoms of the cell center trench and the cell peripheral trench in the drift region, and the base region of the second conductivity type is in contact with the outer sidewalls of the cell center trench and the inner sidewall of the inner circle of the cell peripheral trench; a conductive polysilicon for the center trench is filled in the cell center trench, and the conductive polysilicon for the center trench is insulated from the inner sidewall and the inner bottom wall of the cell center trench through an oxide layer for the cell center trench covering the inner sidewall and the inner bottom wall of the cell center trench; A shielding gate unit with an upper and lower structure distribution is arranged in the cell peripheral trench. Among them, the shielding gate unit with the upper and lower structure distribution includes a peripheral trench gate conductive polysilicon located above and a peripheral trench source conductive polysilicon located below the peripheral trench gate conductive polysilicon. The peripheral trench gate conductive polysilicon and the peripheral trench source conductive polysilicon are insulated from each other. The peripheral trench gate conductive polysilicon is electrically connected to a gate metal layer above the drift region, and the peripheral trench source conductive polysilicon, the conductive polysilicon for the center trench, and the base region of the second conductivity type are electrically connected to a source metal layer above the drift region; It further includes a lead connection region located outside the cell region and a lead connection unit arranged in the lead connection region. The source metal layer can be electrically connected to the peripheral trench source conductive polysilicon through the lead connection unit, and the gate metal layer can be electrically connected to the peripheral trench gate conductive polysilicon through the lead connection unit; The lead connection unit includes a plurality of lead region lead trenches. A lead region lead trench corresponds to the cell peripheral trench on one side inside the corresponding cell, and the peripheral trench gate conductive polysilicon and the peripheral source conductive polysilicon in the cell peripheral trench are respectively introduced into the lead region lead trench to form a lead trench peripheral trench gate conductive polysilicon and a lead trench peripheral trench source conductive polysilicon respectively; The gate metal layer at least includes a gate lead connection part, and the gate lead connection part is in ohmic contact with the lead trench peripheral trench gate conductive polysilicon in the lead region lead trench through a gate polysilicon lead contact hole corresponding to the lead region lead trench; The source metal layer includes a source lead connection part and a source cell connection part connected to the source lead connection part. The source cell connection part is in ohmic contact with the conductive polysilicon for the center trench in the cell center trench, and the source lead connection part is in ohmic contact with the lead trench peripheral trench source conductive polysilicon in the lead region lead trench through a source polysilicon lead contact hole corresponding to the lead region lead trench; An extraction region transition trench is arranged between two extraction trenches in adjacent extraction regions within the extraction connection region. The transition trench conductive polysilicon within the extraction region transition trench is in ohmic contact with the source metal layer. It further includes an extraction region extraction connection trench that is adaptively connected to the ends of all extraction region extraction trenches. The two ends of the extraction region extraction trench are respectively connected to the extraction region extraction connection trench and the cell peripheral trench on one side within the corresponding cell. The horizontal distance between the extraction region transition trench and the extraction trenches on both sides is L1. The first end of the extraction region transition trench corresponds to a cell, and the vertical distance between the first end of the extraction region transition trench and the corresponding cell is L2. The vertical distance between the second end of the extraction region transition trench and the inner side of the extraction region extraction connection trench is L3, and the distances L1, L2, and L3 are equal.

2. The highly reliable SGT device with an upper and lower structure according to claim 1, characterized in that: It further includes a first-conductivity-type source region that contacts the outer wall side above the inner circle of the cell peripheral trench. The depth of the first-conductivity-type source region is less than the depth of the second-conductivity-type base region. The first-conductivity-type source region contacts the second-conductivity-type base region and is in ohmic contact with the source metal layer. The inner sidewall of the inner circle of the cell peripheral trench is square or circular. The second-conductivity-type base region is located above the bottom of the peripheral trench gate conductive polysilicon.

3. The highly reliable SGT device with an upper and lower structure according to claim 2, characterized in that: The width of the peripheral trench gate conductive polysilicon is greater than the width of the peripheral trench source conductive polysilicon. The peripheral trench source conductive polysilicon is insulated and isolated from the inner sidewall and the inner bottom wall of the cell peripheral trench through the peripheral trench lower insulating oxide layer. The peripheral trench gate conductive polysilicon is insulated and isolated from the corresponding inner sidewall of the cell peripheral trench through the peripheral trench upper insulating oxide layer. The peripheral trench gate conductive polysilicon within the cell peripheral trench is insulated and isolated from the source metal through the insulating dielectric layer covering the mouth of the cell peripheral trench.

4. The highly reliable SGT device with an up-down structure according to claim 3, wherein: It further includes a center trench contact hole corresponding to the trench at the center of the cell and a center trench outer contact hole located outside the center trench contact hole. Both the center trench contact hole and the center trench outer contact hole penetrate the insulating dielectric layer. The source metal layer is in ohmic contact with the center trench conductive polysilicon through the first filler connected filled in the center trench contact hole. The source metal layer is in ohmic contact with the second-conductivity-type base region and the first-conductivity-type source region through the second filler connected filled in the center trench outer contact hole.

5. The highly reliable SGT device with an up-down structure according to claim 4, characterized in that: The trench at the center of the cell is square, and the width of the center trench contact hole is less than the width of the center trench conductive polysilicon within the trench at the center of the cell. The center trench outer contact hole is annular outside the trench at the center of the cell.

6. The high-reliability SGT device with an upper and lower structure according to any one of claims 1 to 5, characterized in that: The semiconductor substrate further includes a first-conductivity-type substrate that is adaptively connected to the drift region, and a back electrode structure is provided on the back surface of the substrate.

7. The high-reliability SGT device with an upper and lower structure according to claim 1, characterized in that: The length direction of the gate extraction connection part is consistent with the length direction of the source extraction connection part. The gate extraction connection part is located between the cell region and the source extraction connection part. The extraction region extraction trench is strip-shaped, and the length direction of the extraction region extraction trench is perpendicular to the length direction of the gate extraction connection part.

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